NVMe: Update list of status codes
[linux-2.6-block.git] / drivers / block / nvme-core.c
CommitLineData
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1/*
2 * NVM Express device driver
6eb0d698 3 * Copyright (c) 2011-2014, Intel Corporation.
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4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
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13 */
14
15#include <linux/nvme.h>
16#include <linux/bio.h>
8de05535 17#include <linux/bitops.h>
b60503ba 18#include <linux/blkdev.h>
42f61420 19#include <linux/cpu.h>
fd63e9ce 20#include <linux/delay.h>
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21#include <linux/errno.h>
22#include <linux/fs.h>
23#include <linux/genhd.h>
4cc09e2d 24#include <linux/hdreg.h>
5aff9382 25#include <linux/idr.h>
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26#include <linux/init.h>
27#include <linux/interrupt.h>
28#include <linux/io.h>
29#include <linux/kdev_t.h>
1fa6aead 30#include <linux/kthread.h>
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31#include <linux/kernel.h>
32#include <linux/mm.h>
33#include <linux/module.h>
34#include <linux/moduleparam.h>
35#include <linux/pci.h>
42f61420 36#include <linux/percpu.h>
be7b6275 37#include <linux/poison.h>
c3bfe717 38#include <linux/ptrace.h>
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39#include <linux/sched.h>
40#include <linux/slab.h>
41#include <linux/types.h>
5d0f6131 42#include <scsi/sg.h>
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43#include <asm-generic/io-64-nonatomic-lo-hi.h>
44
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45#include <trace/events/block.h>
46
9d43cf64 47#define NVME_Q_DEPTH 1024
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48#define SQ_SIZE(depth) (depth * sizeof(struct nvme_command))
49#define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion))
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50#define ADMIN_TIMEOUT (admin_timeout * HZ)
51#define IOD_TIMEOUT (retry_time * HZ)
52
53static unsigned char admin_timeout = 60;
54module_param(admin_timeout, byte, 0644);
55MODULE_PARM_DESC(admin_timeout, "timeout in seconds for admin commands");
b60503ba 56
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57unsigned char nvme_io_timeout = 30;
58module_param_named(io_timeout, nvme_io_timeout, byte, 0644);
b355084a 59MODULE_PARM_DESC(io_timeout, "timeout in seconds for I/O");
b60503ba 60
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61static unsigned char retry_time = 30;
62module_param(retry_time, byte, 0644);
63MODULE_PARM_DESC(retry_time, "time in seconds to retry failed I/O");
64
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65static int nvme_major;
66module_param(nvme_major, int, 0);
67
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68static int use_threaded_interrupts;
69module_param(use_threaded_interrupts, int, 0);
70
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71static DEFINE_SPINLOCK(dev_list_lock);
72static LIST_HEAD(dev_list);
73static struct task_struct *nvme_thread;
9a6b9458 74static struct workqueue_struct *nvme_workq;
b9afca3e 75static wait_queue_head_t nvme_kthread_wait;
f3db22fe 76static struct notifier_block nvme_nb;
1fa6aead 77
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78static void nvme_reset_failed_dev(struct work_struct *ws);
79
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80struct async_cmd_info {
81 struct kthread_work work;
82 struct kthread_worker *worker;
83 u32 result;
84 int status;
85 void *ctx;
86};
1fa6aead 87
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88/*
89 * An NVM Express queue. Each device has at least two (one for admin
90 * commands and one for I/O commands).
91 */
92struct nvme_queue {
5a92e700 93 struct rcu_head r_head;
b60503ba 94 struct device *q_dmadev;
091b6092 95 struct nvme_dev *dev;
3193f07b 96 char irqname[24]; /* nvme4294967295-65535\0 */
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97 spinlock_t q_lock;
98 struct nvme_command *sq_cmds;
99 volatile struct nvme_completion *cqes;
100 dma_addr_t sq_dma_addr;
101 dma_addr_t cq_dma_addr;
102 wait_queue_head_t sq_full;
1fa6aead 103 wait_queue_t sq_cong_wait;
b60503ba 104 struct bio_list sq_cong;
edd10d33 105 struct list_head iod_bio;
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106 u32 __iomem *q_db;
107 u16 q_depth;
108 u16 cq_vector;
109 u16 sq_head;
110 u16 sq_tail;
111 u16 cq_head;
c30341dc 112 u16 qid;
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113 u8 cq_phase;
114 u8 cqe_seen;
22404274 115 u8 q_suspended;
42f61420 116 cpumask_var_t cpu_mask;
4d115420 117 struct async_cmd_info cmdinfo;
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118 unsigned long cmdid_data[];
119};
120
121/*
122 * Check we didin't inadvertently grow the command struct
123 */
124static inline void _nvme_check_size(void)
125{
126 BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64);
127 BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
128 BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
129 BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
130 BUILD_BUG_ON(sizeof(struct nvme_features) != 64);
f8ebf840 131 BUILD_BUG_ON(sizeof(struct nvme_format_cmd) != 64);
c30341dc 132 BUILD_BUG_ON(sizeof(struct nvme_abort_cmd) != 64);
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133 BUILD_BUG_ON(sizeof(struct nvme_command) != 64);
134 BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != 4096);
135 BUILD_BUG_ON(sizeof(struct nvme_id_ns) != 4096);
136 BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64);
6ecec745 137 BUILD_BUG_ON(sizeof(struct nvme_smart_log) != 512);
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138}
139
edd10d33 140typedef void (*nvme_completion_fn)(struct nvme_queue *, void *,
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141 struct nvme_completion *);
142
e85248e5 143struct nvme_cmd_info {
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144 nvme_completion_fn fn;
145 void *ctx;
e85248e5 146 unsigned long timeout;
c30341dc 147 int aborted;
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148};
149
150static struct nvme_cmd_info *nvme_cmd_info(struct nvme_queue *nvmeq)
151{
152 return (void *)&nvmeq->cmdid_data[BITS_TO_LONGS(nvmeq->q_depth)];
153}
154
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155static unsigned nvme_queue_extra(int depth)
156{
157 return DIV_ROUND_UP(depth, 8) + (depth * sizeof(struct nvme_cmd_info));
158}
159
b60503ba 160/**
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161 * alloc_cmdid() - Allocate a Command ID
162 * @nvmeq: The queue that will be used for this command
163 * @ctx: A pointer that will be passed to the handler
c2f5b650 164 * @handler: The function to call on completion
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165 *
166 * Allocate a Command ID for a queue. The data passed in will
167 * be passed to the completion handler. This is implemented by using
168 * the bottom two bits of the ctx pointer to store the handler ID.
169 * Passing in a pointer that's not 4-byte aligned will cause a BUG.
170 * We can change this if it becomes a problem.
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171 *
172 * May be called with local interrupts disabled and the q_lock held,
173 * or with interrupts enabled and no locks held.
b60503ba 174 */
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175static int alloc_cmdid(struct nvme_queue *nvmeq, void *ctx,
176 nvme_completion_fn handler, unsigned timeout)
b60503ba 177{
e6d15f79 178 int depth = nvmeq->q_depth - 1;
e85248e5 179 struct nvme_cmd_info *info = nvme_cmd_info(nvmeq);
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180 int cmdid;
181
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182 do {
183 cmdid = find_first_zero_bit(nvmeq->cmdid_data, depth);
184 if (cmdid >= depth)
185 return -EBUSY;
186 } while (test_and_set_bit(cmdid, nvmeq->cmdid_data));
187
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188 info[cmdid].fn = handler;
189 info[cmdid].ctx = ctx;
e85248e5 190 info[cmdid].timeout = jiffies + timeout;
c30341dc 191 info[cmdid].aborted = 0;
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192 return cmdid;
193}
194
195static int alloc_cmdid_killable(struct nvme_queue *nvmeq, void *ctx,
c2f5b650 196 nvme_completion_fn handler, unsigned timeout)
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197{
198 int cmdid;
199 wait_event_killable(nvmeq->sq_full,
e85248e5 200 (cmdid = alloc_cmdid(nvmeq, ctx, handler, timeout)) >= 0);
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201 return (cmdid < 0) ? -EINTR : cmdid;
202}
203
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204/* Special values must be less than 0x1000 */
205#define CMD_CTX_BASE ((void *)POISON_POINTER_DELTA)
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206#define CMD_CTX_CANCELLED (0x30C + CMD_CTX_BASE)
207#define CMD_CTX_COMPLETED (0x310 + CMD_CTX_BASE)
208#define CMD_CTX_INVALID (0x314 + CMD_CTX_BASE)
53562be7 209#define CMD_CTX_ABORT (0x318 + CMD_CTX_BASE)
6fccf938 210#define CMD_CTX_ASYNC (0x31C + CMD_CTX_BASE)
be7b6275 211
edd10d33 212static void special_completion(struct nvme_queue *nvmeq, void *ctx,
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213 struct nvme_completion *cqe)
214{
215 if (ctx == CMD_CTX_CANCELLED)
216 return;
c30341dc 217 if (ctx == CMD_CTX_ABORT) {
edd10d33 218 ++nvmeq->dev->abort_limit;
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219 return;
220 }
c2f5b650 221 if (ctx == CMD_CTX_COMPLETED) {
edd10d33 222 dev_warn(nvmeq->q_dmadev,
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223 "completed id %d twice on queue %d\n",
224 cqe->command_id, le16_to_cpup(&cqe->sq_id));
225 return;
226 }
227 if (ctx == CMD_CTX_INVALID) {
edd10d33 228 dev_warn(nvmeq->q_dmadev,
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229 "invalid id %d completed on queue %d\n",
230 cqe->command_id, le16_to_cpup(&cqe->sq_id));
231 return;
232 }
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233 if (ctx == CMD_CTX_ASYNC) {
234 u32 result = le32_to_cpup(&cqe->result);
235 u16 status = le16_to_cpup(&cqe->status) >> 1;
236
237 if (status == NVME_SC_SUCCESS || status == NVME_SC_ABORT_REQ)
238 ++nvmeq->dev->event_limit;
239 if (status == NVME_SC_SUCCESS)
240 dev_warn(nvmeq->q_dmadev,
241 "async event result %08x\n", result);
242 return;
243 }
c2f5b650 244
edd10d33 245 dev_warn(nvmeq->q_dmadev, "Unknown special completion %p\n", ctx);
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246}
247
edd10d33 248static void async_completion(struct nvme_queue *nvmeq, void *ctx,
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249 struct nvme_completion *cqe)
250{
251 struct async_cmd_info *cmdinfo = ctx;
252 cmdinfo->result = le32_to_cpup(&cqe->result);
253 cmdinfo->status = le16_to_cpup(&cqe->status) >> 1;
254 queue_kthread_work(cmdinfo->worker, &cmdinfo->work);
255}
256
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257/*
258 * Called with local interrupts disabled and the q_lock held. May not sleep.
259 */
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260static void *free_cmdid(struct nvme_queue *nvmeq, int cmdid,
261 nvme_completion_fn *fn)
b60503ba 262{
c2f5b650 263 void *ctx;
e85248e5 264 struct nvme_cmd_info *info = nvme_cmd_info(nvmeq);
b60503ba 265
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266 if (cmdid >= nvmeq->q_depth || !info[cmdid].fn) {
267 if (fn)
268 *fn = special_completion;
48e3d398 269 return CMD_CTX_INVALID;
c2f5b650 270 }
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271 if (fn)
272 *fn = info[cmdid].fn;
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273 ctx = info[cmdid].ctx;
274 info[cmdid].fn = special_completion;
e85248e5 275 info[cmdid].ctx = CMD_CTX_COMPLETED;
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276 clear_bit(cmdid, nvmeq->cmdid_data);
277 wake_up(&nvmeq->sq_full);
c2f5b650 278 return ctx;
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279}
280
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281static void *cancel_cmdid(struct nvme_queue *nvmeq, int cmdid,
282 nvme_completion_fn *fn)
3c0cf138 283{
c2f5b650 284 void *ctx;
e85248e5 285 struct nvme_cmd_info *info = nvme_cmd_info(nvmeq);
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286 if (fn)
287 *fn = info[cmdid].fn;
288 ctx = info[cmdid].ctx;
289 info[cmdid].fn = special_completion;
e85248e5 290 info[cmdid].ctx = CMD_CTX_CANCELLED;
c2f5b650 291 return ctx;
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292}
293
5a92e700 294static struct nvme_queue *raw_nvmeq(struct nvme_dev *dev, int qid)
b60503ba 295{
5a92e700 296 return rcu_dereference_raw(dev->queues[qid]);
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297}
298
4f5099af 299static struct nvme_queue *get_nvmeq(struct nvme_dev *dev) __acquires(RCU)
5a92e700 300{
a51afb54 301 struct nvme_queue *nvmeq;
42f61420 302 unsigned queue_id = get_cpu_var(*dev->io_queue);
a51afb54 303
5a92e700 304 rcu_read_lock();
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305 nvmeq = rcu_dereference(dev->queues[queue_id]);
306 if (nvmeq)
307 return nvmeq;
308
309 rcu_read_unlock();
310 put_cpu_var(*dev->io_queue);
311 return NULL;
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312}
313
4f5099af 314static void put_nvmeq(struct nvme_queue *nvmeq) __releases(RCU)
b60503ba 315{
5a92e700 316 rcu_read_unlock();
42f61420 317 put_cpu_var(nvmeq->dev->io_queue);
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318}
319
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320static struct nvme_queue *lock_nvmeq(struct nvme_dev *dev, int q_idx)
321 __acquires(RCU)
b60503ba 322{
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323 struct nvme_queue *nvmeq;
324
4f5099af 325 rcu_read_lock();
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326 nvmeq = rcu_dereference(dev->queues[q_idx]);
327 if (nvmeq)
328 return nvmeq;
329
330 rcu_read_unlock();
331 return NULL;
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332}
333
334static void unlock_nvmeq(struct nvme_queue *nvmeq) __releases(RCU)
335{
336 rcu_read_unlock();
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337}
338
339/**
714a7a22 340 * nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
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341 * @nvmeq: The queue to use
342 * @cmd: The command to send
343 *
344 * Safe to use from interrupt context
345 */
346static int nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd)
347{
348 unsigned long flags;
349 u16 tail;
b60503ba 350 spin_lock_irqsave(&nvmeq->q_lock, flags);
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351 if (nvmeq->q_suspended) {
352 spin_unlock_irqrestore(&nvmeq->q_lock, flags);
353 return -EBUSY;
354 }
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355 tail = nvmeq->sq_tail;
356 memcpy(&nvmeq->sq_cmds[tail], cmd, sizeof(*cmd));
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357 if (++tail == nvmeq->q_depth)
358 tail = 0;
7547881d 359 writel(tail, nvmeq->q_db);
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360 nvmeq->sq_tail = tail;
361 spin_unlock_irqrestore(&nvmeq->q_lock, flags);
362
363 return 0;
364}
365
eca18b23 366static __le64 **iod_list(struct nvme_iod *iod)
e025344c 367{
eca18b23 368 return ((void *)iod) + iod->offset;
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369}
370
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371/*
372 * Will slightly overestimate the number of pages needed. This is OK
373 * as it only leads to a small amount of wasted memory for the lifetime of
374 * the I/O.
375 */
376static int nvme_npages(unsigned size)
377{
378 unsigned nprps = DIV_ROUND_UP(size + PAGE_SIZE, PAGE_SIZE);
379 return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8);
380}
b60503ba 381
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382static struct nvme_iod *
383nvme_alloc_iod(unsigned nseg, unsigned nbytes, gfp_t gfp)
b60503ba 384{
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385 struct nvme_iod *iod = kmalloc(sizeof(struct nvme_iod) +
386 sizeof(__le64 *) * nvme_npages(nbytes) +
387 sizeof(struct scatterlist) * nseg, gfp);
388
389 if (iod) {
390 iod->offset = offsetof(struct nvme_iod, sg[nseg]);
391 iod->npages = -1;
392 iod->length = nbytes;
2b196034 393 iod->nents = 0;
edd10d33 394 iod->first_dma = 0ULL;
6198221f 395 iod->start_time = jiffies;
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396 }
397
398 return iod;
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399}
400
5d0f6131 401void nvme_free_iod(struct nvme_dev *dev, struct nvme_iod *iod)
b60503ba 402{
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403 const int last_prp = PAGE_SIZE / 8 - 1;
404 int i;
405 __le64 **list = iod_list(iod);
406 dma_addr_t prp_dma = iod->first_dma;
407
408 if (iod->npages == 0)
409 dma_pool_free(dev->prp_small_pool, list[0], prp_dma);
410 for (i = 0; i < iod->npages; i++) {
411 __le64 *prp_list = list[i];
412 dma_addr_t next_prp_dma = le64_to_cpu(prp_list[last_prp]);
413 dma_pool_free(dev->prp_page_pool, prp_list, prp_dma);
414 prp_dma = next_prp_dma;
415 }
416 kfree(iod);
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417}
418
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419static void nvme_start_io_acct(struct bio *bio)
420{
421 struct gendisk *disk = bio->bi_bdev->bd_disk;
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422 if (blk_queue_io_stat(disk->queue)) {
423 const int rw = bio_data_dir(bio);
424 int cpu = part_stat_lock();
425 part_round_stats(cpu, &disk->part0);
426 part_stat_inc(cpu, &disk->part0, ios[rw]);
427 part_stat_add(cpu, &disk->part0, sectors[rw],
428 bio_sectors(bio));
429 part_inc_in_flight(&disk->part0, rw);
430 part_stat_unlock();
431 }
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432}
433
434static void nvme_end_io_acct(struct bio *bio, unsigned long start_time)
435{
436 struct gendisk *disk = bio->bi_bdev->bd_disk;
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437 if (blk_queue_io_stat(disk->queue)) {
438 const int rw = bio_data_dir(bio);
439 unsigned long duration = jiffies - start_time;
440 int cpu = part_stat_lock();
441 part_stat_add(cpu, &disk->part0, ticks[rw], duration);
442 part_round_stats(cpu, &disk->part0);
443 part_dec_in_flight(&disk->part0, rw);
444 part_stat_unlock();
445 }
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446}
447
edd10d33 448static void bio_completion(struct nvme_queue *nvmeq, void *ctx,
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449 struct nvme_completion *cqe)
450{
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451 struct nvme_iod *iod = ctx;
452 struct bio *bio = iod->private;
b60503ba 453 u16 status = le16_to_cpup(&cqe->status) >> 1;
3291fa57 454 int error = 0;
b60503ba 455
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456 if (unlikely(status)) {
457 if (!(status & NVME_SC_DNR ||
458 bio->bi_rw & REQ_FAILFAST_MASK) &&
459 (jiffies - iod->start_time) < IOD_TIMEOUT) {
460 if (!waitqueue_active(&nvmeq->sq_full))
461 add_wait_queue(&nvmeq->sq_full,
462 &nvmeq->sq_cong_wait);
463 list_add_tail(&iod->node, &nvmeq->iod_bio);
464 wake_up(&nvmeq->sq_full);
465 return;
466 }
3291fa57 467 error = -EIO;
edd10d33 468 }
9e59d091 469 if (iod->nents) {
edd10d33 470 dma_unmap_sg(nvmeq->q_dmadev, iod->sg, iod->nents,
b60503ba 471 bio_data_dir(bio) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
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472 nvme_end_io_acct(bio, iod->start_time);
473 }
edd10d33 474 nvme_free_iod(nvmeq->dev, iod);
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475
476 trace_block_bio_complete(bdev_get_queue(bio->bi_bdev), bio, error);
477 bio_endio(bio, error);
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478}
479
184d2944 480/* length is in bytes. gfp flags indicates whether we may sleep. */
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481int nvme_setup_prps(struct nvme_dev *dev, struct nvme_iod *iod, int total_len,
482 gfp_t gfp)
ff22b54f 483{
99802a7a 484 struct dma_pool *pool;
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485 int length = total_len;
486 struct scatterlist *sg = iod->sg;
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487 int dma_len = sg_dma_len(sg);
488 u64 dma_addr = sg_dma_address(sg);
489 int offset = offset_in_page(dma_addr);
e025344c 490 __le64 *prp_list;
eca18b23 491 __le64 **list = iod_list(iod);
e025344c 492 dma_addr_t prp_dma;
eca18b23 493 int nprps, i;
ff22b54f 494
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495 length -= (PAGE_SIZE - offset);
496 if (length <= 0)
eca18b23 497 return total_len;
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498
499 dma_len -= (PAGE_SIZE - offset);
500 if (dma_len) {
501 dma_addr += (PAGE_SIZE - offset);
502 } else {
503 sg = sg_next(sg);
504 dma_addr = sg_dma_address(sg);
505 dma_len = sg_dma_len(sg);
506 }
507
508 if (length <= PAGE_SIZE) {
edd10d33 509 iod->first_dma = dma_addr;
eca18b23 510 return total_len;
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511 }
512
513 nprps = DIV_ROUND_UP(length, PAGE_SIZE);
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514 if (nprps <= (256 / 8)) {
515 pool = dev->prp_small_pool;
eca18b23 516 iod->npages = 0;
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517 } else {
518 pool = dev->prp_page_pool;
eca18b23 519 iod->npages = 1;
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520 }
521
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522 prp_list = dma_pool_alloc(pool, gfp, &prp_dma);
523 if (!prp_list) {
edd10d33 524 iod->first_dma = dma_addr;
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525 iod->npages = -1;
526 return (total_len - length) + PAGE_SIZE;
b77954cb 527 }
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528 list[0] = prp_list;
529 iod->first_dma = prp_dma;
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530 i = 0;
531 for (;;) {
7523d834 532 if (i == PAGE_SIZE / 8) {
e025344c 533 __le64 *old_prp_list = prp_list;
b77954cb 534 prp_list = dma_pool_alloc(pool, gfp, &prp_dma);
eca18b23
MW
535 if (!prp_list)
536 return total_len - length;
537 list[iod->npages++] = prp_list;
7523d834
MW
538 prp_list[0] = old_prp_list[i - 1];
539 old_prp_list[i - 1] = cpu_to_le64(prp_dma);
540 i = 1;
e025344c
SMM
541 }
542 prp_list[i++] = cpu_to_le64(dma_addr);
543 dma_len -= PAGE_SIZE;
544 dma_addr += PAGE_SIZE;
545 length -= PAGE_SIZE;
546 if (length <= 0)
547 break;
548 if (dma_len > 0)
549 continue;
550 BUG_ON(dma_len < 0);
551 sg = sg_next(sg);
552 dma_addr = sg_dma_address(sg);
553 dma_len = sg_dma_len(sg);
ff22b54f
MW
554 }
555
eca18b23 556 return total_len;
ff22b54f
MW
557}
558
427e9708 559static int nvme_split_and_submit(struct bio *bio, struct nvme_queue *nvmeq,
20d0189b 560 int len)
427e9708 561{
20d0189b
KO
562 struct bio *split = bio_split(bio, len >> 9, GFP_ATOMIC, NULL);
563 if (!split)
427e9708
KB
564 return -ENOMEM;
565
3291fa57
KB
566 trace_block_split(bdev_get_queue(bio->bi_bdev), bio,
567 split->bi_iter.bi_sector);
20d0189b
KO
568 bio_chain(split, bio);
569
edd10d33 570 if (!waitqueue_active(&nvmeq->sq_full))
427e9708 571 add_wait_queue(&nvmeq->sq_full, &nvmeq->sq_cong_wait);
20d0189b
KO
572 bio_list_add(&nvmeq->sq_cong, split);
573 bio_list_add(&nvmeq->sq_cong, bio);
edd10d33 574 wake_up(&nvmeq->sq_full);
427e9708
KB
575
576 return 0;
577}
578
1ad2f893
MW
579/* NVMe scatterlists require no holes in the virtual address */
580#define BIOVEC_NOT_VIRT_MERGEABLE(vec1, vec2) ((vec2)->bv_offset || \
581 (((vec1)->bv_offset + (vec1)->bv_len) % PAGE_SIZE))
582
427e9708 583static int nvme_map_bio(struct nvme_queue *nvmeq, struct nvme_iod *iod,
b60503ba
MW
584 struct bio *bio, enum dma_data_direction dma_dir, int psegs)
585{
7988613b
KO
586 struct bio_vec bvec, bvprv;
587 struct bvec_iter iter;
76830840 588 struct scatterlist *sg = NULL;
7988613b
KO
589 int length = 0, nsegs = 0, split_len = bio->bi_iter.bi_size;
590 int first = 1;
159b67d7
KB
591
592 if (nvmeq->dev->stripe_size)
593 split_len = nvmeq->dev->stripe_size -
4f024f37
KO
594 ((bio->bi_iter.bi_sector << 9) &
595 (nvmeq->dev->stripe_size - 1));
b60503ba 596
eca18b23 597 sg_init_table(iod->sg, psegs);
7988613b
KO
598 bio_for_each_segment(bvec, bio, iter) {
599 if (!first && BIOVEC_PHYS_MERGEABLE(&bvprv, &bvec)) {
600 sg->length += bvec.bv_len;
76830840 601 } else {
7988613b
KO
602 if (!first && BIOVEC_NOT_VIRT_MERGEABLE(&bvprv, &bvec))
603 return nvme_split_and_submit(bio, nvmeq,
20d0189b 604 length);
427e9708 605
eca18b23 606 sg = sg ? sg + 1 : iod->sg;
7988613b
KO
607 sg_set_page(sg, bvec.bv_page,
608 bvec.bv_len, bvec.bv_offset);
76830840
MW
609 nsegs++;
610 }
159b67d7 611
7988613b 612 if (split_len - length < bvec.bv_len)
20d0189b 613 return nvme_split_and_submit(bio, nvmeq, split_len);
7988613b 614 length += bvec.bv_len;
76830840 615 bvprv = bvec;
7988613b 616 first = 0;
b60503ba 617 }
eca18b23 618 iod->nents = nsegs;
76830840 619 sg_mark_end(sg);
427e9708 620 if (dma_map_sg(nvmeq->q_dmadev, iod->sg, iod->nents, dma_dir) == 0)
1ad2f893 621 return -ENOMEM;
427e9708 622
4f024f37 623 BUG_ON(length != bio->bi_iter.bi_size);
1ad2f893 624 return length;
b60503ba
MW
625}
626
0e5e4f0e
KB
627static int nvme_submit_discard(struct nvme_queue *nvmeq, struct nvme_ns *ns,
628 struct bio *bio, struct nvme_iod *iod, int cmdid)
629{
edd10d33
KB
630 struct nvme_dsm_range *range =
631 (struct nvme_dsm_range *)iod_list(iod)[0];
0e5e4f0e
KB
632 struct nvme_command *cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail];
633
0e5e4f0e 634 range->cattr = cpu_to_le32(0);
4f024f37
KO
635 range->nlb = cpu_to_le32(bio->bi_iter.bi_size >> ns->lba_shift);
636 range->slba = cpu_to_le64(nvme_block_nr(ns, bio->bi_iter.bi_sector));
0e5e4f0e
KB
637
638 memset(cmnd, 0, sizeof(*cmnd));
639 cmnd->dsm.opcode = nvme_cmd_dsm;
640 cmnd->dsm.command_id = cmdid;
641 cmnd->dsm.nsid = cpu_to_le32(ns->ns_id);
642 cmnd->dsm.prp1 = cpu_to_le64(iod->first_dma);
643 cmnd->dsm.nr = 0;
644 cmnd->dsm.attributes = cpu_to_le32(NVME_DSMGMT_AD);
645
646 if (++nvmeq->sq_tail == nvmeq->q_depth)
647 nvmeq->sq_tail = 0;
648 writel(nvmeq->sq_tail, nvmeq->q_db);
649
650 return 0;
651}
652
00df5cb4
MW
653static int nvme_submit_flush(struct nvme_queue *nvmeq, struct nvme_ns *ns,
654 int cmdid)
655{
656 struct nvme_command *cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail];
657
658 memset(cmnd, 0, sizeof(*cmnd));
659 cmnd->common.opcode = nvme_cmd_flush;
660 cmnd->common.command_id = cmdid;
661 cmnd->common.nsid = cpu_to_le32(ns->ns_id);
662
663 if (++nvmeq->sq_tail == nvmeq->q_depth)
664 nvmeq->sq_tail = 0;
665 writel(nvmeq->sq_tail, nvmeq->q_db);
666
667 return 0;
668}
669
edd10d33 670static int nvme_submit_iod(struct nvme_queue *nvmeq, struct nvme_iod *iod)
b60503ba 671{
edd10d33
KB
672 struct bio *bio = iod->private;
673 struct nvme_ns *ns = bio->bi_bdev->bd_disk->private_data;
ff22b54f 674 struct nvme_command *cmnd;
edd10d33 675 int cmdid;
b60503ba
MW
676 u16 control;
677 u32 dsmgmt;
00df5cb4 678
ff976d72 679 cmdid = alloc_cmdid(nvmeq, iod, bio_completion, NVME_IO_TIMEOUT);
b60503ba 680 if (unlikely(cmdid < 0))
edd10d33 681 return cmdid;
b60503ba 682
edd10d33
KB
683 if (bio->bi_rw & REQ_DISCARD)
684 return nvme_submit_discard(nvmeq, ns, bio, iod, cmdid);
53562be7 685 if (bio->bi_rw & REQ_FLUSH)
00df5cb4
MW
686 return nvme_submit_flush(nvmeq, ns, cmdid);
687
b60503ba
MW
688 control = 0;
689 if (bio->bi_rw & REQ_FUA)
690 control |= NVME_RW_FUA;
691 if (bio->bi_rw & (REQ_FAILFAST_DEV | REQ_RAHEAD))
692 control |= NVME_RW_LR;
693
694 dsmgmt = 0;
695 if (bio->bi_rw & REQ_RAHEAD)
696 dsmgmt |= NVME_RW_DSM_FREQ_PREFETCH;
697
ff22b54f 698 cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail];
b8deb62c 699 memset(cmnd, 0, sizeof(*cmnd));
b60503ba 700
edd10d33 701 cmnd->rw.opcode = bio_data_dir(bio) ? nvme_cmd_write : nvme_cmd_read;
ff22b54f
MW
702 cmnd->rw.command_id = cmdid;
703 cmnd->rw.nsid = cpu_to_le32(ns->ns_id);
edd10d33
KB
704 cmnd->rw.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
705 cmnd->rw.prp2 = cpu_to_le64(iod->first_dma);
4f024f37 706 cmnd->rw.slba = cpu_to_le64(nvme_block_nr(ns, bio->bi_iter.bi_sector));
edd10d33
KB
707 cmnd->rw.length =
708 cpu_to_le16((bio->bi_iter.bi_size >> ns->lba_shift) - 1);
ff22b54f
MW
709 cmnd->rw.control = cpu_to_le16(control);
710 cmnd->rw.dsmgmt = cpu_to_le32(dsmgmt);
b60503ba 711
b60503ba
MW
712 if (++nvmeq->sq_tail == nvmeq->q_depth)
713 nvmeq->sq_tail = 0;
7547881d 714 writel(nvmeq->sq_tail, nvmeq->q_db);
b60503ba 715
1974b1ae 716 return 0;
edd10d33
KB
717}
718
53562be7
KB
719static int nvme_split_flush_data(struct nvme_queue *nvmeq, struct bio *bio)
720{
721 struct bio *split = bio_clone(bio, GFP_ATOMIC);
722 if (!split)
723 return -ENOMEM;
724
725 split->bi_iter.bi_size = 0;
726 split->bi_phys_segments = 0;
727 bio->bi_rw &= ~REQ_FLUSH;
728 bio_chain(split, bio);
729
730 if (!waitqueue_active(&nvmeq->sq_full))
731 add_wait_queue(&nvmeq->sq_full, &nvmeq->sq_cong_wait);
732 bio_list_add(&nvmeq->sq_cong, split);
733 bio_list_add(&nvmeq->sq_cong, bio);
734 wake_up_process(nvme_thread);
735
736 return 0;
737}
738
edd10d33
KB
739/*
740 * Called with local interrupts disabled and the q_lock held. May not sleep.
741 */
742static int nvme_submit_bio_queue(struct nvme_queue *nvmeq, struct nvme_ns *ns,
743 struct bio *bio)
744{
745 struct nvme_iod *iod;
746 int psegs = bio_phys_segments(ns->queue, bio);
747 int result;
748
53562be7
KB
749 if ((bio->bi_rw & REQ_FLUSH) && psegs)
750 return nvme_split_flush_data(nvmeq, bio);
edd10d33
KB
751
752 iod = nvme_alloc_iod(psegs, bio->bi_iter.bi_size, GFP_ATOMIC);
753 if (!iod)
754 return -ENOMEM;
755
756 iod->private = bio;
757 if (bio->bi_rw & REQ_DISCARD) {
758 void *range;
759 /*
760 * We reuse the small pool to allocate the 16-byte range here
761 * as it is not worth having a special pool for these or
762 * additional cases to handle freeing the iod.
763 */
764 range = dma_pool_alloc(nvmeq->dev->prp_small_pool,
765 GFP_ATOMIC,
766 &iod->first_dma);
767 if (!range) {
768 result = -ENOMEM;
769 goto free_iod;
770 }
771 iod_list(iod)[0] = (__le64 *)range;
772 iod->npages = 0;
773 } else if (psegs) {
774 result = nvme_map_bio(nvmeq, iod, bio,
775 bio_data_dir(bio) ? DMA_TO_DEVICE : DMA_FROM_DEVICE,
776 psegs);
777 if (result <= 0)
778 goto free_iod;
779 if (nvme_setup_prps(nvmeq->dev, iod, result, GFP_ATOMIC) !=
780 result) {
781 result = -ENOMEM;
782 goto free_iod;
783 }
784 nvme_start_io_acct(bio);
785 }
786 if (unlikely(nvme_submit_iod(nvmeq, iod))) {
787 if (!waitqueue_active(&nvmeq->sq_full))
788 add_wait_queue(&nvmeq->sq_full, &nvmeq->sq_cong_wait);
789 list_add_tail(&iod->node, &nvmeq->iod_bio);
790 }
791 return 0;
1974b1ae 792
eca18b23
MW
793 free_iod:
794 nvme_free_iod(nvmeq->dev, iod);
eeee3226 795 return result;
b60503ba
MW
796}
797
e9539f47 798static int nvme_process_cq(struct nvme_queue *nvmeq)
b60503ba 799{
82123460 800 u16 head, phase;
b60503ba 801
b60503ba 802 head = nvmeq->cq_head;
82123460 803 phase = nvmeq->cq_phase;
b60503ba
MW
804
805 for (;;) {
c2f5b650
MW
806 void *ctx;
807 nvme_completion_fn fn;
b60503ba 808 struct nvme_completion cqe = nvmeq->cqes[head];
82123460 809 if ((le16_to_cpu(cqe.status) & 1) != phase)
b60503ba
MW
810 break;
811 nvmeq->sq_head = le16_to_cpu(cqe.sq_head);
812 if (++head == nvmeq->q_depth) {
813 head = 0;
82123460 814 phase = !phase;
b60503ba
MW
815 }
816
c2f5b650 817 ctx = free_cmdid(nvmeq, cqe.command_id, &fn);
edd10d33 818 fn(nvmeq, ctx, &cqe);
b60503ba
MW
819 }
820
821 /* If the controller ignores the cq head doorbell and continuously
822 * writes to the queue, it is theoretically possible to wrap around
823 * the queue twice and mistakenly return IRQ_NONE. Linux only
824 * requires that 0.1% of your interrupts are handled, so this isn't
825 * a big problem.
826 */
82123460 827 if (head == nvmeq->cq_head && phase == nvmeq->cq_phase)
e9539f47 828 return 0;
b60503ba 829
b80d5ccc 830 writel(head, nvmeq->q_db + nvmeq->dev->db_stride);
b60503ba 831 nvmeq->cq_head = head;
82123460 832 nvmeq->cq_phase = phase;
b60503ba 833
e9539f47
MW
834 nvmeq->cqe_seen = 1;
835 return 1;
b60503ba
MW
836}
837
7d822457
MW
838static void nvme_make_request(struct request_queue *q, struct bio *bio)
839{
840 struct nvme_ns *ns = q->queuedata;
841 struct nvme_queue *nvmeq = get_nvmeq(ns->dev);
842 int result = -EBUSY;
843
cd638946 844 if (!nvmeq) {
cd638946
KB
845 bio_endio(bio, -EIO);
846 return;
847 }
848
7d822457 849 spin_lock_irq(&nvmeq->q_lock);
22404274 850 if (!nvmeq->q_suspended && bio_list_empty(&nvmeq->sq_cong))
7d822457
MW
851 result = nvme_submit_bio_queue(nvmeq, ns, bio);
852 if (unlikely(result)) {
edd10d33 853 if (!waitqueue_active(&nvmeq->sq_full))
7d822457
MW
854 add_wait_queue(&nvmeq->sq_full, &nvmeq->sq_cong_wait);
855 bio_list_add(&nvmeq->sq_cong, bio);
856 }
857
858 nvme_process_cq(nvmeq);
859 spin_unlock_irq(&nvmeq->q_lock);
860 put_nvmeq(nvmeq);
861}
862
b60503ba 863static irqreturn_t nvme_irq(int irq, void *data)
58ffacb5
MW
864{
865 irqreturn_t result;
866 struct nvme_queue *nvmeq = data;
867 spin_lock(&nvmeq->q_lock);
e9539f47
MW
868 nvme_process_cq(nvmeq);
869 result = nvmeq->cqe_seen ? IRQ_HANDLED : IRQ_NONE;
870 nvmeq->cqe_seen = 0;
58ffacb5
MW
871 spin_unlock(&nvmeq->q_lock);
872 return result;
873}
874
875static irqreturn_t nvme_irq_check(int irq, void *data)
876{
877 struct nvme_queue *nvmeq = data;
878 struct nvme_completion cqe = nvmeq->cqes[nvmeq->cq_head];
879 if ((le16_to_cpu(cqe.status) & 1) != nvmeq->cq_phase)
880 return IRQ_NONE;
881 return IRQ_WAKE_THREAD;
882}
883
3c0cf138
MW
884static void nvme_abort_command(struct nvme_queue *nvmeq, int cmdid)
885{
886 spin_lock_irq(&nvmeq->q_lock);
c2f5b650 887 cancel_cmdid(nvmeq, cmdid, NULL);
3c0cf138
MW
888 spin_unlock_irq(&nvmeq->q_lock);
889}
890
c2f5b650
MW
891struct sync_cmd_info {
892 struct task_struct *task;
893 u32 result;
894 int status;
895};
896
edd10d33 897static void sync_completion(struct nvme_queue *nvmeq, void *ctx,
c2f5b650
MW
898 struct nvme_completion *cqe)
899{
900 struct sync_cmd_info *cmdinfo = ctx;
901 cmdinfo->result = le32_to_cpup(&cqe->result);
902 cmdinfo->status = le16_to_cpup(&cqe->status) >> 1;
903 wake_up_process(cmdinfo->task);
904}
905
b60503ba
MW
906/*
907 * Returns 0 on success. If the result is negative, it's a Linux error code;
908 * if the result is positive, it's an NVM Express status code
909 */
4f5099af
KB
910static int nvme_submit_sync_cmd(struct nvme_dev *dev, int q_idx,
911 struct nvme_command *cmd,
5d0f6131 912 u32 *result, unsigned timeout)
b60503ba 913{
4f5099af 914 int cmdid, ret;
b60503ba 915 struct sync_cmd_info cmdinfo;
4f5099af
KB
916 struct nvme_queue *nvmeq;
917
918 nvmeq = lock_nvmeq(dev, q_idx);
a51afb54 919 if (!nvmeq)
4f5099af 920 return -ENODEV;
b60503ba
MW
921
922 cmdinfo.task = current;
923 cmdinfo.status = -EINTR;
924
4f5099af
KB
925 cmdid = alloc_cmdid(nvmeq, &cmdinfo, sync_completion, timeout);
926 if (cmdid < 0) {
927 unlock_nvmeq(nvmeq);
b60503ba 928 return cmdid;
4f5099af 929 }
b60503ba
MW
930 cmd->common.command_id = cmdid;
931
3c0cf138 932 set_current_state(TASK_KILLABLE);
4f5099af
KB
933 ret = nvme_submit_cmd(nvmeq, cmd);
934 if (ret) {
935 free_cmdid(nvmeq, cmdid, NULL);
936 unlock_nvmeq(nvmeq);
937 set_current_state(TASK_RUNNING);
938 return ret;
939 }
940 unlock_nvmeq(nvmeq);
78f8d257 941 schedule_timeout(timeout);
b60503ba 942
3c0cf138 943 if (cmdinfo.status == -EINTR) {
4f5099af 944 nvmeq = lock_nvmeq(dev, q_idx);
a51afb54 945 if (nvmeq) {
4f5099af 946 nvme_abort_command(nvmeq, cmdid);
a51afb54
KB
947 unlock_nvmeq(nvmeq);
948 }
3c0cf138
MW
949 return -EINTR;
950 }
951
b60503ba
MW
952 if (result)
953 *result = cmdinfo.result;
954
955 return cmdinfo.status;
956}
957
4d115420
KB
958static int nvme_submit_async_cmd(struct nvme_queue *nvmeq,
959 struct nvme_command *cmd,
960 struct async_cmd_info *cmdinfo, unsigned timeout)
961{
962 int cmdid;
963
964 cmdid = alloc_cmdid_killable(nvmeq, cmdinfo, async_completion, timeout);
965 if (cmdid < 0)
966 return cmdid;
967 cmdinfo->status = -EINTR;
968 cmd->common.command_id = cmdid;
4f5099af 969 return nvme_submit_cmd(nvmeq, cmd);
4d115420
KB
970}
971
5d0f6131 972int nvme_submit_admin_cmd(struct nvme_dev *dev, struct nvme_command *cmd,
b60503ba
MW
973 u32 *result)
974{
4f5099af
KB
975 return nvme_submit_sync_cmd(dev, 0, cmd, result, ADMIN_TIMEOUT);
976}
977
978int nvme_submit_io_cmd(struct nvme_dev *dev, struct nvme_command *cmd,
979 u32 *result)
980{
981 return nvme_submit_sync_cmd(dev, smp_processor_id() + 1, cmd, result,
982 NVME_IO_TIMEOUT);
b60503ba
MW
983}
984
4d115420
KB
985static int nvme_submit_admin_cmd_async(struct nvme_dev *dev,
986 struct nvme_command *cmd, struct async_cmd_info *cmdinfo)
987{
5a92e700 988 return nvme_submit_async_cmd(raw_nvmeq(dev, 0), cmd, cmdinfo,
4d115420
KB
989 ADMIN_TIMEOUT);
990}
991
b60503ba
MW
992static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
993{
994 int status;
995 struct nvme_command c;
996
997 memset(&c, 0, sizeof(c));
998 c.delete_queue.opcode = opcode;
999 c.delete_queue.qid = cpu_to_le16(id);
1000
1001 status = nvme_submit_admin_cmd(dev, &c, NULL);
1002 if (status)
1003 return -EIO;
1004 return 0;
1005}
1006
1007static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
1008 struct nvme_queue *nvmeq)
1009{
1010 int status;
1011 struct nvme_command c;
1012 int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED;
1013
1014 memset(&c, 0, sizeof(c));
1015 c.create_cq.opcode = nvme_admin_create_cq;
1016 c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
1017 c.create_cq.cqid = cpu_to_le16(qid);
1018 c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1019 c.create_cq.cq_flags = cpu_to_le16(flags);
1020 c.create_cq.irq_vector = cpu_to_le16(nvmeq->cq_vector);
1021
1022 status = nvme_submit_admin_cmd(dev, &c, NULL);
1023 if (status)
1024 return -EIO;
1025 return 0;
1026}
1027
1028static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
1029 struct nvme_queue *nvmeq)
1030{
1031 int status;
1032 struct nvme_command c;
1033 int flags = NVME_QUEUE_PHYS_CONTIG | NVME_SQ_PRIO_MEDIUM;
1034
1035 memset(&c, 0, sizeof(c));
1036 c.create_sq.opcode = nvme_admin_create_sq;
1037 c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
1038 c.create_sq.sqid = cpu_to_le16(qid);
1039 c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
1040 c.create_sq.sq_flags = cpu_to_le16(flags);
1041 c.create_sq.cqid = cpu_to_le16(qid);
1042
1043 status = nvme_submit_admin_cmd(dev, &c, NULL);
1044 if (status)
1045 return -EIO;
1046 return 0;
1047}
1048
1049static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
1050{
1051 return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
1052}
1053
1054static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
1055{
1056 return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
1057}
1058
5d0f6131 1059int nvme_identify(struct nvme_dev *dev, unsigned nsid, unsigned cns,
bc5fc7e4
MW
1060 dma_addr_t dma_addr)
1061{
1062 struct nvme_command c;
1063
1064 memset(&c, 0, sizeof(c));
1065 c.identify.opcode = nvme_admin_identify;
1066 c.identify.nsid = cpu_to_le32(nsid);
1067 c.identify.prp1 = cpu_to_le64(dma_addr);
1068 c.identify.cns = cpu_to_le32(cns);
1069
1070 return nvme_submit_admin_cmd(dev, &c, NULL);
1071}
1072
5d0f6131 1073int nvme_get_features(struct nvme_dev *dev, unsigned fid, unsigned nsid,
08df1e05 1074 dma_addr_t dma_addr, u32 *result)
bc5fc7e4
MW
1075{
1076 struct nvme_command c;
1077
1078 memset(&c, 0, sizeof(c));
1079 c.features.opcode = nvme_admin_get_features;
a42cecce 1080 c.features.nsid = cpu_to_le32(nsid);
bc5fc7e4
MW
1081 c.features.prp1 = cpu_to_le64(dma_addr);
1082 c.features.fid = cpu_to_le32(fid);
bc5fc7e4 1083
08df1e05 1084 return nvme_submit_admin_cmd(dev, &c, result);
df348139
MW
1085}
1086
5d0f6131
VV
1087int nvme_set_features(struct nvme_dev *dev, unsigned fid, unsigned dword11,
1088 dma_addr_t dma_addr, u32 *result)
df348139
MW
1089{
1090 struct nvme_command c;
1091
1092 memset(&c, 0, sizeof(c));
1093 c.features.opcode = nvme_admin_set_features;
1094 c.features.prp1 = cpu_to_le64(dma_addr);
1095 c.features.fid = cpu_to_le32(fid);
1096 c.features.dword11 = cpu_to_le32(dword11);
1097
bc5fc7e4
MW
1098 return nvme_submit_admin_cmd(dev, &c, result);
1099}
1100
c30341dc
KB
1101/**
1102 * nvme_abort_cmd - Attempt aborting a command
1103 * @cmdid: Command id of a timed out IO
1104 * @queue: The queue with timed out IO
1105 *
1106 * Schedule controller reset if the command was already aborted once before and
1107 * still hasn't been returned to the driver, or if this is the admin queue.
1108 */
1109static void nvme_abort_cmd(int cmdid, struct nvme_queue *nvmeq)
1110{
1111 int a_cmdid;
1112 struct nvme_command cmd;
1113 struct nvme_dev *dev = nvmeq->dev;
1114 struct nvme_cmd_info *info = nvme_cmd_info(nvmeq);
5a92e700 1115 struct nvme_queue *adminq;
c30341dc
KB
1116
1117 if (!nvmeq->qid || info[cmdid].aborted) {
1118 if (work_busy(&dev->reset_work))
1119 return;
1120 list_del_init(&dev->node);
1121 dev_warn(&dev->pci_dev->dev,
1122 "I/O %d QID %d timeout, reset controller\n", cmdid,
1123 nvmeq->qid);
9ca97374 1124 dev->reset_workfn = nvme_reset_failed_dev;
c30341dc
KB
1125 queue_work(nvme_workq, &dev->reset_work);
1126 return;
1127 }
1128
1129 if (!dev->abort_limit)
1130 return;
1131
5a92e700
KB
1132 adminq = rcu_dereference(dev->queues[0]);
1133 a_cmdid = alloc_cmdid(adminq, CMD_CTX_ABORT, special_completion,
c30341dc
KB
1134 ADMIN_TIMEOUT);
1135 if (a_cmdid < 0)
1136 return;
1137
1138 memset(&cmd, 0, sizeof(cmd));
1139 cmd.abort.opcode = nvme_admin_abort_cmd;
1140 cmd.abort.cid = cmdid;
1141 cmd.abort.sqid = cpu_to_le16(nvmeq->qid);
1142 cmd.abort.command_id = a_cmdid;
1143
1144 --dev->abort_limit;
1145 info[cmdid].aborted = 1;
1146 info[cmdid].timeout = jiffies + ADMIN_TIMEOUT;
1147
1148 dev_warn(nvmeq->q_dmadev, "Aborting I/O %d QID %d\n", cmdid,
1149 nvmeq->qid);
5a92e700 1150 nvme_submit_cmd(adminq, &cmd);
c30341dc
KB
1151}
1152
a09115b2
MW
1153/**
1154 * nvme_cancel_ios - Cancel outstanding I/Os
1155 * @queue: The queue to cancel I/Os on
1156 * @timeout: True to only cancel I/Os which have timed out
1157 */
1158static void nvme_cancel_ios(struct nvme_queue *nvmeq, bool timeout)
1159{
1160 int depth = nvmeq->q_depth - 1;
1161 struct nvme_cmd_info *info = nvme_cmd_info(nvmeq);
1162 unsigned long now = jiffies;
1163 int cmdid;
1164
1165 for_each_set_bit(cmdid, nvmeq->cmdid_data, depth) {
1166 void *ctx;
1167 nvme_completion_fn fn;
1168 static struct nvme_completion cqe = {
af2d9ca7 1169 .status = cpu_to_le16(NVME_SC_ABORT_REQ << 1),
a09115b2
MW
1170 };
1171
1172 if (timeout && !time_after(now, info[cmdid].timeout))
1173 continue;
053ab702
KB
1174 if (info[cmdid].ctx == CMD_CTX_CANCELLED)
1175 continue;
6fccf938
KB
1176 if (timeout && info[cmdid].ctx == CMD_CTX_ASYNC)
1177 continue;
c30341dc
KB
1178 if (timeout && nvmeq->dev->initialized) {
1179 nvme_abort_cmd(cmdid, nvmeq);
1180 continue;
1181 }
1182 dev_warn(nvmeq->q_dmadev, "Cancelling I/O %d QID %d\n", cmdid,
1183 nvmeq->qid);
a09115b2 1184 ctx = cancel_cmdid(nvmeq, cmdid, &fn);
edd10d33 1185 fn(nvmeq, ctx, &cqe);
a09115b2
MW
1186 }
1187}
1188
5a92e700 1189static void nvme_free_queue(struct rcu_head *r)
9e866774 1190{
5a92e700
KB
1191 struct nvme_queue *nvmeq = container_of(r, struct nvme_queue, r_head);
1192
22404274
KB
1193 spin_lock_irq(&nvmeq->q_lock);
1194 while (bio_list_peek(&nvmeq->sq_cong)) {
1195 struct bio *bio = bio_list_pop(&nvmeq->sq_cong);
1196 bio_endio(bio, -EIO);
1197 }
edd10d33
KB
1198 while (!list_empty(&nvmeq->iod_bio)) {
1199 static struct nvme_completion cqe = {
1200 .status = cpu_to_le16(
1201 (NVME_SC_ABORT_REQ | NVME_SC_DNR) << 1),
1202 };
1203 struct nvme_iod *iod = list_first_entry(&nvmeq->iod_bio,
1204 struct nvme_iod,
1205 node);
1206 list_del(&iod->node);
1207 bio_completion(nvmeq, iod, &cqe);
1208 }
22404274
KB
1209 spin_unlock_irq(&nvmeq->q_lock);
1210
9e866774
MW
1211 dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth),
1212 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
1213 dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth),
1214 nvmeq->sq_cmds, nvmeq->sq_dma_addr);
42f61420
KB
1215 if (nvmeq->qid)
1216 free_cpumask_var(nvmeq->cpu_mask);
9e866774
MW
1217 kfree(nvmeq);
1218}
1219
a1a5ef99 1220static void nvme_free_queues(struct nvme_dev *dev, int lowest)
22404274
KB
1221{
1222 int i;
1223
a1a5ef99 1224 for (i = dev->queue_count - 1; i >= lowest; i--) {
5a92e700
KB
1225 struct nvme_queue *nvmeq = raw_nvmeq(dev, i);
1226 rcu_assign_pointer(dev->queues[i], NULL);
1227 call_rcu(&nvmeq->r_head, nvme_free_queue);
22404274 1228 dev->queue_count--;
22404274
KB
1229 }
1230}
1231
4d115420
KB
1232/**
1233 * nvme_suspend_queue - put queue into suspended state
1234 * @nvmeq - queue to suspend
1235 *
1236 * Returns 1 if already suspended, 0 otherwise.
1237 */
1238static int nvme_suspend_queue(struct nvme_queue *nvmeq)
b60503ba 1239{
4d115420 1240 int vector = nvmeq->dev->entry[nvmeq->cq_vector].vector;
b60503ba 1241
a09115b2 1242 spin_lock_irq(&nvmeq->q_lock);
22404274
KB
1243 if (nvmeq->q_suspended) {
1244 spin_unlock_irq(&nvmeq->q_lock);
4d115420 1245 return 1;
3295874b 1246 }
22404274 1247 nvmeq->q_suspended = 1;
42f61420 1248 nvmeq->dev->online_queues--;
a09115b2
MW
1249 spin_unlock_irq(&nvmeq->q_lock);
1250
aba2080f
MW
1251 irq_set_affinity_hint(vector, NULL);
1252 free_irq(vector, nvmeq);
b60503ba 1253
4d115420
KB
1254 return 0;
1255}
b60503ba 1256
4d115420
KB
1257static void nvme_clear_queue(struct nvme_queue *nvmeq)
1258{
22404274
KB
1259 spin_lock_irq(&nvmeq->q_lock);
1260 nvme_process_cq(nvmeq);
1261 nvme_cancel_ios(nvmeq, false);
1262 spin_unlock_irq(&nvmeq->q_lock);
b60503ba
MW
1263}
1264
4d115420
KB
1265static void nvme_disable_queue(struct nvme_dev *dev, int qid)
1266{
5a92e700 1267 struct nvme_queue *nvmeq = raw_nvmeq(dev, qid);
4d115420
KB
1268
1269 if (!nvmeq)
1270 return;
1271 if (nvme_suspend_queue(nvmeq))
1272 return;
1273
0e53d180
KB
1274 /* Don't tell the adapter to delete the admin queue.
1275 * Don't tell a removed adapter to delete IO queues. */
1276 if (qid && readl(&dev->bar->csts) != -1) {
b60503ba
MW
1277 adapter_delete_sq(dev, qid);
1278 adapter_delete_cq(dev, qid);
1279 }
4d115420 1280 nvme_clear_queue(nvmeq);
b60503ba
MW
1281}
1282
1283static struct nvme_queue *nvme_alloc_queue(struct nvme_dev *dev, int qid,
1284 int depth, int vector)
1285{
1286 struct device *dmadev = &dev->pci_dev->dev;
22404274 1287 unsigned extra = nvme_queue_extra(depth);
b60503ba
MW
1288 struct nvme_queue *nvmeq = kzalloc(sizeof(*nvmeq) + extra, GFP_KERNEL);
1289 if (!nvmeq)
1290 return NULL;
1291
4d51abf9
JP
1292 nvmeq->cqes = dma_zalloc_coherent(dmadev, CQ_SIZE(depth),
1293 &nvmeq->cq_dma_addr, GFP_KERNEL);
b60503ba
MW
1294 if (!nvmeq->cqes)
1295 goto free_nvmeq;
b60503ba
MW
1296
1297 nvmeq->sq_cmds = dma_alloc_coherent(dmadev, SQ_SIZE(depth),
1298 &nvmeq->sq_dma_addr, GFP_KERNEL);
1299 if (!nvmeq->sq_cmds)
1300 goto free_cqdma;
1301
42f61420
KB
1302 if (qid && !zalloc_cpumask_var(&nvmeq->cpu_mask, GFP_KERNEL))
1303 goto free_sqdma;
1304
b60503ba 1305 nvmeq->q_dmadev = dmadev;
091b6092 1306 nvmeq->dev = dev;
3193f07b
MW
1307 snprintf(nvmeq->irqname, sizeof(nvmeq->irqname), "nvme%dq%d",
1308 dev->instance, qid);
b60503ba
MW
1309 spin_lock_init(&nvmeq->q_lock);
1310 nvmeq->cq_head = 0;
82123460 1311 nvmeq->cq_phase = 1;
b60503ba 1312 init_waitqueue_head(&nvmeq->sq_full);
1fa6aead 1313 init_waitqueue_entry(&nvmeq->sq_cong_wait, nvme_thread);
b60503ba 1314 bio_list_init(&nvmeq->sq_cong);
edd10d33 1315 INIT_LIST_HEAD(&nvmeq->iod_bio);
b80d5ccc 1316 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
b60503ba
MW
1317 nvmeq->q_depth = depth;
1318 nvmeq->cq_vector = vector;
c30341dc 1319 nvmeq->qid = qid;
22404274
KB
1320 nvmeq->q_suspended = 1;
1321 dev->queue_count++;
5a92e700 1322 rcu_assign_pointer(dev->queues[qid], nvmeq);
b60503ba
MW
1323
1324 return nvmeq;
1325
42f61420
KB
1326 free_sqdma:
1327 dma_free_coherent(dmadev, SQ_SIZE(depth), (void *)nvmeq->sq_cmds,
1328 nvmeq->sq_dma_addr);
b60503ba 1329 free_cqdma:
68b8eca5 1330 dma_free_coherent(dmadev, CQ_SIZE(depth), (void *)nvmeq->cqes,
b60503ba
MW
1331 nvmeq->cq_dma_addr);
1332 free_nvmeq:
1333 kfree(nvmeq);
1334 return NULL;
1335}
1336
3001082c
MW
1337static int queue_request_irq(struct nvme_dev *dev, struct nvme_queue *nvmeq,
1338 const char *name)
1339{
58ffacb5
MW
1340 if (use_threaded_interrupts)
1341 return request_threaded_irq(dev->entry[nvmeq->cq_vector].vector,
481e5bad 1342 nvme_irq_check, nvme_irq, IRQF_SHARED,
58ffacb5 1343 name, nvmeq);
3001082c 1344 return request_irq(dev->entry[nvmeq->cq_vector].vector, nvme_irq,
481e5bad 1345 IRQF_SHARED, name, nvmeq);
3001082c
MW
1346}
1347
22404274 1348static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid)
b60503ba 1349{
22404274
KB
1350 struct nvme_dev *dev = nvmeq->dev;
1351 unsigned extra = nvme_queue_extra(nvmeq->q_depth);
b60503ba 1352
22404274
KB
1353 nvmeq->sq_tail = 0;
1354 nvmeq->cq_head = 0;
1355 nvmeq->cq_phase = 1;
b80d5ccc 1356 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
22404274
KB
1357 memset(nvmeq->cmdid_data, 0, extra);
1358 memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq->q_depth));
1359 nvme_cancel_ios(nvmeq, false);
1360 nvmeq->q_suspended = 0;
42f61420 1361 dev->online_queues++;
22404274
KB
1362}
1363
1364static int nvme_create_queue(struct nvme_queue *nvmeq, int qid)
1365{
1366 struct nvme_dev *dev = nvmeq->dev;
1367 int result;
3f85d50b 1368
b60503ba
MW
1369 result = adapter_alloc_cq(dev, qid, nvmeq);
1370 if (result < 0)
22404274 1371 return result;
b60503ba
MW
1372
1373 result = adapter_alloc_sq(dev, qid, nvmeq);
1374 if (result < 0)
1375 goto release_cq;
1376
3193f07b 1377 result = queue_request_irq(dev, nvmeq, nvmeq->irqname);
b60503ba
MW
1378 if (result < 0)
1379 goto release_sq;
1380
0a8d44cb 1381 spin_lock_irq(&nvmeq->q_lock);
22404274 1382 nvme_init_queue(nvmeq, qid);
0a8d44cb 1383 spin_unlock_irq(&nvmeq->q_lock);
22404274
KB
1384
1385 return result;
b60503ba
MW
1386
1387 release_sq:
1388 adapter_delete_sq(dev, qid);
1389 release_cq:
1390 adapter_delete_cq(dev, qid);
22404274 1391 return result;
b60503ba
MW
1392}
1393
ba47e386
MW
1394static int nvme_wait_ready(struct nvme_dev *dev, u64 cap, bool enabled)
1395{
1396 unsigned long timeout;
1397 u32 bit = enabled ? NVME_CSTS_RDY : 0;
1398
1399 timeout = ((NVME_CAP_TIMEOUT(cap) + 1) * HZ / 2) + jiffies;
1400
1401 while ((readl(&dev->bar->csts) & NVME_CSTS_RDY) != bit) {
1402 msleep(100);
1403 if (fatal_signal_pending(current))
1404 return -EINTR;
1405 if (time_after(jiffies, timeout)) {
1406 dev_err(&dev->pci_dev->dev,
27e8166c
MW
1407 "Device not ready; aborting %s\n", enabled ?
1408 "initialisation" : "reset");
ba47e386
MW
1409 return -ENODEV;
1410 }
1411 }
1412
1413 return 0;
1414}
1415
1416/*
1417 * If the device has been passed off to us in an enabled state, just clear
1418 * the enabled bit. The spec says we should set the 'shutdown notification
1419 * bits', but doing so may cause the device to complete commands to the
1420 * admin queue ... and we don't know what memory that might be pointing at!
1421 */
1422static int nvme_disable_ctrl(struct nvme_dev *dev, u64 cap)
1423{
44af146a
MW
1424 u32 cc = readl(&dev->bar->cc);
1425
1426 if (cc & NVME_CC_ENABLE)
1427 writel(cc & ~NVME_CC_ENABLE, &dev->bar->cc);
ba47e386
MW
1428 return nvme_wait_ready(dev, cap, false);
1429}
1430
1431static int nvme_enable_ctrl(struct nvme_dev *dev, u64 cap)
1432{
1433 return nvme_wait_ready(dev, cap, true);
1434}
1435
1894d8f1
KB
1436static int nvme_shutdown_ctrl(struct nvme_dev *dev)
1437{
1438 unsigned long timeout;
1439 u32 cc;
1440
1441 cc = (readl(&dev->bar->cc) & ~NVME_CC_SHN_MASK) | NVME_CC_SHN_NORMAL;
1442 writel(cc, &dev->bar->cc);
1443
1444 timeout = 2 * HZ + jiffies;
1445 while ((readl(&dev->bar->csts) & NVME_CSTS_SHST_MASK) !=
1446 NVME_CSTS_SHST_CMPLT) {
1447 msleep(100);
1448 if (fatal_signal_pending(current))
1449 return -EINTR;
1450 if (time_after(jiffies, timeout)) {
1451 dev_err(&dev->pci_dev->dev,
1452 "Device shutdown incomplete; abort shutdown\n");
1453 return -ENODEV;
1454 }
1455 }
1456
1457 return 0;
1458}
1459
8d85fce7 1460static int nvme_configure_admin_queue(struct nvme_dev *dev)
b60503ba 1461{
ba47e386 1462 int result;
b60503ba 1463 u32 aqa;
ba47e386 1464 u64 cap = readq(&dev->bar->cap);
b60503ba
MW
1465 struct nvme_queue *nvmeq;
1466
ba47e386
MW
1467 result = nvme_disable_ctrl(dev, cap);
1468 if (result < 0)
1469 return result;
b60503ba 1470
5a92e700 1471 nvmeq = raw_nvmeq(dev, 0);
cd638946
KB
1472 if (!nvmeq) {
1473 nvmeq = nvme_alloc_queue(dev, 0, 64, 0);
1474 if (!nvmeq)
1475 return -ENOMEM;
cd638946 1476 }
b60503ba
MW
1477
1478 aqa = nvmeq->q_depth - 1;
1479 aqa |= aqa << 16;
1480
1481 dev->ctrl_config = NVME_CC_ENABLE | NVME_CC_CSS_NVM;
1482 dev->ctrl_config |= (PAGE_SHIFT - 12) << NVME_CC_MPS_SHIFT;
1483 dev->ctrl_config |= NVME_CC_ARB_RR | NVME_CC_SHN_NONE;
7f53f9d2 1484 dev->ctrl_config |= NVME_CC_IOSQES | NVME_CC_IOCQES;
b60503ba
MW
1485
1486 writel(aqa, &dev->bar->aqa);
1487 writeq(nvmeq->sq_dma_addr, &dev->bar->asq);
1488 writeq(nvmeq->cq_dma_addr, &dev->bar->acq);
1489 writel(dev->ctrl_config, &dev->bar->cc);
1490
ba47e386 1491 result = nvme_enable_ctrl(dev, cap);
025c557a 1492 if (result)
cd638946 1493 return result;
9e866774 1494
3193f07b 1495 result = queue_request_irq(dev, nvmeq, nvmeq->irqname);
025c557a 1496 if (result)
cd638946 1497 return result;
025c557a 1498
0a8d44cb 1499 spin_lock_irq(&nvmeq->q_lock);
22404274 1500 nvme_init_queue(nvmeq, 0);
0a8d44cb 1501 spin_unlock_irq(&nvmeq->q_lock);
b60503ba
MW
1502 return result;
1503}
1504
5d0f6131 1505struct nvme_iod *nvme_map_user_pages(struct nvme_dev *dev, int write,
eca18b23 1506 unsigned long addr, unsigned length)
b60503ba 1507{
36c14ed9 1508 int i, err, count, nents, offset;
7fc3cdab
MW
1509 struct scatterlist *sg;
1510 struct page **pages;
eca18b23 1511 struct nvme_iod *iod;
36c14ed9
MW
1512
1513 if (addr & 3)
eca18b23 1514 return ERR_PTR(-EINVAL);
5460fc03 1515 if (!length || length > INT_MAX - PAGE_SIZE)
eca18b23 1516 return ERR_PTR(-EINVAL);
7fc3cdab 1517
36c14ed9 1518 offset = offset_in_page(addr);
7fc3cdab
MW
1519 count = DIV_ROUND_UP(offset + length, PAGE_SIZE);
1520 pages = kcalloc(count, sizeof(*pages), GFP_KERNEL);
22fff826
DC
1521 if (!pages)
1522 return ERR_PTR(-ENOMEM);
36c14ed9
MW
1523
1524 err = get_user_pages_fast(addr, count, 1, pages);
1525 if (err < count) {
1526 count = err;
1527 err = -EFAULT;
1528 goto put_pages;
1529 }
7fc3cdab 1530
6808c5fb 1531 err = -ENOMEM;
eca18b23 1532 iod = nvme_alloc_iod(count, length, GFP_KERNEL);
6808c5fb
S
1533 if (!iod)
1534 goto put_pages;
1535
eca18b23 1536 sg = iod->sg;
36c14ed9 1537 sg_init_table(sg, count);
d0ba1e49
MW
1538 for (i = 0; i < count; i++) {
1539 sg_set_page(&sg[i], pages[i],
5460fc03
DC
1540 min_t(unsigned, length, PAGE_SIZE - offset),
1541 offset);
d0ba1e49
MW
1542 length -= (PAGE_SIZE - offset);
1543 offset = 0;
7fc3cdab 1544 }
fe304c43 1545 sg_mark_end(&sg[i - 1]);
1c2ad9fa 1546 iod->nents = count;
7fc3cdab 1547
7fc3cdab
MW
1548 nents = dma_map_sg(&dev->pci_dev->dev, sg, count,
1549 write ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
36c14ed9 1550 if (!nents)
eca18b23 1551 goto free_iod;
b60503ba 1552
7fc3cdab 1553 kfree(pages);
eca18b23 1554 return iod;
b60503ba 1555
eca18b23
MW
1556 free_iod:
1557 kfree(iod);
7fc3cdab
MW
1558 put_pages:
1559 for (i = 0; i < count; i++)
1560 put_page(pages[i]);
1561 kfree(pages);
eca18b23 1562 return ERR_PTR(err);
7fc3cdab 1563}
b60503ba 1564
5d0f6131 1565void nvme_unmap_user_pages(struct nvme_dev *dev, int write,
1c2ad9fa 1566 struct nvme_iod *iod)
7fc3cdab 1567{
1c2ad9fa 1568 int i;
b60503ba 1569
1c2ad9fa
MW
1570 dma_unmap_sg(&dev->pci_dev->dev, iod->sg, iod->nents,
1571 write ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
7fc3cdab 1572
1c2ad9fa
MW
1573 for (i = 0; i < iod->nents; i++)
1574 put_page(sg_page(&iod->sg[i]));
7fc3cdab 1575}
b60503ba 1576
a53295b6
MW
1577static int nvme_submit_io(struct nvme_ns *ns, struct nvme_user_io __user *uio)
1578{
1579 struct nvme_dev *dev = ns->dev;
a53295b6
MW
1580 struct nvme_user_io io;
1581 struct nvme_command c;
f410c680
KB
1582 unsigned length, meta_len;
1583 int status, i;
1584 struct nvme_iod *iod, *meta_iod = NULL;
1585 dma_addr_t meta_dma_addr;
1586 void *meta, *uninitialized_var(meta_mem);
a53295b6
MW
1587
1588 if (copy_from_user(&io, uio, sizeof(io)))
1589 return -EFAULT;
6c7d4945 1590 length = (io.nblocks + 1) << ns->lba_shift;
f410c680
KB
1591 meta_len = (io.nblocks + 1) * ns->ms;
1592
1593 if (meta_len && ((io.metadata & 3) || !io.metadata))
1594 return -EINVAL;
6c7d4945
MW
1595
1596 switch (io.opcode) {
1597 case nvme_cmd_write:
1598 case nvme_cmd_read:
6bbf1acd 1599 case nvme_cmd_compare:
eca18b23 1600 iod = nvme_map_user_pages(dev, io.opcode & 1, io.addr, length);
6413214c 1601 break;
6c7d4945 1602 default:
6bbf1acd 1603 return -EINVAL;
6c7d4945
MW
1604 }
1605
eca18b23
MW
1606 if (IS_ERR(iod))
1607 return PTR_ERR(iod);
a53295b6
MW
1608
1609 memset(&c, 0, sizeof(c));
1610 c.rw.opcode = io.opcode;
1611 c.rw.flags = io.flags;
6c7d4945 1612 c.rw.nsid = cpu_to_le32(ns->ns_id);
a53295b6 1613 c.rw.slba = cpu_to_le64(io.slba);
6c7d4945 1614 c.rw.length = cpu_to_le16(io.nblocks);
a53295b6 1615 c.rw.control = cpu_to_le16(io.control);
1c9b5265
MW
1616 c.rw.dsmgmt = cpu_to_le32(io.dsmgmt);
1617 c.rw.reftag = cpu_to_le32(io.reftag);
1618 c.rw.apptag = cpu_to_le16(io.apptag);
1619 c.rw.appmask = cpu_to_le16(io.appmask);
f410c680
KB
1620
1621 if (meta_len) {
1b56749e
KB
1622 meta_iod = nvme_map_user_pages(dev, io.opcode & 1, io.metadata,
1623 meta_len);
f410c680
KB
1624 if (IS_ERR(meta_iod)) {
1625 status = PTR_ERR(meta_iod);
1626 meta_iod = NULL;
1627 goto unmap;
1628 }
1629
1630 meta_mem = dma_alloc_coherent(&dev->pci_dev->dev, meta_len,
1631 &meta_dma_addr, GFP_KERNEL);
1632 if (!meta_mem) {
1633 status = -ENOMEM;
1634 goto unmap;
1635 }
1636
1637 if (io.opcode & 1) {
1638 int meta_offset = 0;
1639
1640 for (i = 0; i < meta_iod->nents; i++) {
1641 meta = kmap_atomic(sg_page(&meta_iod->sg[i])) +
1642 meta_iod->sg[i].offset;
1643 memcpy(meta_mem + meta_offset, meta,
1644 meta_iod->sg[i].length);
1645 kunmap_atomic(meta);
1646 meta_offset += meta_iod->sg[i].length;
1647 }
1648 }
1649
1650 c.rw.metadata = cpu_to_le64(meta_dma_addr);
1651 }
1652
edd10d33
KB
1653 length = nvme_setup_prps(dev, iod, length, GFP_KERNEL);
1654 c.rw.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
1655 c.rw.prp2 = cpu_to_le64(iod->first_dma);
a53295b6 1656
b77954cb
MW
1657 if (length != (io.nblocks + 1) << ns->lba_shift)
1658 status = -ENOMEM;
1659 else
4f5099af 1660 status = nvme_submit_io_cmd(dev, &c, NULL);
a53295b6 1661
f410c680
KB
1662 if (meta_len) {
1663 if (status == NVME_SC_SUCCESS && !(io.opcode & 1)) {
1664 int meta_offset = 0;
1665
1666 for (i = 0; i < meta_iod->nents; i++) {
1667 meta = kmap_atomic(sg_page(&meta_iod->sg[i])) +
1668 meta_iod->sg[i].offset;
1669 memcpy(meta, meta_mem + meta_offset,
1670 meta_iod->sg[i].length);
1671 kunmap_atomic(meta);
1672 meta_offset += meta_iod->sg[i].length;
1673 }
1674 }
1675
1676 dma_free_coherent(&dev->pci_dev->dev, meta_len, meta_mem,
1677 meta_dma_addr);
1678 }
1679
1680 unmap:
1c2ad9fa 1681 nvme_unmap_user_pages(dev, io.opcode & 1, iod);
eca18b23 1682 nvme_free_iod(dev, iod);
f410c680
KB
1683
1684 if (meta_iod) {
1685 nvme_unmap_user_pages(dev, io.opcode & 1, meta_iod);
1686 nvme_free_iod(dev, meta_iod);
1687 }
1688
a53295b6
MW
1689 return status;
1690}
1691
50af8bae 1692static int nvme_user_admin_cmd(struct nvme_dev *dev,
6bbf1acd 1693 struct nvme_admin_cmd __user *ucmd)
6ee44cdc 1694{
6bbf1acd 1695 struct nvme_admin_cmd cmd;
6ee44cdc 1696 struct nvme_command c;
eca18b23 1697 int status, length;
c7d36ab8 1698 struct nvme_iod *uninitialized_var(iod);
94f370ca 1699 unsigned timeout;
6ee44cdc 1700
6bbf1acd
MW
1701 if (!capable(CAP_SYS_ADMIN))
1702 return -EACCES;
1703 if (copy_from_user(&cmd, ucmd, sizeof(cmd)))
6ee44cdc 1704 return -EFAULT;
6ee44cdc
MW
1705
1706 memset(&c, 0, sizeof(c));
6bbf1acd
MW
1707 c.common.opcode = cmd.opcode;
1708 c.common.flags = cmd.flags;
1709 c.common.nsid = cpu_to_le32(cmd.nsid);
1710 c.common.cdw2[0] = cpu_to_le32(cmd.cdw2);
1711 c.common.cdw2[1] = cpu_to_le32(cmd.cdw3);
1712 c.common.cdw10[0] = cpu_to_le32(cmd.cdw10);
1713 c.common.cdw10[1] = cpu_to_le32(cmd.cdw11);
1714 c.common.cdw10[2] = cpu_to_le32(cmd.cdw12);
1715 c.common.cdw10[3] = cpu_to_le32(cmd.cdw13);
1716 c.common.cdw10[4] = cpu_to_le32(cmd.cdw14);
1717 c.common.cdw10[5] = cpu_to_le32(cmd.cdw15);
1718
1719 length = cmd.data_len;
1720 if (cmd.data_len) {
49742188
MW
1721 iod = nvme_map_user_pages(dev, cmd.opcode & 1, cmd.addr,
1722 length);
eca18b23
MW
1723 if (IS_ERR(iod))
1724 return PTR_ERR(iod);
edd10d33
KB
1725 length = nvme_setup_prps(dev, iod, length, GFP_KERNEL);
1726 c.common.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
1727 c.common.prp2 = cpu_to_le64(iod->first_dma);
6bbf1acd
MW
1728 }
1729
94f370ca
KB
1730 timeout = cmd.timeout_ms ? msecs_to_jiffies(cmd.timeout_ms) :
1731 ADMIN_TIMEOUT;
6bbf1acd 1732 if (length != cmd.data_len)
b77954cb
MW
1733 status = -ENOMEM;
1734 else
4f5099af 1735 status = nvme_submit_sync_cmd(dev, 0, &c, &cmd.result, timeout);
eca18b23 1736
6bbf1acd 1737 if (cmd.data_len) {
1c2ad9fa 1738 nvme_unmap_user_pages(dev, cmd.opcode & 1, iod);
eca18b23 1739 nvme_free_iod(dev, iod);
6bbf1acd 1740 }
f4f117f6 1741
cf90bc48 1742 if ((status >= 0) && copy_to_user(&ucmd->result, &cmd.result,
f4f117f6
KB
1743 sizeof(cmd.result)))
1744 status = -EFAULT;
1745
6ee44cdc
MW
1746 return status;
1747}
1748
b60503ba
MW
1749static int nvme_ioctl(struct block_device *bdev, fmode_t mode, unsigned int cmd,
1750 unsigned long arg)
1751{
1752 struct nvme_ns *ns = bdev->bd_disk->private_data;
1753
1754 switch (cmd) {
6bbf1acd 1755 case NVME_IOCTL_ID:
c3bfe717 1756 force_successful_syscall_return();
6bbf1acd
MW
1757 return ns->ns_id;
1758 case NVME_IOCTL_ADMIN_CMD:
50af8bae 1759 return nvme_user_admin_cmd(ns->dev, (void __user *)arg);
a53295b6
MW
1760 case NVME_IOCTL_SUBMIT_IO:
1761 return nvme_submit_io(ns, (void __user *)arg);
5d0f6131
VV
1762 case SG_GET_VERSION_NUM:
1763 return nvme_sg_get_version_num((void __user *)arg);
1764 case SG_IO:
1765 return nvme_sg_io(ns, (void __user *)arg);
b60503ba
MW
1766 default:
1767 return -ENOTTY;
1768 }
1769}
1770
320a3827
KB
1771#ifdef CONFIG_COMPAT
1772static int nvme_compat_ioctl(struct block_device *bdev, fmode_t mode,
1773 unsigned int cmd, unsigned long arg)
1774{
1775 struct nvme_ns *ns = bdev->bd_disk->private_data;
1776
1777 switch (cmd) {
1778 case SG_IO:
1779 return nvme_sg_io32(ns, arg);
1780 }
1781 return nvme_ioctl(bdev, mode, cmd, arg);
1782}
1783#else
1784#define nvme_compat_ioctl NULL
1785#endif
1786
9ac27090
KB
1787static int nvme_open(struct block_device *bdev, fmode_t mode)
1788{
1789 struct nvme_ns *ns = bdev->bd_disk->private_data;
1790 struct nvme_dev *dev = ns->dev;
1791
1792 kref_get(&dev->kref);
1793 return 0;
1794}
1795
1796static void nvme_free_dev(struct kref *kref);
1797
1798static void nvme_release(struct gendisk *disk, fmode_t mode)
1799{
1800 struct nvme_ns *ns = disk->private_data;
1801 struct nvme_dev *dev = ns->dev;
1802
1803 kref_put(&dev->kref, nvme_free_dev);
1804}
1805
4cc09e2d
KB
1806static int nvme_getgeo(struct block_device *bd, struct hd_geometry *geo)
1807{
1808 /* some standard values */
1809 geo->heads = 1 << 6;
1810 geo->sectors = 1 << 5;
1811 geo->cylinders = get_capacity(bd->bd_disk) >> 11;
1812 return 0;
1813}
1814
b60503ba
MW
1815static const struct block_device_operations nvme_fops = {
1816 .owner = THIS_MODULE,
1817 .ioctl = nvme_ioctl,
320a3827 1818 .compat_ioctl = nvme_compat_ioctl,
9ac27090
KB
1819 .open = nvme_open,
1820 .release = nvme_release,
4cc09e2d 1821 .getgeo = nvme_getgeo,
b60503ba
MW
1822};
1823
edd10d33
KB
1824static void nvme_resubmit_iods(struct nvme_queue *nvmeq)
1825{
1826 struct nvme_iod *iod, *next;
1827
1828 list_for_each_entry_safe(iod, next, &nvmeq->iod_bio, node) {
1829 if (unlikely(nvme_submit_iod(nvmeq, iod)))
1830 break;
1831 list_del(&iod->node);
1832 if (bio_list_empty(&nvmeq->sq_cong) &&
1833 list_empty(&nvmeq->iod_bio))
1834 remove_wait_queue(&nvmeq->sq_full,
1835 &nvmeq->sq_cong_wait);
1836 }
1837}
1838
1fa6aead
MW
1839static void nvme_resubmit_bios(struct nvme_queue *nvmeq)
1840{
1841 while (bio_list_peek(&nvmeq->sq_cong)) {
1842 struct bio *bio = bio_list_pop(&nvmeq->sq_cong);
1843 struct nvme_ns *ns = bio->bi_bdev->bd_disk->private_data;
427e9708 1844
edd10d33
KB
1845 if (bio_list_empty(&nvmeq->sq_cong) &&
1846 list_empty(&nvmeq->iod_bio))
427e9708
KB
1847 remove_wait_queue(&nvmeq->sq_full,
1848 &nvmeq->sq_cong_wait);
1fa6aead 1849 if (nvme_submit_bio_queue(nvmeq, ns, bio)) {
edd10d33 1850 if (!waitqueue_active(&nvmeq->sq_full))
427e9708
KB
1851 add_wait_queue(&nvmeq->sq_full,
1852 &nvmeq->sq_cong_wait);
1fa6aead
MW
1853 bio_list_add_head(&nvmeq->sq_cong, bio);
1854 break;
1855 }
1856 }
1857}
1858
6fccf938
KB
1859static int nvme_submit_async_req(struct nvme_queue *nvmeq)
1860{
1861 struct nvme_command *c;
1862 int cmdid;
1863
1864 cmdid = alloc_cmdid(nvmeq, CMD_CTX_ASYNC, special_completion, 0);
1865 if (cmdid < 0)
1866 return cmdid;
1867
1868 c = &nvmeq->sq_cmds[nvmeq->sq_tail];
1869 memset(c, 0, sizeof(*c));
1870 c->common.opcode = nvme_admin_async_event;
1871 c->common.command_id = cmdid;
1872
1873 if (++nvmeq->sq_tail == nvmeq->q_depth)
1874 nvmeq->sq_tail = 0;
1875 writel(nvmeq->sq_tail, nvmeq->q_db);
1876
1877 return 0;
1878}
1879
1fa6aead
MW
1880static int nvme_kthread(void *data)
1881{
d4b4ff8e 1882 struct nvme_dev *dev, *next;
1fa6aead
MW
1883
1884 while (!kthread_should_stop()) {
564a232c 1885 set_current_state(TASK_INTERRUPTIBLE);
1fa6aead 1886 spin_lock(&dev_list_lock);
d4b4ff8e 1887 list_for_each_entry_safe(dev, next, &dev_list, node) {
1fa6aead 1888 int i;
d4b4ff8e
KB
1889 if (readl(&dev->bar->csts) & NVME_CSTS_CFS &&
1890 dev->initialized) {
1891 if (work_busy(&dev->reset_work))
1892 continue;
1893 list_del_init(&dev->node);
1894 dev_warn(&dev->pci_dev->dev,
1895 "Failed status, reset controller\n");
9ca97374 1896 dev->reset_workfn = nvme_reset_failed_dev;
d4b4ff8e
KB
1897 queue_work(nvme_workq, &dev->reset_work);
1898 continue;
1899 }
5a92e700 1900 rcu_read_lock();
1fa6aead 1901 for (i = 0; i < dev->queue_count; i++) {
5a92e700
KB
1902 struct nvme_queue *nvmeq =
1903 rcu_dereference(dev->queues[i]);
740216fc
MW
1904 if (!nvmeq)
1905 continue;
1fa6aead 1906 spin_lock_irq(&nvmeq->q_lock);
22404274
KB
1907 if (nvmeq->q_suspended)
1908 goto unlock;
bc57a0f7 1909 nvme_process_cq(nvmeq);
a09115b2 1910 nvme_cancel_ios(nvmeq, true);
1fa6aead 1911 nvme_resubmit_bios(nvmeq);
edd10d33 1912 nvme_resubmit_iods(nvmeq);
6fccf938
KB
1913
1914 while ((i == 0) && (dev->event_limit > 0)) {
1915 if (nvme_submit_async_req(nvmeq))
1916 break;
1917 dev->event_limit--;
1918 }
22404274 1919 unlock:
1fa6aead
MW
1920 spin_unlock_irq(&nvmeq->q_lock);
1921 }
5a92e700 1922 rcu_read_unlock();
1fa6aead
MW
1923 }
1924 spin_unlock(&dev_list_lock);
acb7aa0d 1925 schedule_timeout(round_jiffies_relative(HZ));
1fa6aead
MW
1926 }
1927 return 0;
1928}
1929
0e5e4f0e
KB
1930static void nvme_config_discard(struct nvme_ns *ns)
1931{
1932 u32 logical_block_size = queue_logical_block_size(ns->queue);
1933 ns->queue->limits.discard_zeroes_data = 0;
1934 ns->queue->limits.discard_alignment = logical_block_size;
1935 ns->queue->limits.discard_granularity = logical_block_size;
1936 ns->queue->limits.max_discard_sectors = 0xffffffff;
1937 queue_flag_set_unlocked(QUEUE_FLAG_DISCARD, ns->queue);
1938}
1939
c3bfe717 1940static struct nvme_ns *nvme_alloc_ns(struct nvme_dev *dev, unsigned nsid,
b60503ba
MW
1941 struct nvme_id_ns *id, struct nvme_lba_range_type *rt)
1942{
1943 struct nvme_ns *ns;
1944 struct gendisk *disk;
1945 int lbaf;
1946
1947 if (rt->attributes & NVME_LBART_ATTRIB_HIDE)
1948 return NULL;
1949
1950 ns = kzalloc(sizeof(*ns), GFP_KERNEL);
1951 if (!ns)
1952 return NULL;
1953 ns->queue = blk_alloc_queue(GFP_KERNEL);
1954 if (!ns->queue)
1955 goto out_free_ns;
4eeb9215
MW
1956 ns->queue->queue_flags = QUEUE_FLAG_DEFAULT;
1957 queue_flag_set_unlocked(QUEUE_FLAG_NOMERGES, ns->queue);
1958 queue_flag_set_unlocked(QUEUE_FLAG_NONROT, ns->queue);
b277da0a 1959 queue_flag_clear_unlocked(QUEUE_FLAG_ADD_RANDOM, ns->queue);
b60503ba
MW
1960 blk_queue_make_request(ns->queue, nvme_make_request);
1961 ns->dev = dev;
1962 ns->queue->queuedata = ns;
1963
469071a3 1964 disk = alloc_disk(0);
b60503ba
MW
1965 if (!disk)
1966 goto out_free_queue;
5aff9382 1967 ns->ns_id = nsid;
b60503ba
MW
1968 ns->disk = disk;
1969 lbaf = id->flbas & 0xf;
1970 ns->lba_shift = id->lbaf[lbaf].ds;
f410c680 1971 ns->ms = le16_to_cpu(id->lbaf[lbaf].ms);
e9ef4636 1972 blk_queue_logical_block_size(ns->queue, 1 << ns->lba_shift);
8fc23e03
KB
1973 if (dev->max_hw_sectors)
1974 blk_queue_max_hw_sectors(ns->queue, dev->max_hw_sectors);
a7d2ce28
KB
1975 if (dev->vwc & NVME_CTRL_VWC_PRESENT)
1976 blk_queue_flush(ns->queue, REQ_FLUSH | REQ_FUA);
b60503ba
MW
1977
1978 disk->major = nvme_major;
469071a3 1979 disk->first_minor = 0;
b60503ba
MW
1980 disk->fops = &nvme_fops;
1981 disk->private_data = ns;
1982 disk->queue = ns->queue;
388f037f 1983 disk->driverfs_dev = &dev->pci_dev->dev;
469071a3 1984 disk->flags = GENHD_FL_EXT_DEVT;
5aff9382 1985 sprintf(disk->disk_name, "nvme%dn%d", dev->instance, nsid);
b60503ba
MW
1986 set_capacity(disk, le64_to_cpup(&id->nsze) << (ns->lba_shift - 9));
1987
0e5e4f0e
KB
1988 if (dev->oncs & NVME_CTRL_ONCS_DSM)
1989 nvme_config_discard(ns);
1990
b60503ba
MW
1991 return ns;
1992
1993 out_free_queue:
1994 blk_cleanup_queue(ns->queue);
1995 out_free_ns:
1996 kfree(ns);
1997 return NULL;
1998}
1999
42f61420
KB
2000static int nvme_find_closest_node(int node)
2001{
2002 int n, val, min_val = INT_MAX, best_node = node;
2003
2004 for_each_online_node(n) {
2005 if (n == node)
2006 continue;
2007 val = node_distance(node, n);
2008 if (val < min_val) {
2009 min_val = val;
2010 best_node = n;
2011 }
2012 }
2013 return best_node;
2014}
2015
2016static void nvme_set_queue_cpus(cpumask_t *qmask, struct nvme_queue *nvmeq,
2017 int count)
2018{
2019 int cpu;
2020 for_each_cpu(cpu, qmask) {
2021 if (cpumask_weight(nvmeq->cpu_mask) >= count)
2022 break;
2023 if (!cpumask_test_and_set_cpu(cpu, nvmeq->cpu_mask))
2024 *per_cpu_ptr(nvmeq->dev->io_queue, cpu) = nvmeq->qid;
2025 }
2026}
2027
2028static void nvme_add_cpus(cpumask_t *mask, const cpumask_t *unassigned_cpus,
2029 const cpumask_t *new_mask, struct nvme_queue *nvmeq, int cpus_per_queue)
2030{
2031 int next_cpu;
2032 for_each_cpu(next_cpu, new_mask) {
2033 cpumask_or(mask, mask, get_cpu_mask(next_cpu));
2034 cpumask_or(mask, mask, topology_thread_cpumask(next_cpu));
2035 cpumask_and(mask, mask, unassigned_cpus);
2036 nvme_set_queue_cpus(mask, nvmeq, cpus_per_queue);
2037 }
2038}
2039
2040static void nvme_create_io_queues(struct nvme_dev *dev)
2041{
2042 unsigned i, max;
2043
2044 max = min(dev->max_qid, num_online_cpus());
2045 for (i = dev->queue_count; i <= max; i++)
2046 if (!nvme_alloc_queue(dev, i, dev->q_depth, i - 1))
2047 break;
2048
2049 max = min(dev->queue_count - 1, num_online_cpus());
2050 for (i = dev->online_queues; i <= max; i++)
2051 if (nvme_create_queue(raw_nvmeq(dev, i), i))
2052 break;
2053}
2054
2055/*
2056 * If there are fewer queues than online cpus, this will try to optimally
2057 * assign a queue to multiple cpus by grouping cpus that are "close" together:
2058 * thread siblings, core, socket, closest node, then whatever else is
2059 * available.
2060 */
2061static void nvme_assign_io_queues(struct nvme_dev *dev)
2062{
2063 unsigned cpu, cpus_per_queue, queues, remainder, i;
2064 cpumask_var_t unassigned_cpus;
2065
2066 nvme_create_io_queues(dev);
2067
2068 queues = min(dev->online_queues - 1, num_online_cpus());
2069 if (!queues)
2070 return;
2071
2072 cpus_per_queue = num_online_cpus() / queues;
2073 remainder = queues - (num_online_cpus() - queues * cpus_per_queue);
2074
2075 if (!alloc_cpumask_var(&unassigned_cpus, GFP_KERNEL))
2076 return;
2077
2078 cpumask_copy(unassigned_cpus, cpu_online_mask);
2079 cpu = cpumask_first(unassigned_cpus);
2080 for (i = 1; i <= queues; i++) {
2081 struct nvme_queue *nvmeq = lock_nvmeq(dev, i);
2082 cpumask_t mask;
2083
2084 cpumask_clear(nvmeq->cpu_mask);
2085 if (!cpumask_weight(unassigned_cpus)) {
2086 unlock_nvmeq(nvmeq);
2087 break;
2088 }
2089
2090 mask = *get_cpu_mask(cpu);
2091 nvme_set_queue_cpus(&mask, nvmeq, cpus_per_queue);
2092 if (cpus_weight(mask) < cpus_per_queue)
2093 nvme_add_cpus(&mask, unassigned_cpus,
2094 topology_thread_cpumask(cpu),
2095 nvmeq, cpus_per_queue);
2096 if (cpus_weight(mask) < cpus_per_queue)
2097 nvme_add_cpus(&mask, unassigned_cpus,
2098 topology_core_cpumask(cpu),
2099 nvmeq, cpus_per_queue);
2100 if (cpus_weight(mask) < cpus_per_queue)
2101 nvme_add_cpus(&mask, unassigned_cpus,
2102 cpumask_of_node(cpu_to_node(cpu)),
2103 nvmeq, cpus_per_queue);
2104 if (cpus_weight(mask) < cpus_per_queue)
2105 nvme_add_cpus(&mask, unassigned_cpus,
2106 cpumask_of_node(
2107 nvme_find_closest_node(
2108 cpu_to_node(cpu))),
2109 nvmeq, cpus_per_queue);
2110 if (cpus_weight(mask) < cpus_per_queue)
2111 nvme_add_cpus(&mask, unassigned_cpus,
2112 unassigned_cpus,
2113 nvmeq, cpus_per_queue);
2114
2115 WARN(cpumask_weight(nvmeq->cpu_mask) != cpus_per_queue,
2116 "nvme%d qid:%d mis-matched queue-to-cpu assignment\n",
2117 dev->instance, i);
2118
2119 irq_set_affinity_hint(dev->entry[nvmeq->cq_vector].vector,
2120 nvmeq->cpu_mask);
2121 cpumask_andnot(unassigned_cpus, unassigned_cpus,
2122 nvmeq->cpu_mask);
2123 cpu = cpumask_next(cpu, unassigned_cpus);
2124 if (remainder && !--remainder)
2125 cpus_per_queue++;
2126 unlock_nvmeq(nvmeq);
2127 }
2128 WARN(cpumask_weight(unassigned_cpus), "nvme%d unassigned online cpus\n",
2129 dev->instance);
2130 i = 0;
2131 cpumask_andnot(unassigned_cpus, cpu_possible_mask, cpu_online_mask);
2132 for_each_cpu(cpu, unassigned_cpus)
2133 *per_cpu_ptr(dev->io_queue, cpu) = (i++ % queues) + 1;
2134 free_cpumask_var(unassigned_cpus);
2135}
2136
b3b06812 2137static int set_queue_count(struct nvme_dev *dev, int count)
b60503ba
MW
2138{
2139 int status;
2140 u32 result;
b3b06812 2141 u32 q_count = (count - 1) | ((count - 1) << 16);
b60503ba 2142
df348139 2143 status = nvme_set_features(dev, NVME_FEAT_NUM_QUEUES, q_count, 0,
bc5fc7e4 2144 &result);
27e8166c
MW
2145 if (status < 0)
2146 return status;
2147 if (status > 0) {
2148 dev_err(&dev->pci_dev->dev, "Could not set queue count (%d)\n",
2149 status);
2150 return -EBUSY;
2151 }
b60503ba
MW
2152 return min(result & 0xffff, result >> 16) + 1;
2153}
2154
9d713c2b
KB
2155static size_t db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues)
2156{
b80d5ccc 2157 return 4096 + ((nr_io_queues + 1) * 8 * dev->db_stride);
9d713c2b
KB
2158}
2159
f3db22fe
KB
2160static void nvme_cpu_workfn(struct work_struct *work)
2161{
2162 struct nvme_dev *dev = container_of(work, struct nvme_dev, cpu_work);
2163 if (dev->initialized)
2164 nvme_assign_io_queues(dev);
2165}
2166
33b1e95c
KB
2167static int nvme_cpu_notify(struct notifier_block *self,
2168 unsigned long action, void *hcpu)
2169{
f3db22fe
KB
2170 struct nvme_dev *dev;
2171
33b1e95c
KB
2172 switch (action) {
2173 case CPU_ONLINE:
2174 case CPU_DEAD:
f3db22fe
KB
2175 spin_lock(&dev_list_lock);
2176 list_for_each_entry(dev, &dev_list, node)
2177 schedule_work(&dev->cpu_work);
2178 spin_unlock(&dev_list_lock);
33b1e95c
KB
2179 break;
2180 }
2181 return NOTIFY_OK;
2182}
2183
8d85fce7 2184static int nvme_setup_io_queues(struct nvme_dev *dev)
b60503ba 2185{
5a92e700 2186 struct nvme_queue *adminq = raw_nvmeq(dev, 0);
fa08a396 2187 struct pci_dev *pdev = dev->pci_dev;
42f61420 2188 int result, i, vecs, nr_io_queues, size;
b60503ba 2189
42f61420 2190 nr_io_queues = num_possible_cpus();
b348b7d5 2191 result = set_queue_count(dev, nr_io_queues);
1b23484b
MW
2192 if (result < 0)
2193 return result;
b348b7d5
MW
2194 if (result < nr_io_queues)
2195 nr_io_queues = result;
b60503ba 2196
9d713c2b
KB
2197 size = db_bar_size(dev, nr_io_queues);
2198 if (size > 8192) {
f1938f6e 2199 iounmap(dev->bar);
9d713c2b
KB
2200 do {
2201 dev->bar = ioremap(pci_resource_start(pdev, 0), size);
2202 if (dev->bar)
2203 break;
2204 if (!--nr_io_queues)
2205 return -ENOMEM;
2206 size = db_bar_size(dev, nr_io_queues);
2207 } while (1);
f1938f6e 2208 dev->dbs = ((void __iomem *)dev->bar) + 4096;
5a92e700 2209 adminq->q_db = dev->dbs;
f1938f6e
MW
2210 }
2211
9d713c2b 2212 /* Deregister the admin queue's interrupt */
3193f07b 2213 free_irq(dev->entry[0].vector, adminq);
9d713c2b 2214
be577fab 2215 for (i = 0; i < nr_io_queues; i++)
1b23484b 2216 dev->entry[i].entry = i;
be577fab
AG
2217 vecs = pci_enable_msix_range(pdev, dev->entry, 1, nr_io_queues);
2218 if (vecs < 0) {
2219 vecs = pci_enable_msi_range(pdev, 1, min(nr_io_queues, 32));
2220 if (vecs < 0) {
2221 vecs = 1;
2222 } else {
2223 for (i = 0; i < vecs; i++)
2224 dev->entry[i].vector = i + pdev->irq;
fa08a396
RRG
2225 }
2226 }
2227
063a8096
MW
2228 /*
2229 * Should investigate if there's a performance win from allocating
2230 * more queues than interrupt vectors; it might allow the submission
2231 * path to scale better, even if the receive path is limited by the
2232 * number of interrupts.
2233 */
2234 nr_io_queues = vecs;
42f61420 2235 dev->max_qid = nr_io_queues;
063a8096 2236
3193f07b 2237 result = queue_request_irq(dev, adminq, adminq->irqname);
9d713c2b 2238 if (result) {
3193f07b 2239 adminq->q_suspended = 1;
22404274 2240 goto free_queues;
9d713c2b 2241 }
1b23484b 2242
cd638946 2243 /* Free previously allocated queues that are no longer usable */
42f61420
KB
2244 nvme_free_queues(dev, nr_io_queues + 1);
2245 nvme_assign_io_queues(dev);
9ecdc946 2246
22404274 2247 return 0;
b60503ba 2248
22404274 2249 free_queues:
a1a5ef99 2250 nvme_free_queues(dev, 1);
22404274 2251 return result;
b60503ba
MW
2252}
2253
422ef0c7
MW
2254/*
2255 * Return: error value if an error occurred setting up the queues or calling
2256 * Identify Device. 0 if these succeeded, even if adding some of the
2257 * namespaces failed. At the moment, these failures are silent. TBD which
2258 * failures should be reported.
2259 */
8d85fce7 2260static int nvme_dev_add(struct nvme_dev *dev)
b60503ba 2261{
68608c26 2262 struct pci_dev *pdev = dev->pci_dev;
c3bfe717
MW
2263 int res;
2264 unsigned nn, i;
cbb6218f 2265 struct nvme_ns *ns;
51814232 2266 struct nvme_id_ctrl *ctrl;
bc5fc7e4
MW
2267 struct nvme_id_ns *id_ns;
2268 void *mem;
b60503ba 2269 dma_addr_t dma_addr;
159b67d7 2270 int shift = NVME_CAP_MPSMIN(readq(&dev->bar->cap)) + 12;
b60503ba 2271
68608c26 2272 mem = dma_alloc_coherent(&pdev->dev, 8192, &dma_addr, GFP_KERNEL);
a9ef4343
KB
2273 if (!mem)
2274 return -ENOMEM;
b60503ba 2275
bc5fc7e4 2276 res = nvme_identify(dev, 0, 1, dma_addr);
b60503ba 2277 if (res) {
27e8166c 2278 dev_err(&pdev->dev, "Identify Controller failed (%d)\n", res);
b60503ba 2279 res = -EIO;
cbb6218f 2280 goto out;
b60503ba
MW
2281 }
2282
bc5fc7e4 2283 ctrl = mem;
51814232 2284 nn = le32_to_cpup(&ctrl->nn);
0e5e4f0e 2285 dev->oncs = le16_to_cpup(&ctrl->oncs);
c30341dc 2286 dev->abort_limit = ctrl->acl + 1;
a7d2ce28 2287 dev->vwc = ctrl->vwc;
6fccf938 2288 dev->event_limit = min(ctrl->aerl + 1, 8);
51814232
MW
2289 memcpy(dev->serial, ctrl->sn, sizeof(ctrl->sn));
2290 memcpy(dev->model, ctrl->mn, sizeof(ctrl->mn));
2291 memcpy(dev->firmware_rev, ctrl->fr, sizeof(ctrl->fr));
159b67d7 2292 if (ctrl->mdts)
8fc23e03 2293 dev->max_hw_sectors = 1 << (ctrl->mdts + shift - 9);
68608c26
MW
2294 if ((pdev->vendor == PCI_VENDOR_ID_INTEL) &&
2295 (pdev->device == 0x0953) && ctrl->vs[3])
159b67d7 2296 dev->stripe_size = 1 << (ctrl->vs[3] + shift);
b60503ba 2297
bc5fc7e4 2298 id_ns = mem;
2b2c1896 2299 for (i = 1; i <= nn; i++) {
bc5fc7e4 2300 res = nvme_identify(dev, i, 0, dma_addr);
b60503ba
MW
2301 if (res)
2302 continue;
2303
bc5fc7e4 2304 if (id_ns->ncap == 0)
b60503ba
MW
2305 continue;
2306
bc5fc7e4 2307 res = nvme_get_features(dev, NVME_FEAT_LBA_RANGE, i,
08df1e05 2308 dma_addr + 4096, NULL);
b60503ba 2309 if (res)
12209036 2310 memset(mem + 4096, 0, 4096);
b60503ba 2311
bc5fc7e4 2312 ns = nvme_alloc_ns(dev, i, mem, mem + 4096);
b60503ba
MW
2313 if (ns)
2314 list_add_tail(&ns->list, &dev->namespaces);
2315 }
2316 list_for_each_entry(ns, &dev->namespaces, list)
2317 add_disk(ns->disk);
422ef0c7 2318 res = 0;
b60503ba 2319
bc5fc7e4 2320 out:
684f5c20 2321 dma_free_coherent(&dev->pci_dev->dev, 8192, mem, dma_addr);
b60503ba
MW
2322 return res;
2323}
2324
0877cb0d
KB
2325static int nvme_dev_map(struct nvme_dev *dev)
2326{
42f61420 2327 u64 cap;
0877cb0d
KB
2328 int bars, result = -ENOMEM;
2329 struct pci_dev *pdev = dev->pci_dev;
2330
2331 if (pci_enable_device_mem(pdev))
2332 return result;
2333
2334 dev->entry[0].vector = pdev->irq;
2335 pci_set_master(pdev);
2336 bars = pci_select_bars(pdev, IORESOURCE_MEM);
2337 if (pci_request_selected_regions(pdev, bars, "nvme"))
2338 goto disable_pci;
2339
052d0efa
RK
2340 if (dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)) &&
2341 dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)))
2342 goto disable;
0877cb0d 2343
0877cb0d
KB
2344 dev->bar = ioremap(pci_resource_start(pdev, 0), 8192);
2345 if (!dev->bar)
2346 goto disable;
0e53d180
KB
2347 if (readl(&dev->bar->csts) == -1) {
2348 result = -ENODEV;
2349 goto unmap;
2350 }
42f61420
KB
2351 cap = readq(&dev->bar->cap);
2352 dev->q_depth = min_t(int, NVME_CAP_MQES(cap) + 1, NVME_Q_DEPTH);
2353 dev->db_stride = 1 << NVME_CAP_STRIDE(cap);
0877cb0d
KB
2354 dev->dbs = ((void __iomem *)dev->bar) + 4096;
2355
2356 return 0;
2357
0e53d180
KB
2358 unmap:
2359 iounmap(dev->bar);
2360 dev->bar = NULL;
0877cb0d
KB
2361 disable:
2362 pci_release_regions(pdev);
2363 disable_pci:
2364 pci_disable_device(pdev);
2365 return result;
2366}
2367
2368static void nvme_dev_unmap(struct nvme_dev *dev)
2369{
2370 if (dev->pci_dev->msi_enabled)
2371 pci_disable_msi(dev->pci_dev);
2372 else if (dev->pci_dev->msix_enabled)
2373 pci_disable_msix(dev->pci_dev);
2374
2375 if (dev->bar) {
2376 iounmap(dev->bar);
2377 dev->bar = NULL;
9a6b9458 2378 pci_release_regions(dev->pci_dev);
0877cb0d
KB
2379 }
2380
0877cb0d
KB
2381 if (pci_is_enabled(dev->pci_dev))
2382 pci_disable_device(dev->pci_dev);
2383}
2384
4d115420
KB
2385struct nvme_delq_ctx {
2386 struct task_struct *waiter;
2387 struct kthread_worker *worker;
2388 atomic_t refcount;
2389};
2390
2391static void nvme_wait_dq(struct nvme_delq_ctx *dq, struct nvme_dev *dev)
2392{
2393 dq->waiter = current;
2394 mb();
2395
2396 for (;;) {
2397 set_current_state(TASK_KILLABLE);
2398 if (!atomic_read(&dq->refcount))
2399 break;
2400 if (!schedule_timeout(ADMIN_TIMEOUT) ||
2401 fatal_signal_pending(current)) {
2402 set_current_state(TASK_RUNNING);
2403
2404 nvme_disable_ctrl(dev, readq(&dev->bar->cap));
2405 nvme_disable_queue(dev, 0);
2406
2407 send_sig(SIGKILL, dq->worker->task, 1);
2408 flush_kthread_worker(dq->worker);
2409 return;
2410 }
2411 }
2412 set_current_state(TASK_RUNNING);
2413}
2414
2415static void nvme_put_dq(struct nvme_delq_ctx *dq)
2416{
2417 atomic_dec(&dq->refcount);
2418 if (dq->waiter)
2419 wake_up_process(dq->waiter);
2420}
2421
2422static struct nvme_delq_ctx *nvme_get_dq(struct nvme_delq_ctx *dq)
2423{
2424 atomic_inc(&dq->refcount);
2425 return dq;
2426}
2427
2428static void nvme_del_queue_end(struct nvme_queue *nvmeq)
2429{
2430 struct nvme_delq_ctx *dq = nvmeq->cmdinfo.ctx;
2431
2432 nvme_clear_queue(nvmeq);
2433 nvme_put_dq(dq);
2434}
2435
2436static int adapter_async_del_queue(struct nvme_queue *nvmeq, u8 opcode,
2437 kthread_work_func_t fn)
2438{
2439 struct nvme_command c;
2440
2441 memset(&c, 0, sizeof(c));
2442 c.delete_queue.opcode = opcode;
2443 c.delete_queue.qid = cpu_to_le16(nvmeq->qid);
2444
2445 init_kthread_work(&nvmeq->cmdinfo.work, fn);
2446 return nvme_submit_admin_cmd_async(nvmeq->dev, &c, &nvmeq->cmdinfo);
2447}
2448
2449static void nvme_del_cq_work_handler(struct kthread_work *work)
2450{
2451 struct nvme_queue *nvmeq = container_of(work, struct nvme_queue,
2452 cmdinfo.work);
2453 nvme_del_queue_end(nvmeq);
2454}
2455
2456static int nvme_delete_cq(struct nvme_queue *nvmeq)
2457{
2458 return adapter_async_del_queue(nvmeq, nvme_admin_delete_cq,
2459 nvme_del_cq_work_handler);
2460}
2461
2462static void nvme_del_sq_work_handler(struct kthread_work *work)
2463{
2464 struct nvme_queue *nvmeq = container_of(work, struct nvme_queue,
2465 cmdinfo.work);
2466 int status = nvmeq->cmdinfo.status;
2467
2468 if (!status)
2469 status = nvme_delete_cq(nvmeq);
2470 if (status)
2471 nvme_del_queue_end(nvmeq);
2472}
2473
2474static int nvme_delete_sq(struct nvme_queue *nvmeq)
2475{
2476 return adapter_async_del_queue(nvmeq, nvme_admin_delete_sq,
2477 nvme_del_sq_work_handler);
2478}
2479
2480static void nvme_del_queue_start(struct kthread_work *work)
2481{
2482 struct nvme_queue *nvmeq = container_of(work, struct nvme_queue,
2483 cmdinfo.work);
2484 allow_signal(SIGKILL);
2485 if (nvme_delete_sq(nvmeq))
2486 nvme_del_queue_end(nvmeq);
2487}
2488
2489static void nvme_disable_io_queues(struct nvme_dev *dev)
2490{
2491 int i;
2492 DEFINE_KTHREAD_WORKER_ONSTACK(worker);
2493 struct nvme_delq_ctx dq;
2494 struct task_struct *kworker_task = kthread_run(kthread_worker_fn,
2495 &worker, "nvme%d", dev->instance);
2496
2497 if (IS_ERR(kworker_task)) {
2498 dev_err(&dev->pci_dev->dev,
2499 "Failed to create queue del task\n");
2500 for (i = dev->queue_count - 1; i > 0; i--)
2501 nvme_disable_queue(dev, i);
2502 return;
2503 }
2504
2505 dq.waiter = NULL;
2506 atomic_set(&dq.refcount, 0);
2507 dq.worker = &worker;
2508 for (i = dev->queue_count - 1; i > 0; i--) {
5a92e700 2509 struct nvme_queue *nvmeq = raw_nvmeq(dev, i);
4d115420
KB
2510
2511 if (nvme_suspend_queue(nvmeq))
2512 continue;
2513 nvmeq->cmdinfo.ctx = nvme_get_dq(&dq);
2514 nvmeq->cmdinfo.worker = dq.worker;
2515 init_kthread_work(&nvmeq->cmdinfo.work, nvme_del_queue_start);
2516 queue_kthread_work(dq.worker, &nvmeq->cmdinfo.work);
2517 }
2518 nvme_wait_dq(&dq, dev);
2519 kthread_stop(kworker_task);
2520}
2521
b9afca3e
DM
2522/*
2523* Remove the node from the device list and check
2524* for whether or not we need to stop the nvme_thread.
2525*/
2526static void nvme_dev_list_remove(struct nvme_dev *dev)
2527{
2528 struct task_struct *tmp = NULL;
2529
2530 spin_lock(&dev_list_lock);
2531 list_del_init(&dev->node);
2532 if (list_empty(&dev_list) && !IS_ERR_OR_NULL(nvme_thread)) {
2533 tmp = nvme_thread;
2534 nvme_thread = NULL;
2535 }
2536 spin_unlock(&dev_list_lock);
2537
2538 if (tmp)
2539 kthread_stop(tmp);
2540}
2541
f0b50732 2542static void nvme_dev_shutdown(struct nvme_dev *dev)
b60503ba 2543{
22404274
KB
2544 int i;
2545
d4b4ff8e 2546 dev->initialized = 0;
b9afca3e 2547 nvme_dev_list_remove(dev);
1fa6aead 2548
4d115420
KB
2549 if (!dev->bar || (dev->bar && readl(&dev->bar->csts) == -1)) {
2550 for (i = dev->queue_count - 1; i >= 0; i--) {
5a92e700 2551 struct nvme_queue *nvmeq = raw_nvmeq(dev, i);
4d115420
KB
2552 nvme_suspend_queue(nvmeq);
2553 nvme_clear_queue(nvmeq);
2554 }
2555 } else {
2556 nvme_disable_io_queues(dev);
1894d8f1 2557 nvme_shutdown_ctrl(dev);
4d115420
KB
2558 nvme_disable_queue(dev, 0);
2559 }
f0b50732
KB
2560 nvme_dev_unmap(dev);
2561}
2562
2563static void nvme_dev_remove(struct nvme_dev *dev)
2564{
9ac27090 2565 struct nvme_ns *ns;
f0b50732 2566
9ac27090
KB
2567 list_for_each_entry(ns, &dev->namespaces, list) {
2568 if (ns->disk->flags & GENHD_FL_UP)
2569 del_gendisk(ns->disk);
2570 if (!blk_queue_dying(ns->queue))
2571 blk_cleanup_queue(ns->queue);
b60503ba 2572 }
b60503ba
MW
2573}
2574
091b6092
MW
2575static int nvme_setup_prp_pools(struct nvme_dev *dev)
2576{
2577 struct device *dmadev = &dev->pci_dev->dev;
2578 dev->prp_page_pool = dma_pool_create("prp list page", dmadev,
2579 PAGE_SIZE, PAGE_SIZE, 0);
2580 if (!dev->prp_page_pool)
2581 return -ENOMEM;
2582
99802a7a
MW
2583 /* Optimisation for I/Os between 4k and 128k */
2584 dev->prp_small_pool = dma_pool_create("prp list 256", dmadev,
2585 256, 256, 0);
2586 if (!dev->prp_small_pool) {
2587 dma_pool_destroy(dev->prp_page_pool);
2588 return -ENOMEM;
2589 }
091b6092
MW
2590 return 0;
2591}
2592
2593static void nvme_release_prp_pools(struct nvme_dev *dev)
2594{
2595 dma_pool_destroy(dev->prp_page_pool);
99802a7a 2596 dma_pool_destroy(dev->prp_small_pool);
091b6092
MW
2597}
2598
cd58ad7d
QSA
2599static DEFINE_IDA(nvme_instance_ida);
2600
2601static int nvme_set_instance(struct nvme_dev *dev)
b60503ba 2602{
cd58ad7d
QSA
2603 int instance, error;
2604
2605 do {
2606 if (!ida_pre_get(&nvme_instance_ida, GFP_KERNEL))
2607 return -ENODEV;
2608
2609 spin_lock(&dev_list_lock);
2610 error = ida_get_new(&nvme_instance_ida, &instance);
2611 spin_unlock(&dev_list_lock);
2612 } while (error == -EAGAIN);
2613
2614 if (error)
2615 return -ENODEV;
2616
2617 dev->instance = instance;
2618 return 0;
b60503ba
MW
2619}
2620
2621static void nvme_release_instance(struct nvme_dev *dev)
2622{
cd58ad7d
QSA
2623 spin_lock(&dev_list_lock);
2624 ida_remove(&nvme_instance_ida, dev->instance);
2625 spin_unlock(&dev_list_lock);
b60503ba
MW
2626}
2627
9ac27090
KB
2628static void nvme_free_namespaces(struct nvme_dev *dev)
2629{
2630 struct nvme_ns *ns, *next;
2631
2632 list_for_each_entry_safe(ns, next, &dev->namespaces, list) {
2633 list_del(&ns->list);
2634 put_disk(ns->disk);
2635 kfree(ns);
2636 }
2637}
2638
5e82e952
KB
2639static void nvme_free_dev(struct kref *kref)
2640{
2641 struct nvme_dev *dev = container_of(kref, struct nvme_dev, kref);
9ac27090
KB
2642
2643 nvme_free_namespaces(dev);
42f61420 2644 free_percpu(dev->io_queue);
5e82e952
KB
2645 kfree(dev->queues);
2646 kfree(dev->entry);
2647 kfree(dev);
2648}
2649
2650static int nvme_dev_open(struct inode *inode, struct file *f)
2651{
2652 struct nvme_dev *dev = container_of(f->private_data, struct nvme_dev,
2653 miscdev);
2654 kref_get(&dev->kref);
2655 f->private_data = dev;
2656 return 0;
2657}
2658
2659static int nvme_dev_release(struct inode *inode, struct file *f)
2660{
2661 struct nvme_dev *dev = f->private_data;
2662 kref_put(&dev->kref, nvme_free_dev);
2663 return 0;
2664}
2665
2666static long nvme_dev_ioctl(struct file *f, unsigned int cmd, unsigned long arg)
2667{
2668 struct nvme_dev *dev = f->private_data;
2669 switch (cmd) {
2670 case NVME_IOCTL_ADMIN_CMD:
2671 return nvme_user_admin_cmd(dev, (void __user *)arg);
2672 default:
2673 return -ENOTTY;
2674 }
2675}
2676
2677static const struct file_operations nvme_dev_fops = {
2678 .owner = THIS_MODULE,
2679 .open = nvme_dev_open,
2680 .release = nvme_dev_release,
2681 .unlocked_ioctl = nvme_dev_ioctl,
2682 .compat_ioctl = nvme_dev_ioctl,
2683};
2684
f0b50732
KB
2685static int nvme_dev_start(struct nvme_dev *dev)
2686{
2687 int result;
b9afca3e 2688 bool start_thread = false;
f0b50732
KB
2689
2690 result = nvme_dev_map(dev);
2691 if (result)
2692 return result;
2693
2694 result = nvme_configure_admin_queue(dev);
2695 if (result)
2696 goto unmap;
2697
2698 spin_lock(&dev_list_lock);
b9afca3e
DM
2699 if (list_empty(&dev_list) && IS_ERR_OR_NULL(nvme_thread)) {
2700 start_thread = true;
2701 nvme_thread = NULL;
2702 }
f0b50732
KB
2703 list_add(&dev->node, &dev_list);
2704 spin_unlock(&dev_list_lock);
2705
b9afca3e
DM
2706 if (start_thread) {
2707 nvme_thread = kthread_run(nvme_kthread, NULL, "nvme");
2708 wake_up(&nvme_kthread_wait);
2709 } else
2710 wait_event_killable(nvme_kthread_wait, nvme_thread);
2711
2712 if (IS_ERR_OR_NULL(nvme_thread)) {
2713 result = nvme_thread ? PTR_ERR(nvme_thread) : -EINTR;
2714 goto disable;
2715 }
2716
f0b50732 2717 result = nvme_setup_io_queues(dev);
d82e8bfd 2718 if (result && result != -EBUSY)
f0b50732
KB
2719 goto disable;
2720
d82e8bfd 2721 return result;
f0b50732
KB
2722
2723 disable:
a1a5ef99 2724 nvme_disable_queue(dev, 0);
b9afca3e 2725 nvme_dev_list_remove(dev);
f0b50732
KB
2726 unmap:
2727 nvme_dev_unmap(dev);
2728 return result;
2729}
2730
9a6b9458
KB
2731static int nvme_remove_dead_ctrl(void *arg)
2732{
2733 struct nvme_dev *dev = (struct nvme_dev *)arg;
2734 struct pci_dev *pdev = dev->pci_dev;
2735
2736 if (pci_get_drvdata(pdev))
2737 pci_stop_and_remove_bus_device(pdev);
2738 kref_put(&dev->kref, nvme_free_dev);
2739 return 0;
2740}
2741
2742static void nvme_remove_disks(struct work_struct *ws)
2743{
9a6b9458
KB
2744 struct nvme_dev *dev = container_of(ws, struct nvme_dev, reset_work);
2745
2746 nvme_dev_remove(dev);
5a92e700 2747 nvme_free_queues(dev, 1);
9a6b9458
KB
2748}
2749
2750static int nvme_dev_resume(struct nvme_dev *dev)
2751{
2752 int ret;
2753
2754 ret = nvme_dev_start(dev);
2755 if (ret && ret != -EBUSY)
2756 return ret;
2757 if (ret == -EBUSY) {
2758 spin_lock(&dev_list_lock);
9ca97374 2759 dev->reset_workfn = nvme_remove_disks;
9a6b9458
KB
2760 queue_work(nvme_workq, &dev->reset_work);
2761 spin_unlock(&dev_list_lock);
2762 }
d4b4ff8e 2763 dev->initialized = 1;
9a6b9458
KB
2764 return 0;
2765}
2766
2767static void nvme_dev_reset(struct nvme_dev *dev)
2768{
2769 nvme_dev_shutdown(dev);
2770 if (nvme_dev_resume(dev)) {
2771 dev_err(&dev->pci_dev->dev, "Device failed to resume\n");
2772 kref_get(&dev->kref);
2773 if (IS_ERR(kthread_run(nvme_remove_dead_ctrl, dev, "nvme%d",
2774 dev->instance))) {
2775 dev_err(&dev->pci_dev->dev,
2776 "Failed to start controller remove task\n");
2777 kref_put(&dev->kref, nvme_free_dev);
2778 }
2779 }
2780}
2781
2782static void nvme_reset_failed_dev(struct work_struct *ws)
2783{
2784 struct nvme_dev *dev = container_of(ws, struct nvme_dev, reset_work);
2785 nvme_dev_reset(dev);
2786}
2787
9ca97374
TH
2788static void nvme_reset_workfn(struct work_struct *work)
2789{
2790 struct nvme_dev *dev = container_of(work, struct nvme_dev, reset_work);
2791 dev->reset_workfn(work);
2792}
2793
8d85fce7 2794static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id)
b60503ba 2795{
0877cb0d 2796 int result = -ENOMEM;
b60503ba
MW
2797 struct nvme_dev *dev;
2798
2799 dev = kzalloc(sizeof(*dev), GFP_KERNEL);
2800 if (!dev)
2801 return -ENOMEM;
2802 dev->entry = kcalloc(num_possible_cpus(), sizeof(*dev->entry),
2803 GFP_KERNEL);
2804 if (!dev->entry)
2805 goto free;
1b23484b
MW
2806 dev->queues = kcalloc(num_possible_cpus() + 1, sizeof(void *),
2807 GFP_KERNEL);
b60503ba
MW
2808 if (!dev->queues)
2809 goto free;
42f61420
KB
2810 dev->io_queue = alloc_percpu(unsigned short);
2811 if (!dev->io_queue)
2812 goto free;
b60503ba
MW
2813
2814 INIT_LIST_HEAD(&dev->namespaces);
9ca97374
TH
2815 dev->reset_workfn = nvme_reset_failed_dev;
2816 INIT_WORK(&dev->reset_work, nvme_reset_workfn);
f3db22fe 2817 INIT_WORK(&dev->cpu_work, nvme_cpu_workfn);
b60503ba 2818 dev->pci_dev = pdev;
9a6b9458 2819 pci_set_drvdata(pdev, dev);
cd58ad7d
QSA
2820 result = nvme_set_instance(dev);
2821 if (result)
0877cb0d 2822 goto free;
b60503ba 2823
091b6092
MW
2824 result = nvme_setup_prp_pools(dev);
2825 if (result)
0877cb0d 2826 goto release;
091b6092 2827
fb35e914 2828 kref_init(&dev->kref);
f0b50732 2829 result = nvme_dev_start(dev);
d82e8bfd
KB
2830 if (result) {
2831 if (result == -EBUSY)
2832 goto create_cdev;
0877cb0d 2833 goto release_pools;
d82e8bfd 2834 }
b60503ba 2835
740216fc 2836 result = nvme_dev_add(dev);
d82e8bfd 2837 if (result)
f0b50732 2838 goto shutdown;
740216fc 2839
d82e8bfd 2840 create_cdev:
5e82e952
KB
2841 scnprintf(dev->name, sizeof(dev->name), "nvme%d", dev->instance);
2842 dev->miscdev.minor = MISC_DYNAMIC_MINOR;
2843 dev->miscdev.parent = &pdev->dev;
2844 dev->miscdev.name = dev->name;
2845 dev->miscdev.fops = &nvme_dev_fops;
2846 result = misc_register(&dev->miscdev);
2847 if (result)
2848 goto remove;
2849
d4b4ff8e 2850 dev->initialized = 1;
b60503ba
MW
2851 return 0;
2852
5e82e952
KB
2853 remove:
2854 nvme_dev_remove(dev);
9ac27090 2855 nvme_free_namespaces(dev);
f0b50732
KB
2856 shutdown:
2857 nvme_dev_shutdown(dev);
0877cb0d 2858 release_pools:
a1a5ef99 2859 nvme_free_queues(dev, 0);
091b6092 2860 nvme_release_prp_pools(dev);
0877cb0d
KB
2861 release:
2862 nvme_release_instance(dev);
b60503ba 2863 free:
42f61420 2864 free_percpu(dev->io_queue);
b60503ba
MW
2865 kfree(dev->queues);
2866 kfree(dev->entry);
2867 kfree(dev);
2868 return result;
2869}
2870
f0d54a54
KB
2871static void nvme_reset_notify(struct pci_dev *pdev, bool prepare)
2872{
2873 struct nvme_dev *dev = pci_get_drvdata(pdev);
2874
2875 if (prepare)
2876 nvme_dev_shutdown(dev);
2877 else
2878 nvme_dev_resume(dev);
2879}
2880
09ece142
KB
2881static void nvme_shutdown(struct pci_dev *pdev)
2882{
2883 struct nvme_dev *dev = pci_get_drvdata(pdev);
2884 nvme_dev_shutdown(dev);
2885}
2886
8d85fce7 2887static void nvme_remove(struct pci_dev *pdev)
b60503ba
MW
2888{
2889 struct nvme_dev *dev = pci_get_drvdata(pdev);
9a6b9458
KB
2890
2891 spin_lock(&dev_list_lock);
2892 list_del_init(&dev->node);
2893 spin_unlock(&dev_list_lock);
2894
2895 pci_set_drvdata(pdev, NULL);
2896 flush_work(&dev->reset_work);
f3db22fe 2897 flush_work(&dev->cpu_work);
5e82e952 2898 misc_deregister(&dev->miscdev);
9a6b9458
KB
2899 nvme_dev_remove(dev);
2900 nvme_dev_shutdown(dev);
a1a5ef99 2901 nvme_free_queues(dev, 0);
5a92e700 2902 rcu_barrier();
9a6b9458
KB
2903 nvme_release_instance(dev);
2904 nvme_release_prp_pools(dev);
5e82e952 2905 kref_put(&dev->kref, nvme_free_dev);
b60503ba
MW
2906}
2907
2908/* These functions are yet to be implemented */
2909#define nvme_error_detected NULL
2910#define nvme_dump_registers NULL
2911#define nvme_link_reset NULL
2912#define nvme_slot_reset NULL
2913#define nvme_error_resume NULL
cd638946 2914
671a6018 2915#ifdef CONFIG_PM_SLEEP
cd638946
KB
2916static int nvme_suspend(struct device *dev)
2917{
2918 struct pci_dev *pdev = to_pci_dev(dev);
2919 struct nvme_dev *ndev = pci_get_drvdata(pdev);
2920
2921 nvme_dev_shutdown(ndev);
2922 return 0;
2923}
2924
2925static int nvme_resume(struct device *dev)
2926{
2927 struct pci_dev *pdev = to_pci_dev(dev);
2928 struct nvme_dev *ndev = pci_get_drvdata(pdev);
cd638946 2929
9a6b9458 2930 if (nvme_dev_resume(ndev) && !work_busy(&ndev->reset_work)) {
9ca97374 2931 ndev->reset_workfn = nvme_reset_failed_dev;
9a6b9458
KB
2932 queue_work(nvme_workq, &ndev->reset_work);
2933 }
2934 return 0;
cd638946 2935}
671a6018 2936#endif
cd638946
KB
2937
2938static SIMPLE_DEV_PM_OPS(nvme_dev_pm_ops, nvme_suspend, nvme_resume);
b60503ba 2939
1d352035 2940static const struct pci_error_handlers nvme_err_handler = {
b60503ba
MW
2941 .error_detected = nvme_error_detected,
2942 .mmio_enabled = nvme_dump_registers,
2943 .link_reset = nvme_link_reset,
2944 .slot_reset = nvme_slot_reset,
2945 .resume = nvme_error_resume,
f0d54a54 2946 .reset_notify = nvme_reset_notify,
b60503ba
MW
2947};
2948
2949/* Move to pci_ids.h later */
2950#define PCI_CLASS_STORAGE_EXPRESS 0x010802
2951
6eb0d698 2952static const struct pci_device_id nvme_id_table[] = {
b60503ba
MW
2953 { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
2954 { 0, }
2955};
2956MODULE_DEVICE_TABLE(pci, nvme_id_table);
2957
2958static struct pci_driver nvme_driver = {
2959 .name = "nvme",
2960 .id_table = nvme_id_table,
2961 .probe = nvme_probe,
8d85fce7 2962 .remove = nvme_remove,
09ece142 2963 .shutdown = nvme_shutdown,
cd638946
KB
2964 .driver = {
2965 .pm = &nvme_dev_pm_ops,
2966 },
b60503ba
MW
2967 .err_handler = &nvme_err_handler,
2968};
2969
2970static int __init nvme_init(void)
2971{
0ac13140 2972 int result;
1fa6aead 2973
b9afca3e 2974 init_waitqueue_head(&nvme_kthread_wait);
b60503ba 2975
9a6b9458
KB
2976 nvme_workq = create_singlethread_workqueue("nvme");
2977 if (!nvme_workq)
b9afca3e 2978 return -ENOMEM;
9a6b9458 2979
5c42ea16
KB
2980 result = register_blkdev(nvme_major, "nvme");
2981 if (result < 0)
9a6b9458 2982 goto kill_workq;
5c42ea16 2983 else if (result > 0)
0ac13140 2984 nvme_major = result;
b60503ba 2985
f3db22fe
KB
2986 nvme_nb.notifier_call = &nvme_cpu_notify;
2987 result = register_hotcpu_notifier(&nvme_nb);
1fa6aead
MW
2988 if (result)
2989 goto unregister_blkdev;
f3db22fe
KB
2990
2991 result = pci_register_driver(&nvme_driver);
2992 if (result)
2993 goto unregister_hotcpu;
1fa6aead 2994 return 0;
b60503ba 2995
f3db22fe
KB
2996 unregister_hotcpu:
2997 unregister_hotcpu_notifier(&nvme_nb);
1fa6aead 2998 unregister_blkdev:
b60503ba 2999 unregister_blkdev(nvme_major, "nvme");
9a6b9458
KB
3000 kill_workq:
3001 destroy_workqueue(nvme_workq);
b60503ba
MW
3002 return result;
3003}
3004
3005static void __exit nvme_exit(void)
3006{
3007 pci_unregister_driver(&nvme_driver);
f3db22fe 3008 unregister_hotcpu_notifier(&nvme_nb);
b60503ba 3009 unregister_blkdev(nvme_major, "nvme");
9a6b9458 3010 destroy_workqueue(nvme_workq);
b9afca3e 3011 BUG_ON(nvme_thread && !IS_ERR(nvme_thread));
21bd78bc 3012 _nvme_check_size();
b60503ba
MW
3013}
3014
3015MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
3016MODULE_LICENSE("GPL");
6eb0d698 3017MODULE_VERSION("0.9");
b60503ba
MW
3018module_init(nvme_init);
3019module_exit(nvme_exit);