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PCI: Notify driver before and after device reset
[linux-2.6-block.git] / drivers / block / nvme-core.c
CommitLineData
b60503ba
MW		 1/*
2 * NVM Express device driver
6eb0d698 3 * Copyright (c) 2011-2014, Intel Corporation.
b60503ba
MW		 4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
13 *
14 * You should have received a copy of the GNU General Public License along with
15 * this program; if not, write to the Free Software Foundation, Inc.,
16 * 51 Franklin St - Fifth Floor, Boston, MA 02110-1301 USA.
17 */
18
19#include <linux/nvme.h>
20#include <linux/bio.h>
8de05535 21#include <linux/bitops.h>
b60503ba 22#include <linux/blkdev.h>
42f61420 23#include <linux/cpu.h>
fd63e9ce 24#include <linux/delay.h>
b60503ba
MW		 25#include <linux/errno.h>
26#include <linux/fs.h>
27#include <linux/genhd.h>
4cc09e2d 28#include <linux/hdreg.h>
5aff9382 29#include <linux/idr.h>
b60503ba
MW		 30#include <linux/init.h>
31#include <linux/interrupt.h>
32#include <linux/io.h>
33#include <linux/kdev_t.h>
1fa6aead 34#include <linux/kthread.h>
b60503ba
MW		 35#include <linux/kernel.h>
36#include <linux/mm.h>
37#include <linux/module.h>
38#include <linux/moduleparam.h>
39#include <linux/pci.h>
42f61420 40#include <linux/percpu.h>
be7b6275 41#include <linux/poison.h>
c3bfe717 42#include <linux/ptrace.h>
b60503ba
MW		 43#include <linux/sched.h>
44#include <linux/slab.h>
45#include <linux/types.h>
5d0f6131 46#include <scsi/sg.h>
797a796a
HM		 47#include <asm-generic/io-64-nonatomic-lo-hi.h>
48
b60503ba
MW		 49#define NVME_Q_DEPTH 1024
50#define SQ_SIZE(depth) (depth * sizeof(struct nvme_command))
51#define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion))
e85248e5 52#define ADMIN_TIMEOUT (60 * HZ)
edd10d33 53#define IOD_TIMEOUT (4 * NVME_IO_TIMEOUT)
b60503ba 54
b355084a
KB		 55unsigned char io_timeout = 30;
56module_param(io_timeout, byte, 0644);
57MODULE_PARM_DESC(io_timeout, "timeout in seconds for I/O");
b60503ba
MW		 58
59static int nvme_major;
60module_param(nvme_major, int, 0);
61
58ffacb5
MW		 62static int use_threaded_interrupts;
63module_param(use_threaded_interrupts, int, 0);
64
1fa6aead
MW		 65static DEFINE_SPINLOCK(dev_list_lock);
66static LIST_HEAD(dev_list);
67static struct task_struct *nvme_thread;
9a6b9458 68static struct workqueue_struct *nvme_workq;
b9afca3e 69static wait_queue_head_t nvme_kthread_wait;
1fa6aead 70
d4b4ff8e
KB		 71static void nvme_reset_failed_dev(struct work_struct *ws);
72
4d115420
KB		 73struct async_cmd_info {
74 struct kthread_work work;
75 struct kthread_worker *worker;
76 u32 result;
77 int status;
78 void *ctx;
79};
1fa6aead 80
b60503ba
MW		 81/*
82 * An NVM Express queue. Each device has at least two (one for admin
83 * commands and one for I/O commands).
84 */
85struct nvme_queue {
5a92e700 86 struct rcu_head r_head;
b60503ba 87 struct device *q_dmadev;
091b6092 88 struct nvme_dev *dev;
3193f07b 89 char irqname[24]; /* nvme4294967295-65535\0 */
b60503ba
MW		 90 spinlock_t q_lock;
91 struct nvme_command *sq_cmds;
92 volatile struct nvme_completion *cqes;
93 dma_addr_t sq_dma_addr;
94 dma_addr_t cq_dma_addr;
95 wait_queue_head_t sq_full;
1fa6aead 96 wait_queue_t sq_cong_wait;
b60503ba 97 struct bio_list sq_cong;
edd10d33 98 struct list_head iod_bio;
b60503ba
MW		 99 u32 __iomem *q_db;
100 u16 q_depth;
101 u16 cq_vector;
102 u16 sq_head;
103 u16 sq_tail;
104 u16 cq_head;
c30341dc 105 u16 qid;
e9539f47
MW		 106 u8 cq_phase;
107 u8 cqe_seen;
22404274 108 u8 q_suspended;
42f61420 109 cpumask_var_t cpu_mask;
4d115420 110 struct async_cmd_info cmdinfo;
b60503ba
MW		 111 unsigned long cmdid_data[];
112};
113
114/*
115 * Check we didin't inadvertently grow the command struct
116 */
117static inline void _nvme_check_size(void)
118{
119 BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64);
120 BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
121 BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
122 BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
123 BUILD_BUG_ON(sizeof(struct nvme_features) != 64);
f8ebf840 124 BUILD_BUG_ON(sizeof(struct nvme_format_cmd) != 64);
c30341dc 125 BUILD_BUG_ON(sizeof(struct nvme_abort_cmd) != 64);
b60503ba
MW		 126 BUILD_BUG_ON(sizeof(struct nvme_command) != 64);
127 BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != 4096);
128 BUILD_BUG_ON(sizeof(struct nvme_id_ns) != 4096);
129 BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64);
6ecec745 130 BUILD_BUG_ON(sizeof(struct nvme_smart_log) != 512);
b60503ba
MW		 131}
132
edd10d33 133typedef void (*nvme_completion_fn)(struct nvme_queue *, void *,
c2f5b650
MW		 134 struct nvme_completion *);
135
e85248e5 136struct nvme_cmd_info {
c2f5b650
MW		 137 nvme_completion_fn fn;
138 void *ctx;
e85248e5 139 unsigned long timeout;
c30341dc 140 int aborted;
e85248e5
MW		 141};
142
143static struct nvme_cmd_info *nvme_cmd_info(struct nvme_queue *nvmeq)
144{
145 return (void *)&nvmeq->cmdid_data[BITS_TO_LONGS(nvmeq->q_depth)];
146}
147
22404274
KB		 148static unsigned nvme_queue_extra(int depth)
149{
150 return DIV_ROUND_UP(depth, 8) + (depth * sizeof(struct nvme_cmd_info));
151}
152
b60503ba 153/**
714a7a22
MW		 154 * alloc_cmdid() - Allocate a Command ID
155 * @nvmeq: The queue that will be used for this command
156 * @ctx: A pointer that will be passed to the handler
c2f5b650 157 * @handler: The function to call on completion
b60503ba
MW		 158 *
159 * Allocate a Command ID for a queue. The data passed in will
160 * be passed to the completion handler. This is implemented by using
161 * the bottom two bits of the ctx pointer to store the handler ID.
162 * Passing in a pointer that's not 4-byte aligned will cause a BUG.
163 * We can change this if it becomes a problem.
184d2944
MW		 164 *
165 * May be called with local interrupts disabled and the q_lock held,
166 * or with interrupts enabled and no locks held.
b60503ba 167 */
c2f5b650
MW		 168static int alloc_cmdid(struct nvme_queue *nvmeq, void *ctx,
169 nvme_completion_fn handler, unsigned timeout)
b60503ba 170{
e6d15f79 171 int depth = nvmeq->q_depth - 1;
e85248e5 172 struct nvme_cmd_info *info = nvme_cmd_info(nvmeq);
b60503ba
MW		 173 int cmdid;
174
b60503ba
MW		 175 do {
176 cmdid = find_first_zero_bit(nvmeq->cmdid_data, depth);
177 if (cmdid >= depth)
178 return -EBUSY;
179 } while (test_and_set_bit(cmdid, nvmeq->cmdid_data));
180
c2f5b650
MW		 181 info[cmdid].fn = handler;
182 info[cmdid].ctx = ctx;
e85248e5 183 info[cmdid].timeout = jiffies + timeout;
c30341dc 184 info[cmdid].aborted = 0;
b60503ba
MW		 185 return cmdid;
186}
187
188static int alloc_cmdid_killable(struct nvme_queue *nvmeq, void *ctx,
c2f5b650 189 nvme_completion_fn handler, unsigned timeout)
b60503ba
MW		 190{
191 int cmdid;
192 wait_event_killable(nvmeq->sq_full,
e85248e5 193 (cmdid = alloc_cmdid(nvmeq, ctx, handler, timeout)) >= 0);
b60503ba
MW		 194 return (cmdid < 0) ? -EINTR : cmdid;
195}
196
c2f5b650
MW		 197/* Special values must be less than 0x1000 */
198#define CMD_CTX_BASE ((void *)POISON_POINTER_DELTA)
d2d87034
MW		 199#define CMD_CTX_CANCELLED (0x30C + CMD_CTX_BASE)
200#define CMD_CTX_COMPLETED (0x310 + CMD_CTX_BASE)
201#define CMD_CTX_INVALID (0x314 + CMD_CTX_BASE)
00df5cb4 202#define CMD_CTX_FLUSH (0x318 + CMD_CTX_BASE)
c30341dc 203#define CMD_CTX_ABORT (0x31C + CMD_CTX_BASE)
be7b6275 204
edd10d33 205static void special_completion(struct nvme_queue *nvmeq, void *ctx,
c2f5b650
MW		 206 struct nvme_completion *cqe)
207{
208 if (ctx == CMD_CTX_CANCELLED)
209 return;
210 if (ctx == CMD_CTX_FLUSH)
211 return;
c30341dc 212 if (ctx == CMD_CTX_ABORT) {
edd10d33 213 ++nvmeq->dev->abort_limit;
c30341dc
KB		 214 return;
215 }
c2f5b650 216 if (ctx == CMD_CTX_COMPLETED) {
edd10d33 217 dev_warn(nvmeq->q_dmadev,
c2f5b650
MW		 218 "completed id %d twice on queue %d\n",
219 cqe->command_id, le16_to_cpup(&cqe->sq_id));
220 return;
221 }
222 if (ctx == CMD_CTX_INVALID) {
edd10d33 223 dev_warn(nvmeq->q_dmadev,
c2f5b650
MW		 224 "invalid id %d completed on queue %d\n",
225 cqe->command_id, le16_to_cpup(&cqe->sq_id));
226 return;
227 }
228
edd10d33 229 dev_warn(nvmeq->q_dmadev, "Unknown special completion %p\n", ctx);
c2f5b650
MW		 230}
231
edd10d33 232static void async_completion(struct nvme_queue *nvmeq, void *ctx,
4d115420
KB		 233 struct nvme_completion *cqe)
234{
235 struct async_cmd_info *cmdinfo = ctx;
236 cmdinfo->result = le32_to_cpup(&cqe->result);
237 cmdinfo->status = le16_to_cpup(&cqe->status) >> 1;
238 queue_kthread_work(cmdinfo->worker, &cmdinfo->work);
239}
240
184d2944
MW		 241/*
242 * Called with local interrupts disabled and the q_lock held. May not sleep.
243 */
c2f5b650
MW		 244static void *free_cmdid(struct nvme_queue *nvmeq, int cmdid,
245 nvme_completion_fn *fn)
b60503ba 246{
c2f5b650 247 void *ctx;
e85248e5 248 struct nvme_cmd_info *info = nvme_cmd_info(nvmeq);
b60503ba 249
c2f5b650
MW		 250 if (cmdid >= nvmeq->q_depth) {
251 *fn = special_completion;
48e3d398 252 return CMD_CTX_INVALID;
c2f5b650 253 }
859361a2
KB		 254 if (fn)
255 *fn = info[cmdid].fn;
c2f5b650
MW		 256 ctx = info[cmdid].ctx;
257 info[cmdid].fn = special_completion;
e85248e5 258 info[cmdid].ctx = CMD_CTX_COMPLETED;
b60503ba
MW		 259 clear_bit(cmdid, nvmeq->cmdid_data);
260 wake_up(&nvmeq->sq_full);
c2f5b650 261 return ctx;
b60503ba
MW		 262}
263
c2f5b650
MW		 264static void *cancel_cmdid(struct nvme_queue *nvmeq, int cmdid,
265 nvme_completion_fn *fn)
3c0cf138 266{
c2f5b650 267 void *ctx;
e85248e5 268 struct nvme_cmd_info *info = nvme_cmd_info(nvmeq);
c2f5b650
MW		 269 if (fn)
270 *fn = info[cmdid].fn;
271 ctx = info[cmdid].ctx;
272 info[cmdid].fn = special_completion;
e85248e5 273 info[cmdid].ctx = CMD_CTX_CANCELLED;
c2f5b650 274 return ctx;
3c0cf138
MW		 275}
276
5a92e700 277static struct nvme_queue *raw_nvmeq(struct nvme_dev *dev, int qid)
b60503ba 278{
5a92e700 279 return rcu_dereference_raw(dev->queues[qid]);
b60503ba
MW		 280}
281
4f5099af 282static struct nvme_queue *get_nvmeq(struct nvme_dev *dev) __acquires(RCU)
5a92e700 283{
42f61420 284 unsigned queue_id = get_cpu_var(*dev->io_queue);
5a92e700 285 rcu_read_lock();
42f61420 286 return rcu_dereference(dev->queues[queue_id]);
5a92e700
KB		 287}
288
4f5099af 289static void put_nvmeq(struct nvme_queue *nvmeq) __releases(RCU)
b60503ba 290{
5a92e700 291 rcu_read_unlock();
42f61420 292 put_cpu_var(nvmeq->dev->io_queue);
b60503ba
MW		 293}
294
4f5099af
KB		 295static struct nvme_queue *lock_nvmeq(struct nvme_dev *dev, int q_idx)
296 __acquires(RCU)
b60503ba 297{
4f5099af
KB		 298 rcu_read_lock();
299 return rcu_dereference(dev->queues[q_idx]);
300}
301
302static void unlock_nvmeq(struct nvme_queue *nvmeq) __releases(RCU)
303{
304 rcu_read_unlock();
b60503ba
MW		 305}
306
307/**
714a7a22 308 * nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
b60503ba
MW		 309 * @nvmeq: The queue to use
310 * @cmd: The command to send
311 *
312 * Safe to use from interrupt context
313 */
314static int nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd)
315{
316 unsigned long flags;
317 u16 tail;
b60503ba 318 spin_lock_irqsave(&nvmeq->q_lock, flags);
4f5099af
KB		 319 if (nvmeq->q_suspended) {
320 spin_unlock_irqrestore(&nvmeq->q_lock, flags);
321 return -EBUSY;
322 }
b60503ba
MW		 323 tail = nvmeq->sq_tail;
324 memcpy(&nvmeq->sq_cmds[tail], cmd, sizeof(*cmd));
b60503ba
MW		 325 if (++tail == nvmeq->q_depth)
326 tail = 0;
7547881d 327 writel(tail, nvmeq->q_db);
b60503ba
MW		 328 nvmeq->sq_tail = tail;
329 spin_unlock_irqrestore(&nvmeq->q_lock, flags);
330
331 return 0;
332}
333
eca18b23 334static __le64 **iod_list(struct nvme_iod *iod)
e025344c 335{
eca18b23 336 return ((void *)iod) + iod->offset;
e025344c
SMM		 337}
338
eca18b23
MW		 339/*
340 * Will slightly overestimate the number of pages needed. This is OK
341 * as it only leads to a small amount of wasted memory for the lifetime of
342 * the I/O.
343 */
344static int nvme_npages(unsigned size)
345{
346 unsigned nprps = DIV_ROUND_UP(size + PAGE_SIZE, PAGE_SIZE);
347 return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8);
348}
b60503ba 349
eca18b23
MW		 350static struct nvme_iod *
351nvme_alloc_iod(unsigned nseg, unsigned nbytes, gfp_t gfp)
b60503ba 352{
eca18b23
MW		 353 struct nvme_iod *iod = kmalloc(sizeof(struct nvme_iod) +
354 sizeof(__le64 *) * nvme_npages(nbytes) +
355 sizeof(struct scatterlist) * nseg, gfp);
356
357 if (iod) {
358 iod->offset = offsetof(struct nvme_iod, sg[nseg]);
359 iod->npages = -1;
360 iod->length = nbytes;
2b196034 361 iod->nents = 0;
edd10d33 362 iod->first_dma = 0ULL;
6198221f 363 iod->start_time = jiffies;
eca18b23
MW		 364 }
365
366 return iod;
b60503ba
MW		 367}
368
5d0f6131 369void nvme_free_iod(struct nvme_dev *dev, struct nvme_iod *iod)
b60503ba 370{
eca18b23
MW		 371 const int last_prp = PAGE_SIZE / 8 - 1;
372 int i;
373 __le64 **list = iod_list(iod);
374 dma_addr_t prp_dma = iod->first_dma;
375
376 if (iod->npages == 0)
377 dma_pool_free(dev->prp_small_pool, list[0], prp_dma);
378 for (i = 0; i < iod->npages; i++) {
379 __le64 *prp_list = list[i];
380 dma_addr_t next_prp_dma = le64_to_cpu(prp_list[last_prp]);
381 dma_pool_free(dev->prp_page_pool, prp_list, prp_dma);
382 prp_dma = next_prp_dma;
383 }
384 kfree(iod);
b60503ba
MW		 385}
386
6198221f
KB		 387static void nvme_start_io_acct(struct bio *bio)
388{
389 struct gendisk *disk = bio->bi_bdev->bd_disk;
390 const int rw = bio_data_dir(bio);
391 int cpu = part_stat_lock();
392 part_round_stats(cpu, &disk->part0);
393 part_stat_inc(cpu, &disk->part0, ios[rw]);
394 part_stat_add(cpu, &disk->part0, sectors[rw], bio_sectors(bio));
395 part_inc_in_flight(&disk->part0, rw);
396 part_stat_unlock();
397}
398
399static void nvme_end_io_acct(struct bio *bio, unsigned long start_time)
400{
401 struct gendisk *disk = bio->bi_bdev->bd_disk;
402 const int rw = bio_data_dir(bio);
403 unsigned long duration = jiffies - start_time;
404 int cpu = part_stat_lock();
405 part_stat_add(cpu, &disk->part0, ticks[rw], duration);
406 part_round_stats(cpu, &disk->part0);
407 part_dec_in_flight(&disk->part0, rw);
408 part_stat_unlock();
409}
410
edd10d33 411static void bio_completion(struct nvme_queue *nvmeq, void *ctx,
b60503ba
MW		 412 struct nvme_completion *cqe)
413{
eca18b23
MW		 414 struct nvme_iod *iod = ctx;
415 struct bio *bio = iod->private;
b60503ba
MW		 416 u16 status = le16_to_cpup(&cqe->status) >> 1;
417
edd10d33
KB		 418 if (unlikely(status)) {
419 if (!(status & NVME_SC_DNR ||
420 bio->bi_rw & REQ_FAILFAST_MASK) &&
421 (jiffies - iod->start_time) < IOD_TIMEOUT) {
422 if (!waitqueue_active(&nvmeq->sq_full))
423 add_wait_queue(&nvmeq->sq_full,
424 &nvmeq->sq_cong_wait);
425 list_add_tail(&iod->node, &nvmeq->iod_bio);
426 wake_up(&nvmeq->sq_full);
427 return;
428 }
429 }
9e59d091 430 if (iod->nents) {
edd10d33 431 dma_unmap_sg(nvmeq->q_dmadev, iod->sg, iod->nents,
b60503ba 432 bio_data_dir(bio) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
9e59d091
KB		 433 nvme_end_io_acct(bio, iod->start_time);
434 }
edd10d33 435 nvme_free_iod(nvmeq->dev, iod);
427e9708 436 if (status)
1ad2f893 437 bio_endio(bio, -EIO);
427e9708 438 else
1ad2f893 439 bio_endio(bio, 0);
b60503ba
MW		 440}
441
184d2944 442/* length is in bytes. gfp flags indicates whether we may sleep. */
edd10d33
KB		 443int nvme_setup_prps(struct nvme_dev *dev, struct nvme_iod *iod, int total_len,
444 gfp_t gfp)
ff22b54f 445{
99802a7a 446 struct dma_pool *pool;
eca18b23
MW		 447 int length = total_len;
448 struct scatterlist *sg = iod->sg;
ff22b54f
MW		 449 int dma_len = sg_dma_len(sg);
450 u64 dma_addr = sg_dma_address(sg);
451 int offset = offset_in_page(dma_addr);
e025344c 452 __le64 *prp_list;
eca18b23 453 __le64 **list = iod_list(iod);
e025344c 454 dma_addr_t prp_dma;
eca18b23 455 int nprps, i;
ff22b54f 456
ff22b54f
MW		 457 length -= (PAGE_SIZE - offset);
458 if (length <= 0)
eca18b23 459 return total_len;
ff22b54f
MW		 460
461 dma_len -= (PAGE_SIZE - offset);
462 if (dma_len) {
463 dma_addr += (PAGE_SIZE - offset);
464 } else {
465 sg = sg_next(sg);
466 dma_addr = sg_dma_address(sg);
467 dma_len = sg_dma_len(sg);
468 }
469
470 if (length <= PAGE_SIZE) {
edd10d33 471 iod->first_dma = dma_addr;
eca18b23 472 return total_len;
e025344c
SMM		 473 }
474
475 nprps = DIV_ROUND_UP(length, PAGE_SIZE);
99802a7a
MW		 476 if (nprps <= (256 / 8)) {
477 pool = dev->prp_small_pool;
eca18b23 478 iod->npages = 0;
99802a7a
MW		 479 } else {
480 pool = dev->prp_page_pool;
eca18b23 481 iod->npages = 1;
99802a7a
MW		 482 }
483
b77954cb
MW		 484 prp_list = dma_pool_alloc(pool, gfp, &prp_dma);
485 if (!prp_list) {
edd10d33 486 iod->first_dma = dma_addr;
eca18b23
MW		 487 iod->npages = -1;
488 return (total_len - length) + PAGE_SIZE;
b77954cb 489 }
eca18b23
MW		 490 list[0] = prp_list;
491 iod->first_dma = prp_dma;
e025344c
SMM		 492 i = 0;
493 for (;;) {
7523d834 494 if (i == PAGE_SIZE / 8) {
e025344c 495 __le64 *old_prp_list = prp_list;
b77954cb 496 prp_list = dma_pool_alloc(pool, gfp, &prp_dma);
eca18b23
MW		 497 if (!prp_list)
498 return total_len - length;
499 list[iod->npages++] = prp_list;
7523d834
MW		 500 prp_list[0] = old_prp_list[i - 1];
501 old_prp_list[i - 1] = cpu_to_le64(prp_dma);
502 i = 1;
e025344c
SMM		 503 }
504 prp_list[i++] = cpu_to_le64(dma_addr);
505 dma_len -= PAGE_SIZE;
506 dma_addr += PAGE_SIZE;
507 length -= PAGE_SIZE;
508 if (length <= 0)
509 break;
510 if (dma_len > 0)
511 continue;
512 BUG_ON(dma_len < 0);
513 sg = sg_next(sg);
514 dma_addr = sg_dma_address(sg);
515 dma_len = sg_dma_len(sg);
ff22b54f
MW		 516 }
517
eca18b23 518 return total_len;
ff22b54f
MW		 519}
520
427e9708 521static int nvme_split_and_submit(struct bio *bio, struct nvme_queue *nvmeq,
20d0189b 522 int len)
427e9708 523{
20d0189b
KO		 524 struct bio *split = bio_split(bio, len >> 9, GFP_ATOMIC, NULL);
525 if (!split)
427e9708
KB		 526 return -ENOMEM;
527
20d0189b
KO		 528 bio_chain(split, bio);
529
edd10d33 530 if (!waitqueue_active(&nvmeq->sq_full))
427e9708 531 add_wait_queue(&nvmeq->sq_full, &nvmeq->sq_cong_wait);
20d0189b
KO		 532 bio_list_add(&nvmeq->sq_cong, split);
533 bio_list_add(&nvmeq->sq_cong, bio);
edd10d33 534 wake_up(&nvmeq->sq_full);
427e9708
KB		 535
536 return 0;
537}
538
1ad2f893
MW		 539/* NVMe scatterlists require no holes in the virtual address */
540#define BIOVEC_NOT_VIRT_MERGEABLE(vec1, vec2) ((vec2)->bv_offset || \
541 (((vec1)->bv_offset + (vec1)->bv_len) % PAGE_SIZE))
542
427e9708 543static int nvme_map_bio(struct nvme_queue *nvmeq, struct nvme_iod *iod,
b60503ba
MW		 544 struct bio *bio, enum dma_data_direction dma_dir, int psegs)
545{
7988613b
KO		 546 struct bio_vec bvec, bvprv;
547 struct bvec_iter iter;
76830840 548 struct scatterlist *sg = NULL;
7988613b
KO		 549 int length = 0, nsegs = 0, split_len = bio->bi_iter.bi_size;
550 int first = 1;
159b67d7
KB		 551
552 if (nvmeq->dev->stripe_size)
553 split_len = nvmeq->dev->stripe_size -
4f024f37
KO		 554 ((bio->bi_iter.bi_sector << 9) &
555 (nvmeq->dev->stripe_size - 1));
b60503ba 556
eca18b23 557 sg_init_table(iod->sg, psegs);
7988613b
KO		 558 bio_for_each_segment(bvec, bio, iter) {
559 if (!first && BIOVEC_PHYS_MERGEABLE(&bvprv, &bvec)) {
560 sg->length += bvec.bv_len;
76830840 561 } else {
7988613b
KO		 562 if (!first && BIOVEC_NOT_VIRT_MERGEABLE(&bvprv, &bvec))
563 return nvme_split_and_submit(bio, nvmeq,
20d0189b 564 length);
427e9708 565
eca18b23 566 sg = sg ? sg + 1 : iod->sg;
7988613b
KO		 567 sg_set_page(sg, bvec.bv_page,
568 bvec.bv_len, bvec.bv_offset);
76830840
MW		 569 nsegs++;
570 }
159b67d7 571
7988613b 572 if (split_len - length < bvec.bv_len)
20d0189b 573 return nvme_split_and_submit(bio, nvmeq, split_len);
7988613b 574 length += bvec.bv_len;
76830840 575 bvprv = bvec;
7988613b 576 first = 0;
b60503ba 577 }
eca18b23 578 iod->nents = nsegs;
76830840 579 sg_mark_end(sg);
427e9708 580 if (dma_map_sg(nvmeq->q_dmadev, iod->sg, iod->nents, dma_dir) == 0)
1ad2f893 581 return -ENOMEM;
427e9708 582
4f024f37 583 BUG_ON(length != bio->bi_iter.bi_size);
1ad2f893 584 return length;
b60503ba
MW		 585}
586
0e5e4f0e
KB		 587static int nvme_submit_discard(struct nvme_queue *nvmeq, struct nvme_ns *ns,
588 struct bio *bio, struct nvme_iod *iod, int cmdid)
589{
edd10d33
KB		 590 struct nvme_dsm_range *range =
591 (struct nvme_dsm_range *)iod_list(iod)[0];
0e5e4f0e
KB		 592 struct nvme_command *cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail];
593
0e5e4f0e 594 range->cattr = cpu_to_le32(0);
4f024f37
KO		 595 range->nlb = cpu_to_le32(bio->bi_iter.bi_size >> ns->lba_shift);
596 range->slba = cpu_to_le64(nvme_block_nr(ns, bio->bi_iter.bi_sector));
0e5e4f0e
KB		 597
598 memset(cmnd, 0, sizeof(*cmnd));
599 cmnd->dsm.opcode = nvme_cmd_dsm;
600 cmnd->dsm.command_id = cmdid;
601 cmnd->dsm.nsid = cpu_to_le32(ns->ns_id);
602 cmnd->dsm.prp1 = cpu_to_le64(iod->first_dma);
603 cmnd->dsm.nr = 0;
604 cmnd->dsm.attributes = cpu_to_le32(NVME_DSMGMT_AD);
605
606 if (++nvmeq->sq_tail == nvmeq->q_depth)
607 nvmeq->sq_tail = 0;
608 writel(nvmeq->sq_tail, nvmeq->q_db);
609
610 return 0;
611}
612
00df5cb4
MW		 613static int nvme_submit_flush(struct nvme_queue *nvmeq, struct nvme_ns *ns,
614 int cmdid)
615{
616 struct nvme_command *cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail];
617
618 memset(cmnd, 0, sizeof(*cmnd));
619 cmnd->common.opcode = nvme_cmd_flush;
620 cmnd->common.command_id = cmdid;
621 cmnd->common.nsid = cpu_to_le32(ns->ns_id);
622
623 if (++nvmeq->sq_tail == nvmeq->q_depth)
624 nvmeq->sq_tail = 0;
625 writel(nvmeq->sq_tail, nvmeq->q_db);
626
627 return 0;
628}
629
5d0f6131 630int nvme_submit_flush_data(struct nvme_queue *nvmeq, struct nvme_ns *ns)
00df5cb4
MW		 631{
632 int cmdid = alloc_cmdid(nvmeq, (void *)CMD_CTX_FLUSH,
ff976d72 633 special_completion, NVME_IO_TIMEOUT);
00df5cb4
MW		 634 if (unlikely(cmdid < 0))
635 return cmdid;
636
637 return nvme_submit_flush(nvmeq, ns, cmdid);
638}
639
edd10d33 640static int nvme_submit_iod(struct nvme_queue *nvmeq, struct nvme_iod *iod)
b60503ba 641{
edd10d33
KB		 642 struct bio *bio = iod->private;
643 struct nvme_ns *ns = bio->bi_bdev->bd_disk->private_data;
ff22b54f 644 struct nvme_command *cmnd;
edd10d33 645 int cmdid;
b60503ba
MW		 646 u16 control;
647 u32 dsmgmt;
00df5cb4 648
ff976d72 649 cmdid = alloc_cmdid(nvmeq, iod, bio_completion, NVME_IO_TIMEOUT);
b60503ba 650 if (unlikely(cmdid < 0))
edd10d33 651 return cmdid;
b60503ba 652
edd10d33
KB		 653 if (bio->bi_rw & REQ_DISCARD)
654 return nvme_submit_discard(nvmeq, ns, bio, iod, cmdid);
655 if ((bio->bi_rw & REQ_FLUSH) && !iod->nents)
00df5cb4
MW		 656 return nvme_submit_flush(nvmeq, ns, cmdid);
657
b60503ba
MW		 658 control = 0;
659 if (bio->bi_rw & REQ_FUA)
660 control |= NVME_RW_FUA;
661 if (bio->bi_rw & (REQ_FAILFAST_DEV | REQ_RAHEAD))
662 control |= NVME_RW_LR;
663
664 dsmgmt = 0;
665 if (bio->bi_rw & REQ_RAHEAD)
666 dsmgmt |= NVME_RW_DSM_FREQ_PREFETCH;
667
ff22b54f 668 cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail];
b8deb62c 669 memset(cmnd, 0, sizeof(*cmnd));
b60503ba 670
edd10d33 671 cmnd->rw.opcode = bio_data_dir(bio) ? nvme_cmd_write : nvme_cmd_read;
ff22b54f
MW		 672 cmnd->rw.command_id = cmdid;
673 cmnd->rw.nsid = cpu_to_le32(ns->ns_id);
edd10d33
KB		 674 cmnd->rw.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
675 cmnd->rw.prp2 = cpu_to_le64(iod->first_dma);
4f024f37 676 cmnd->rw.slba = cpu_to_le64(nvme_block_nr(ns, bio->bi_iter.bi_sector));
edd10d33
KB		 677 cmnd->rw.length =
678 cpu_to_le16((bio->bi_iter.bi_size >> ns->lba_shift) - 1);
ff22b54f
MW		 679 cmnd->rw.control = cpu_to_le16(control);
680 cmnd->rw.dsmgmt = cpu_to_le32(dsmgmt);
b60503ba 681
b60503ba
MW		 682 if (++nvmeq->sq_tail == nvmeq->q_depth)
683 nvmeq->sq_tail = 0;
7547881d 684 writel(nvmeq->sq_tail, nvmeq->q_db);
b60503ba 685
1974b1ae 686 return 0;
edd10d33
KB		 687}
688
689/*
690 * Called with local interrupts disabled and the q_lock held. May not sleep.
691 */
692static int nvme_submit_bio_queue(struct nvme_queue *nvmeq, struct nvme_ns *ns,
693 struct bio *bio)
694{
695 struct nvme_iod *iod;
696 int psegs = bio_phys_segments(ns->queue, bio);
697 int result;
698
699 if ((bio->bi_rw & REQ_FLUSH) && psegs) {
700 result = nvme_submit_flush_data(nvmeq, ns);
701 if (result)
702 return result;
703 }
704
705 iod = nvme_alloc_iod(psegs, bio->bi_iter.bi_size, GFP_ATOMIC);
706 if (!iod)
707 return -ENOMEM;
708
709 iod->private = bio;
710 if (bio->bi_rw & REQ_DISCARD) {
711 void *range;
712 /*
713 * We reuse the small pool to allocate the 16-byte range here
714 * as it is not worth having a special pool for these or
715 * additional cases to handle freeing the iod.
716 */
717 range = dma_pool_alloc(nvmeq->dev->prp_small_pool,
718 GFP_ATOMIC,
719 &iod->first_dma);
720 if (!range) {
721 result = -ENOMEM;
722 goto free_iod;
723 }
724 iod_list(iod)[0] = (__le64 *)range;
725 iod->npages = 0;
726 } else if (psegs) {
727 result = nvme_map_bio(nvmeq, iod, bio,
728 bio_data_dir(bio) ? DMA_TO_DEVICE : DMA_FROM_DEVICE,
729 psegs);
730 if (result <= 0)
731 goto free_iod;
732 if (nvme_setup_prps(nvmeq->dev, iod, result, GFP_ATOMIC) !=
733 result) {
734 result = -ENOMEM;
735 goto free_iod;
736 }
737 nvme_start_io_acct(bio);
738 }
739 if (unlikely(nvme_submit_iod(nvmeq, iod))) {
740 if (!waitqueue_active(&nvmeq->sq_full))
741 add_wait_queue(&nvmeq->sq_full, &nvmeq->sq_cong_wait);
742 list_add_tail(&iod->node, &nvmeq->iod_bio);
743 }
744 return 0;
1974b1ae 745
eca18b23
MW		 746 free_iod:
747 nvme_free_iod(nvmeq->dev, iod);
eeee3226 748 return result;
b60503ba
MW		 749}
750
e9539f47 751static int nvme_process_cq(struct nvme_queue *nvmeq)
b60503ba 752{
82123460 753 u16 head, phase;
b60503ba 754
b60503ba 755 head = nvmeq->cq_head;
82123460 756 phase = nvmeq->cq_phase;
b60503ba
MW		 757
758 for (;;) {
c2f5b650
MW		 759 void *ctx;
760 nvme_completion_fn fn;
b60503ba 761 struct nvme_completion cqe = nvmeq->cqes[head];
82123460 762 if ((le16_to_cpu(cqe.status) & 1) != phase)
b60503ba
MW		 763 break;
764 nvmeq->sq_head = le16_to_cpu(cqe.sq_head);
765 if (++head == nvmeq->q_depth) {
766 head = 0;
82123460 767 phase = !phase;
b60503ba
MW		 768 }
769
c2f5b650 770 ctx = free_cmdid(nvmeq, cqe.command_id, &fn);
edd10d33 771 fn(nvmeq, ctx, &cqe);
b60503ba
MW		 772 }
773
774 /* If the controller ignores the cq head doorbell and continuously
775 * writes to the queue, it is theoretically possible to wrap around
776 * the queue twice and mistakenly return IRQ_NONE. Linux only
777 * requires that 0.1% of your interrupts are handled, so this isn't
778 * a big problem.
779 */
82123460 780 if (head == nvmeq->cq_head && phase == nvmeq->cq_phase)
e9539f47 781 return 0;
b60503ba 782
b80d5ccc 783 writel(head, nvmeq->q_db + nvmeq->dev->db_stride);
b60503ba 784 nvmeq->cq_head = head;
82123460 785 nvmeq->cq_phase = phase;
b60503ba 786
e9539f47
MW		 787 nvmeq->cqe_seen = 1;
788 return 1;
b60503ba
MW		 789}
790
7d822457
MW		 791static void nvme_make_request(struct request_queue *q, struct bio *bio)
792{
793 struct nvme_ns *ns = q->queuedata;
794 struct nvme_queue *nvmeq = get_nvmeq(ns->dev);
795 int result = -EBUSY;
796
cd638946
KB		 797 if (!nvmeq) {
798 put_nvmeq(NULL);
799 bio_endio(bio, -EIO);
800 return;
801 }
802
7d822457 803 spin_lock_irq(&nvmeq->q_lock);
22404274 804 if (!nvmeq->q_suspended && bio_list_empty(&nvmeq->sq_cong))
7d822457
MW		 805 result = nvme_submit_bio_queue(nvmeq, ns, bio);
806 if (unlikely(result)) {
edd10d33 807 if (!waitqueue_active(&nvmeq->sq_full))
7d822457
MW		 808 add_wait_queue(&nvmeq->sq_full, &nvmeq->sq_cong_wait);
809 bio_list_add(&nvmeq->sq_cong, bio);
810 }
811
812 nvme_process_cq(nvmeq);
813 spin_unlock_irq(&nvmeq->q_lock);
814 put_nvmeq(nvmeq);
815}
816
b60503ba 817static irqreturn_t nvme_irq(int irq, void *data)
58ffacb5
MW		 818{
819 irqreturn_t result;
820 struct nvme_queue *nvmeq = data;
821 spin_lock(&nvmeq->q_lock);
e9539f47
MW		 822 nvme_process_cq(nvmeq);
823 result = nvmeq->cqe_seen ? IRQ_HANDLED : IRQ_NONE;
824 nvmeq->cqe_seen = 0;
58ffacb5
MW		 825 spin_unlock(&nvmeq->q_lock);
826 return result;
827}
828
829static irqreturn_t nvme_irq_check(int irq, void *data)
830{
831 struct nvme_queue *nvmeq = data;
832 struct nvme_completion cqe = nvmeq->cqes[nvmeq->cq_head];
833 if ((le16_to_cpu(cqe.status) & 1) != nvmeq->cq_phase)
834 return IRQ_NONE;
835 return IRQ_WAKE_THREAD;
836}
837
3c0cf138
MW		 838static void nvme_abort_command(struct nvme_queue *nvmeq, int cmdid)
839{
840 spin_lock_irq(&nvmeq->q_lock);
c2f5b650 841 cancel_cmdid(nvmeq, cmdid, NULL);
3c0cf138
MW		 842 spin_unlock_irq(&nvmeq->q_lock);
843}
844
c2f5b650
MW		 845struct sync_cmd_info {
846 struct task_struct *task;
847 u32 result;
848 int status;
849};
850
edd10d33 851static void sync_completion(struct nvme_queue *nvmeq, void *ctx,
c2f5b650
MW		 852 struct nvme_completion *cqe)
853{
854 struct sync_cmd_info *cmdinfo = ctx;
855 cmdinfo->result = le32_to_cpup(&cqe->result);
856 cmdinfo->status = le16_to_cpup(&cqe->status) >> 1;
857 wake_up_process(cmdinfo->task);
858}
859
b60503ba
MW		 860/*
861 * Returns 0 on success. If the result is negative, it's a Linux error code;
862 * if the result is positive, it's an NVM Express status code
863 */
4f5099af
KB		 864static int nvme_submit_sync_cmd(struct nvme_dev *dev, int q_idx,
865 struct nvme_command *cmd,
5d0f6131 866 u32 *result, unsigned timeout)
b60503ba 867{
4f5099af 868 int cmdid, ret;
b60503ba 869 struct sync_cmd_info cmdinfo;
4f5099af
KB		 870 struct nvme_queue *nvmeq;
871
872 nvmeq = lock_nvmeq(dev, q_idx);
873 if (!nvmeq) {
874 unlock_nvmeq(nvmeq);
875 return -ENODEV;
876 }
b60503ba
MW		 877
878 cmdinfo.task = current;
879 cmdinfo.status = -EINTR;
880
4f5099af
KB		 881 cmdid = alloc_cmdid(nvmeq, &cmdinfo, sync_completion, timeout);
882 if (cmdid < 0) {
883 unlock_nvmeq(nvmeq);
b60503ba 884 return cmdid;
4f5099af 885 }
b60503ba
MW		 886 cmd->common.command_id = cmdid;
887
3c0cf138 888 set_current_state(TASK_KILLABLE);
4f5099af
KB		 889 ret = nvme_submit_cmd(nvmeq, cmd);
890 if (ret) {
891 free_cmdid(nvmeq, cmdid, NULL);
892 unlock_nvmeq(nvmeq);
893 set_current_state(TASK_RUNNING);
894 return ret;
895 }
896 unlock_nvmeq(nvmeq);
78f8d257 897 schedule_timeout(timeout);
b60503ba 898
3c0cf138 899 if (cmdinfo.status == -EINTR) {
4f5099af
KB		 900 nvmeq = lock_nvmeq(dev, q_idx);
901 if (nvmeq)
902 nvme_abort_command(nvmeq, cmdid);
903 unlock_nvmeq(nvmeq);
3c0cf138
MW		 904 return -EINTR;
905 }
906
b60503ba
MW		 907 if (result)
908 *result = cmdinfo.result;
909
910 return cmdinfo.status;
911}
912
4d115420
KB		 913static int nvme_submit_async_cmd(struct nvme_queue *nvmeq,
914 struct nvme_command *cmd,
915 struct async_cmd_info *cmdinfo, unsigned timeout)
916{
917 int cmdid;
918
919 cmdid = alloc_cmdid_killable(nvmeq, cmdinfo, async_completion, timeout);
920 if (cmdid < 0)
921 return cmdid;
922 cmdinfo->status = -EINTR;
923 cmd->common.command_id = cmdid;
4f5099af 924 return nvme_submit_cmd(nvmeq, cmd);
4d115420
KB		 925}
926
5d0f6131 927int nvme_submit_admin_cmd(struct nvme_dev *dev, struct nvme_command *cmd,
b60503ba
MW		 928 u32 *result)
929{
4f5099af
KB		 930 return nvme_submit_sync_cmd(dev, 0, cmd, result, ADMIN_TIMEOUT);
931}
932
933int nvme_submit_io_cmd(struct nvme_dev *dev, struct nvme_command *cmd,
934 u32 *result)
935{
936 return nvme_submit_sync_cmd(dev, smp_processor_id() + 1, cmd, result,
937 NVME_IO_TIMEOUT);
b60503ba
MW		 938}
939
4d115420
KB		 940static int nvme_submit_admin_cmd_async(struct nvme_dev *dev,
941 struct nvme_command *cmd, struct async_cmd_info *cmdinfo)
942{
5a92e700 943 return nvme_submit_async_cmd(raw_nvmeq(dev, 0), cmd, cmdinfo,
4d115420
KB		 944 ADMIN_TIMEOUT);
945}
946
b60503ba
MW		 947static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
948{
949 int status;
950 struct nvme_command c;
951
952 memset(&c, 0, sizeof(c));
953 c.delete_queue.opcode = opcode;
954 c.delete_queue.qid = cpu_to_le16(id);
955
956 status = nvme_submit_admin_cmd(dev, &c, NULL);
957 if (status)
958 return -EIO;
959 return 0;
960}
961
962static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
963 struct nvme_queue *nvmeq)
964{
965 int status;
966 struct nvme_command c;
967 int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED;
968
969 memset(&c, 0, sizeof(c));
970 c.create_cq.opcode = nvme_admin_create_cq;
971 c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
972 c.create_cq.cqid = cpu_to_le16(qid);
973 c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
974 c.create_cq.cq_flags = cpu_to_le16(flags);
975 c.create_cq.irq_vector = cpu_to_le16(nvmeq->cq_vector);
976
977 status = nvme_submit_admin_cmd(dev, &c, NULL);
978 if (status)
979 return -EIO;
980 return 0;
981}
982
983static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
984 struct nvme_queue *nvmeq)
985{
986 int status;
987 struct nvme_command c;
988 int flags = NVME_QUEUE_PHYS_CONTIG | NVME_SQ_PRIO_MEDIUM;
989
990 memset(&c, 0, sizeof(c));
991 c.create_sq.opcode = nvme_admin_create_sq;
992 c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
993 c.create_sq.sqid = cpu_to_le16(qid);
994 c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
995 c.create_sq.sq_flags = cpu_to_le16(flags);
996 c.create_sq.cqid = cpu_to_le16(qid);
997
998 status = nvme_submit_admin_cmd(dev, &c, NULL);
999 if (status)
1000 return -EIO;
1001 return 0;
1002}
1003
1004static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
1005{
1006 return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
1007}
1008
1009static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
1010{
1011 return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
1012}
1013
5d0f6131 1014int nvme_identify(struct nvme_dev *dev, unsigned nsid, unsigned cns,
bc5fc7e4
MW		 1015 dma_addr_t dma_addr)
1016{
1017 struct nvme_command c;
1018
1019 memset(&c, 0, sizeof(c));
1020 c.identify.opcode = nvme_admin_identify;
1021 c.identify.nsid = cpu_to_le32(nsid);
1022 c.identify.prp1 = cpu_to_le64(dma_addr);
1023 c.identify.cns = cpu_to_le32(cns);
1024
1025 return nvme_submit_admin_cmd(dev, &c, NULL);
1026}
1027
5d0f6131 1028int nvme_get_features(struct nvme_dev *dev, unsigned fid, unsigned nsid,
08df1e05 1029 dma_addr_t dma_addr, u32 *result)
bc5fc7e4
MW		 1030{
1031 struct nvme_command c;
1032
1033 memset(&c, 0, sizeof(c));
1034 c.features.opcode = nvme_admin_get_features;
a42cecce 1035 c.features.nsid = cpu_to_le32(nsid);
bc5fc7e4
MW		 1036 c.features.prp1 = cpu_to_le64(dma_addr);
1037 c.features.fid = cpu_to_le32(fid);
bc5fc7e4 1038
08df1e05 1039 return nvme_submit_admin_cmd(dev, &c, result);
df348139
MW		 1040}
1041
5d0f6131
VV		 1042int nvme_set_features(struct nvme_dev *dev, unsigned fid, unsigned dword11,
1043 dma_addr_t dma_addr, u32 *result)
df348139
MW		 1044{
1045 struct nvme_command c;
1046
1047 memset(&c, 0, sizeof(c));
1048 c.features.opcode = nvme_admin_set_features;
1049 c.features.prp1 = cpu_to_le64(dma_addr);
1050 c.features.fid = cpu_to_le32(fid);
1051 c.features.dword11 = cpu_to_le32(dword11);
1052
bc5fc7e4
MW		 1053 return nvme_submit_admin_cmd(dev, &c, result);
1054}
1055
c30341dc
KB		 1056/**
1057 * nvme_abort_cmd - Attempt aborting a command
1058 * @cmdid: Command id of a timed out IO
1059 * @queue: The queue with timed out IO
1060 *
1061 * Schedule controller reset if the command was already aborted once before and
1062 * still hasn't been returned to the driver, or if this is the admin queue.
1063 */
1064static void nvme_abort_cmd(int cmdid, struct nvme_queue *nvmeq)
1065{
1066 int a_cmdid;
1067 struct nvme_command cmd;
1068 struct nvme_dev *dev = nvmeq->dev;
1069 struct nvme_cmd_info *info = nvme_cmd_info(nvmeq);
5a92e700 1070 struct nvme_queue *adminq;
c30341dc
KB		 1071
1072 if (!nvmeq->qid || info[cmdid].aborted) {
1073 if (work_busy(&dev->reset_work))
1074 return;
1075 list_del_init(&dev->node);
1076 dev_warn(&dev->pci_dev->dev,
1077 "I/O %d QID %d timeout, reset controller\n", cmdid,
1078 nvmeq->qid);
9ca97374 1079 dev->reset_workfn = nvme_reset_failed_dev;
c30341dc
KB		 1080 queue_work(nvme_workq, &dev->reset_work);
1081 return;
1082 }
1083
1084 if (!dev->abort_limit)
1085 return;
1086
5a92e700
KB		 1087 adminq = rcu_dereference(dev->queues[0]);
1088 a_cmdid = alloc_cmdid(adminq, CMD_CTX_ABORT, special_completion,
c30341dc
KB		 1089 ADMIN_TIMEOUT);
1090 if (a_cmdid < 0)
1091 return;
1092
1093 memset(&cmd, 0, sizeof(cmd));
1094 cmd.abort.opcode = nvme_admin_abort_cmd;
1095 cmd.abort.cid = cmdid;
1096 cmd.abort.sqid = cpu_to_le16(nvmeq->qid);
1097 cmd.abort.command_id = a_cmdid;
1098
1099 --dev->abort_limit;
1100 info[cmdid].aborted = 1;
1101 info[cmdid].timeout = jiffies + ADMIN_TIMEOUT;
1102
1103 dev_warn(nvmeq->q_dmadev, "Aborting I/O %d QID %d\n", cmdid,
1104 nvmeq->qid);
5a92e700 1105 nvme_submit_cmd(adminq, &cmd);
c30341dc
KB		 1106}
1107
a09115b2
MW		 1108/**
1109 * nvme_cancel_ios - Cancel outstanding I/Os
1110 * @queue: The queue to cancel I/Os on
1111 * @timeout: True to only cancel I/Os which have timed out
1112 */
1113static void nvme_cancel_ios(struct nvme_queue *nvmeq, bool timeout)
1114{
1115 int depth = nvmeq->q_depth - 1;
1116 struct nvme_cmd_info *info = nvme_cmd_info(nvmeq);
1117 unsigned long now = jiffies;
1118 int cmdid;
1119
1120 for_each_set_bit(cmdid, nvmeq->cmdid_data, depth) {
1121 void *ctx;
1122 nvme_completion_fn fn;
1123 static struct nvme_completion cqe = {
af2d9ca7 1124 .status = cpu_to_le16(NVME_SC_ABORT_REQ << 1),
a09115b2
MW		 1125 };
1126
1127 if (timeout && !time_after(now, info[cmdid].timeout))
1128 continue;
053ab702
KB		 1129 if (info[cmdid].ctx == CMD_CTX_CANCELLED)
1130 continue;
c30341dc
KB		 1131 if (timeout && nvmeq->dev->initialized) {
1132 nvme_abort_cmd(cmdid, nvmeq);
1133 continue;
1134 }
1135 dev_warn(nvmeq->q_dmadev, "Cancelling I/O %d QID %d\n", cmdid,
1136 nvmeq->qid);
a09115b2 1137 ctx = cancel_cmdid(nvmeq, cmdid, &fn);
edd10d33 1138 fn(nvmeq, ctx, &cqe);
a09115b2
MW		 1139 }
1140}
1141
5a92e700 1142static void nvme_free_queue(struct rcu_head *r)
9e866774 1143{
5a92e700
KB		 1144 struct nvme_queue *nvmeq = container_of(r, struct nvme_queue, r_head);
1145
22404274
KB		 1146 spin_lock_irq(&nvmeq->q_lock);
1147 while (bio_list_peek(&nvmeq->sq_cong)) {
1148 struct bio *bio = bio_list_pop(&nvmeq->sq_cong);
1149 bio_endio(bio, -EIO);
1150 }
edd10d33
KB		 1151 while (!list_empty(&nvmeq->iod_bio)) {
1152 static struct nvme_completion cqe = {
1153 .status = cpu_to_le16(
1154 (NVME_SC_ABORT_REQ | NVME_SC_DNR) << 1),
1155 };
1156 struct nvme_iod *iod = list_first_entry(&nvmeq->iod_bio,
1157 struct nvme_iod,
1158 node);
1159 list_del(&iod->node);
1160 bio_completion(nvmeq, iod, &cqe);
1161 }
22404274
KB		 1162 spin_unlock_irq(&nvmeq->q_lock);
1163
9e866774
MW		 1164 dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth),
1165 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
1166 dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth),
1167 nvmeq->sq_cmds, nvmeq->sq_dma_addr);
42f61420
KB		 1168 if (nvmeq->qid)
1169 free_cpumask_var(nvmeq->cpu_mask);
9e866774
MW		 1170 kfree(nvmeq);
1171}
1172
a1a5ef99 1173static void nvme_free_queues(struct nvme_dev *dev, int lowest)
22404274
KB		 1174{
1175 int i;
1176
a1a5ef99 1177 for (i = dev->queue_count - 1; i >= lowest; i--) {
5a92e700
KB		 1178 struct nvme_queue *nvmeq = raw_nvmeq(dev, i);
1179 rcu_assign_pointer(dev->queues[i], NULL);
1180 call_rcu(&nvmeq->r_head, nvme_free_queue);
22404274 1181 dev->queue_count--;
22404274
KB		 1182 }
1183}
1184
4d115420
KB		 1185/**
1186 * nvme_suspend_queue - put queue into suspended state
1187 * @nvmeq - queue to suspend
1188 *
1189 * Returns 1 if already suspended, 0 otherwise.
1190 */
1191static int nvme_suspend_queue(struct nvme_queue *nvmeq)
b60503ba 1192{
4d115420 1193 int vector = nvmeq->dev->entry[nvmeq->cq_vector].vector;
b60503ba 1194
a09115b2 1195 spin_lock_irq(&nvmeq->q_lock);
22404274
KB		 1196 if (nvmeq->q_suspended) {
1197 spin_unlock_irq(&nvmeq->q_lock);
4d115420 1198 return 1;
3295874b 1199 }
22404274 1200 nvmeq->q_suspended = 1;
42f61420 1201 nvmeq->dev->online_queues--;
a09115b2
MW		 1202 spin_unlock_irq(&nvmeq->q_lock);
1203
aba2080f
MW		 1204 irq_set_affinity_hint(vector, NULL);
1205 free_irq(vector, nvmeq);
b60503ba 1206
4d115420
KB		 1207 return 0;
1208}
b60503ba 1209
4d115420
KB		 1210static void nvme_clear_queue(struct nvme_queue *nvmeq)
1211{
22404274
KB		 1212 spin_lock_irq(&nvmeq->q_lock);
1213 nvme_process_cq(nvmeq);
1214 nvme_cancel_ios(nvmeq, false);
1215 spin_unlock_irq(&nvmeq->q_lock);
b60503ba
MW		 1216}
1217
4d115420
KB		 1218static void nvme_disable_queue(struct nvme_dev *dev, int qid)
1219{
5a92e700 1220 struct nvme_queue *nvmeq = raw_nvmeq(dev, qid);
4d115420
KB		 1221
1222 if (!nvmeq)
1223 return;
1224 if (nvme_suspend_queue(nvmeq))
1225 return;
1226
0e53d180
KB		 1227 /* Don't tell the adapter to delete the admin queue.
1228 * Don't tell a removed adapter to delete IO queues. */
1229 if (qid && readl(&dev->bar->csts) != -1) {
b60503ba
MW		 1230 adapter_delete_sq(dev, qid);
1231 adapter_delete_cq(dev, qid);
1232 }
4d115420 1233 nvme_clear_queue(nvmeq);
b60503ba
MW		 1234}
1235
1236static struct nvme_queue *nvme_alloc_queue(struct nvme_dev *dev, int qid,
1237 int depth, int vector)
1238{
1239 struct device *dmadev = &dev->pci_dev->dev;
22404274 1240 unsigned extra = nvme_queue_extra(depth);
b60503ba
MW		 1241 struct nvme_queue *nvmeq = kzalloc(sizeof(*nvmeq) + extra, GFP_KERNEL);
1242 if (!nvmeq)
1243 return NULL;
1244
1245 nvmeq->cqes = dma_alloc_coherent(dmadev, CQ_SIZE(depth),
1246 &nvmeq->cq_dma_addr, GFP_KERNEL);
1247 if (!nvmeq->cqes)
1248 goto free_nvmeq;
1249 memset((void *)nvmeq->cqes, 0, CQ_SIZE(depth));
1250
1251 nvmeq->sq_cmds = dma_alloc_coherent(dmadev, SQ_SIZE(depth),
1252 &nvmeq->sq_dma_addr, GFP_KERNEL);
1253 if (!nvmeq->sq_cmds)
1254 goto free_cqdma;
1255
42f61420
KB		 1256 if (qid && !zalloc_cpumask_var(&nvmeq->cpu_mask, GFP_KERNEL))
1257 goto free_sqdma;
1258
b60503ba 1259 nvmeq->q_dmadev = dmadev;
091b6092 1260 nvmeq->dev = dev;
3193f07b
MW		 1261 snprintf(nvmeq->irqname, sizeof(nvmeq->irqname), "nvme%dq%d",
1262 dev->instance, qid);
b60503ba
MW		 1263 spin_lock_init(&nvmeq->q_lock);
1264 nvmeq->cq_head = 0;
82123460 1265 nvmeq->cq_phase = 1;
b60503ba 1266 init_waitqueue_head(&nvmeq->sq_full);
1fa6aead 1267 init_waitqueue_entry(&nvmeq->sq_cong_wait, nvme_thread);
b60503ba 1268 bio_list_init(&nvmeq->sq_cong);
edd10d33 1269 INIT_LIST_HEAD(&nvmeq->iod_bio);
b80d5ccc 1270 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
b60503ba
MW		 1271 nvmeq->q_depth = depth;
1272 nvmeq->cq_vector = vector;
c30341dc 1273 nvmeq->qid = qid;
22404274
KB		 1274 nvmeq->q_suspended = 1;
1275 dev->queue_count++;
5a92e700 1276 rcu_assign_pointer(dev->queues[qid], nvmeq);
b60503ba
MW		 1277
1278 return nvmeq;
1279
42f61420
KB		 1280 free_sqdma:
1281 dma_free_coherent(dmadev, SQ_SIZE(depth), (void *)nvmeq->sq_cmds,
1282 nvmeq->sq_dma_addr);
b60503ba 1283 free_cqdma:
68b8eca5 1284 dma_free_coherent(dmadev, CQ_SIZE(depth), (void *)nvmeq->cqes,
b60503ba
MW		 1285 nvmeq->cq_dma_addr);
1286 free_nvmeq:
1287 kfree(nvmeq);
1288 return NULL;
1289}
1290
3001082c
MW		 1291static int queue_request_irq(struct nvme_dev *dev, struct nvme_queue *nvmeq,
1292 const char *name)
1293{
58ffacb5
MW		 1294 if (use_threaded_interrupts)
1295 return request_threaded_irq(dev->entry[nvmeq->cq_vector].vector,
481e5bad 1296 nvme_irq_check, nvme_irq, IRQF_SHARED,
58ffacb5 1297 name, nvmeq);
3001082c 1298 return request_irq(dev->entry[nvmeq->cq_vector].vector, nvme_irq,
481e5bad 1299 IRQF_SHARED, name, nvmeq);
3001082c
MW		 1300}
1301
22404274 1302static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid)
b60503ba 1303{
22404274
KB		 1304 struct nvme_dev *dev = nvmeq->dev;
1305 unsigned extra = nvme_queue_extra(nvmeq->q_depth);
b60503ba 1306
22404274
KB		 1307 nvmeq->sq_tail = 0;
1308 nvmeq->cq_head = 0;
1309 nvmeq->cq_phase = 1;
b80d5ccc 1310 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
22404274
KB		 1311 memset(nvmeq->cmdid_data, 0, extra);
1312 memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq->q_depth));
1313 nvme_cancel_ios(nvmeq, false);
1314 nvmeq->q_suspended = 0;
42f61420 1315 dev->online_queues++;
22404274
KB		 1316}
1317
1318static int nvme_create_queue(struct nvme_queue *nvmeq, int qid)
1319{
1320 struct nvme_dev *dev = nvmeq->dev;
1321 int result;
3f85d50b 1322
b60503ba
MW		 1323 result = adapter_alloc_cq(dev, qid, nvmeq);
1324 if (result < 0)
22404274 1325 return result;
b60503ba
MW		 1326
1327 result = adapter_alloc_sq(dev, qid, nvmeq);
1328 if (result < 0)
1329 goto release_cq;
1330
3193f07b 1331 result = queue_request_irq(dev, nvmeq, nvmeq->irqname);
b60503ba
MW		 1332 if (result < 0)
1333 goto release_sq;
1334
0a8d44cb 1335 spin_lock_irq(&nvmeq->q_lock);
22404274 1336 nvme_init_queue(nvmeq, qid);
0a8d44cb 1337 spin_unlock_irq(&nvmeq->q_lock);
22404274
KB		 1338
1339 return result;
b60503ba
MW		 1340
1341 release_sq:
1342 adapter_delete_sq(dev, qid);
1343 release_cq:
1344 adapter_delete_cq(dev, qid);
22404274 1345 return result;
b60503ba
MW		 1346}
1347
ba47e386
MW		 1348static int nvme_wait_ready(struct nvme_dev *dev, u64 cap, bool enabled)
1349{
1350 unsigned long timeout;
1351 u32 bit = enabled ? NVME_CSTS_RDY : 0;
1352
1353 timeout = ((NVME_CAP_TIMEOUT(cap) + 1) * HZ / 2) + jiffies;
1354
1355 while ((readl(&dev->bar->csts) & NVME_CSTS_RDY) != bit) {
1356 msleep(100);
1357 if (fatal_signal_pending(current))
1358 return -EINTR;
1359 if (time_after(jiffies, timeout)) {
1360 dev_err(&dev->pci_dev->dev,
1361 "Device not ready; aborting initialisation\n");
1362 return -ENODEV;
1363 }
1364 }
1365
1366 return 0;
1367}
1368
1369/*
1370 * If the device has been passed off to us in an enabled state, just clear
1371 * the enabled bit. The spec says we should set the 'shutdown notification
1372 * bits', but doing so may cause the device to complete commands to the
1373 * admin queue ... and we don't know what memory that might be pointing at!
1374 */
1375static int nvme_disable_ctrl(struct nvme_dev *dev, u64 cap)
1376{
44af146a
MW		 1377 u32 cc = readl(&dev->bar->cc);
1378
1379 if (cc & NVME_CC_ENABLE)
1380 writel(cc & ~NVME_CC_ENABLE, &dev->bar->cc);
ba47e386
MW		 1381 return nvme_wait_ready(dev, cap, false);
1382}
1383
1384static int nvme_enable_ctrl(struct nvme_dev *dev, u64 cap)
1385{
1386 return nvme_wait_ready(dev, cap, true);
1387}
1388
1894d8f1
KB		 1389static int nvme_shutdown_ctrl(struct nvme_dev *dev)
1390{
1391 unsigned long timeout;
1392 u32 cc;
1393
1394 cc = (readl(&dev->bar->cc) & ~NVME_CC_SHN_MASK) | NVME_CC_SHN_NORMAL;
1395 writel(cc, &dev->bar->cc);
1396
1397 timeout = 2 * HZ + jiffies;
1398 while ((readl(&dev->bar->csts) & NVME_CSTS_SHST_MASK) !=
1399 NVME_CSTS_SHST_CMPLT) {
1400 msleep(100);
1401 if (fatal_signal_pending(current))
1402 return -EINTR;
1403 if (time_after(jiffies, timeout)) {
1404 dev_err(&dev->pci_dev->dev,
1405 "Device shutdown incomplete; abort shutdown\n");
1406 return -ENODEV;
1407 }
1408 }
1409
1410 return 0;
1411}
1412
8d85fce7 1413static int nvme_configure_admin_queue(struct nvme_dev *dev)
b60503ba 1414{
ba47e386 1415 int result;
b60503ba 1416 u32 aqa;
ba47e386 1417 u64 cap = readq(&dev->bar->cap);
b60503ba
MW		 1418 struct nvme_queue *nvmeq;
1419
ba47e386
MW		 1420 result = nvme_disable_ctrl(dev, cap);
1421 if (result < 0)
1422 return result;
b60503ba 1423
5a92e700 1424 nvmeq = raw_nvmeq(dev, 0);
cd638946
KB		 1425 if (!nvmeq) {
1426 nvmeq = nvme_alloc_queue(dev, 0, 64, 0);
1427 if (!nvmeq)
1428 return -ENOMEM;
cd638946 1429 }
b60503ba
MW		 1430
1431 aqa = nvmeq->q_depth - 1;
1432 aqa |= aqa << 16;
1433
1434 dev->ctrl_config = NVME_CC_ENABLE | NVME_CC_CSS_NVM;
1435 dev->ctrl_config |= (PAGE_SHIFT - 12) << NVME_CC_MPS_SHIFT;
1436 dev->ctrl_config |= NVME_CC_ARB_RR | NVME_CC_SHN_NONE;
7f53f9d2 1437 dev->ctrl_config |= NVME_CC_IOSQES | NVME_CC_IOCQES;
b60503ba
MW		 1438
1439 writel(aqa, &dev->bar->aqa);
1440 writeq(nvmeq->sq_dma_addr, &dev->bar->asq);
1441 writeq(nvmeq->cq_dma_addr, &dev->bar->acq);
1442 writel(dev->ctrl_config, &dev->bar->cc);
1443
ba47e386 1444 result = nvme_enable_ctrl(dev, cap);
025c557a 1445 if (result)
cd638946 1446 return result;
9e866774 1447
3193f07b 1448 result = queue_request_irq(dev, nvmeq, nvmeq->irqname);
025c557a 1449 if (result)
cd638946 1450 return result;
025c557a 1451
0a8d44cb 1452 spin_lock_irq(&nvmeq->q_lock);
22404274 1453 nvme_init_queue(nvmeq, 0);
0a8d44cb 1454 spin_unlock_irq(&nvmeq->q_lock);
b60503ba
MW		 1455 return result;
1456}
1457
5d0f6131 1458struct nvme_iod *nvme_map_user_pages(struct nvme_dev *dev, int write,
eca18b23 1459 unsigned long addr, unsigned length)
b60503ba 1460{
36c14ed9 1461 int i, err, count, nents, offset;
7fc3cdab
MW		 1462 struct scatterlist *sg;
1463 struct page **pages;
eca18b23 1464 struct nvme_iod *iod;
36c14ed9
MW		 1465
1466 if (addr & 3)
eca18b23 1467 return ERR_PTR(-EINVAL);
5460fc03 1468 if (!length || length > INT_MAX - PAGE_SIZE)
eca18b23 1469 return ERR_PTR(-EINVAL);
7fc3cdab 1470
36c14ed9 1471 offset = offset_in_page(addr);
7fc3cdab
MW		 1472 count = DIV_ROUND_UP(offset + length, PAGE_SIZE);
1473 pages = kcalloc(count, sizeof(*pages), GFP_KERNEL);
22fff826
DC		 1474 if (!pages)
1475 return ERR_PTR(-ENOMEM);
36c14ed9
MW		 1476
1477 err = get_user_pages_fast(addr, count, 1, pages);
1478 if (err < count) {
1479 count = err;
1480 err = -EFAULT;
1481 goto put_pages;
1482 }
7fc3cdab 1483
eca18b23
MW		 1484 iod = nvme_alloc_iod(count, length, GFP_KERNEL);
1485 sg = iod->sg;
36c14ed9 1486 sg_init_table(sg, count);
d0ba1e49
MW		 1487 for (i = 0; i < count; i++) {
1488 sg_set_page(&sg[i], pages[i],
5460fc03
DC		 1489 min_t(unsigned, length, PAGE_SIZE - offset),
1490 offset);
d0ba1e49
MW		 1491 length -= (PAGE_SIZE - offset);
1492 offset = 0;
7fc3cdab 1493 }
fe304c43 1494 sg_mark_end(&sg[i - 1]);
1c2ad9fa 1495 iod->nents = count;
7fc3cdab
MW		 1496
1497 err = -ENOMEM;
1498 nents = dma_map_sg(&dev->pci_dev->dev, sg, count,
1499 write ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
36c14ed9 1500 if (!nents)
eca18b23 1501 goto free_iod;
b60503ba 1502
7fc3cdab 1503 kfree(pages);
eca18b23 1504 return iod;
b60503ba 1505
eca18b23
MW		 1506 free_iod:
1507 kfree(iod);
7fc3cdab
MW		 1508 put_pages:
1509 for (i = 0; i < count; i++)
1510 put_page(pages[i]);
1511 kfree(pages);
eca18b23 1512 return ERR_PTR(err);
7fc3cdab 1513}
b60503ba 1514
5d0f6131 1515void nvme_unmap_user_pages(struct nvme_dev *dev, int write,
1c2ad9fa 1516 struct nvme_iod *iod)
7fc3cdab 1517{
1c2ad9fa 1518 int i;
b60503ba 1519
1c2ad9fa
MW		 1520 dma_unmap_sg(&dev->pci_dev->dev, iod->sg, iod->nents,
1521 write ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
7fc3cdab 1522
1c2ad9fa
MW		 1523 for (i = 0; i < iod->nents; i++)
1524 put_page(sg_page(&iod->sg[i]));
7fc3cdab 1525}
b60503ba 1526
a53295b6
MW		 1527static int nvme_submit_io(struct nvme_ns *ns, struct nvme_user_io __user *uio)
1528{
1529 struct nvme_dev *dev = ns->dev;
a53295b6
MW		 1530 struct nvme_user_io io;
1531 struct nvme_command c;
f410c680
KB		 1532 unsigned length, meta_len;
1533 int status, i;
1534 struct nvme_iod *iod, *meta_iod = NULL;
1535 dma_addr_t meta_dma_addr;
1536 void *meta, *uninitialized_var(meta_mem);
a53295b6
MW		 1537
1538 if (copy_from_user(&io, uio, sizeof(io)))
1539 return -EFAULT;
6c7d4945 1540 length = (io.nblocks + 1) << ns->lba_shift;
f410c680
KB		 1541 meta_len = (io.nblocks + 1) * ns->ms;
1542
1543 if (meta_len && ((io.metadata & 3) || !io.metadata))
1544 return -EINVAL;
6c7d4945
MW		 1545
1546 switch (io.opcode) {
1547 case nvme_cmd_write:
1548 case nvme_cmd_read:
6bbf1acd 1549 case nvme_cmd_compare:
eca18b23 1550 iod = nvme_map_user_pages(dev, io.opcode & 1, io.addr, length);
6413214c 1551 break;
6c7d4945 1552 default:
6bbf1acd 1553 return -EINVAL;
6c7d4945
MW		 1554 }
1555
eca18b23
MW		 1556 if (IS_ERR(iod))
1557 return PTR_ERR(iod);
a53295b6
MW		 1558
1559 memset(&c, 0, sizeof(c));
1560 c.rw.opcode = io.opcode;
1561 c.rw.flags = io.flags;
6c7d4945 1562 c.rw.nsid = cpu_to_le32(ns->ns_id);
a53295b6 1563 c.rw.slba = cpu_to_le64(io.slba);
6c7d4945 1564 c.rw.length = cpu_to_le16(io.nblocks);
a53295b6 1565 c.rw.control = cpu_to_le16(io.control);
1c9b5265
MW		 1566 c.rw.dsmgmt = cpu_to_le32(io.dsmgmt);
1567 c.rw.reftag = cpu_to_le32(io.reftag);
1568 c.rw.apptag = cpu_to_le16(io.apptag);
1569 c.rw.appmask = cpu_to_le16(io.appmask);
f410c680
KB		 1570
1571 if (meta_len) {
1b56749e
KB		 1572 meta_iod = nvme_map_user_pages(dev, io.opcode & 1, io.metadata,
1573 meta_len);
f410c680
KB		 1574 if (IS_ERR(meta_iod)) {
1575 status = PTR_ERR(meta_iod);
1576 meta_iod = NULL;
1577 goto unmap;
1578 }
1579
1580 meta_mem = dma_alloc_coherent(&dev->pci_dev->dev, meta_len,
1581 &meta_dma_addr, GFP_KERNEL);
1582 if (!meta_mem) {
1583 status = -ENOMEM;
1584 goto unmap;
1585 }
1586
1587 if (io.opcode & 1) {
1588 int meta_offset = 0;
1589
1590 for (i = 0; i < meta_iod->nents; i++) {
1591 meta = kmap_atomic(sg_page(&meta_iod->sg[i])) +
1592 meta_iod->sg[i].offset;
1593 memcpy(meta_mem + meta_offset, meta,
1594 meta_iod->sg[i].length);
1595 kunmap_atomic(meta);
1596 meta_offset += meta_iod->sg[i].length;
1597 }
1598 }
1599
1600 c.rw.metadata = cpu_to_le64(meta_dma_addr);
1601 }
1602
edd10d33
KB		 1603 length = nvme_setup_prps(dev, iod, length, GFP_KERNEL);
1604 c.rw.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
1605 c.rw.prp2 = cpu_to_le64(iod->first_dma);
a53295b6 1606
b77954cb
MW		 1607 if (length != (io.nblocks + 1) << ns->lba_shift)
1608 status = -ENOMEM;
1609 else
4f5099af 1610 status = nvme_submit_io_cmd(dev, &c, NULL);
a53295b6 1611
f410c680
KB		 1612 if (meta_len) {
1613 if (status == NVME_SC_SUCCESS && !(io.opcode & 1)) {
1614 int meta_offset = 0;
1615
1616 for (i = 0; i < meta_iod->nents; i++) {
1617 meta = kmap_atomic(sg_page(&meta_iod->sg[i])) +
1618 meta_iod->sg[i].offset;
1619 memcpy(meta, meta_mem + meta_offset,
1620 meta_iod->sg[i].length);
1621 kunmap_atomic(meta);
1622 meta_offset += meta_iod->sg[i].length;
1623 }
1624 }
1625
1626 dma_free_coherent(&dev->pci_dev->dev, meta_len, meta_mem,
1627 meta_dma_addr);
1628 }
1629
1630 unmap:
1c2ad9fa 1631 nvme_unmap_user_pages(dev, io.opcode & 1, iod);
eca18b23 1632 nvme_free_iod(dev, iod);
f410c680
KB		 1633
1634 if (meta_iod) {
1635 nvme_unmap_user_pages(dev, io.opcode & 1, meta_iod);
1636 nvme_free_iod(dev, meta_iod);
1637 }
1638
a53295b6
MW		 1639 return status;
1640}
1641
50af8bae 1642static int nvme_user_admin_cmd(struct nvme_dev *dev,
6bbf1acd 1643 struct nvme_admin_cmd __user *ucmd)
6ee44cdc 1644{
6bbf1acd 1645 struct nvme_admin_cmd cmd;
6ee44cdc 1646 struct nvme_command c;
eca18b23 1647 int status, length;
c7d36ab8 1648 struct nvme_iod *uninitialized_var(iod);
94f370ca 1649 unsigned timeout;
6ee44cdc 1650
6bbf1acd
MW		 1651 if (!capable(CAP_SYS_ADMIN))
1652 return -EACCES;
1653 if (copy_from_user(&cmd, ucmd, sizeof(cmd)))
6ee44cdc 1654 return -EFAULT;
6ee44cdc
MW		 1655
1656 memset(&c, 0, sizeof(c));
6bbf1acd
MW		 1657 c.common.opcode = cmd.opcode;
1658 c.common.flags = cmd.flags;
1659 c.common.nsid = cpu_to_le32(cmd.nsid);
1660 c.common.cdw2[0] = cpu_to_le32(cmd.cdw2);
1661 c.common.cdw2[1] = cpu_to_le32(cmd.cdw3);
1662 c.common.cdw10[0] = cpu_to_le32(cmd.cdw10);
1663 c.common.cdw10[1] = cpu_to_le32(cmd.cdw11);
1664 c.common.cdw10[2] = cpu_to_le32(cmd.cdw12);
1665 c.common.cdw10[3] = cpu_to_le32(cmd.cdw13);
1666 c.common.cdw10[4] = cpu_to_le32(cmd.cdw14);
1667 c.common.cdw10[5] = cpu_to_le32(cmd.cdw15);
1668
1669 length = cmd.data_len;
1670 if (cmd.data_len) {
49742188
MW		 1671 iod = nvme_map_user_pages(dev, cmd.opcode & 1, cmd.addr,
1672 length);
eca18b23
MW		 1673 if (IS_ERR(iod))
1674 return PTR_ERR(iod);
edd10d33
KB		 1675 length = nvme_setup_prps(dev, iod, length, GFP_KERNEL);
1676 c.common.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
1677 c.common.prp2 = cpu_to_le64(iod->first_dma);
6bbf1acd
MW		 1678 }
1679
94f370ca
KB		 1680 timeout = cmd.timeout_ms ? msecs_to_jiffies(cmd.timeout_ms) :
1681 ADMIN_TIMEOUT;
6bbf1acd 1682 if (length != cmd.data_len)
b77954cb
MW		 1683 status = -ENOMEM;
1684 else
4f5099af 1685 status = nvme_submit_sync_cmd(dev, 0, &c, &cmd.result, timeout);
eca18b23 1686
6bbf1acd 1687 if (cmd.data_len) {
1c2ad9fa 1688 nvme_unmap_user_pages(dev, cmd.opcode & 1, iod);
eca18b23 1689 nvme_free_iod(dev, iod);
6bbf1acd 1690 }
f4f117f6 1691
cf90bc48 1692 if ((status >= 0) && copy_to_user(&ucmd->result, &cmd.result,
f4f117f6
KB		 1693 sizeof(cmd.result)))
1694 status = -EFAULT;
1695
6ee44cdc
MW		 1696 return status;
1697}
1698
b60503ba
MW		 1699static int nvme_ioctl(struct block_device *bdev, fmode_t mode, unsigned int cmd,
1700 unsigned long arg)
1701{
1702 struct nvme_ns *ns = bdev->bd_disk->private_data;
1703
1704 switch (cmd) {
6bbf1acd 1705 case NVME_IOCTL_ID:
c3bfe717 1706 force_successful_syscall_return();
6bbf1acd
MW		 1707 return ns->ns_id;
1708 case NVME_IOCTL_ADMIN_CMD:
50af8bae 1709 return nvme_user_admin_cmd(ns->dev, (void __user *)arg);
a53295b6
MW		 1710 case NVME_IOCTL_SUBMIT_IO:
1711 return nvme_submit_io(ns, (void __user *)arg);
5d0f6131
VV		 1712 case SG_GET_VERSION_NUM:
1713 return nvme_sg_get_version_num((void __user *)arg);
1714 case SG_IO:
1715 return nvme_sg_io(ns, (void __user *)arg);
b60503ba
MW		 1716 default:
1717 return -ENOTTY;
1718 }
1719}
1720
320a3827
KB		 1721#ifdef CONFIG_COMPAT
1722static int nvme_compat_ioctl(struct block_device *bdev, fmode_t mode,
1723 unsigned int cmd, unsigned long arg)
1724{
1725 struct nvme_ns *ns = bdev->bd_disk->private_data;
1726
1727 switch (cmd) {
1728 case SG_IO:
1729 return nvme_sg_io32(ns, arg);
1730 }
1731 return nvme_ioctl(bdev, mode, cmd, arg);
1732}
1733#else
1734#define nvme_compat_ioctl NULL
1735#endif
1736
9ac27090
KB		 1737static int nvme_open(struct block_device *bdev, fmode_t mode)
1738{
1739 struct nvme_ns *ns = bdev->bd_disk->private_data;
1740 struct nvme_dev *dev = ns->dev;
1741
1742 kref_get(&dev->kref);
1743 return 0;
1744}
1745
1746static void nvme_free_dev(struct kref *kref);
1747
1748static void nvme_release(struct gendisk *disk, fmode_t mode)
1749{
1750 struct nvme_ns *ns = disk->private_data;
1751 struct nvme_dev *dev = ns->dev;
1752
1753 kref_put(&dev->kref, nvme_free_dev);
1754}
1755
4cc09e2d
KB		 1756static int nvme_getgeo(struct block_device *bd, struct hd_geometry *geo)
1757{
1758 /* some standard values */
1759 geo->heads = 1 << 6;
1760 geo->sectors = 1 << 5;
1761 geo->cylinders = get_capacity(bd->bd_disk) >> 11;
1762 return 0;
1763}
1764
b60503ba
MW		 1765static const struct block_device_operations nvme_fops = {
1766 .owner = THIS_MODULE,
1767 .ioctl = nvme_ioctl,
320a3827 1768 .compat_ioctl = nvme_compat_ioctl,
9ac27090
KB		 1769 .open = nvme_open,
1770 .release = nvme_release,
4cc09e2d 1771 .getgeo = nvme_getgeo,
b60503ba
MW		 1772};
1773
edd10d33
KB		 1774static void nvme_resubmit_iods(struct nvme_queue *nvmeq)
1775{
1776 struct nvme_iod *iod, *next;
1777
1778 list_for_each_entry_safe(iod, next, &nvmeq->iod_bio, node) {
1779 if (unlikely(nvme_submit_iod(nvmeq, iod)))
1780 break;
1781 list_del(&iod->node);
1782 if (bio_list_empty(&nvmeq->sq_cong) &&
1783 list_empty(&nvmeq->iod_bio))
1784 remove_wait_queue(&nvmeq->sq_full,
1785 &nvmeq->sq_cong_wait);
1786 }
1787}
1788
1fa6aead
MW		 1789static void nvme_resubmit_bios(struct nvme_queue *nvmeq)
1790{
1791 while (bio_list_peek(&nvmeq->sq_cong)) {
1792 struct bio *bio = bio_list_pop(&nvmeq->sq_cong);
1793 struct nvme_ns *ns = bio->bi_bdev->bd_disk->private_data;
427e9708 1794
edd10d33
KB		 1795 if (bio_list_empty(&nvmeq->sq_cong) &&
1796 list_empty(&nvmeq->iod_bio))
427e9708
KB		 1797 remove_wait_queue(&nvmeq->sq_full,
1798 &nvmeq->sq_cong_wait);
1fa6aead 1799 if (nvme_submit_bio_queue(nvmeq, ns, bio)) {
edd10d33 1800 if (!waitqueue_active(&nvmeq->sq_full))
427e9708
KB		 1801 add_wait_queue(&nvmeq->sq_full,
1802 &nvmeq->sq_cong_wait);
1fa6aead
MW		 1803 bio_list_add_head(&nvmeq->sq_cong, bio);
1804 break;
1805 }
1806 }
1807}
1808
1809static int nvme_kthread(void *data)
1810{
d4b4ff8e 1811 struct nvme_dev *dev, *next;
1fa6aead
MW		 1812
1813 while (!kthread_should_stop()) {
564a232c 1814 set_current_state(TASK_INTERRUPTIBLE);
1fa6aead 1815 spin_lock(&dev_list_lock);
d4b4ff8e 1816 list_for_each_entry_safe(dev, next, &dev_list, node) {
1fa6aead 1817 int i;
d4b4ff8e
KB		 1818 if (readl(&dev->bar->csts) & NVME_CSTS_CFS &&
1819 dev->initialized) {
1820 if (work_busy(&dev->reset_work))
1821 continue;
1822 list_del_init(&dev->node);
1823 dev_warn(&dev->pci_dev->dev,
1824 "Failed status, reset controller\n");
9ca97374 1825 dev->reset_workfn = nvme_reset_failed_dev;
d4b4ff8e
KB		 1826 queue_work(nvme_workq, &dev->reset_work);
1827 continue;
1828 }
5a92e700 1829 rcu_read_lock();
1fa6aead 1830 for (i = 0; i < dev->queue_count; i++) {
5a92e700
KB		 1831 struct nvme_queue *nvmeq =
1832 rcu_dereference(dev->queues[i]);
740216fc
MW		 1833 if (!nvmeq)
1834 continue;
1fa6aead 1835 spin_lock_irq(&nvmeq->q_lock);
22404274
KB		 1836 if (nvmeq->q_suspended)
1837 goto unlock;
bc57a0f7 1838 nvme_process_cq(nvmeq);
a09115b2 1839 nvme_cancel_ios(nvmeq, true);
1fa6aead 1840 nvme_resubmit_bios(nvmeq);
edd10d33 1841 nvme_resubmit_iods(nvmeq);
22404274 1842 unlock:
1fa6aead
MW		 1843 spin_unlock_irq(&nvmeq->q_lock);
1844 }
5a92e700 1845 rcu_read_unlock();
1fa6aead
MW		 1846 }
1847 spin_unlock(&dev_list_lock);
acb7aa0d 1848 schedule_timeout(round_jiffies_relative(HZ));
1fa6aead
MW		 1849 }
1850 return 0;
1851}
1852
0e5e4f0e
KB		 1853static void nvme_config_discard(struct nvme_ns *ns)
1854{
1855 u32 logical_block_size = queue_logical_block_size(ns->queue);
1856 ns->queue->limits.discard_zeroes_data = 0;
1857 ns->queue->limits.discard_alignment = logical_block_size;
1858 ns->queue->limits.discard_granularity = logical_block_size;
1859 ns->queue->limits.max_discard_sectors = 0xffffffff;
1860 queue_flag_set_unlocked(QUEUE_FLAG_DISCARD, ns->queue);
1861}
1862
c3bfe717 1863static struct nvme_ns *nvme_alloc_ns(struct nvme_dev *dev, unsigned nsid,
b60503ba
MW		 1864 struct nvme_id_ns *id, struct nvme_lba_range_type *rt)
1865{
1866 struct nvme_ns *ns;
1867 struct gendisk *disk;
1868 int lbaf;
1869
1870 if (rt->attributes & NVME_LBART_ATTRIB_HIDE)
1871 return NULL;
1872
1873 ns = kzalloc(sizeof(*ns), GFP_KERNEL);
1874 if (!ns)
1875 return NULL;
1876 ns->queue = blk_alloc_queue(GFP_KERNEL);
1877 if (!ns->queue)
1878 goto out_free_ns;
4eeb9215
MW		 1879 ns->queue->queue_flags = QUEUE_FLAG_DEFAULT;
1880 queue_flag_set_unlocked(QUEUE_FLAG_NOMERGES, ns->queue);
1881 queue_flag_set_unlocked(QUEUE_FLAG_NONROT, ns->queue);
b60503ba
MW		 1882 blk_queue_make_request(ns->queue, nvme_make_request);
1883 ns->dev = dev;
1884 ns->queue->queuedata = ns;
1885
469071a3 1886 disk = alloc_disk(0);
b60503ba
MW		 1887 if (!disk)
1888 goto out_free_queue;
5aff9382 1889 ns->ns_id = nsid;
b60503ba
MW		 1890 ns->disk = disk;
1891 lbaf = id->flbas & 0xf;
1892 ns->lba_shift = id->lbaf[lbaf].ds;
f410c680 1893 ns->ms = le16_to_cpu(id->lbaf[lbaf].ms);
e9ef4636 1894 blk_queue_logical_block_size(ns->queue, 1 << ns->lba_shift);
8fc23e03
KB		 1895 if (dev->max_hw_sectors)
1896 blk_queue_max_hw_sectors(ns->queue, dev->max_hw_sectors);
b60503ba
MW		 1897
1898 disk->major = nvme_major;
469071a3 1899 disk->first_minor = 0;
b60503ba
MW		 1900 disk->fops = &nvme_fops;
1901 disk->private_data = ns;
1902 disk->queue = ns->queue;
388f037f 1903 disk->driverfs_dev = &dev->pci_dev->dev;
469071a3 1904 disk->flags = GENHD_FL_EXT_DEVT;
5aff9382 1905 sprintf(disk->disk_name, "nvme%dn%d", dev->instance, nsid);
b60503ba
MW		 1906 set_capacity(disk, le64_to_cpup(&id->nsze) << (ns->lba_shift - 9));
1907
0e5e4f0e
KB		 1908 if (dev->oncs & NVME_CTRL_ONCS_DSM)
1909 nvme_config_discard(ns);
1910
b60503ba
MW		 1911 return ns;
1912
1913 out_free_queue:
1914 blk_cleanup_queue(ns->queue);
1915 out_free_ns:
1916 kfree(ns);
1917 return NULL;
1918}
1919
42f61420
KB		 1920static int nvme_find_closest_node(int node)
1921{
1922 int n, val, min_val = INT_MAX, best_node = node;
1923
1924 for_each_online_node(n) {
1925 if (n == node)
1926 continue;
1927 val = node_distance(node, n);
1928 if (val < min_val) {
1929 min_val = val;
1930 best_node = n;
1931 }
1932 }
1933 return best_node;
1934}
1935
1936static void nvme_set_queue_cpus(cpumask_t *qmask, struct nvme_queue *nvmeq,
1937 int count)
1938{
1939 int cpu;
1940 for_each_cpu(cpu, qmask) {
1941 if (cpumask_weight(nvmeq->cpu_mask) >= count)
1942 break;
1943 if (!cpumask_test_and_set_cpu(cpu, nvmeq->cpu_mask))
1944 *per_cpu_ptr(nvmeq->dev->io_queue, cpu) = nvmeq->qid;
1945 }
1946}
1947
1948static void nvme_add_cpus(cpumask_t *mask, const cpumask_t *unassigned_cpus,
1949 const cpumask_t *new_mask, struct nvme_queue *nvmeq, int cpus_per_queue)
1950{
1951 int next_cpu;
1952 for_each_cpu(next_cpu, new_mask) {
1953 cpumask_or(mask, mask, get_cpu_mask(next_cpu));
1954 cpumask_or(mask, mask, topology_thread_cpumask(next_cpu));
1955 cpumask_and(mask, mask, unassigned_cpus);
1956 nvme_set_queue_cpus(mask, nvmeq, cpus_per_queue);
1957 }
1958}
1959
1960static void nvme_create_io_queues(struct nvme_dev *dev)
1961{
1962 unsigned i, max;
1963
1964 max = min(dev->max_qid, num_online_cpus());
1965 for (i = dev->queue_count; i <= max; i++)
1966 if (!nvme_alloc_queue(dev, i, dev->q_depth, i - 1))
1967 break;
1968
1969 max = min(dev->queue_count - 1, num_online_cpus());
1970 for (i = dev->online_queues; i <= max; i++)
1971 if (nvme_create_queue(raw_nvmeq(dev, i), i))
1972 break;
1973}
1974
1975/*
1976 * If there are fewer queues than online cpus, this will try to optimally
1977 * assign a queue to multiple cpus by grouping cpus that are "close" together:
1978 * thread siblings, core, socket, closest node, then whatever else is
1979 * available.
1980 */
1981static void nvme_assign_io_queues(struct nvme_dev *dev)
1982{
1983 unsigned cpu, cpus_per_queue, queues, remainder, i;
1984 cpumask_var_t unassigned_cpus;
1985
1986 nvme_create_io_queues(dev);
1987
1988 queues = min(dev->online_queues - 1, num_online_cpus());
1989 if (!queues)
1990 return;
1991
1992 cpus_per_queue = num_online_cpus() / queues;
1993 remainder = queues - (num_online_cpus() - queues * cpus_per_queue);
1994
1995 if (!alloc_cpumask_var(&unassigned_cpus, GFP_KERNEL))
1996 return;
1997
1998 cpumask_copy(unassigned_cpus, cpu_online_mask);
1999 cpu = cpumask_first(unassigned_cpus);
2000 for (i = 1; i <= queues; i++) {
2001 struct nvme_queue *nvmeq = lock_nvmeq(dev, i);
2002 cpumask_t mask;
2003
2004 cpumask_clear(nvmeq->cpu_mask);
2005 if (!cpumask_weight(unassigned_cpus)) {
2006 unlock_nvmeq(nvmeq);
2007 break;
2008 }
2009
2010 mask = *get_cpu_mask(cpu);
2011 nvme_set_queue_cpus(&mask, nvmeq, cpus_per_queue);
2012 if (cpus_weight(mask) < cpus_per_queue)
2013 nvme_add_cpus(&mask, unassigned_cpus,
2014 topology_thread_cpumask(cpu),
2015 nvmeq, cpus_per_queue);
2016 if (cpus_weight(mask) < cpus_per_queue)
2017 nvme_add_cpus(&mask, unassigned_cpus,
2018 topology_core_cpumask(cpu),
2019 nvmeq, cpus_per_queue);
2020 if (cpus_weight(mask) < cpus_per_queue)
2021 nvme_add_cpus(&mask, unassigned_cpus,
2022 cpumask_of_node(cpu_to_node(cpu)),
2023 nvmeq, cpus_per_queue);
2024 if (cpus_weight(mask) < cpus_per_queue)
2025 nvme_add_cpus(&mask, unassigned_cpus,
2026 cpumask_of_node(
2027 nvme_find_closest_node(
2028 cpu_to_node(cpu))),
2029 nvmeq, cpus_per_queue);
2030 if (cpus_weight(mask) < cpus_per_queue)
2031 nvme_add_cpus(&mask, unassigned_cpus,
2032 unassigned_cpus,
2033 nvmeq, cpus_per_queue);
2034
2035 WARN(cpumask_weight(nvmeq->cpu_mask) != cpus_per_queue,
2036 "nvme%d qid:%d mis-matched queue-to-cpu assignment\n",
2037 dev->instance, i);
2038
2039 irq_set_affinity_hint(dev->entry[nvmeq->cq_vector].vector,
2040 nvmeq->cpu_mask);
2041 cpumask_andnot(unassigned_cpus, unassigned_cpus,
2042 nvmeq->cpu_mask);
2043 cpu = cpumask_next(cpu, unassigned_cpus);
2044 if (remainder && !--remainder)
2045 cpus_per_queue++;
2046 unlock_nvmeq(nvmeq);
2047 }
2048 WARN(cpumask_weight(unassigned_cpus), "nvme%d unassigned online cpus\n",
2049 dev->instance);
2050 i = 0;
2051 cpumask_andnot(unassigned_cpus, cpu_possible_mask, cpu_online_mask);
2052 for_each_cpu(cpu, unassigned_cpus)
2053 *per_cpu_ptr(dev->io_queue, cpu) = (i++ % queues) + 1;
2054 free_cpumask_var(unassigned_cpus);
2055}
2056
b3b06812 2057static int set_queue_count(struct nvme_dev *dev, int count)
b60503ba
MW		 2058{
2059 int status;
2060 u32 result;
b3b06812 2061 u32 q_count = (count - 1) | ((count - 1) << 16);
b60503ba 2062
df348139 2063 status = nvme_set_features(dev, NVME_FEAT_NUM_QUEUES, q_count, 0,
bc5fc7e4 2064 &result);
b60503ba 2065 if (status)
7e03b124 2066 return status < 0 ? -EIO : -EBUSY;
b60503ba
MW		 2067 return min(result & 0xffff, result >> 16) + 1;
2068}
2069
9d713c2b
KB		 2070static size_t db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues)
2071{
b80d5ccc 2072 return 4096 + ((nr_io_queues + 1) * 8 * dev->db_stride);
9d713c2b
KB		 2073}
2074
33b1e95c
KB		 2075static int nvme_cpu_notify(struct notifier_block *self,
2076 unsigned long action, void *hcpu)
2077{
2078 struct nvme_dev *dev = container_of(self, struct nvme_dev, nb);
2079 switch (action) {
2080 case CPU_ONLINE:
2081 case CPU_DEAD:
2082 nvme_assign_io_queues(dev);
2083 break;
2084 }
2085 return NOTIFY_OK;
2086}
2087
8d85fce7 2088static int nvme_setup_io_queues(struct nvme_dev *dev)
b60503ba 2089{
5a92e700 2090 struct nvme_queue *adminq = raw_nvmeq(dev, 0);
fa08a396 2091 struct pci_dev *pdev = dev->pci_dev;
42f61420 2092 int result, i, vecs, nr_io_queues, size;
b60503ba 2093
42f61420 2094 nr_io_queues = num_possible_cpus();
b348b7d5 2095 result = set_queue_count(dev, nr_io_queues);
1b23484b
MW		 2096 if (result < 0)
2097 return result;
b348b7d5
MW		 2098 if (result < nr_io_queues)
2099 nr_io_queues = result;
b60503ba 2100
9d713c2b
KB		 2101 size = db_bar_size(dev, nr_io_queues);
2102 if (size > 8192) {
f1938f6e 2103 iounmap(dev->bar);
9d713c2b
KB		 2104 do {
2105 dev->bar = ioremap(pci_resource_start(pdev, 0), size);
2106 if (dev->bar)
2107 break;
2108 if (!--nr_io_queues)
2109 return -ENOMEM;
2110 size = db_bar_size(dev, nr_io_queues);
2111 } while (1);
f1938f6e 2112 dev->dbs = ((void __iomem *)dev->bar) + 4096;
5a92e700 2113 adminq->q_db = dev->dbs;
f1938f6e
MW		 2114 }
2115
9d713c2b 2116 /* Deregister the admin queue's interrupt */
3193f07b 2117 free_irq(dev->entry[0].vector, adminq);
9d713c2b 2118
be577fab 2119 for (i = 0; i < nr_io_queues; i++)
1b23484b 2120 dev->entry[i].entry = i;
be577fab
AG		 2121 vecs = pci_enable_msix_range(pdev, dev->entry, 1, nr_io_queues);
2122 if (vecs < 0) {
2123 vecs = pci_enable_msi_range(pdev, 1, min(nr_io_queues, 32));
2124 if (vecs < 0) {
2125 vecs = 1;
2126 } else {
2127 for (i = 0; i < vecs; i++)
2128 dev->entry[i].vector = i + pdev->irq;
fa08a396
RRG		 2129 }
2130 }
2131
063a8096
MW		 2132 /*
2133 * Should investigate if there's a performance win from allocating
2134 * more queues than interrupt vectors; it might allow the submission
2135 * path to scale better, even if the receive path is limited by the
2136 * number of interrupts.
2137 */
2138 nr_io_queues = vecs;
42f61420 2139 dev->max_qid = nr_io_queues;
063a8096 2140
3193f07b 2141 result = queue_request_irq(dev, adminq, adminq->irqname);
9d713c2b 2142 if (result) {
3193f07b 2143 adminq->q_suspended = 1;
22404274 2144 goto free_queues;
9d713c2b 2145 }
1b23484b 2146
cd638946 2147 /* Free previously allocated queues that are no longer usable */
42f61420
KB		 2148 nvme_free_queues(dev, nr_io_queues + 1);
2149 nvme_assign_io_queues(dev);
9ecdc946 2150
33b1e95c
KB		 2151 dev->nb.notifier_call = &nvme_cpu_notify;
2152 result = register_hotcpu_notifier(&dev->nb);
2153 if (result)
2154 goto free_queues;
b60503ba 2155
22404274 2156 return 0;
b60503ba 2157
22404274 2158 free_queues:
a1a5ef99 2159 nvme_free_queues(dev, 1);
22404274 2160 return result;
b60503ba
MW		 2161}
2162
422ef0c7
MW		 2163/*
2164 * Return: error value if an error occurred setting up the queues or calling
2165 * Identify Device. 0 if these succeeded, even if adding some of the
2166 * namespaces failed. At the moment, these failures are silent. TBD which
2167 * failures should be reported.
2168 */
8d85fce7 2169static int nvme_dev_add(struct nvme_dev *dev)
b60503ba 2170{
68608c26 2171 struct pci_dev *pdev = dev->pci_dev;
c3bfe717
MW		 2172 int res;
2173 unsigned nn, i;
cbb6218f 2174 struct nvme_ns *ns;
51814232 2175 struct nvme_id_ctrl *ctrl;
bc5fc7e4
MW		 2176 struct nvme_id_ns *id_ns;
2177 void *mem;
b60503ba 2178 dma_addr_t dma_addr;
159b67d7 2179 int shift = NVME_CAP_MPSMIN(readq(&dev->bar->cap)) + 12;
b60503ba 2180
68608c26 2181 mem = dma_alloc_coherent(&pdev->dev, 8192, &dma_addr, GFP_KERNEL);
a9ef4343
KB		 2182 if (!mem)
2183 return -ENOMEM;
b60503ba 2184
bc5fc7e4 2185 res = nvme_identify(dev, 0, 1, dma_addr);
b60503ba
MW		 2186 if (res) {
2187 res = -EIO;
cbb6218f 2188 goto out;
b60503ba
MW		 2189 }
2190
bc5fc7e4 2191 ctrl = mem;
51814232 2192 nn = le32_to_cpup(&ctrl->nn);
0e5e4f0e 2193 dev->oncs = le16_to_cpup(&ctrl->oncs);
c30341dc 2194 dev->abort_limit = ctrl->acl + 1;
51814232
MW		 2195 memcpy(dev->serial, ctrl->sn, sizeof(ctrl->sn));
2196 memcpy(dev->model, ctrl->mn, sizeof(ctrl->mn));
2197 memcpy(dev->firmware_rev, ctrl->fr, sizeof(ctrl->fr));
159b67d7 2198 if (ctrl->mdts)
8fc23e03 2199 dev->max_hw_sectors = 1 << (ctrl->mdts + shift - 9);
68608c26
MW		 2200 if ((pdev->vendor == PCI_VENDOR_ID_INTEL) &&
2201 (pdev->device == 0x0953) && ctrl->vs[3])
159b67d7 2202 dev->stripe_size = 1 << (ctrl->vs[3] + shift);
b60503ba 2203
bc5fc7e4 2204 id_ns = mem;
2b2c1896 2205 for (i = 1; i <= nn; i++) {
bc5fc7e4 2206 res = nvme_identify(dev, i, 0, dma_addr);
b60503ba
MW		 2207 if (res)
2208 continue;
2209
bc5fc7e4 2210 if (id_ns->ncap == 0)
b60503ba
MW		 2211 continue;
2212
bc5fc7e4 2213 res = nvme_get_features(dev, NVME_FEAT_LBA_RANGE, i,
08df1e05 2214 dma_addr + 4096, NULL);
b60503ba 2215 if (res)
12209036 2216 memset(mem + 4096, 0, 4096);
b60503ba 2217
bc5fc7e4 2218 ns = nvme_alloc_ns(dev, i, mem, mem + 4096);
b60503ba
MW		 2219 if (ns)
2220 list_add_tail(&ns->list, &dev->namespaces);
2221 }
2222 list_for_each_entry(ns, &dev->namespaces, list)
2223 add_disk(ns->disk);
422ef0c7 2224 res = 0;
b60503ba 2225
bc5fc7e4 2226 out:
684f5c20 2227 dma_free_coherent(&dev->pci_dev->dev, 8192, mem, dma_addr);
b60503ba
MW		 2228 return res;
2229}
2230
0877cb0d
KB		 2231static int nvme_dev_map(struct nvme_dev *dev)
2232{
42f61420 2233 u64 cap;
0877cb0d
KB		 2234 int bars, result = -ENOMEM;
2235 struct pci_dev *pdev = dev->pci_dev;
2236
2237 if (pci_enable_device_mem(pdev))
2238 return result;
2239
2240 dev->entry[0].vector = pdev->irq;
2241 pci_set_master(pdev);
2242 bars = pci_select_bars(pdev, IORESOURCE_MEM);
2243 if (pci_request_selected_regions(pdev, bars, "nvme"))
2244 goto disable_pci;
2245
052d0efa
RK		 2246 if (dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)) &&
2247 dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)))
2248 goto disable;
0877cb0d 2249
0877cb0d
KB		 2250 dev->bar = ioremap(pci_resource_start(pdev, 0), 8192);
2251 if (!dev->bar)
2252 goto disable;
0e53d180
KB		 2253 if (readl(&dev->bar->csts) == -1) {
2254 result = -ENODEV;
2255 goto unmap;
2256 }
42f61420
KB		 2257 cap = readq(&dev->bar->cap);
2258 dev->q_depth = min_t(int, NVME_CAP_MQES(cap) + 1, NVME_Q_DEPTH);
2259 dev->db_stride = 1 << NVME_CAP_STRIDE(cap);
0877cb0d
KB		 2260 dev->dbs = ((void __iomem *)dev->bar) + 4096;
2261
2262 return 0;
2263
0e53d180
KB		 2264 unmap:
2265 iounmap(dev->bar);
2266 dev->bar = NULL;
0877cb0d
KB		 2267 disable:
2268 pci_release_regions(pdev);
2269 disable_pci:
2270 pci_disable_device(pdev);
2271 return result;
2272}
2273
2274static void nvme_dev_unmap(struct nvme_dev *dev)
2275{
2276 if (dev->pci_dev->msi_enabled)
2277 pci_disable_msi(dev->pci_dev);
2278 else if (dev->pci_dev->msix_enabled)
2279 pci_disable_msix(dev->pci_dev);
2280
2281 if (dev->bar) {
2282 iounmap(dev->bar);
2283 dev->bar = NULL;
9a6b9458 2284 pci_release_regions(dev->pci_dev);
0877cb0d
KB		 2285 }
2286
0877cb0d
KB		 2287 if (pci_is_enabled(dev->pci_dev))
2288 pci_disable_device(dev->pci_dev);
2289}
2290
4d115420
KB		 2291struct nvme_delq_ctx {
2292 struct task_struct *waiter;
2293 struct kthread_worker *worker;
2294 atomic_t refcount;
2295};
2296
2297static void nvme_wait_dq(struct nvme_delq_ctx *dq, struct nvme_dev *dev)
2298{
2299 dq->waiter = current;
2300 mb();
2301
2302 for (;;) {
2303 set_current_state(TASK_KILLABLE);
2304 if (!atomic_read(&dq->refcount))
2305 break;
2306 if (!schedule_timeout(ADMIN_TIMEOUT) ||
2307 fatal_signal_pending(current)) {
2308 set_current_state(TASK_RUNNING);
2309
2310 nvme_disable_ctrl(dev, readq(&dev->bar->cap));
2311 nvme_disable_queue(dev, 0);
2312
2313 send_sig(SIGKILL, dq->worker->task, 1);
2314 flush_kthread_worker(dq->worker);
2315 return;
2316 }
2317 }
2318 set_current_state(TASK_RUNNING);
2319}
2320
2321static void nvme_put_dq(struct nvme_delq_ctx *dq)
2322{
2323 atomic_dec(&dq->refcount);
2324 if (dq->waiter)
2325 wake_up_process(dq->waiter);
2326}
2327
2328static struct nvme_delq_ctx *nvme_get_dq(struct nvme_delq_ctx *dq)
2329{
2330 atomic_inc(&dq->refcount);
2331 return dq;
2332}
2333
2334static void nvme_del_queue_end(struct nvme_queue *nvmeq)
2335{
2336 struct nvme_delq_ctx *dq = nvmeq->cmdinfo.ctx;
2337
2338 nvme_clear_queue(nvmeq);
2339 nvme_put_dq(dq);
2340}
2341
2342static int adapter_async_del_queue(struct nvme_queue *nvmeq, u8 opcode,
2343 kthread_work_func_t fn)
2344{
2345 struct nvme_command c;
2346
2347 memset(&c, 0, sizeof(c));
2348 c.delete_queue.opcode = opcode;
2349 c.delete_queue.qid = cpu_to_le16(nvmeq->qid);
2350
2351 init_kthread_work(&nvmeq->cmdinfo.work, fn);
2352 return nvme_submit_admin_cmd_async(nvmeq->dev, &c, &nvmeq->cmdinfo);
2353}
2354
2355static void nvme_del_cq_work_handler(struct kthread_work *work)
2356{
2357 struct nvme_queue *nvmeq = container_of(work, struct nvme_queue,
2358 cmdinfo.work);
2359 nvme_del_queue_end(nvmeq);
2360}
2361
2362static int nvme_delete_cq(struct nvme_queue *nvmeq)
2363{
2364 return adapter_async_del_queue(nvmeq, nvme_admin_delete_cq,
2365 nvme_del_cq_work_handler);
2366}
2367
2368static void nvme_del_sq_work_handler(struct kthread_work *work)
2369{
2370 struct nvme_queue *nvmeq = container_of(work, struct nvme_queue,
2371 cmdinfo.work);
2372 int status = nvmeq->cmdinfo.status;
2373
2374 if (!status)
2375 status = nvme_delete_cq(nvmeq);
2376 if (status)
2377 nvme_del_queue_end(nvmeq);
2378}
2379
2380static int nvme_delete_sq(struct nvme_queue *nvmeq)
2381{
2382 return adapter_async_del_queue(nvmeq, nvme_admin_delete_sq,
2383 nvme_del_sq_work_handler);
2384}
2385
2386static void nvme_del_queue_start(struct kthread_work *work)
2387{
2388 struct nvme_queue *nvmeq = container_of(work, struct nvme_queue,
2389 cmdinfo.work);
2390 allow_signal(SIGKILL);
2391 if (nvme_delete_sq(nvmeq))
2392 nvme_del_queue_end(nvmeq);
2393}
2394
2395static void nvme_disable_io_queues(struct nvme_dev *dev)
2396{
2397 int i;
2398 DEFINE_KTHREAD_WORKER_ONSTACK(worker);
2399 struct nvme_delq_ctx dq;
2400 struct task_struct *kworker_task = kthread_run(kthread_worker_fn,
2401 &worker, "nvme%d", dev->instance);
2402
2403 if (IS_ERR(kworker_task)) {
2404 dev_err(&dev->pci_dev->dev,
2405 "Failed to create queue del task\n");
2406 for (i = dev->queue_count - 1; i > 0; i--)
2407 nvme_disable_queue(dev, i);
2408 return;
2409 }
2410
2411 dq.waiter = NULL;
2412 atomic_set(&dq.refcount, 0);
2413 dq.worker = &worker;
2414 for (i = dev->queue_count - 1; i > 0; i--) {
5a92e700 2415 struct nvme_queue *nvmeq = raw_nvmeq(dev, i);
4d115420
KB		 2416
2417 if (nvme_suspend_queue(nvmeq))
2418 continue;
2419 nvmeq->cmdinfo.ctx = nvme_get_dq(&dq);
2420 nvmeq->cmdinfo.worker = dq.worker;
2421 init_kthread_work(&nvmeq->cmdinfo.work, nvme_del_queue_start);
2422 queue_kthread_work(dq.worker, &nvmeq->cmdinfo.work);
2423 }
2424 nvme_wait_dq(&dq, dev);
2425 kthread_stop(kworker_task);
2426}
2427
b9afca3e
DM		 2428/*
2429* Remove the node from the device list and check
2430* for whether or not we need to stop the nvme_thread.
2431*/
2432static void nvme_dev_list_remove(struct nvme_dev *dev)
2433{
2434 struct task_struct *tmp = NULL;
2435
2436 spin_lock(&dev_list_lock);
2437 list_del_init(&dev->node);
2438 if (list_empty(&dev_list) && !IS_ERR_OR_NULL(nvme_thread)) {
2439 tmp = nvme_thread;
2440 nvme_thread = NULL;
2441 }
2442 spin_unlock(&dev_list_lock);
2443
2444 if (tmp)
2445 kthread_stop(tmp);
2446}
2447
f0b50732 2448static void nvme_dev_shutdown(struct nvme_dev *dev)
b60503ba 2449{
22404274
KB		 2450 int i;
2451
d4b4ff8e 2452 dev->initialized = 0;
33b1e95c 2453 unregister_hotcpu_notifier(&dev->nb);
b60503ba 2454
b9afca3e 2455 nvme_dev_list_remove(dev);
1fa6aead 2456
4d115420
KB		 2457 if (!dev->bar || (dev->bar && readl(&dev->bar->csts) == -1)) {
2458 for (i = dev->queue_count - 1; i >= 0; i--) {
5a92e700 2459 struct nvme_queue *nvmeq = raw_nvmeq(dev, i);
4d115420
KB		 2460 nvme_suspend_queue(nvmeq);
2461 nvme_clear_queue(nvmeq);
2462 }
2463 } else {
2464 nvme_disable_io_queues(dev);
1894d8f1 2465 nvme_shutdown_ctrl(dev);
4d115420
KB		 2466 nvme_disable_queue(dev, 0);
2467 }
f0b50732
KB		 2468 nvme_dev_unmap(dev);
2469}
2470
2471static void nvme_dev_remove(struct nvme_dev *dev)
2472{
9ac27090 2473 struct nvme_ns *ns;
f0b50732 2474
9ac27090
KB		 2475 list_for_each_entry(ns, &dev->namespaces, list) {
2476 if (ns->disk->flags & GENHD_FL_UP)
2477 del_gendisk(ns->disk);
2478 if (!blk_queue_dying(ns->queue))
2479 blk_cleanup_queue(ns->queue);
b60503ba 2480 }
b60503ba
MW		 2481}
2482
091b6092
MW		 2483static int nvme_setup_prp_pools(struct nvme_dev *dev)
2484{
2485 struct device *dmadev = &dev->pci_dev->dev;
2486 dev->prp_page_pool = dma_pool_create("prp list page", dmadev,
2487 PAGE_SIZE, PAGE_SIZE, 0);
2488 if (!dev->prp_page_pool)
2489 return -ENOMEM;
2490
99802a7a
MW		 2491 /* Optimisation for I/Os between 4k and 128k */
2492 dev->prp_small_pool = dma_pool_create("prp list 256", dmadev,
2493 256, 256, 0);
2494 if (!dev->prp_small_pool) {
2495 dma_pool_destroy(dev->prp_page_pool);
2496 return -ENOMEM;
2497 }
091b6092
MW		 2498 return 0;
2499}
2500
2501static void nvme_release_prp_pools(struct nvme_dev *dev)
2502{
2503 dma_pool_destroy(dev->prp_page_pool);
99802a7a 2504 dma_pool_destroy(dev->prp_small_pool);
091b6092
MW		 2505}
2506
cd58ad7d
QSA		 2507static DEFINE_IDA(nvme_instance_ida);
2508
2509static int nvme_set_instance(struct nvme_dev *dev)
b60503ba 2510{
cd58ad7d
QSA		 2511 int instance, error;
2512
2513 do {
2514 if (!ida_pre_get(&nvme_instance_ida, GFP_KERNEL))
2515 return -ENODEV;
2516
2517 spin_lock(&dev_list_lock);
2518 error = ida_get_new(&nvme_instance_ida, &instance);
2519 spin_unlock(&dev_list_lock);
2520 } while (error == -EAGAIN);
2521
2522 if (error)
2523 return -ENODEV;
2524
2525 dev->instance = instance;
2526 return 0;
b60503ba
MW		 2527}
2528
2529static void nvme_release_instance(struct nvme_dev *dev)
2530{
cd58ad7d
QSA		 2531 spin_lock(&dev_list_lock);
2532 ida_remove(&nvme_instance_ida, dev->instance);
2533 spin_unlock(&dev_list_lock);
b60503ba
MW		 2534}
2535
9ac27090
KB		 2536static void nvme_free_namespaces(struct nvme_dev *dev)
2537{
2538 struct nvme_ns *ns, *next;
2539
2540 list_for_each_entry_safe(ns, next, &dev->namespaces, list) {
2541 list_del(&ns->list);
2542 put_disk(ns->disk);
2543 kfree(ns);
2544 }
2545}
2546
5e82e952
KB		 2547static void nvme_free_dev(struct kref *kref)
2548{
2549 struct nvme_dev *dev = container_of(kref, struct nvme_dev, kref);
9ac27090
KB		 2550
2551 nvme_free_namespaces(dev);
42f61420 2552 free_percpu(dev->io_queue);
5e82e952
KB		 2553 kfree(dev->queues);
2554 kfree(dev->entry);
2555 kfree(dev);
2556}
2557
2558static int nvme_dev_open(struct inode *inode, struct file *f)
2559{
2560 struct nvme_dev *dev = container_of(f->private_data, struct nvme_dev,
2561 miscdev);
2562 kref_get(&dev->kref);
2563 f->private_data = dev;
2564 return 0;
2565}
2566
2567static int nvme_dev_release(struct inode *inode, struct file *f)
2568{
2569 struct nvme_dev *dev = f->private_data;
2570 kref_put(&dev->kref, nvme_free_dev);
2571 return 0;
2572}
2573
2574static long nvme_dev_ioctl(struct file *f, unsigned int cmd, unsigned long arg)
2575{
2576 struct nvme_dev *dev = f->private_data;
2577 switch (cmd) {
2578 case NVME_IOCTL_ADMIN_CMD:
2579 return nvme_user_admin_cmd(dev, (void __user *)arg);
2580 default:
2581 return -ENOTTY;
2582 }
2583}
2584
2585static const struct file_operations nvme_dev_fops = {
2586 .owner = THIS_MODULE,
2587 .open = nvme_dev_open,
2588 .release = nvme_dev_release,
2589 .unlocked_ioctl = nvme_dev_ioctl,
2590 .compat_ioctl = nvme_dev_ioctl,
2591};
2592
f0b50732
KB		 2593static int nvme_dev_start(struct nvme_dev *dev)
2594{
2595 int result;
b9afca3e 2596 bool start_thread = false;
f0b50732
KB		 2597
2598 result = nvme_dev_map(dev);
2599 if (result)
2600 return result;
2601
2602 result = nvme_configure_admin_queue(dev);
2603 if (result)
2604 goto unmap;
2605
2606 spin_lock(&dev_list_lock);
b9afca3e
DM		 2607 if (list_empty(&dev_list) && IS_ERR_OR_NULL(nvme_thread)) {
2608 start_thread = true;
2609 nvme_thread = NULL;
2610 }
f0b50732
KB		 2611 list_add(&dev->node, &dev_list);
2612 spin_unlock(&dev_list_lock);
2613
b9afca3e
DM		 2614 if (start_thread) {
2615 nvme_thread = kthread_run(nvme_kthread, NULL, "nvme");
2616 wake_up(&nvme_kthread_wait);
2617 } else
2618 wait_event_killable(nvme_kthread_wait, nvme_thread);
2619
2620 if (IS_ERR_OR_NULL(nvme_thread)) {
2621 result = nvme_thread ? PTR_ERR(nvme_thread) : -EINTR;
2622 goto disable;
2623 }
2624
f0b50732 2625 result = nvme_setup_io_queues(dev);
d82e8bfd 2626 if (result && result != -EBUSY)
f0b50732
KB		 2627 goto disable;
2628
d82e8bfd 2629 return result;
f0b50732
KB		 2630
2631 disable:
a1a5ef99 2632 nvme_disable_queue(dev, 0);
b9afca3e 2633 nvme_dev_list_remove(dev);
f0b50732
KB		 2634 unmap:
2635 nvme_dev_unmap(dev);
2636 return result;
2637}
2638
9a6b9458
KB		 2639static int nvme_remove_dead_ctrl(void *arg)
2640{
2641 struct nvme_dev *dev = (struct nvme_dev *)arg;
2642 struct pci_dev *pdev = dev->pci_dev;
2643
2644 if (pci_get_drvdata(pdev))
2645 pci_stop_and_remove_bus_device(pdev);
2646 kref_put(&dev->kref, nvme_free_dev);
2647 return 0;
2648}
2649
2650static void nvme_remove_disks(struct work_struct *ws)
2651{
9a6b9458
KB		 2652 struct nvme_dev *dev = container_of(ws, struct nvme_dev, reset_work);
2653
2654 nvme_dev_remove(dev);
5a92e700 2655 nvme_free_queues(dev, 1);
9a6b9458
KB		 2656}
2657
2658static int nvme_dev_resume(struct nvme_dev *dev)
2659{
2660 int ret;
2661
2662 ret = nvme_dev_start(dev);
2663 if (ret && ret != -EBUSY)
2664 return ret;
2665 if (ret == -EBUSY) {
2666 spin_lock(&dev_list_lock);
9ca97374 2667 dev->reset_workfn = nvme_remove_disks;
9a6b9458
KB		 2668 queue_work(nvme_workq, &dev->reset_work);
2669 spin_unlock(&dev_list_lock);
2670 }
d4b4ff8e 2671 dev->initialized = 1;
9a6b9458
KB		 2672 return 0;
2673}
2674
2675static void nvme_dev_reset(struct nvme_dev *dev)
2676{
2677 nvme_dev_shutdown(dev);
2678 if (nvme_dev_resume(dev)) {
2679 dev_err(&dev->pci_dev->dev, "Device failed to resume\n");
2680 kref_get(&dev->kref);
2681 if (IS_ERR(kthread_run(nvme_remove_dead_ctrl, dev, "nvme%d",
2682 dev->instance))) {
2683 dev_err(&dev->pci_dev->dev,
2684 "Failed to start controller remove task\n");
2685 kref_put(&dev->kref, nvme_free_dev);
2686 }
2687 }
2688}
2689
2690static void nvme_reset_failed_dev(struct work_struct *ws)
2691{
2692 struct nvme_dev *dev = container_of(ws, struct nvme_dev, reset_work);
2693 nvme_dev_reset(dev);
2694}
2695
9ca97374
TH		 2696static void nvme_reset_workfn(struct work_struct *work)
2697{
2698 struct nvme_dev *dev = container_of(work, struct nvme_dev, reset_work);
2699 dev->reset_workfn(work);
2700}
2701
8d85fce7 2702static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id)
b60503ba 2703{
0877cb0d 2704 int result = -ENOMEM;
b60503ba
MW		 2705 struct nvme_dev *dev;
2706
2707 dev = kzalloc(sizeof(*dev), GFP_KERNEL);
2708 if (!dev)
2709 return -ENOMEM;
2710 dev->entry = kcalloc(num_possible_cpus(), sizeof(*dev->entry),
2711 GFP_KERNEL);
2712 if (!dev->entry)
2713 goto free;
1b23484b
MW		 2714 dev->queues = kcalloc(num_possible_cpus() + 1, sizeof(void *),
2715 GFP_KERNEL);
b60503ba
MW		 2716 if (!dev->queues)
2717 goto free;
42f61420
KB		 2718 dev->io_queue = alloc_percpu(unsigned short);
2719 if (!dev->io_queue)
2720 goto free;
b60503ba
MW		 2721
2722 INIT_LIST_HEAD(&dev->namespaces);
9ca97374
TH		 2723 dev->reset_workfn = nvme_reset_failed_dev;
2724 INIT_WORK(&dev->reset_work, nvme_reset_workfn);
b60503ba 2725 dev->pci_dev = pdev;
9a6b9458 2726 pci_set_drvdata(pdev, dev);
cd58ad7d
QSA		 2727 result = nvme_set_instance(dev);
2728 if (result)
0877cb0d 2729 goto free;
b60503ba 2730
091b6092
MW		 2731 result = nvme_setup_prp_pools(dev);
2732 if (result)
0877cb0d 2733 goto release;
091b6092 2734
fb35e914 2735 kref_init(&dev->kref);
f0b50732 2736 result = nvme_dev_start(dev);
d82e8bfd
KB		 2737 if (result) {
2738 if (result == -EBUSY)
2739 goto create_cdev;
0877cb0d 2740 goto release_pools;
d82e8bfd 2741 }
b60503ba 2742
740216fc 2743 result = nvme_dev_add(dev);
d82e8bfd 2744 if (result)
f0b50732 2745 goto shutdown;
740216fc 2746
d82e8bfd 2747 create_cdev:
5e82e952
KB		 2748 scnprintf(dev->name, sizeof(dev->name), "nvme%d", dev->instance);
2749 dev->miscdev.minor = MISC_DYNAMIC_MINOR;
2750 dev->miscdev.parent = &pdev->dev;
2751 dev->miscdev.name = dev->name;
2752 dev->miscdev.fops = &nvme_dev_fops;
2753 result = misc_register(&dev->miscdev);
2754 if (result)
2755 goto remove;
2756
d4b4ff8e 2757 dev->initialized = 1;
b60503ba
MW		 2758 return 0;
2759
5e82e952
KB		 2760 remove:
2761 nvme_dev_remove(dev);
9ac27090 2762 nvme_free_namespaces(dev);
f0b50732
KB		 2763 shutdown:
2764 nvme_dev_shutdown(dev);
0877cb0d 2765 release_pools:
a1a5ef99 2766 nvme_free_queues(dev, 0);
091b6092 2767 nvme_release_prp_pools(dev);
0877cb0d
KB		 2768 release:
2769 nvme_release_instance(dev);
b60503ba 2770 free:
42f61420 2771 free_percpu(dev->io_queue);
b60503ba
MW		 2772 kfree(dev->queues);
2773 kfree(dev->entry);
2774 kfree(dev);
2775 return result;
2776}
2777
09ece142
KB		 2778static void nvme_shutdown(struct pci_dev *pdev)
2779{
2780 struct nvme_dev *dev = pci_get_drvdata(pdev);
2781 nvme_dev_shutdown(dev);
2782}
2783
8d85fce7 2784static void nvme_remove(struct pci_dev *pdev)
b60503ba
MW		 2785{
2786 struct nvme_dev *dev = pci_get_drvdata(pdev);
9a6b9458
KB		 2787
2788 spin_lock(&dev_list_lock);
2789 list_del_init(&dev->node);
2790 spin_unlock(&dev_list_lock);
2791
2792 pci_set_drvdata(pdev, NULL);
2793 flush_work(&dev->reset_work);
5e82e952 2794 misc_deregister(&dev->miscdev);
9a6b9458
KB		 2795 nvme_dev_remove(dev);
2796 nvme_dev_shutdown(dev);
a1a5ef99 2797 nvme_free_queues(dev, 0);
5a92e700 2798 rcu_barrier();
9a6b9458
KB		 2799 nvme_release_instance(dev);
2800 nvme_release_prp_pools(dev);
5e82e952 2801 kref_put(&dev->kref, nvme_free_dev);
b60503ba
MW		 2802}
2803
2804/* These functions are yet to be implemented */
2805#define nvme_error_detected NULL
2806#define nvme_dump_registers NULL
2807#define nvme_link_reset NULL
2808#define nvme_slot_reset NULL
2809#define nvme_error_resume NULL
cd638946 2810
671a6018 2811#ifdef CONFIG_PM_SLEEP
cd638946
KB		 2812static int nvme_suspend(struct device *dev)
2813{
2814 struct pci_dev *pdev = to_pci_dev(dev);
2815 struct nvme_dev *ndev = pci_get_drvdata(pdev);
2816
2817 nvme_dev_shutdown(ndev);
2818 return 0;
2819}
2820
2821static int nvme_resume(struct device *dev)
2822{
2823 struct pci_dev *pdev = to_pci_dev(dev);
2824 struct nvme_dev *ndev = pci_get_drvdata(pdev);
cd638946 2825
9a6b9458 2826 if (nvme_dev_resume(ndev) && !work_busy(&ndev->reset_work)) {
9ca97374 2827 ndev->reset_workfn = nvme_reset_failed_dev;
9a6b9458
KB		 2828 queue_work(nvme_workq, &ndev->reset_work);
2829 }
2830 return 0;
cd638946 2831}
671a6018 2832#endif
cd638946
KB		 2833
2834static SIMPLE_DEV_PM_OPS(nvme_dev_pm_ops, nvme_suspend, nvme_resume);
b60503ba 2835
1d352035 2836static const struct pci_error_handlers nvme_err_handler = {
b60503ba
MW		 2837 .error_detected = nvme_error_detected,
2838 .mmio_enabled = nvme_dump_registers,
2839 .link_reset = nvme_link_reset,
2840 .slot_reset = nvme_slot_reset,
2841 .resume = nvme_error_resume,
2842};
2843
2844/* Move to pci_ids.h later */
2845#define PCI_CLASS_STORAGE_EXPRESS 0x010802
2846
6eb0d698 2847static const struct pci_device_id nvme_id_table[] = {
b60503ba
MW		 2848 { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
2849 { 0, }
2850};
2851MODULE_DEVICE_TABLE(pci, nvme_id_table);
2852
2853static struct pci_driver nvme_driver = {
2854 .name = "nvme",
2855 .id_table = nvme_id_table,
2856 .probe = nvme_probe,
8d85fce7 2857 .remove = nvme_remove,
09ece142 2858 .shutdown = nvme_shutdown,
cd638946
KB		 2859 .driver = {
2860 .pm = &nvme_dev_pm_ops,
2861 },
b60503ba
MW		 2862 .err_handler = &nvme_err_handler,
2863};
2864
2865static int __init nvme_init(void)
2866{
0ac13140 2867 int result;
1fa6aead 2868
b9afca3e 2869 init_waitqueue_head(&nvme_kthread_wait);
b60503ba 2870
9a6b9458
KB		 2871 nvme_workq = create_singlethread_workqueue("nvme");
2872 if (!nvme_workq)
b9afca3e 2873 return -ENOMEM;
9a6b9458 2874
5c42ea16
KB		 2875 result = register_blkdev(nvme_major, "nvme");
2876 if (result < 0)
9a6b9458 2877 goto kill_workq;
5c42ea16 2878 else if (result > 0)
0ac13140 2879 nvme_major = result;
b60503ba
MW		 2880
2881 result = pci_register_driver(&nvme_driver);
1fa6aead
MW		 2882 if (result)
2883 goto unregister_blkdev;
2884 return 0;
b60503ba 2885
1fa6aead 2886 unregister_blkdev:
b60503ba 2887 unregister_blkdev(nvme_major, "nvme");
9a6b9458
KB		 2888 kill_workq:
2889 destroy_workqueue(nvme_workq);
b60503ba
MW		 2890 return result;
2891}
2892
2893static void __exit nvme_exit(void)
2894{
2895 pci_unregister_driver(&nvme_driver);
2896 unregister_blkdev(nvme_major, "nvme");
9a6b9458 2897 destroy_workqueue(nvme_workq);
b9afca3e 2898 BUG_ON(nvme_thread && !IS_ERR(nvme_thread));
b60503ba
MW		 2899}
2900
2901MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
2902MODULE_LICENSE("GPL");
6eb0d698 2903MODULE_VERSION("0.9");
b60503ba
MW		 2904module_init(nvme_init);
2905module_exit(nvme_exit);
Linux 6.x block layer and io_uring tree(s)