projects / linux-block.git / blame
? search:
summary | shortlog | log | commit | commitdiff | tree
blob | blame (incremental) | history | HEAD
NVMe: Improve error messages
[linux-block.git] / drivers / block / nvme-core.c
CommitLineData
b60503ba
MW		 1/*
2 * NVM Express device driver
6eb0d698 3 * Copyright (c) 2011-2014, Intel Corporation.
b60503ba
MW		 4 *
5 * This program is free software; you can redistribute it and/or modify it
6 * under the terms and conditions of the GNU General Public License,
7 * version 2, as published by the Free Software Foundation.
8 *
9 * This program is distributed in the hope it will be useful, but WITHOUT
10 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
11 * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
12 * more details.
b60503ba
MW		 13 */
14
15#include <linux/nvme.h>
16#include <linux/bio.h>
8de05535 17#include <linux/bitops.h>
b60503ba 18#include <linux/blkdev.h>
42f61420 19#include <linux/cpu.h>
fd63e9ce 20#include <linux/delay.h>
b60503ba
MW		 21#include <linux/errno.h>
22#include <linux/fs.h>
23#include <linux/genhd.h>
4cc09e2d 24#include <linux/hdreg.h>
5aff9382 25#include <linux/idr.h>
b60503ba
MW		 26#include <linux/init.h>
27#include <linux/interrupt.h>
28#include <linux/io.h>
29#include <linux/kdev_t.h>
1fa6aead 30#include <linux/kthread.h>
b60503ba
MW		 31#include <linux/kernel.h>
32#include <linux/mm.h>
33#include <linux/module.h>
34#include <linux/moduleparam.h>
35#include <linux/pci.h>
42f61420 36#include <linux/percpu.h>
be7b6275 37#include <linux/poison.h>
c3bfe717 38#include <linux/ptrace.h>
b60503ba
MW		 39#include <linux/sched.h>
40#include <linux/slab.h>
41#include <linux/types.h>
5d0f6131 42#include <scsi/sg.h>
797a796a
HM		 43#include <asm-generic/io-64-nonatomic-lo-hi.h>
44
b60503ba
MW		 45#define NVME_Q_DEPTH 1024
46#define SQ_SIZE(depth) (depth * sizeof(struct nvme_command))
47#define CQ_SIZE(depth) (depth * sizeof(struct nvme_completion))
e85248e5 48#define ADMIN_TIMEOUT (60 * HZ)
edd10d33 49#define IOD_TIMEOUT (4 * NVME_IO_TIMEOUT)
b60503ba 50
b355084a
KB		 51unsigned char io_timeout = 30;
52module_param(io_timeout, byte, 0644);
53MODULE_PARM_DESC(io_timeout, "timeout in seconds for I/O");
b60503ba
MW		 54
55static int nvme_major;
56module_param(nvme_major, int, 0);
57
58ffacb5
MW		 58static int use_threaded_interrupts;
59module_param(use_threaded_interrupts, int, 0);
60
1fa6aead
MW		 61static DEFINE_SPINLOCK(dev_list_lock);
62static LIST_HEAD(dev_list);
63static struct task_struct *nvme_thread;
9a6b9458 64static struct workqueue_struct *nvme_workq;
b9afca3e 65static wait_queue_head_t nvme_kthread_wait;
1fa6aead 66
d4b4ff8e
KB		 67static void nvme_reset_failed_dev(struct work_struct *ws);
68
4d115420
KB		 69struct async_cmd_info {
70 struct kthread_work work;
71 struct kthread_worker *worker;
72 u32 result;
73 int status;
74 void *ctx;
75};
1fa6aead 76
b60503ba
MW		 77/*
78 * An NVM Express queue. Each device has at least two (one for admin
79 * commands and one for I/O commands).
80 */
81struct nvme_queue {
5a92e700 82 struct rcu_head r_head;
b60503ba 83 struct device *q_dmadev;
091b6092 84 struct nvme_dev *dev;
3193f07b 85 char irqname[24]; /* nvme4294967295-65535\0 */
b60503ba
MW		 86 spinlock_t q_lock;
87 struct nvme_command *sq_cmds;
88 volatile struct nvme_completion *cqes;
89 dma_addr_t sq_dma_addr;
90 dma_addr_t cq_dma_addr;
91 wait_queue_head_t sq_full;
1fa6aead 92 wait_queue_t sq_cong_wait;
b60503ba 93 struct bio_list sq_cong;
edd10d33 94 struct list_head iod_bio;
b60503ba
MW		 95 u32 __iomem *q_db;
96 u16 q_depth;
97 u16 cq_vector;
98 u16 sq_head;
99 u16 sq_tail;
100 u16 cq_head;
c30341dc 101 u16 qid;
e9539f47
MW		 102 u8 cq_phase;
103 u8 cqe_seen;
22404274 104 u8 q_suspended;
42f61420 105 cpumask_var_t cpu_mask;
4d115420 106 struct async_cmd_info cmdinfo;
b60503ba
MW		 107 unsigned long cmdid_data[];
108};
109
110/*
111 * Check we didin't inadvertently grow the command struct
112 */
113static inline void _nvme_check_size(void)
114{
115 BUILD_BUG_ON(sizeof(struct nvme_rw_command) != 64);
116 BUILD_BUG_ON(sizeof(struct nvme_create_cq) != 64);
117 BUILD_BUG_ON(sizeof(struct nvme_create_sq) != 64);
118 BUILD_BUG_ON(sizeof(struct nvme_delete_queue) != 64);
119 BUILD_BUG_ON(sizeof(struct nvme_features) != 64);
f8ebf840 120 BUILD_BUG_ON(sizeof(struct nvme_format_cmd) != 64);
c30341dc 121 BUILD_BUG_ON(sizeof(struct nvme_abort_cmd) != 64);
b60503ba
MW		 122 BUILD_BUG_ON(sizeof(struct nvme_command) != 64);
123 BUILD_BUG_ON(sizeof(struct nvme_id_ctrl) != 4096);
124 BUILD_BUG_ON(sizeof(struct nvme_id_ns) != 4096);
125 BUILD_BUG_ON(sizeof(struct nvme_lba_range_type) != 64);
6ecec745 126 BUILD_BUG_ON(sizeof(struct nvme_smart_log) != 512);
b60503ba
MW		 127}
128
edd10d33 129typedef void (*nvme_completion_fn)(struct nvme_queue *, void *,
c2f5b650
MW		 130 struct nvme_completion *);
131
e85248e5 132struct nvme_cmd_info {
c2f5b650
MW		 133 nvme_completion_fn fn;
134 void *ctx;
e85248e5 135 unsigned long timeout;
c30341dc 136 int aborted;
e85248e5
MW		 137};
138
139static struct nvme_cmd_info *nvme_cmd_info(struct nvme_queue *nvmeq)
140{
141 return (void *)&nvmeq->cmdid_data[BITS_TO_LONGS(nvmeq->q_depth)];
142}
143
22404274
KB		 144static unsigned nvme_queue_extra(int depth)
145{
146 return DIV_ROUND_UP(depth, 8) + (depth * sizeof(struct nvme_cmd_info));
147}
148
b60503ba 149/**
714a7a22
MW		 150 * alloc_cmdid() - Allocate a Command ID
151 * @nvmeq: The queue that will be used for this command
152 * @ctx: A pointer that will be passed to the handler
c2f5b650 153 * @handler: The function to call on completion
b60503ba
MW		 154 *
155 * Allocate a Command ID for a queue. The data passed in will
156 * be passed to the completion handler. This is implemented by using
157 * the bottom two bits of the ctx pointer to store the handler ID.
158 * Passing in a pointer that's not 4-byte aligned will cause a BUG.
159 * We can change this if it becomes a problem.
184d2944
MW		 160 *
161 * May be called with local interrupts disabled and the q_lock held,
162 * or with interrupts enabled and no locks held.
b60503ba 163 */
c2f5b650
MW		 164static int alloc_cmdid(struct nvme_queue *nvmeq, void *ctx,
165 nvme_completion_fn handler, unsigned timeout)
b60503ba 166{
e6d15f79 167 int depth = nvmeq->q_depth - 1;
e85248e5 168 struct nvme_cmd_info *info = nvme_cmd_info(nvmeq);
b60503ba
MW		 169 int cmdid;
170
b60503ba
MW		 171 do {
172 cmdid = find_first_zero_bit(nvmeq->cmdid_data, depth);
173 if (cmdid >= depth)
174 return -EBUSY;
175 } while (test_and_set_bit(cmdid, nvmeq->cmdid_data));
176
c2f5b650
MW		 177 info[cmdid].fn = handler;
178 info[cmdid].ctx = ctx;
e85248e5 179 info[cmdid].timeout = jiffies + timeout;
c30341dc 180 info[cmdid].aborted = 0;
b60503ba
MW		 181 return cmdid;
182}
183
184static int alloc_cmdid_killable(struct nvme_queue *nvmeq, void *ctx,
c2f5b650 185 nvme_completion_fn handler, unsigned timeout)
b60503ba
MW		 186{
187 int cmdid;
188 wait_event_killable(nvmeq->sq_full,
e85248e5 189 (cmdid = alloc_cmdid(nvmeq, ctx, handler, timeout)) >= 0);
b60503ba
MW		 190 return (cmdid < 0) ? -EINTR : cmdid;
191}
192
c2f5b650
MW		 193/* Special values must be less than 0x1000 */
194#define CMD_CTX_BASE ((void *)POISON_POINTER_DELTA)
d2d87034
MW		 195#define CMD_CTX_CANCELLED (0x30C + CMD_CTX_BASE)
196#define CMD_CTX_COMPLETED (0x310 + CMD_CTX_BASE)
197#define CMD_CTX_INVALID (0x314 + CMD_CTX_BASE)
00df5cb4 198#define CMD_CTX_FLUSH (0x318 + CMD_CTX_BASE)
c30341dc 199#define CMD_CTX_ABORT (0x31C + CMD_CTX_BASE)
be7b6275 200
edd10d33 201static void special_completion(struct nvme_queue *nvmeq, void *ctx,
c2f5b650
MW		 202 struct nvme_completion *cqe)
203{
204 if (ctx == CMD_CTX_CANCELLED)
205 return;
206 if (ctx == CMD_CTX_FLUSH)
207 return;
c30341dc 208 if (ctx == CMD_CTX_ABORT) {
edd10d33 209 ++nvmeq->dev->abort_limit;
c30341dc
KB		 210 return;
211 }
c2f5b650 212 if (ctx == CMD_CTX_COMPLETED) {
edd10d33 213 dev_warn(nvmeq->q_dmadev,
c2f5b650
MW		 214 "completed id %d twice on queue %d\n",
215 cqe->command_id, le16_to_cpup(&cqe->sq_id));
216 return;
217 }
218 if (ctx == CMD_CTX_INVALID) {
edd10d33 219 dev_warn(nvmeq->q_dmadev,
c2f5b650
MW		 220 "invalid id %d completed on queue %d\n",
221 cqe->command_id, le16_to_cpup(&cqe->sq_id));
222 return;
223 }
224
edd10d33 225 dev_warn(nvmeq->q_dmadev, "Unknown special completion %p\n", ctx);
c2f5b650
MW		 226}
227
edd10d33 228static void async_completion(struct nvme_queue *nvmeq, void *ctx,
4d115420
KB		 229 struct nvme_completion *cqe)
230{
231 struct async_cmd_info *cmdinfo = ctx;
232 cmdinfo->result = le32_to_cpup(&cqe->result);
233 cmdinfo->status = le16_to_cpup(&cqe->status) >> 1;
234 queue_kthread_work(cmdinfo->worker, &cmdinfo->work);
235}
236
184d2944
MW		 237/*
238 * Called with local interrupts disabled and the q_lock held. May not sleep.
239 */
c2f5b650
MW		 240static void *free_cmdid(struct nvme_queue *nvmeq, int cmdid,
241 nvme_completion_fn *fn)
b60503ba 242{
c2f5b650 243 void *ctx;
e85248e5 244 struct nvme_cmd_info *info = nvme_cmd_info(nvmeq);
b60503ba 245
c2f5b650
MW		 246 if (cmdid >= nvmeq->q_depth) {
247 *fn = special_completion;
48e3d398 248 return CMD_CTX_INVALID;
c2f5b650 249 }
859361a2
KB		 250 if (fn)
251 *fn = info[cmdid].fn;
c2f5b650
MW		 252 ctx = info[cmdid].ctx;
253 info[cmdid].fn = special_completion;
e85248e5 254 info[cmdid].ctx = CMD_CTX_COMPLETED;
b60503ba
MW		 255 clear_bit(cmdid, nvmeq->cmdid_data);
256 wake_up(&nvmeq->sq_full);
c2f5b650 257 return ctx;
b60503ba
MW		 258}
259
c2f5b650
MW		 260static void *cancel_cmdid(struct nvme_queue *nvmeq, int cmdid,
261 nvme_completion_fn *fn)
3c0cf138 262{
c2f5b650 263 void *ctx;
e85248e5 264 struct nvme_cmd_info *info = nvme_cmd_info(nvmeq);
c2f5b650
MW		 265 if (fn)
266 *fn = info[cmdid].fn;
267 ctx = info[cmdid].ctx;
268 info[cmdid].fn = special_completion;
e85248e5 269 info[cmdid].ctx = CMD_CTX_CANCELLED;
c2f5b650 270 return ctx;
3c0cf138
MW		 271}
272
5a92e700 273static struct nvme_queue *raw_nvmeq(struct nvme_dev *dev, int qid)
b60503ba 274{
5a92e700 275 return rcu_dereference_raw(dev->queues[qid]);
b60503ba
MW		 276}
277
4f5099af 278static struct nvme_queue *get_nvmeq(struct nvme_dev *dev) __acquires(RCU)
5a92e700 279{
42f61420 280 unsigned queue_id = get_cpu_var(*dev->io_queue);
5a92e700 281 rcu_read_lock();
42f61420 282 return rcu_dereference(dev->queues[queue_id]);
5a92e700
KB		 283}
284
4f5099af 285static void put_nvmeq(struct nvme_queue *nvmeq) __releases(RCU)
b60503ba 286{
5a92e700 287 rcu_read_unlock();
42f61420 288 put_cpu_var(nvmeq->dev->io_queue);
b60503ba
MW		 289}
290
4f5099af
KB		 291static struct nvme_queue *lock_nvmeq(struct nvme_dev *dev, int q_idx)
292 __acquires(RCU)
b60503ba 293{
4f5099af
KB		 294 rcu_read_lock();
295 return rcu_dereference(dev->queues[q_idx]);
296}
297
298static void unlock_nvmeq(struct nvme_queue *nvmeq) __releases(RCU)
299{
300 rcu_read_unlock();
b60503ba
MW		 301}
302
303/**
714a7a22 304 * nvme_submit_cmd() - Copy a command into a queue and ring the doorbell
b60503ba
MW		 305 * @nvmeq: The queue to use
306 * @cmd: The command to send
307 *
308 * Safe to use from interrupt context
309 */
310static int nvme_submit_cmd(struct nvme_queue *nvmeq, struct nvme_command *cmd)
311{
312 unsigned long flags;
313 u16 tail;
b60503ba 314 spin_lock_irqsave(&nvmeq->q_lock, flags);
4f5099af
KB		 315 if (nvmeq->q_suspended) {
316 spin_unlock_irqrestore(&nvmeq->q_lock, flags);
317 return -EBUSY;
318 }
b60503ba
MW		 319 tail = nvmeq->sq_tail;
320 memcpy(&nvmeq->sq_cmds[tail], cmd, sizeof(*cmd));
b60503ba
MW		 321 if (++tail == nvmeq->q_depth)
322 tail = 0;
7547881d 323 writel(tail, nvmeq->q_db);
b60503ba
MW		 324 nvmeq->sq_tail = tail;
325 spin_unlock_irqrestore(&nvmeq->q_lock, flags);
326
327 return 0;
328}
329
eca18b23 330static __le64 **iod_list(struct nvme_iod *iod)
e025344c 331{
eca18b23 332 return ((void *)iod) + iod->offset;
e025344c
SMM		 333}
334
eca18b23
MW		 335/*
336 * Will slightly overestimate the number of pages needed. This is OK
337 * as it only leads to a small amount of wasted memory for the lifetime of
338 * the I/O.
339 */
340static int nvme_npages(unsigned size)
341{
342 unsigned nprps = DIV_ROUND_UP(size + PAGE_SIZE, PAGE_SIZE);
343 return DIV_ROUND_UP(8 * nprps, PAGE_SIZE - 8);
344}
b60503ba 345
eca18b23
MW		 346static struct nvme_iod *
347nvme_alloc_iod(unsigned nseg, unsigned nbytes, gfp_t gfp)
b60503ba 348{
eca18b23
MW		 349 struct nvme_iod *iod = kmalloc(sizeof(struct nvme_iod) +
350 sizeof(__le64 *) * nvme_npages(nbytes) +
351 sizeof(struct scatterlist) * nseg, gfp);
352
353 if (iod) {
354 iod->offset = offsetof(struct nvme_iod, sg[nseg]);
355 iod->npages = -1;
356 iod->length = nbytes;
2b196034 357 iod->nents = 0;
edd10d33 358 iod->first_dma = 0ULL;
6198221f 359 iod->start_time = jiffies;
eca18b23
MW		 360 }
361
362 return iod;
b60503ba
MW		 363}
364
5d0f6131 365void nvme_free_iod(struct nvme_dev *dev, struct nvme_iod *iod)
b60503ba 366{
eca18b23
MW		 367 const int last_prp = PAGE_SIZE / 8 - 1;
368 int i;
369 __le64 **list = iod_list(iod);
370 dma_addr_t prp_dma = iod->first_dma;
371
372 if (iod->npages == 0)
373 dma_pool_free(dev->prp_small_pool, list[0], prp_dma);
374 for (i = 0; i < iod->npages; i++) {
375 __le64 *prp_list = list[i];
376 dma_addr_t next_prp_dma = le64_to_cpu(prp_list[last_prp]);
377 dma_pool_free(dev->prp_page_pool, prp_list, prp_dma);
378 prp_dma = next_prp_dma;
379 }
380 kfree(iod);
b60503ba
MW		 381}
382
6198221f
KB		 383static void nvme_start_io_acct(struct bio *bio)
384{
385 struct gendisk *disk = bio->bi_bdev->bd_disk;
386 const int rw = bio_data_dir(bio);
387 int cpu = part_stat_lock();
388 part_round_stats(cpu, &disk->part0);
389 part_stat_inc(cpu, &disk->part0, ios[rw]);
390 part_stat_add(cpu, &disk->part0, sectors[rw], bio_sectors(bio));
391 part_inc_in_flight(&disk->part0, rw);
392 part_stat_unlock();
393}
394
395static void nvme_end_io_acct(struct bio *bio, unsigned long start_time)
396{
397 struct gendisk *disk = bio->bi_bdev->bd_disk;
398 const int rw = bio_data_dir(bio);
399 unsigned long duration = jiffies - start_time;
400 int cpu = part_stat_lock();
401 part_stat_add(cpu, &disk->part0, ticks[rw], duration);
402 part_round_stats(cpu, &disk->part0);
403 part_dec_in_flight(&disk->part0, rw);
404 part_stat_unlock();
405}
406
edd10d33 407static void bio_completion(struct nvme_queue *nvmeq, void *ctx,
b60503ba
MW		 408 struct nvme_completion *cqe)
409{
eca18b23
MW		 410 struct nvme_iod *iod = ctx;
411 struct bio *bio = iod->private;
b60503ba
MW		 412 u16 status = le16_to_cpup(&cqe->status) >> 1;
413
edd10d33
KB		 414 if (unlikely(status)) {
415 if (!(status & NVME_SC_DNR ||
416 bio->bi_rw & REQ_FAILFAST_MASK) &&
417 (jiffies - iod->start_time) < IOD_TIMEOUT) {
418 if (!waitqueue_active(&nvmeq->sq_full))
419 add_wait_queue(&nvmeq->sq_full,
420 &nvmeq->sq_cong_wait);
421 list_add_tail(&iod->node, &nvmeq->iod_bio);
422 wake_up(&nvmeq->sq_full);
423 return;
424 }
425 }
9e59d091 426 if (iod->nents) {
edd10d33 427 dma_unmap_sg(nvmeq->q_dmadev, iod->sg, iod->nents,
b60503ba 428 bio_data_dir(bio) ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
9e59d091
KB		 429 nvme_end_io_acct(bio, iod->start_time);
430 }
edd10d33 431 nvme_free_iod(nvmeq->dev, iod);
427e9708 432 if (status)
1ad2f893 433 bio_endio(bio, -EIO);
427e9708 434 else
1ad2f893 435 bio_endio(bio, 0);
b60503ba
MW		 436}
437
184d2944 438/* length is in bytes. gfp flags indicates whether we may sleep. */
edd10d33
KB		 439int nvme_setup_prps(struct nvme_dev *dev, struct nvme_iod *iod, int total_len,
440 gfp_t gfp)
ff22b54f 441{
99802a7a 442 struct dma_pool *pool;
eca18b23
MW		 443 int length = total_len;
444 struct scatterlist *sg = iod->sg;
ff22b54f
MW		 445 int dma_len = sg_dma_len(sg);
446 u64 dma_addr = sg_dma_address(sg);
447 int offset = offset_in_page(dma_addr);
e025344c 448 __le64 *prp_list;
eca18b23 449 __le64 **list = iod_list(iod);
e025344c 450 dma_addr_t prp_dma;
eca18b23 451 int nprps, i;
ff22b54f 452
ff22b54f
MW		 453 length -= (PAGE_SIZE - offset);
454 if (length <= 0)
eca18b23 455 return total_len;
ff22b54f
MW		 456
457 dma_len -= (PAGE_SIZE - offset);
458 if (dma_len) {
459 dma_addr += (PAGE_SIZE - offset);
460 } else {
461 sg = sg_next(sg);
462 dma_addr = sg_dma_address(sg);
463 dma_len = sg_dma_len(sg);
464 }
465
466 if (length <= PAGE_SIZE) {
edd10d33 467 iod->first_dma = dma_addr;
eca18b23 468 return total_len;
e025344c
SMM		 469 }
470
471 nprps = DIV_ROUND_UP(length, PAGE_SIZE);
99802a7a
MW		 472 if (nprps <= (256 / 8)) {
473 pool = dev->prp_small_pool;
eca18b23 474 iod->npages = 0;
99802a7a
MW		 475 } else {
476 pool = dev->prp_page_pool;
eca18b23 477 iod->npages = 1;
99802a7a
MW		 478 }
479
b77954cb
MW		 480 prp_list = dma_pool_alloc(pool, gfp, &prp_dma);
481 if (!prp_list) {
edd10d33 482 iod->first_dma = dma_addr;
eca18b23
MW		 483 iod->npages = -1;
484 return (total_len - length) + PAGE_SIZE;
b77954cb 485 }
eca18b23
MW		 486 list[0] = prp_list;
487 iod->first_dma = prp_dma;
e025344c
SMM		 488 i = 0;
489 for (;;) {
7523d834 490 if (i == PAGE_SIZE / 8) {
e025344c 491 __le64 *old_prp_list = prp_list;
b77954cb 492 prp_list = dma_pool_alloc(pool, gfp, &prp_dma);
eca18b23
MW		 493 if (!prp_list)
494 return total_len - length;
495 list[iod->npages++] = prp_list;
7523d834
MW		 496 prp_list[0] = old_prp_list[i - 1];
497 old_prp_list[i - 1] = cpu_to_le64(prp_dma);
498 i = 1;
e025344c
SMM		 499 }
500 prp_list[i++] = cpu_to_le64(dma_addr);
501 dma_len -= PAGE_SIZE;
502 dma_addr += PAGE_SIZE;
503 length -= PAGE_SIZE;
504 if (length <= 0)
505 break;
506 if (dma_len > 0)
507 continue;
508 BUG_ON(dma_len < 0);
509 sg = sg_next(sg);
510 dma_addr = sg_dma_address(sg);
511 dma_len = sg_dma_len(sg);
ff22b54f
MW		 512 }
513
eca18b23 514 return total_len;
ff22b54f
MW		 515}
516
427e9708 517static int nvme_split_and_submit(struct bio *bio, struct nvme_queue *nvmeq,
20d0189b 518 int len)
427e9708 519{
20d0189b
KO		 520 struct bio *split = bio_split(bio, len >> 9, GFP_ATOMIC, NULL);
521 if (!split)
427e9708
KB		 522 return -ENOMEM;
523
20d0189b
KO		 524 bio_chain(split, bio);
525
edd10d33 526 if (!waitqueue_active(&nvmeq->sq_full))
427e9708 527 add_wait_queue(&nvmeq->sq_full, &nvmeq->sq_cong_wait);
20d0189b
KO		 528 bio_list_add(&nvmeq->sq_cong, split);
529 bio_list_add(&nvmeq->sq_cong, bio);
edd10d33 530 wake_up(&nvmeq->sq_full);
427e9708
KB		 531
532 return 0;
533}
534
1ad2f893
MW		 535/* NVMe scatterlists require no holes in the virtual address */
536#define BIOVEC_NOT_VIRT_MERGEABLE(vec1, vec2) ((vec2)->bv_offset || \
537 (((vec1)->bv_offset + (vec1)->bv_len) % PAGE_SIZE))
538
427e9708 539static int nvme_map_bio(struct nvme_queue *nvmeq, struct nvme_iod *iod,
b60503ba
MW		 540 struct bio *bio, enum dma_data_direction dma_dir, int psegs)
541{
7988613b
KO		 542 struct bio_vec bvec, bvprv;
543 struct bvec_iter iter;
76830840 544 struct scatterlist *sg = NULL;
7988613b
KO		 545 int length = 0, nsegs = 0, split_len = bio->bi_iter.bi_size;
546 int first = 1;
159b67d7
KB		 547
548 if (nvmeq->dev->stripe_size)
549 split_len = nvmeq->dev->stripe_size -
4f024f37
KO		 550 ((bio->bi_iter.bi_sector << 9) &
551 (nvmeq->dev->stripe_size - 1));
b60503ba 552
eca18b23 553 sg_init_table(iod->sg, psegs);
7988613b
KO		 554 bio_for_each_segment(bvec, bio, iter) {
555 if (!first && BIOVEC_PHYS_MERGEABLE(&bvprv, &bvec)) {
556 sg->length += bvec.bv_len;
76830840 557 } else {
7988613b
KO		 558 if (!first && BIOVEC_NOT_VIRT_MERGEABLE(&bvprv, &bvec))
559 return nvme_split_and_submit(bio, nvmeq,
20d0189b 560 length);
427e9708 561
eca18b23 562 sg = sg ? sg + 1 : iod->sg;
7988613b
KO		 563 sg_set_page(sg, bvec.bv_page,
564 bvec.bv_len, bvec.bv_offset);
76830840
MW		 565 nsegs++;
566 }
159b67d7 567
7988613b 568 if (split_len - length < bvec.bv_len)
20d0189b 569 return nvme_split_and_submit(bio, nvmeq, split_len);
7988613b 570 length += bvec.bv_len;
76830840 571 bvprv = bvec;
7988613b 572 first = 0;
b60503ba 573 }
eca18b23 574 iod->nents = nsegs;
76830840 575 sg_mark_end(sg);
427e9708 576 if (dma_map_sg(nvmeq->q_dmadev, iod->sg, iod->nents, dma_dir) == 0)
1ad2f893 577 return -ENOMEM;
427e9708 578
4f024f37 579 BUG_ON(length != bio->bi_iter.bi_size);
1ad2f893 580 return length;
b60503ba
MW		 581}
582
0e5e4f0e
KB		 583static int nvme_submit_discard(struct nvme_queue *nvmeq, struct nvme_ns *ns,
584 struct bio *bio, struct nvme_iod *iod, int cmdid)
585{
edd10d33
KB		 586 struct nvme_dsm_range *range =
587 (struct nvme_dsm_range *)iod_list(iod)[0];
0e5e4f0e
KB		 588 struct nvme_command *cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail];
589
0e5e4f0e 590 range->cattr = cpu_to_le32(0);
4f024f37
KO		 591 range->nlb = cpu_to_le32(bio->bi_iter.bi_size >> ns->lba_shift);
592 range->slba = cpu_to_le64(nvme_block_nr(ns, bio->bi_iter.bi_sector));
0e5e4f0e
KB		 593
594 memset(cmnd, 0, sizeof(*cmnd));
595 cmnd->dsm.opcode = nvme_cmd_dsm;
596 cmnd->dsm.command_id = cmdid;
597 cmnd->dsm.nsid = cpu_to_le32(ns->ns_id);
598 cmnd->dsm.prp1 = cpu_to_le64(iod->first_dma);
599 cmnd->dsm.nr = 0;
600 cmnd->dsm.attributes = cpu_to_le32(NVME_DSMGMT_AD);
601
602 if (++nvmeq->sq_tail == nvmeq->q_depth)
603 nvmeq->sq_tail = 0;
604 writel(nvmeq->sq_tail, nvmeq->q_db);
605
606 return 0;
607}
608
00df5cb4
MW		 609static int nvme_submit_flush(struct nvme_queue *nvmeq, struct nvme_ns *ns,
610 int cmdid)
611{
612 struct nvme_command *cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail];
613
614 memset(cmnd, 0, sizeof(*cmnd));
615 cmnd->common.opcode = nvme_cmd_flush;
616 cmnd->common.command_id = cmdid;
617 cmnd->common.nsid = cpu_to_le32(ns->ns_id);
618
619 if (++nvmeq->sq_tail == nvmeq->q_depth)
620 nvmeq->sq_tail = 0;
621 writel(nvmeq->sq_tail, nvmeq->q_db);
622
623 return 0;
624}
625
5d0f6131 626int nvme_submit_flush_data(struct nvme_queue *nvmeq, struct nvme_ns *ns)
00df5cb4
MW		 627{
628 int cmdid = alloc_cmdid(nvmeq, (void *)CMD_CTX_FLUSH,
ff976d72 629 special_completion, NVME_IO_TIMEOUT);
00df5cb4
MW		 630 if (unlikely(cmdid < 0))
631 return cmdid;
632
633 return nvme_submit_flush(nvmeq, ns, cmdid);
634}
635
edd10d33 636static int nvme_submit_iod(struct nvme_queue *nvmeq, struct nvme_iod *iod)
b60503ba 637{
edd10d33
KB		 638 struct bio *bio = iod->private;
639 struct nvme_ns *ns = bio->bi_bdev->bd_disk->private_data;
ff22b54f 640 struct nvme_command *cmnd;
edd10d33 641 int cmdid;
b60503ba
MW		 642 u16 control;
643 u32 dsmgmt;
00df5cb4 644
ff976d72 645 cmdid = alloc_cmdid(nvmeq, iod, bio_completion, NVME_IO_TIMEOUT);
b60503ba 646 if (unlikely(cmdid < 0))
edd10d33 647 return cmdid;
b60503ba 648
edd10d33
KB		 649 if (bio->bi_rw & REQ_DISCARD)
650 return nvme_submit_discard(nvmeq, ns, bio, iod, cmdid);
651 if ((bio->bi_rw & REQ_FLUSH) && !iod->nents)
00df5cb4
MW		 652 return nvme_submit_flush(nvmeq, ns, cmdid);
653
b60503ba
MW		 654 control = 0;
655 if (bio->bi_rw & REQ_FUA)
656 control |= NVME_RW_FUA;
657 if (bio->bi_rw & (REQ_FAILFAST_DEV | REQ_RAHEAD))
658 control |= NVME_RW_LR;
659
660 dsmgmt = 0;
661 if (bio->bi_rw & REQ_RAHEAD)
662 dsmgmt |= NVME_RW_DSM_FREQ_PREFETCH;
663
ff22b54f 664 cmnd = &nvmeq->sq_cmds[nvmeq->sq_tail];
b8deb62c 665 memset(cmnd, 0, sizeof(*cmnd));
b60503ba 666
edd10d33 667 cmnd->rw.opcode = bio_data_dir(bio) ? nvme_cmd_write : nvme_cmd_read;
ff22b54f
MW		 668 cmnd->rw.command_id = cmdid;
669 cmnd->rw.nsid = cpu_to_le32(ns->ns_id);
edd10d33
KB		 670 cmnd->rw.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
671 cmnd->rw.prp2 = cpu_to_le64(iod->first_dma);
4f024f37 672 cmnd->rw.slba = cpu_to_le64(nvme_block_nr(ns, bio->bi_iter.bi_sector));
edd10d33
KB		 673 cmnd->rw.length =
674 cpu_to_le16((bio->bi_iter.bi_size >> ns->lba_shift) - 1);
ff22b54f
MW		 675 cmnd->rw.control = cpu_to_le16(control);
676 cmnd->rw.dsmgmt = cpu_to_le32(dsmgmt);
b60503ba 677
b60503ba
MW		 678 if (++nvmeq->sq_tail == nvmeq->q_depth)
679 nvmeq->sq_tail = 0;
7547881d 680 writel(nvmeq->sq_tail, nvmeq->q_db);
b60503ba 681
1974b1ae 682 return 0;
edd10d33
KB		 683}
684
685/*
686 * Called with local interrupts disabled and the q_lock held. May not sleep.
687 */
688static int nvme_submit_bio_queue(struct nvme_queue *nvmeq, struct nvme_ns *ns,
689 struct bio *bio)
690{
691 struct nvme_iod *iod;
692 int psegs = bio_phys_segments(ns->queue, bio);
693 int result;
694
695 if ((bio->bi_rw & REQ_FLUSH) && psegs) {
696 result = nvme_submit_flush_data(nvmeq, ns);
697 if (result)
698 return result;
699 }
700
701 iod = nvme_alloc_iod(psegs, bio->bi_iter.bi_size, GFP_ATOMIC);
702 if (!iod)
703 return -ENOMEM;
704
705 iod->private = bio;
706 if (bio->bi_rw & REQ_DISCARD) {
707 void *range;
708 /*
709 * We reuse the small pool to allocate the 16-byte range here
710 * as it is not worth having a special pool for these or
711 * additional cases to handle freeing the iod.
712 */
713 range = dma_pool_alloc(nvmeq->dev->prp_small_pool,
714 GFP_ATOMIC,
715 &iod->first_dma);
716 if (!range) {
717 result = -ENOMEM;
718 goto free_iod;
719 }
720 iod_list(iod)[0] = (__le64 *)range;
721 iod->npages = 0;
722 } else if (psegs) {
723 result = nvme_map_bio(nvmeq, iod, bio,
724 bio_data_dir(bio) ? DMA_TO_DEVICE : DMA_FROM_DEVICE,
725 psegs);
726 if (result <= 0)
727 goto free_iod;
728 if (nvme_setup_prps(nvmeq->dev, iod, result, GFP_ATOMIC) !=
729 result) {
730 result = -ENOMEM;
731 goto free_iod;
732 }
733 nvme_start_io_acct(bio);
734 }
735 if (unlikely(nvme_submit_iod(nvmeq, iod))) {
736 if (!waitqueue_active(&nvmeq->sq_full))
737 add_wait_queue(&nvmeq->sq_full, &nvmeq->sq_cong_wait);
738 list_add_tail(&iod->node, &nvmeq->iod_bio);
739 }
740 return 0;
1974b1ae 741
eca18b23
MW		 742 free_iod:
743 nvme_free_iod(nvmeq->dev, iod);
eeee3226 744 return result;
b60503ba
MW		 745}
746
e9539f47 747static int nvme_process_cq(struct nvme_queue *nvmeq)
b60503ba 748{
82123460 749 u16 head, phase;
b60503ba 750
b60503ba 751 head = nvmeq->cq_head;
82123460 752 phase = nvmeq->cq_phase;
b60503ba
MW		 753
754 for (;;) {
c2f5b650
MW		 755 void *ctx;
756 nvme_completion_fn fn;
b60503ba 757 struct nvme_completion cqe = nvmeq->cqes[head];
82123460 758 if ((le16_to_cpu(cqe.status) & 1) != phase)
b60503ba
MW		 759 break;
760 nvmeq->sq_head = le16_to_cpu(cqe.sq_head);
761 if (++head == nvmeq->q_depth) {
762 head = 0;
82123460 763 phase = !phase;
b60503ba
MW		 764 }
765
c2f5b650 766 ctx = free_cmdid(nvmeq, cqe.command_id, &fn);
edd10d33 767 fn(nvmeq, ctx, &cqe);
b60503ba
MW		 768 }
769
770 /* If the controller ignores the cq head doorbell and continuously
771 * writes to the queue, it is theoretically possible to wrap around
772 * the queue twice and mistakenly return IRQ_NONE. Linux only
773 * requires that 0.1% of your interrupts are handled, so this isn't
774 * a big problem.
775 */
82123460 776 if (head == nvmeq->cq_head && phase == nvmeq->cq_phase)
e9539f47 777 return 0;
b60503ba 778
b80d5ccc 779 writel(head, nvmeq->q_db + nvmeq->dev->db_stride);
b60503ba 780 nvmeq->cq_head = head;
82123460 781 nvmeq->cq_phase = phase;
b60503ba 782
e9539f47
MW		 783 nvmeq->cqe_seen = 1;
784 return 1;
b60503ba
MW		 785}
786
7d822457
MW		 787static void nvme_make_request(struct request_queue *q, struct bio *bio)
788{
789 struct nvme_ns *ns = q->queuedata;
790 struct nvme_queue *nvmeq = get_nvmeq(ns->dev);
791 int result = -EBUSY;
792
cd638946
KB		 793 if (!nvmeq) {
794 put_nvmeq(NULL);
795 bio_endio(bio, -EIO);
796 return;
797 }
798
7d822457 799 spin_lock_irq(&nvmeq->q_lock);
22404274 800 if (!nvmeq->q_suspended && bio_list_empty(&nvmeq->sq_cong))
7d822457
MW		 801 result = nvme_submit_bio_queue(nvmeq, ns, bio);
802 if (unlikely(result)) {
edd10d33 803 if (!waitqueue_active(&nvmeq->sq_full))
7d822457
MW		 804 add_wait_queue(&nvmeq->sq_full, &nvmeq->sq_cong_wait);
805 bio_list_add(&nvmeq->sq_cong, bio);
806 }
807
808 nvme_process_cq(nvmeq);
809 spin_unlock_irq(&nvmeq->q_lock);
810 put_nvmeq(nvmeq);
811}
812
b60503ba 813static irqreturn_t nvme_irq(int irq, void *data)
58ffacb5
MW		 814{
815 irqreturn_t result;
816 struct nvme_queue *nvmeq = data;
817 spin_lock(&nvmeq->q_lock);
e9539f47
MW		 818 nvme_process_cq(nvmeq);
819 result = nvmeq->cqe_seen ? IRQ_HANDLED : IRQ_NONE;
820 nvmeq->cqe_seen = 0;
58ffacb5
MW		 821 spin_unlock(&nvmeq->q_lock);
822 return result;
823}
824
825static irqreturn_t nvme_irq_check(int irq, void *data)
826{
827 struct nvme_queue *nvmeq = data;
828 struct nvme_completion cqe = nvmeq->cqes[nvmeq->cq_head];
829 if ((le16_to_cpu(cqe.status) & 1) != nvmeq->cq_phase)
830 return IRQ_NONE;
831 return IRQ_WAKE_THREAD;
832}
833
3c0cf138
MW		 834static void nvme_abort_command(struct nvme_queue *nvmeq, int cmdid)
835{
836 spin_lock_irq(&nvmeq->q_lock);
c2f5b650 837 cancel_cmdid(nvmeq, cmdid, NULL);
3c0cf138
MW		 838 spin_unlock_irq(&nvmeq->q_lock);
839}
840
c2f5b650
MW		 841struct sync_cmd_info {
842 struct task_struct *task;
843 u32 result;
844 int status;
845};
846
edd10d33 847static void sync_completion(struct nvme_queue *nvmeq, void *ctx,
c2f5b650
MW		 848 struct nvme_completion *cqe)
849{
850 struct sync_cmd_info *cmdinfo = ctx;
851 cmdinfo->result = le32_to_cpup(&cqe->result);
852 cmdinfo->status = le16_to_cpup(&cqe->status) >> 1;
853 wake_up_process(cmdinfo->task);
854}
855
b60503ba
MW		 856/*
857 * Returns 0 on success. If the result is negative, it's a Linux error code;
858 * if the result is positive, it's an NVM Express status code
859 */
4f5099af
KB		 860static int nvme_submit_sync_cmd(struct nvme_dev *dev, int q_idx,
861 struct nvme_command *cmd,
5d0f6131 862 u32 *result, unsigned timeout)
b60503ba 863{
4f5099af 864 int cmdid, ret;
b60503ba 865 struct sync_cmd_info cmdinfo;
4f5099af
KB		 866 struct nvme_queue *nvmeq;
867
868 nvmeq = lock_nvmeq(dev, q_idx);
869 if (!nvmeq) {
870 unlock_nvmeq(nvmeq);
871 return -ENODEV;
872 }
b60503ba
MW		 873
874 cmdinfo.task = current;
875 cmdinfo.status = -EINTR;
876
4f5099af
KB		 877 cmdid = alloc_cmdid(nvmeq, &cmdinfo, sync_completion, timeout);
878 if (cmdid < 0) {
879 unlock_nvmeq(nvmeq);
b60503ba 880 return cmdid;
4f5099af 881 }
b60503ba
MW		 882 cmd->common.command_id = cmdid;
883
3c0cf138 884 set_current_state(TASK_KILLABLE);
4f5099af
KB		 885 ret = nvme_submit_cmd(nvmeq, cmd);
886 if (ret) {
887 free_cmdid(nvmeq, cmdid, NULL);
888 unlock_nvmeq(nvmeq);
889 set_current_state(TASK_RUNNING);
890 return ret;
891 }
892 unlock_nvmeq(nvmeq);
78f8d257 893 schedule_timeout(timeout);
b60503ba 894
3c0cf138 895 if (cmdinfo.status == -EINTR) {
4f5099af
KB		 896 nvmeq = lock_nvmeq(dev, q_idx);
897 if (nvmeq)
898 nvme_abort_command(nvmeq, cmdid);
899 unlock_nvmeq(nvmeq);
3c0cf138
MW		 900 return -EINTR;
901 }
902
b60503ba
MW		 903 if (result)
904 *result = cmdinfo.result;
905
906 return cmdinfo.status;
907}
908
4d115420
KB		 909static int nvme_submit_async_cmd(struct nvme_queue *nvmeq,
910 struct nvme_command *cmd,
911 struct async_cmd_info *cmdinfo, unsigned timeout)
912{
913 int cmdid;
914
915 cmdid = alloc_cmdid_killable(nvmeq, cmdinfo, async_completion, timeout);
916 if (cmdid < 0)
917 return cmdid;
918 cmdinfo->status = -EINTR;
919 cmd->common.command_id = cmdid;
4f5099af 920 return nvme_submit_cmd(nvmeq, cmd);
4d115420
KB		 921}
922
5d0f6131 923int nvme_submit_admin_cmd(struct nvme_dev *dev, struct nvme_command *cmd,
b60503ba
MW		 924 u32 *result)
925{
4f5099af
KB		 926 return nvme_submit_sync_cmd(dev, 0, cmd, result, ADMIN_TIMEOUT);
927}
928
929int nvme_submit_io_cmd(struct nvme_dev *dev, struct nvme_command *cmd,
930 u32 *result)
931{
932 return nvme_submit_sync_cmd(dev, smp_processor_id() + 1, cmd, result,
933 NVME_IO_TIMEOUT);
b60503ba
MW		 934}
935
4d115420
KB		 936static int nvme_submit_admin_cmd_async(struct nvme_dev *dev,
937 struct nvme_command *cmd, struct async_cmd_info *cmdinfo)
938{
5a92e700 939 return nvme_submit_async_cmd(raw_nvmeq(dev, 0), cmd, cmdinfo,
4d115420
KB		 940 ADMIN_TIMEOUT);
941}
942
b60503ba
MW		 943static int adapter_delete_queue(struct nvme_dev *dev, u8 opcode, u16 id)
944{
945 int status;
946 struct nvme_command c;
947
948 memset(&c, 0, sizeof(c));
949 c.delete_queue.opcode = opcode;
950 c.delete_queue.qid = cpu_to_le16(id);
951
952 status = nvme_submit_admin_cmd(dev, &c, NULL);
953 if (status)
954 return -EIO;
955 return 0;
956}
957
958static int adapter_alloc_cq(struct nvme_dev *dev, u16 qid,
959 struct nvme_queue *nvmeq)
960{
961 int status;
962 struct nvme_command c;
963 int flags = NVME_QUEUE_PHYS_CONTIG | NVME_CQ_IRQ_ENABLED;
964
965 memset(&c, 0, sizeof(c));
966 c.create_cq.opcode = nvme_admin_create_cq;
967 c.create_cq.prp1 = cpu_to_le64(nvmeq->cq_dma_addr);
968 c.create_cq.cqid = cpu_to_le16(qid);
969 c.create_cq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
970 c.create_cq.cq_flags = cpu_to_le16(flags);
971 c.create_cq.irq_vector = cpu_to_le16(nvmeq->cq_vector);
972
973 status = nvme_submit_admin_cmd(dev, &c, NULL);
974 if (status)
975 return -EIO;
976 return 0;
977}
978
979static int adapter_alloc_sq(struct nvme_dev *dev, u16 qid,
980 struct nvme_queue *nvmeq)
981{
982 int status;
983 struct nvme_command c;
984 int flags = NVME_QUEUE_PHYS_CONTIG | NVME_SQ_PRIO_MEDIUM;
985
986 memset(&c, 0, sizeof(c));
987 c.create_sq.opcode = nvme_admin_create_sq;
988 c.create_sq.prp1 = cpu_to_le64(nvmeq->sq_dma_addr);
989 c.create_sq.sqid = cpu_to_le16(qid);
990 c.create_sq.qsize = cpu_to_le16(nvmeq->q_depth - 1);
991 c.create_sq.sq_flags = cpu_to_le16(flags);
992 c.create_sq.cqid = cpu_to_le16(qid);
993
994 status = nvme_submit_admin_cmd(dev, &c, NULL);
995 if (status)
996 return -EIO;
997 return 0;
998}
999
1000static int adapter_delete_cq(struct nvme_dev *dev, u16 cqid)
1001{
1002 return adapter_delete_queue(dev, nvme_admin_delete_cq, cqid);
1003}
1004
1005static int adapter_delete_sq(struct nvme_dev *dev, u16 sqid)
1006{
1007 return adapter_delete_queue(dev, nvme_admin_delete_sq, sqid);
1008}
1009
5d0f6131 1010int nvme_identify(struct nvme_dev *dev, unsigned nsid, unsigned cns,
bc5fc7e4
MW		 1011 dma_addr_t dma_addr)
1012{
1013 struct nvme_command c;
1014
1015 memset(&c, 0, sizeof(c));
1016 c.identify.opcode = nvme_admin_identify;
1017 c.identify.nsid = cpu_to_le32(nsid);
1018 c.identify.prp1 = cpu_to_le64(dma_addr);
1019 c.identify.cns = cpu_to_le32(cns);
1020
1021 return nvme_submit_admin_cmd(dev, &c, NULL);
1022}
1023
5d0f6131 1024int nvme_get_features(struct nvme_dev *dev, unsigned fid, unsigned nsid,
08df1e05 1025 dma_addr_t dma_addr, u32 *result)
bc5fc7e4
MW		 1026{
1027 struct nvme_command c;
1028
1029 memset(&c, 0, sizeof(c));
1030 c.features.opcode = nvme_admin_get_features;
a42cecce 1031 c.features.nsid = cpu_to_le32(nsid);
bc5fc7e4
MW		 1032 c.features.prp1 = cpu_to_le64(dma_addr);
1033 c.features.fid = cpu_to_le32(fid);
bc5fc7e4 1034
08df1e05 1035 return nvme_submit_admin_cmd(dev, &c, result);
df348139
MW		 1036}
1037
5d0f6131
VV		 1038int nvme_set_features(struct nvme_dev *dev, unsigned fid, unsigned dword11,
1039 dma_addr_t dma_addr, u32 *result)
df348139
MW		 1040{
1041 struct nvme_command c;
1042
1043 memset(&c, 0, sizeof(c));
1044 c.features.opcode = nvme_admin_set_features;
1045 c.features.prp1 = cpu_to_le64(dma_addr);
1046 c.features.fid = cpu_to_le32(fid);
1047 c.features.dword11 = cpu_to_le32(dword11);
1048
bc5fc7e4
MW		 1049 return nvme_submit_admin_cmd(dev, &c, result);
1050}
1051
c30341dc
KB		 1052/**
1053 * nvme_abort_cmd - Attempt aborting a command
1054 * @cmdid: Command id of a timed out IO
1055 * @queue: The queue with timed out IO
1056 *
1057 * Schedule controller reset if the command was already aborted once before and
1058 * still hasn't been returned to the driver, or if this is the admin queue.
1059 */
1060static void nvme_abort_cmd(int cmdid, struct nvme_queue *nvmeq)
1061{
1062 int a_cmdid;
1063 struct nvme_command cmd;
1064 struct nvme_dev *dev = nvmeq->dev;
1065 struct nvme_cmd_info *info = nvme_cmd_info(nvmeq);
5a92e700 1066 struct nvme_queue *adminq;
c30341dc
KB		 1067
1068 if (!nvmeq->qid || info[cmdid].aborted) {
1069 if (work_busy(&dev->reset_work))
1070 return;
1071 list_del_init(&dev->node);
1072 dev_warn(&dev->pci_dev->dev,
1073 "I/O %d QID %d timeout, reset controller\n", cmdid,
1074 nvmeq->qid);
9ca97374 1075 dev->reset_workfn = nvme_reset_failed_dev;
c30341dc
KB		 1076 queue_work(nvme_workq, &dev->reset_work);
1077 return;
1078 }
1079
1080 if (!dev->abort_limit)
1081 return;
1082
5a92e700
KB		 1083 adminq = rcu_dereference(dev->queues[0]);
1084 a_cmdid = alloc_cmdid(adminq, CMD_CTX_ABORT, special_completion,
c30341dc
KB		 1085 ADMIN_TIMEOUT);
1086 if (a_cmdid < 0)
1087 return;
1088
1089 memset(&cmd, 0, sizeof(cmd));
1090 cmd.abort.opcode = nvme_admin_abort_cmd;
1091 cmd.abort.cid = cmdid;
1092 cmd.abort.sqid = cpu_to_le16(nvmeq->qid);
1093 cmd.abort.command_id = a_cmdid;
1094
1095 --dev->abort_limit;
1096 info[cmdid].aborted = 1;
1097 info[cmdid].timeout = jiffies + ADMIN_TIMEOUT;
1098
1099 dev_warn(nvmeq->q_dmadev, "Aborting I/O %d QID %d\n", cmdid,
1100 nvmeq->qid);
5a92e700 1101 nvme_submit_cmd(adminq, &cmd);
c30341dc
KB		 1102}
1103
a09115b2
MW		 1104/**
1105 * nvme_cancel_ios - Cancel outstanding I/Os
1106 * @queue: The queue to cancel I/Os on
1107 * @timeout: True to only cancel I/Os which have timed out
1108 */
1109static void nvme_cancel_ios(struct nvme_queue *nvmeq, bool timeout)
1110{
1111 int depth = nvmeq->q_depth - 1;
1112 struct nvme_cmd_info *info = nvme_cmd_info(nvmeq);
1113 unsigned long now = jiffies;
1114 int cmdid;
1115
1116 for_each_set_bit(cmdid, nvmeq->cmdid_data, depth) {
1117 void *ctx;
1118 nvme_completion_fn fn;
1119 static struct nvme_completion cqe = {
af2d9ca7 1120 .status = cpu_to_le16(NVME_SC_ABORT_REQ << 1),
a09115b2
MW		 1121 };
1122
1123 if (timeout && !time_after(now, info[cmdid].timeout))
1124 continue;
053ab702
KB		 1125 if (info[cmdid].ctx == CMD_CTX_CANCELLED)
1126 continue;
c30341dc
KB		 1127 if (timeout && nvmeq->dev->initialized) {
1128 nvme_abort_cmd(cmdid, nvmeq);
1129 continue;
1130 }
1131 dev_warn(nvmeq->q_dmadev, "Cancelling I/O %d QID %d\n", cmdid,
1132 nvmeq->qid);
a09115b2 1133 ctx = cancel_cmdid(nvmeq, cmdid, &fn);
edd10d33 1134 fn(nvmeq, ctx, &cqe);
a09115b2
MW		 1135 }
1136}
1137
5a92e700 1138static void nvme_free_queue(struct rcu_head *r)
9e866774 1139{
5a92e700
KB		 1140 struct nvme_queue *nvmeq = container_of(r, struct nvme_queue, r_head);
1141
22404274
KB		 1142 spin_lock_irq(&nvmeq->q_lock);
1143 while (bio_list_peek(&nvmeq->sq_cong)) {
1144 struct bio *bio = bio_list_pop(&nvmeq->sq_cong);
1145 bio_endio(bio, -EIO);
1146 }
edd10d33
KB		 1147 while (!list_empty(&nvmeq->iod_bio)) {
1148 static struct nvme_completion cqe = {
1149 .status = cpu_to_le16(
1150 (NVME_SC_ABORT_REQ | NVME_SC_DNR) << 1),
1151 };
1152 struct nvme_iod *iod = list_first_entry(&nvmeq->iod_bio,
1153 struct nvme_iod,
1154 node);
1155 list_del(&iod->node);
1156 bio_completion(nvmeq, iod, &cqe);
1157 }
22404274
KB		 1158 spin_unlock_irq(&nvmeq->q_lock);
1159
9e866774
MW		 1160 dma_free_coherent(nvmeq->q_dmadev, CQ_SIZE(nvmeq->q_depth),
1161 (void *)nvmeq->cqes, nvmeq->cq_dma_addr);
1162 dma_free_coherent(nvmeq->q_dmadev, SQ_SIZE(nvmeq->q_depth),
1163 nvmeq->sq_cmds, nvmeq->sq_dma_addr);
42f61420
KB		 1164 if (nvmeq->qid)
1165 free_cpumask_var(nvmeq->cpu_mask);
9e866774
MW		 1166 kfree(nvmeq);
1167}
1168
a1a5ef99 1169static void nvme_free_queues(struct nvme_dev *dev, int lowest)
22404274
KB		 1170{
1171 int i;
1172
a1a5ef99 1173 for (i = dev->queue_count - 1; i >= lowest; i--) {
5a92e700
KB		 1174 struct nvme_queue *nvmeq = raw_nvmeq(dev, i);
1175 rcu_assign_pointer(dev->queues[i], NULL);
1176 call_rcu(&nvmeq->r_head, nvme_free_queue);
22404274 1177 dev->queue_count--;
22404274
KB		 1178 }
1179}
1180
4d115420
KB		 1181/**
1182 * nvme_suspend_queue - put queue into suspended state
1183 * @nvmeq - queue to suspend
1184 *
1185 * Returns 1 if already suspended, 0 otherwise.
1186 */
1187static int nvme_suspend_queue(struct nvme_queue *nvmeq)
b60503ba 1188{
4d115420 1189 int vector = nvmeq->dev->entry[nvmeq->cq_vector].vector;
b60503ba 1190
a09115b2 1191 spin_lock_irq(&nvmeq->q_lock);
22404274
KB		 1192 if (nvmeq->q_suspended) {
1193 spin_unlock_irq(&nvmeq->q_lock);
4d115420 1194 return 1;
3295874b 1195 }
22404274 1196 nvmeq->q_suspended = 1;
42f61420 1197 nvmeq->dev->online_queues--;
a09115b2
MW		 1198 spin_unlock_irq(&nvmeq->q_lock);
1199
aba2080f
MW		 1200 irq_set_affinity_hint(vector, NULL);
1201 free_irq(vector, nvmeq);
b60503ba 1202
4d115420
KB		 1203 return 0;
1204}
b60503ba 1205
4d115420
KB		 1206static void nvme_clear_queue(struct nvme_queue *nvmeq)
1207{
22404274
KB		 1208 spin_lock_irq(&nvmeq->q_lock);
1209 nvme_process_cq(nvmeq);
1210 nvme_cancel_ios(nvmeq, false);
1211 spin_unlock_irq(&nvmeq->q_lock);
b60503ba
MW		 1212}
1213
4d115420
KB		 1214static void nvme_disable_queue(struct nvme_dev *dev, int qid)
1215{
5a92e700 1216 struct nvme_queue *nvmeq = raw_nvmeq(dev, qid);
4d115420
KB		 1217
1218 if (!nvmeq)
1219 return;
1220 if (nvme_suspend_queue(nvmeq))
1221 return;
1222
0e53d180
KB		 1223 /* Don't tell the adapter to delete the admin queue.
1224 * Don't tell a removed adapter to delete IO queues. */
1225 if (qid && readl(&dev->bar->csts) != -1) {
b60503ba
MW		 1226 adapter_delete_sq(dev, qid);
1227 adapter_delete_cq(dev, qid);
1228 }
4d115420 1229 nvme_clear_queue(nvmeq);
b60503ba
MW		 1230}
1231
1232static struct nvme_queue *nvme_alloc_queue(struct nvme_dev *dev, int qid,
1233 int depth, int vector)
1234{
1235 struct device *dmadev = &dev->pci_dev->dev;
22404274 1236 unsigned extra = nvme_queue_extra(depth);
b60503ba
MW		 1237 struct nvme_queue *nvmeq = kzalloc(sizeof(*nvmeq) + extra, GFP_KERNEL);
1238 if (!nvmeq)
1239 return NULL;
1240
1241 nvmeq->cqes = dma_alloc_coherent(dmadev, CQ_SIZE(depth),
1242 &nvmeq->cq_dma_addr, GFP_KERNEL);
1243 if (!nvmeq->cqes)
1244 goto free_nvmeq;
1245 memset((void *)nvmeq->cqes, 0, CQ_SIZE(depth));
1246
1247 nvmeq->sq_cmds = dma_alloc_coherent(dmadev, SQ_SIZE(depth),
1248 &nvmeq->sq_dma_addr, GFP_KERNEL);
1249 if (!nvmeq->sq_cmds)
1250 goto free_cqdma;
1251
42f61420
KB		 1252 if (qid && !zalloc_cpumask_var(&nvmeq->cpu_mask, GFP_KERNEL))
1253 goto free_sqdma;
1254
b60503ba 1255 nvmeq->q_dmadev = dmadev;
091b6092 1256 nvmeq->dev = dev;
3193f07b
MW		 1257 snprintf(nvmeq->irqname, sizeof(nvmeq->irqname), "nvme%dq%d",
1258 dev->instance, qid);
b60503ba
MW		 1259 spin_lock_init(&nvmeq->q_lock);
1260 nvmeq->cq_head = 0;
82123460 1261 nvmeq->cq_phase = 1;
b60503ba 1262 init_waitqueue_head(&nvmeq->sq_full);
1fa6aead 1263 init_waitqueue_entry(&nvmeq->sq_cong_wait, nvme_thread);
b60503ba 1264 bio_list_init(&nvmeq->sq_cong);
edd10d33 1265 INIT_LIST_HEAD(&nvmeq->iod_bio);
b80d5ccc 1266 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
b60503ba
MW		 1267 nvmeq->q_depth = depth;
1268 nvmeq->cq_vector = vector;
c30341dc 1269 nvmeq->qid = qid;
22404274
KB		 1270 nvmeq->q_suspended = 1;
1271 dev->queue_count++;
5a92e700 1272 rcu_assign_pointer(dev->queues[qid], nvmeq);
b60503ba
MW		 1273
1274 return nvmeq;
1275
42f61420
KB		 1276 free_sqdma:
1277 dma_free_coherent(dmadev, SQ_SIZE(depth), (void *)nvmeq->sq_cmds,
1278 nvmeq->sq_dma_addr);
b60503ba 1279 free_cqdma:
68b8eca5 1280 dma_free_coherent(dmadev, CQ_SIZE(depth), (void *)nvmeq->cqes,
b60503ba
MW		 1281 nvmeq->cq_dma_addr);
1282 free_nvmeq:
1283 kfree(nvmeq);
1284 return NULL;
1285}
1286
3001082c
MW		 1287static int queue_request_irq(struct nvme_dev *dev, struct nvme_queue *nvmeq,
1288 const char *name)
1289{
58ffacb5
MW		 1290 if (use_threaded_interrupts)
1291 return request_threaded_irq(dev->entry[nvmeq->cq_vector].vector,
481e5bad 1292 nvme_irq_check, nvme_irq, IRQF_SHARED,
58ffacb5 1293 name, nvmeq);
3001082c 1294 return request_irq(dev->entry[nvmeq->cq_vector].vector, nvme_irq,
481e5bad 1295 IRQF_SHARED, name, nvmeq);
3001082c
MW		 1296}
1297
22404274 1298static void nvme_init_queue(struct nvme_queue *nvmeq, u16 qid)
b60503ba 1299{
22404274
KB		 1300 struct nvme_dev *dev = nvmeq->dev;
1301 unsigned extra = nvme_queue_extra(nvmeq->q_depth);
b60503ba 1302
22404274
KB		 1303 nvmeq->sq_tail = 0;
1304 nvmeq->cq_head = 0;
1305 nvmeq->cq_phase = 1;
b80d5ccc 1306 nvmeq->q_db = &dev->dbs[qid * 2 * dev->db_stride];
22404274
KB		 1307 memset(nvmeq->cmdid_data, 0, extra);
1308 memset((void *)nvmeq->cqes, 0, CQ_SIZE(nvmeq->q_depth));
1309 nvme_cancel_ios(nvmeq, false);
1310 nvmeq->q_suspended = 0;
42f61420 1311 dev->online_queues++;
22404274
KB		 1312}
1313
1314static int nvme_create_queue(struct nvme_queue *nvmeq, int qid)
1315{
1316 struct nvme_dev *dev = nvmeq->dev;
1317 int result;
3f85d50b 1318
b60503ba
MW		 1319 result = adapter_alloc_cq(dev, qid, nvmeq);
1320 if (result < 0)
22404274 1321 return result;
b60503ba
MW		 1322
1323 result = adapter_alloc_sq(dev, qid, nvmeq);
1324 if (result < 0)
1325 goto release_cq;
1326
3193f07b 1327 result = queue_request_irq(dev, nvmeq, nvmeq->irqname);
b60503ba
MW		 1328 if (result < 0)
1329 goto release_sq;
1330
0a8d44cb 1331 spin_lock_irq(&nvmeq->q_lock);
22404274 1332 nvme_init_queue(nvmeq, qid);
0a8d44cb 1333 spin_unlock_irq(&nvmeq->q_lock);
22404274
KB		 1334
1335 return result;
b60503ba
MW		 1336
1337 release_sq:
1338 adapter_delete_sq(dev, qid);
1339 release_cq:
1340 adapter_delete_cq(dev, qid);
22404274 1341 return result;
b60503ba
MW		 1342}
1343
ba47e386
MW		 1344static int nvme_wait_ready(struct nvme_dev *dev, u64 cap, bool enabled)
1345{
1346 unsigned long timeout;
1347 u32 bit = enabled ? NVME_CSTS_RDY : 0;
1348
1349 timeout = ((NVME_CAP_TIMEOUT(cap) + 1) * HZ / 2) + jiffies;
1350
1351 while ((readl(&dev->bar->csts) & NVME_CSTS_RDY) != bit) {
1352 msleep(100);
1353 if (fatal_signal_pending(current))
1354 return -EINTR;
1355 if (time_after(jiffies, timeout)) {
1356 dev_err(&dev->pci_dev->dev,
27e8166c
MW		 1357 "Device not ready; aborting %s\n", enabled ?
1358 "initialisation" : "reset");
ba47e386
MW		 1359 return -ENODEV;
1360 }
1361 }
1362
1363 return 0;
1364}
1365
1366/*
1367 * If the device has been passed off to us in an enabled state, just clear
1368 * the enabled bit. The spec says we should set the 'shutdown notification
1369 * bits', but doing so may cause the device to complete commands to the
1370 * admin queue ... and we don't know what memory that might be pointing at!
1371 */
1372static int nvme_disable_ctrl(struct nvme_dev *dev, u64 cap)
1373{
44af146a
MW		 1374 u32 cc = readl(&dev->bar->cc);
1375
1376 if (cc & NVME_CC_ENABLE)
1377 writel(cc & ~NVME_CC_ENABLE, &dev->bar->cc);
ba47e386
MW		 1378 return nvme_wait_ready(dev, cap, false);
1379}
1380
1381static int nvme_enable_ctrl(struct nvme_dev *dev, u64 cap)
1382{
1383 return nvme_wait_ready(dev, cap, true);
1384}
1385
1894d8f1
KB		 1386static int nvme_shutdown_ctrl(struct nvme_dev *dev)
1387{
1388 unsigned long timeout;
1389 u32 cc;
1390
1391 cc = (readl(&dev->bar->cc) & ~NVME_CC_SHN_MASK) | NVME_CC_SHN_NORMAL;
1392 writel(cc, &dev->bar->cc);
1393
1394 timeout = 2 * HZ + jiffies;
1395 while ((readl(&dev->bar->csts) & NVME_CSTS_SHST_MASK) !=
1396 NVME_CSTS_SHST_CMPLT) {
1397 msleep(100);
1398 if (fatal_signal_pending(current))
1399 return -EINTR;
1400 if (time_after(jiffies, timeout)) {
1401 dev_err(&dev->pci_dev->dev,
1402 "Device shutdown incomplete; abort shutdown\n");
1403 return -ENODEV;
1404 }
1405 }
1406
1407 return 0;
1408}
1409
8d85fce7 1410static int nvme_configure_admin_queue(struct nvme_dev *dev)
b60503ba 1411{
ba47e386 1412 int result;
b60503ba 1413 u32 aqa;
ba47e386 1414 u64 cap = readq(&dev->bar->cap);
b60503ba
MW		 1415 struct nvme_queue *nvmeq;
1416
ba47e386
MW		 1417 result = nvme_disable_ctrl(dev, cap);
1418 if (result < 0)
1419 return result;
b60503ba 1420
5a92e700 1421 nvmeq = raw_nvmeq(dev, 0);
cd638946
KB		 1422 if (!nvmeq) {
1423 nvmeq = nvme_alloc_queue(dev, 0, 64, 0);
1424 if (!nvmeq)
1425 return -ENOMEM;
cd638946 1426 }
b60503ba
MW		 1427
1428 aqa = nvmeq->q_depth - 1;
1429 aqa |= aqa << 16;
1430
1431 dev->ctrl_config = NVME_CC_ENABLE | NVME_CC_CSS_NVM;
1432 dev->ctrl_config |= (PAGE_SHIFT - 12) << NVME_CC_MPS_SHIFT;
1433 dev->ctrl_config |= NVME_CC_ARB_RR | NVME_CC_SHN_NONE;
7f53f9d2 1434 dev->ctrl_config |= NVME_CC_IOSQES | NVME_CC_IOCQES;
b60503ba
MW		 1435
1436 writel(aqa, &dev->bar->aqa);
1437 writeq(nvmeq->sq_dma_addr, &dev->bar->asq);
1438 writeq(nvmeq->cq_dma_addr, &dev->bar->acq);
1439 writel(dev->ctrl_config, &dev->bar->cc);
1440
ba47e386 1441 result = nvme_enable_ctrl(dev, cap);
025c557a 1442 if (result)
cd638946 1443 return result;
9e866774 1444
3193f07b 1445 result = queue_request_irq(dev, nvmeq, nvmeq->irqname);
025c557a 1446 if (result)
cd638946 1447 return result;
025c557a 1448
0a8d44cb 1449 spin_lock_irq(&nvmeq->q_lock);
22404274 1450 nvme_init_queue(nvmeq, 0);
0a8d44cb 1451 spin_unlock_irq(&nvmeq->q_lock);
b60503ba
MW		 1452 return result;
1453}
1454
5d0f6131 1455struct nvme_iod *nvme_map_user_pages(struct nvme_dev *dev, int write,
eca18b23 1456 unsigned long addr, unsigned length)
b60503ba 1457{
36c14ed9 1458 int i, err, count, nents, offset;
7fc3cdab
MW		 1459 struct scatterlist *sg;
1460 struct page **pages;
eca18b23 1461 struct nvme_iod *iod;
36c14ed9
MW		 1462
1463 if (addr & 3)
eca18b23 1464 return ERR_PTR(-EINVAL);
5460fc03 1465 if (!length || length > INT_MAX - PAGE_SIZE)
eca18b23 1466 return ERR_PTR(-EINVAL);
7fc3cdab 1467
36c14ed9 1468 offset = offset_in_page(addr);
7fc3cdab
MW		 1469 count = DIV_ROUND_UP(offset + length, PAGE_SIZE);
1470 pages = kcalloc(count, sizeof(*pages), GFP_KERNEL);
22fff826
DC		 1471 if (!pages)
1472 return ERR_PTR(-ENOMEM);
36c14ed9
MW		 1473
1474 err = get_user_pages_fast(addr, count, 1, pages);
1475 if (err < count) {
1476 count = err;
1477 err = -EFAULT;
1478 goto put_pages;
1479 }
7fc3cdab 1480
eca18b23
MW		 1481 iod = nvme_alloc_iod(count, length, GFP_KERNEL);
1482 sg = iod->sg;
36c14ed9 1483 sg_init_table(sg, count);
d0ba1e49
MW		 1484 for (i = 0; i < count; i++) {
1485 sg_set_page(&sg[i], pages[i],
5460fc03
DC		 1486 min_t(unsigned, length, PAGE_SIZE - offset),
1487 offset);
d0ba1e49
MW		 1488 length -= (PAGE_SIZE - offset);
1489 offset = 0;
7fc3cdab 1490 }
fe304c43 1491 sg_mark_end(&sg[i - 1]);
1c2ad9fa 1492 iod->nents = count;
7fc3cdab
MW		 1493
1494 err = -ENOMEM;
1495 nents = dma_map_sg(&dev->pci_dev->dev, sg, count,
1496 write ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
36c14ed9 1497 if (!nents)
eca18b23 1498 goto free_iod;
b60503ba 1499
7fc3cdab 1500 kfree(pages);
eca18b23 1501 return iod;
b60503ba 1502
eca18b23
MW		 1503 free_iod:
1504 kfree(iod);
7fc3cdab
MW		 1505 put_pages:
1506 for (i = 0; i < count; i++)
1507 put_page(pages[i]);
1508 kfree(pages);
eca18b23 1509 return ERR_PTR(err);
7fc3cdab 1510}
b60503ba 1511
5d0f6131 1512void nvme_unmap_user_pages(struct nvme_dev *dev, int write,
1c2ad9fa 1513 struct nvme_iod *iod)
7fc3cdab 1514{
1c2ad9fa 1515 int i;
b60503ba 1516
1c2ad9fa
MW		 1517 dma_unmap_sg(&dev->pci_dev->dev, iod->sg, iod->nents,
1518 write ? DMA_TO_DEVICE : DMA_FROM_DEVICE);
7fc3cdab 1519
1c2ad9fa
MW		 1520 for (i = 0; i < iod->nents; i++)
1521 put_page(sg_page(&iod->sg[i]));
7fc3cdab 1522}
b60503ba 1523
a53295b6
MW		 1524static int nvme_submit_io(struct nvme_ns *ns, struct nvme_user_io __user *uio)
1525{
1526 struct nvme_dev *dev = ns->dev;
a53295b6
MW		 1527 struct nvme_user_io io;
1528 struct nvme_command c;
f410c680
KB		 1529 unsigned length, meta_len;
1530 int status, i;
1531 struct nvme_iod *iod, *meta_iod = NULL;
1532 dma_addr_t meta_dma_addr;
1533 void *meta, *uninitialized_var(meta_mem);
a53295b6
MW		 1534
1535 if (copy_from_user(&io, uio, sizeof(io)))
1536 return -EFAULT;
6c7d4945 1537 length = (io.nblocks + 1) << ns->lba_shift;
f410c680
KB		 1538 meta_len = (io.nblocks + 1) * ns->ms;
1539
1540 if (meta_len && ((io.metadata & 3) || !io.metadata))
1541 return -EINVAL;
6c7d4945
MW		 1542
1543 switch (io.opcode) {
1544 case nvme_cmd_write:
1545 case nvme_cmd_read:
6bbf1acd 1546 case nvme_cmd_compare:
eca18b23 1547 iod = nvme_map_user_pages(dev, io.opcode & 1, io.addr, length);
6413214c 1548 break;
6c7d4945 1549 default:
6bbf1acd 1550 return -EINVAL;
6c7d4945
MW		 1551 }
1552
eca18b23
MW		 1553 if (IS_ERR(iod))
1554 return PTR_ERR(iod);
a53295b6
MW		 1555
1556 memset(&c, 0, sizeof(c));
1557 c.rw.opcode = io.opcode;
1558 c.rw.flags = io.flags;
6c7d4945 1559 c.rw.nsid = cpu_to_le32(ns->ns_id);
a53295b6 1560 c.rw.slba = cpu_to_le64(io.slba);
6c7d4945 1561 c.rw.length = cpu_to_le16(io.nblocks);
a53295b6 1562 c.rw.control = cpu_to_le16(io.control);
1c9b5265
MW		 1563 c.rw.dsmgmt = cpu_to_le32(io.dsmgmt);
1564 c.rw.reftag = cpu_to_le32(io.reftag);
1565 c.rw.apptag = cpu_to_le16(io.apptag);
1566 c.rw.appmask = cpu_to_le16(io.appmask);
f410c680
KB		 1567
1568 if (meta_len) {
1b56749e
KB		 1569 meta_iod = nvme_map_user_pages(dev, io.opcode & 1, io.metadata,
1570 meta_len);
f410c680
KB		 1571 if (IS_ERR(meta_iod)) {
1572 status = PTR_ERR(meta_iod);
1573 meta_iod = NULL;
1574 goto unmap;
1575 }
1576
1577 meta_mem = dma_alloc_coherent(&dev->pci_dev->dev, meta_len,
1578 &meta_dma_addr, GFP_KERNEL);
1579 if (!meta_mem) {
1580 status = -ENOMEM;
1581 goto unmap;
1582 }
1583
1584 if (io.opcode & 1) {
1585 int meta_offset = 0;
1586
1587 for (i = 0; i < meta_iod->nents; i++) {
1588 meta = kmap_atomic(sg_page(&meta_iod->sg[i])) +
1589 meta_iod->sg[i].offset;
1590 memcpy(meta_mem + meta_offset, meta,
1591 meta_iod->sg[i].length);
1592 kunmap_atomic(meta);
1593 meta_offset += meta_iod->sg[i].length;
1594 }
1595 }
1596
1597 c.rw.metadata = cpu_to_le64(meta_dma_addr);
1598 }
1599
edd10d33
KB		 1600 length = nvme_setup_prps(dev, iod, length, GFP_KERNEL);
1601 c.rw.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
1602 c.rw.prp2 = cpu_to_le64(iod->first_dma);
a53295b6 1603
b77954cb
MW		 1604 if (length != (io.nblocks + 1) << ns->lba_shift)
1605 status = -ENOMEM;
1606 else
4f5099af 1607 status = nvme_submit_io_cmd(dev, &c, NULL);
a53295b6 1608
f410c680
KB		 1609 if (meta_len) {
1610 if (status == NVME_SC_SUCCESS && !(io.opcode & 1)) {
1611 int meta_offset = 0;
1612
1613 for (i = 0; i < meta_iod->nents; i++) {
1614 meta = kmap_atomic(sg_page(&meta_iod->sg[i])) +
1615 meta_iod->sg[i].offset;
1616 memcpy(meta, meta_mem + meta_offset,
1617 meta_iod->sg[i].length);
1618 kunmap_atomic(meta);
1619 meta_offset += meta_iod->sg[i].length;
1620 }
1621 }
1622
1623 dma_free_coherent(&dev->pci_dev->dev, meta_len, meta_mem,
1624 meta_dma_addr);
1625 }
1626
1627 unmap:
1c2ad9fa 1628 nvme_unmap_user_pages(dev, io.opcode & 1, iod);
eca18b23 1629 nvme_free_iod(dev, iod);
f410c680
KB		 1630
1631 if (meta_iod) {
1632 nvme_unmap_user_pages(dev, io.opcode & 1, meta_iod);
1633 nvme_free_iod(dev, meta_iod);
1634 }
1635
a53295b6
MW		 1636 return status;
1637}
1638
50af8bae 1639static int nvme_user_admin_cmd(struct nvme_dev *dev,
6bbf1acd 1640 struct nvme_admin_cmd __user *ucmd)
6ee44cdc 1641{
6bbf1acd 1642 struct nvme_admin_cmd cmd;
6ee44cdc 1643 struct nvme_command c;
eca18b23 1644 int status, length;
c7d36ab8 1645 struct nvme_iod *uninitialized_var(iod);
94f370ca 1646 unsigned timeout;
6ee44cdc 1647
6bbf1acd
MW		 1648 if (!capable(CAP_SYS_ADMIN))
1649 return -EACCES;
1650 if (copy_from_user(&cmd, ucmd, sizeof(cmd)))
6ee44cdc 1651 return -EFAULT;
6ee44cdc
MW		 1652
1653 memset(&c, 0, sizeof(c));
6bbf1acd
MW		 1654 c.common.opcode = cmd.opcode;
1655 c.common.flags = cmd.flags;
1656 c.common.nsid = cpu_to_le32(cmd.nsid);
1657 c.common.cdw2[0] = cpu_to_le32(cmd.cdw2);
1658 c.common.cdw2[1] = cpu_to_le32(cmd.cdw3);
1659 c.common.cdw10[0] = cpu_to_le32(cmd.cdw10);
1660 c.common.cdw10[1] = cpu_to_le32(cmd.cdw11);
1661 c.common.cdw10[2] = cpu_to_le32(cmd.cdw12);
1662 c.common.cdw10[3] = cpu_to_le32(cmd.cdw13);
1663 c.common.cdw10[4] = cpu_to_le32(cmd.cdw14);
1664 c.common.cdw10[5] = cpu_to_le32(cmd.cdw15);
1665
1666 length = cmd.data_len;
1667 if (cmd.data_len) {
49742188
MW		 1668 iod = nvme_map_user_pages(dev, cmd.opcode & 1, cmd.addr,
1669 length);
eca18b23
MW		 1670 if (IS_ERR(iod))
1671 return PTR_ERR(iod);
edd10d33
KB		 1672 length = nvme_setup_prps(dev, iod, length, GFP_KERNEL);
1673 c.common.prp1 = cpu_to_le64(sg_dma_address(iod->sg));
1674 c.common.prp2 = cpu_to_le64(iod->first_dma);
6bbf1acd
MW		 1675 }
1676
94f370ca
KB		 1677 timeout = cmd.timeout_ms ? msecs_to_jiffies(cmd.timeout_ms) :
1678 ADMIN_TIMEOUT;
6bbf1acd 1679 if (length != cmd.data_len)
b77954cb
MW		 1680 status = -ENOMEM;
1681 else
4f5099af 1682 status = nvme_submit_sync_cmd(dev, 0, &c, &cmd.result, timeout);
eca18b23 1683
6bbf1acd 1684 if (cmd.data_len) {
1c2ad9fa 1685 nvme_unmap_user_pages(dev, cmd.opcode & 1, iod);
eca18b23 1686 nvme_free_iod(dev, iod);
6bbf1acd 1687 }
f4f117f6 1688
cf90bc48 1689 if ((status >= 0) && copy_to_user(&ucmd->result, &cmd.result,
f4f117f6
KB		 1690 sizeof(cmd.result)))
1691 status = -EFAULT;
1692
6ee44cdc
MW		 1693 return status;
1694}
1695
b60503ba
MW		 1696static int nvme_ioctl(struct block_device *bdev, fmode_t mode, unsigned int cmd,
1697 unsigned long arg)
1698{
1699 struct nvme_ns *ns = bdev->bd_disk->private_data;
1700
1701 switch (cmd) {
6bbf1acd 1702 case NVME_IOCTL_ID:
c3bfe717 1703 force_successful_syscall_return();
6bbf1acd
MW		 1704 return ns->ns_id;
1705 case NVME_IOCTL_ADMIN_CMD:
50af8bae 1706 return nvme_user_admin_cmd(ns->dev, (void __user *)arg);
a53295b6
MW		 1707 case NVME_IOCTL_SUBMIT_IO:
1708 return nvme_submit_io(ns, (void __user *)arg);
5d0f6131
VV		 1709 case SG_GET_VERSION_NUM:
1710 return nvme_sg_get_version_num((void __user *)arg);
1711 case SG_IO:
1712 return nvme_sg_io(ns, (void __user *)arg);
b60503ba
MW		 1713 default:
1714 return -ENOTTY;
1715 }
1716}
1717
320a3827
KB		 1718#ifdef CONFIG_COMPAT
1719static int nvme_compat_ioctl(struct block_device *bdev, fmode_t mode,
1720 unsigned int cmd, unsigned long arg)
1721{
1722 struct nvme_ns *ns = bdev->bd_disk->private_data;
1723
1724 switch (cmd) {
1725 case SG_IO:
1726 return nvme_sg_io32(ns, arg);
1727 }
1728 return nvme_ioctl(bdev, mode, cmd, arg);
1729}
1730#else
1731#define nvme_compat_ioctl NULL
1732#endif
1733
9ac27090
KB		 1734static int nvme_open(struct block_device *bdev, fmode_t mode)
1735{
1736 struct nvme_ns *ns = bdev->bd_disk->private_data;
1737 struct nvme_dev *dev = ns->dev;
1738
1739 kref_get(&dev->kref);
1740 return 0;
1741}
1742
1743static void nvme_free_dev(struct kref *kref);
1744
1745static void nvme_release(struct gendisk *disk, fmode_t mode)
1746{
1747 struct nvme_ns *ns = disk->private_data;
1748 struct nvme_dev *dev = ns->dev;
1749
1750 kref_put(&dev->kref, nvme_free_dev);
1751}
1752
4cc09e2d
KB		 1753static int nvme_getgeo(struct block_device *bd, struct hd_geometry *geo)
1754{
1755 /* some standard values */
1756 geo->heads = 1 << 6;
1757 geo->sectors = 1 << 5;
1758 geo->cylinders = get_capacity(bd->bd_disk) >> 11;
1759 return 0;
1760}
1761
b60503ba
MW		 1762static const struct block_device_operations nvme_fops = {
1763 .owner = THIS_MODULE,
1764 .ioctl = nvme_ioctl,
320a3827 1765 .compat_ioctl = nvme_compat_ioctl,
9ac27090
KB		 1766 .open = nvme_open,
1767 .release = nvme_release,
4cc09e2d 1768 .getgeo = nvme_getgeo,
b60503ba
MW		 1769};
1770
edd10d33
KB		 1771static void nvme_resubmit_iods(struct nvme_queue *nvmeq)
1772{
1773 struct nvme_iod *iod, *next;
1774
1775 list_for_each_entry_safe(iod, next, &nvmeq->iod_bio, node) {
1776 if (unlikely(nvme_submit_iod(nvmeq, iod)))
1777 break;
1778 list_del(&iod->node);
1779 if (bio_list_empty(&nvmeq->sq_cong) &&
1780 list_empty(&nvmeq->iod_bio))
1781 remove_wait_queue(&nvmeq->sq_full,
1782 &nvmeq->sq_cong_wait);
1783 }
1784}
1785
1fa6aead
MW		 1786static void nvme_resubmit_bios(struct nvme_queue *nvmeq)
1787{
1788 while (bio_list_peek(&nvmeq->sq_cong)) {
1789 struct bio *bio = bio_list_pop(&nvmeq->sq_cong);
1790 struct nvme_ns *ns = bio->bi_bdev->bd_disk->private_data;
427e9708 1791
edd10d33
KB		 1792 if (bio_list_empty(&nvmeq->sq_cong) &&
1793 list_empty(&nvmeq->iod_bio))
427e9708
KB		 1794 remove_wait_queue(&nvmeq->sq_full,
1795 &nvmeq->sq_cong_wait);
1fa6aead 1796 if (nvme_submit_bio_queue(nvmeq, ns, bio)) {
edd10d33 1797 if (!waitqueue_active(&nvmeq->sq_full))
427e9708
KB		 1798 add_wait_queue(&nvmeq->sq_full,
1799 &nvmeq->sq_cong_wait);
1fa6aead
MW		 1800 bio_list_add_head(&nvmeq->sq_cong, bio);
1801 break;
1802 }
1803 }
1804}
1805
1806static int nvme_kthread(void *data)
1807{
d4b4ff8e 1808 struct nvme_dev *dev, *next;
1fa6aead
MW		 1809
1810 while (!kthread_should_stop()) {
564a232c 1811 set_current_state(TASK_INTERRUPTIBLE);
1fa6aead 1812 spin_lock(&dev_list_lock);
d4b4ff8e 1813 list_for_each_entry_safe(dev, next, &dev_list, node) {
1fa6aead 1814 int i;
d4b4ff8e
KB		 1815 if (readl(&dev->bar->csts) & NVME_CSTS_CFS &&
1816 dev->initialized) {
1817 if (work_busy(&dev->reset_work))
1818 continue;
1819 list_del_init(&dev->node);
1820 dev_warn(&dev->pci_dev->dev,
1821 "Failed status, reset controller\n");
9ca97374 1822 dev->reset_workfn = nvme_reset_failed_dev;
d4b4ff8e
KB		 1823 queue_work(nvme_workq, &dev->reset_work);
1824 continue;
1825 }
5a92e700 1826 rcu_read_lock();
1fa6aead 1827 for (i = 0; i < dev->queue_count; i++) {
5a92e700
KB		 1828 struct nvme_queue *nvmeq =
1829 rcu_dereference(dev->queues[i]);
740216fc
MW		 1830 if (!nvmeq)
1831 continue;
1fa6aead 1832 spin_lock_irq(&nvmeq->q_lock);
22404274
KB		 1833 if (nvmeq->q_suspended)
1834 goto unlock;
bc57a0f7 1835 nvme_process_cq(nvmeq);
a09115b2 1836 nvme_cancel_ios(nvmeq, true);
1fa6aead 1837 nvme_resubmit_bios(nvmeq);
edd10d33 1838 nvme_resubmit_iods(nvmeq);
22404274 1839 unlock:
1fa6aead
MW		 1840 spin_unlock_irq(&nvmeq->q_lock);
1841 }
5a92e700 1842 rcu_read_unlock();
1fa6aead
MW		 1843 }
1844 spin_unlock(&dev_list_lock);
acb7aa0d 1845 schedule_timeout(round_jiffies_relative(HZ));
1fa6aead
MW		 1846 }
1847 return 0;
1848}
1849
0e5e4f0e
KB		 1850static void nvme_config_discard(struct nvme_ns *ns)
1851{
1852 u32 logical_block_size = queue_logical_block_size(ns->queue);
1853 ns->queue->limits.discard_zeroes_data = 0;
1854 ns->queue->limits.discard_alignment = logical_block_size;
1855 ns->queue->limits.discard_granularity = logical_block_size;
1856 ns->queue->limits.max_discard_sectors = 0xffffffff;
1857 queue_flag_set_unlocked(QUEUE_FLAG_DISCARD, ns->queue);
1858}
1859
c3bfe717 1860static struct nvme_ns *nvme_alloc_ns(struct nvme_dev *dev, unsigned nsid,
b60503ba
MW		 1861 struct nvme_id_ns *id, struct nvme_lba_range_type *rt)
1862{
1863 struct nvme_ns *ns;
1864 struct gendisk *disk;
1865 int lbaf;
1866
1867 if (rt->attributes & NVME_LBART_ATTRIB_HIDE)
1868 return NULL;
1869
1870 ns = kzalloc(sizeof(*ns), GFP_KERNEL);
1871 if (!ns)
1872 return NULL;
1873 ns->queue = blk_alloc_queue(GFP_KERNEL);
1874 if (!ns->queue)
1875 goto out_free_ns;
4eeb9215
MW		 1876 ns->queue->queue_flags = QUEUE_FLAG_DEFAULT;
1877 queue_flag_set_unlocked(QUEUE_FLAG_NOMERGES, ns->queue);
1878 queue_flag_set_unlocked(QUEUE_FLAG_NONROT, ns->queue);
b60503ba
MW		 1879 blk_queue_make_request(ns->queue, nvme_make_request);
1880 ns->dev = dev;
1881 ns->queue->queuedata = ns;
1882
469071a3 1883 disk = alloc_disk(0);
b60503ba
MW		 1884 if (!disk)
1885 goto out_free_queue;
5aff9382 1886 ns->ns_id = nsid;
b60503ba
MW		 1887 ns->disk = disk;
1888 lbaf = id->flbas & 0xf;
1889 ns->lba_shift = id->lbaf[lbaf].ds;
f410c680 1890 ns->ms = le16_to_cpu(id->lbaf[lbaf].ms);
e9ef4636 1891 blk_queue_logical_block_size(ns->queue, 1 << ns->lba_shift);
8fc23e03
KB		 1892 if (dev->max_hw_sectors)
1893 blk_queue_max_hw_sectors(ns->queue, dev->max_hw_sectors);
b60503ba
MW		 1894
1895 disk->major = nvme_major;
469071a3 1896 disk->first_minor = 0;
b60503ba
MW		 1897 disk->fops = &nvme_fops;
1898 disk->private_data = ns;
1899 disk->queue = ns->queue;
388f037f 1900 disk->driverfs_dev = &dev->pci_dev->dev;
469071a3 1901 disk->flags = GENHD_FL_EXT_DEVT;
5aff9382 1902 sprintf(disk->disk_name, "nvme%dn%d", dev->instance, nsid);
b60503ba
MW		 1903 set_capacity(disk, le64_to_cpup(&id->nsze) << (ns->lba_shift - 9));
1904
0e5e4f0e
KB		 1905 if (dev->oncs & NVME_CTRL_ONCS_DSM)
1906 nvme_config_discard(ns);
1907
b60503ba
MW		 1908 return ns;
1909
1910 out_free_queue:
1911 blk_cleanup_queue(ns->queue);
1912 out_free_ns:
1913 kfree(ns);
1914 return NULL;
1915}
1916
42f61420
KB		 1917static int nvme_find_closest_node(int node)
1918{
1919 int n, val, min_val = INT_MAX, best_node = node;
1920
1921 for_each_online_node(n) {
1922 if (n == node)
1923 continue;
1924 val = node_distance(node, n);
1925 if (val < min_val) {
1926 min_val = val;
1927 best_node = n;
1928 }
1929 }
1930 return best_node;
1931}
1932
1933static void nvme_set_queue_cpus(cpumask_t *qmask, struct nvme_queue *nvmeq,
1934 int count)
1935{
1936 int cpu;
1937 for_each_cpu(cpu, qmask) {
1938 if (cpumask_weight(nvmeq->cpu_mask) >= count)
1939 break;
1940 if (!cpumask_test_and_set_cpu(cpu, nvmeq->cpu_mask))
1941 *per_cpu_ptr(nvmeq->dev->io_queue, cpu) = nvmeq->qid;
1942 }
1943}
1944
1945static void nvme_add_cpus(cpumask_t *mask, const cpumask_t *unassigned_cpus,
1946 const cpumask_t *new_mask, struct nvme_queue *nvmeq, int cpus_per_queue)
1947{
1948 int next_cpu;
1949 for_each_cpu(next_cpu, new_mask) {
1950 cpumask_or(mask, mask, get_cpu_mask(next_cpu));
1951 cpumask_or(mask, mask, topology_thread_cpumask(next_cpu));
1952 cpumask_and(mask, mask, unassigned_cpus);
1953 nvme_set_queue_cpus(mask, nvmeq, cpus_per_queue);
1954 }
1955}
1956
1957static void nvme_create_io_queues(struct nvme_dev *dev)
1958{
1959 unsigned i, max;
1960
1961 max = min(dev->max_qid, num_online_cpus());
1962 for (i = dev->queue_count; i <= max; i++)
1963 if (!nvme_alloc_queue(dev, i, dev->q_depth, i - 1))
1964 break;
1965
1966 max = min(dev->queue_count - 1, num_online_cpus());
1967 for (i = dev->online_queues; i <= max; i++)
1968 if (nvme_create_queue(raw_nvmeq(dev, i), i))
1969 break;
1970}
1971
1972/*
1973 * If there are fewer queues than online cpus, this will try to optimally
1974 * assign a queue to multiple cpus by grouping cpus that are "close" together:
1975 * thread siblings, core, socket, closest node, then whatever else is
1976 * available.
1977 */
1978static void nvme_assign_io_queues(struct nvme_dev *dev)
1979{
1980 unsigned cpu, cpus_per_queue, queues, remainder, i;
1981 cpumask_var_t unassigned_cpus;
1982
1983 nvme_create_io_queues(dev);
1984
1985 queues = min(dev->online_queues - 1, num_online_cpus());
1986 if (!queues)
1987 return;
1988
1989 cpus_per_queue = num_online_cpus() / queues;
1990 remainder = queues - (num_online_cpus() - queues * cpus_per_queue);
1991
1992 if (!alloc_cpumask_var(&unassigned_cpus, GFP_KERNEL))
1993 return;
1994
1995 cpumask_copy(unassigned_cpus, cpu_online_mask);
1996 cpu = cpumask_first(unassigned_cpus);
1997 for (i = 1; i <= queues; i++) {
1998 struct nvme_queue *nvmeq = lock_nvmeq(dev, i);
1999 cpumask_t mask;
2000
2001 cpumask_clear(nvmeq->cpu_mask);
2002 if (!cpumask_weight(unassigned_cpus)) {
2003 unlock_nvmeq(nvmeq);
2004 break;
2005 }
2006
2007 mask = *get_cpu_mask(cpu);
2008 nvme_set_queue_cpus(&mask, nvmeq, cpus_per_queue);
2009 if (cpus_weight(mask) < cpus_per_queue)
2010 nvme_add_cpus(&mask, unassigned_cpus,
2011 topology_thread_cpumask(cpu),
2012 nvmeq, cpus_per_queue);
2013 if (cpus_weight(mask) < cpus_per_queue)
2014 nvme_add_cpus(&mask, unassigned_cpus,
2015 topology_core_cpumask(cpu),
2016 nvmeq, cpus_per_queue);
2017 if (cpus_weight(mask) < cpus_per_queue)
2018 nvme_add_cpus(&mask, unassigned_cpus,
2019 cpumask_of_node(cpu_to_node(cpu)),
2020 nvmeq, cpus_per_queue);
2021 if (cpus_weight(mask) < cpus_per_queue)
2022 nvme_add_cpus(&mask, unassigned_cpus,
2023 cpumask_of_node(
2024 nvme_find_closest_node(
2025 cpu_to_node(cpu))),
2026 nvmeq, cpus_per_queue);
2027 if (cpus_weight(mask) < cpus_per_queue)
2028 nvme_add_cpus(&mask, unassigned_cpus,
2029 unassigned_cpus,
2030 nvmeq, cpus_per_queue);
2031
2032 WARN(cpumask_weight(nvmeq->cpu_mask) != cpus_per_queue,
2033 "nvme%d qid:%d mis-matched queue-to-cpu assignment\n",
2034 dev->instance, i);
2035
2036 irq_set_affinity_hint(dev->entry[nvmeq->cq_vector].vector,
2037 nvmeq->cpu_mask);
2038 cpumask_andnot(unassigned_cpus, unassigned_cpus,
2039 nvmeq->cpu_mask);
2040 cpu = cpumask_next(cpu, unassigned_cpus);
2041 if (remainder && !--remainder)
2042 cpus_per_queue++;
2043 unlock_nvmeq(nvmeq);
2044 }
2045 WARN(cpumask_weight(unassigned_cpus), "nvme%d unassigned online cpus\n",
2046 dev->instance);
2047 i = 0;
2048 cpumask_andnot(unassigned_cpus, cpu_possible_mask, cpu_online_mask);
2049 for_each_cpu(cpu, unassigned_cpus)
2050 *per_cpu_ptr(dev->io_queue, cpu) = (i++ % queues) + 1;
2051 free_cpumask_var(unassigned_cpus);
2052}
2053
b3b06812 2054static int set_queue_count(struct nvme_dev *dev, int count)
b60503ba
MW		 2055{
2056 int status;
2057 u32 result;
b3b06812 2058 u32 q_count = (count - 1) | ((count - 1) << 16);
b60503ba 2059
df348139 2060 status = nvme_set_features(dev, NVME_FEAT_NUM_QUEUES, q_count, 0,
bc5fc7e4 2061 &result);
27e8166c
MW		 2062 if (status < 0)
2063 return status;
2064 if (status > 0) {
2065 dev_err(&dev->pci_dev->dev, "Could not set queue count (%d)\n",
2066 status);
2067 return -EBUSY;
2068 }
b60503ba
MW		 2069 return min(result & 0xffff, result >> 16) + 1;
2070}
2071
9d713c2b
KB		 2072static size_t db_bar_size(struct nvme_dev *dev, unsigned nr_io_queues)
2073{
b80d5ccc 2074 return 4096 + ((nr_io_queues + 1) * 8 * dev->db_stride);
9d713c2b
KB		 2075}
2076
33b1e95c
KB		 2077static int nvme_cpu_notify(struct notifier_block *self,
2078 unsigned long action, void *hcpu)
2079{
2080 struct nvme_dev *dev = container_of(self, struct nvme_dev, nb);
2081 switch (action) {
2082 case CPU_ONLINE:
2083 case CPU_DEAD:
2084 nvme_assign_io_queues(dev);
2085 break;
2086 }
2087 return NOTIFY_OK;
2088}
2089
8d85fce7 2090static int nvme_setup_io_queues(struct nvme_dev *dev)
b60503ba 2091{
5a92e700 2092 struct nvme_queue *adminq = raw_nvmeq(dev, 0);
fa08a396 2093 struct pci_dev *pdev = dev->pci_dev;
42f61420 2094 int result, i, vecs, nr_io_queues, size;
b60503ba 2095
42f61420 2096 nr_io_queues = num_possible_cpus();
b348b7d5 2097 result = set_queue_count(dev, nr_io_queues);
1b23484b
MW		 2098 if (result < 0)
2099 return result;
b348b7d5
MW		 2100 if (result < nr_io_queues)
2101 nr_io_queues = result;
b60503ba 2102
9d713c2b
KB		 2103 size = db_bar_size(dev, nr_io_queues);
2104 if (size > 8192) {
f1938f6e 2105 iounmap(dev->bar);
9d713c2b
KB		 2106 do {
2107 dev->bar = ioremap(pci_resource_start(pdev, 0), size);
2108 if (dev->bar)
2109 break;
2110 if (!--nr_io_queues)
2111 return -ENOMEM;
2112 size = db_bar_size(dev, nr_io_queues);
2113 } while (1);
f1938f6e 2114 dev->dbs = ((void __iomem *)dev->bar) + 4096;
5a92e700 2115 adminq->q_db = dev->dbs;
f1938f6e
MW		 2116 }
2117
9d713c2b 2118 /* Deregister the admin queue's interrupt */
3193f07b 2119 free_irq(dev->entry[0].vector, adminq);
9d713c2b 2120
be577fab 2121 for (i = 0; i < nr_io_queues; i++)
1b23484b 2122 dev->entry[i].entry = i;
be577fab
AG		 2123 vecs = pci_enable_msix_range(pdev, dev->entry, 1, nr_io_queues);
2124 if (vecs < 0) {
2125 vecs = pci_enable_msi_range(pdev, 1, min(nr_io_queues, 32));
2126 if (vecs < 0) {
2127 vecs = 1;
2128 } else {
2129 for (i = 0; i < vecs; i++)
2130 dev->entry[i].vector = i + pdev->irq;
fa08a396
RRG		 2131 }
2132 }
2133
063a8096
MW		 2134 /*
2135 * Should investigate if there's a performance win from allocating
2136 * more queues than interrupt vectors; it might allow the submission
2137 * path to scale better, even if the receive path is limited by the
2138 * number of interrupts.
2139 */
2140 nr_io_queues = vecs;
42f61420 2141 dev->max_qid = nr_io_queues;
063a8096 2142
3193f07b 2143 result = queue_request_irq(dev, adminq, adminq->irqname);
9d713c2b 2144 if (result) {
3193f07b 2145 adminq->q_suspended = 1;
22404274 2146 goto free_queues;
9d713c2b 2147 }
1b23484b 2148
cd638946 2149 /* Free previously allocated queues that are no longer usable */
42f61420
KB		 2150 nvme_free_queues(dev, nr_io_queues + 1);
2151 nvme_assign_io_queues(dev);
9ecdc946 2152
33b1e95c
KB		 2153 dev->nb.notifier_call = &nvme_cpu_notify;
2154 result = register_hotcpu_notifier(&dev->nb);
2155 if (result)
2156 goto free_queues;
b60503ba 2157
22404274 2158 return 0;
b60503ba 2159
22404274 2160 free_queues:
a1a5ef99 2161 nvme_free_queues(dev, 1);
22404274 2162 return result;
b60503ba
MW		 2163}
2164
422ef0c7
MW		 2165/*
2166 * Return: error value if an error occurred setting up the queues or calling
2167 * Identify Device. 0 if these succeeded, even if adding some of the
2168 * namespaces failed. At the moment, these failures are silent. TBD which
2169 * failures should be reported.
2170 */
8d85fce7 2171static int nvme_dev_add(struct nvme_dev *dev)
b60503ba 2172{
68608c26 2173 struct pci_dev *pdev = dev->pci_dev;
c3bfe717
MW		 2174 int res;
2175 unsigned nn, i;
cbb6218f 2176 struct nvme_ns *ns;
51814232 2177 struct nvme_id_ctrl *ctrl;
bc5fc7e4
MW		 2178 struct nvme_id_ns *id_ns;
2179 void *mem;
b60503ba 2180 dma_addr_t dma_addr;
159b67d7 2181 int shift = NVME_CAP_MPSMIN(readq(&dev->bar->cap)) + 12;
b60503ba 2182
68608c26 2183 mem = dma_alloc_coherent(&pdev->dev, 8192, &dma_addr, GFP_KERNEL);
a9ef4343
KB		 2184 if (!mem)
2185 return -ENOMEM;
b60503ba 2186
bc5fc7e4 2187 res = nvme_identify(dev, 0, 1, dma_addr);
b60503ba 2188 if (res) {
27e8166c 2189 dev_err(&pdev->dev, "Identify Controller failed (%d)\n", res);
b60503ba 2190 res = -EIO;
cbb6218f 2191 goto out;
b60503ba
MW		 2192 }
2193
bc5fc7e4 2194 ctrl = mem;
51814232 2195 nn = le32_to_cpup(&ctrl->nn);
0e5e4f0e 2196 dev->oncs = le16_to_cpup(&ctrl->oncs);
c30341dc 2197 dev->abort_limit = ctrl->acl + 1;
51814232
MW		 2198 memcpy(dev->serial, ctrl->sn, sizeof(ctrl->sn));
2199 memcpy(dev->model, ctrl->mn, sizeof(ctrl->mn));
2200 memcpy(dev->firmware_rev, ctrl->fr, sizeof(ctrl->fr));
159b67d7 2201 if (ctrl->mdts)
8fc23e03 2202 dev->max_hw_sectors = 1 << (ctrl->mdts + shift - 9);
68608c26
MW		 2203 if ((pdev->vendor == PCI_VENDOR_ID_INTEL) &&
2204 (pdev->device == 0x0953) && ctrl->vs[3])
159b67d7 2205 dev->stripe_size = 1 << (ctrl->vs[3] + shift);
b60503ba 2206
bc5fc7e4 2207 id_ns = mem;
2b2c1896 2208 for (i = 1; i <= nn; i++) {
bc5fc7e4 2209 res = nvme_identify(dev, i, 0, dma_addr);
b60503ba
MW		 2210 if (res)
2211 continue;
2212
bc5fc7e4 2213 if (id_ns->ncap == 0)
b60503ba
MW		 2214 continue;
2215
bc5fc7e4 2216 res = nvme_get_features(dev, NVME_FEAT_LBA_RANGE, i,
08df1e05 2217 dma_addr + 4096, NULL);
b60503ba 2218 if (res)
12209036 2219 memset(mem + 4096, 0, 4096);
b60503ba 2220
bc5fc7e4 2221 ns = nvme_alloc_ns(dev, i, mem, mem + 4096);
b60503ba
MW		 2222 if (ns)
2223 list_add_tail(&ns->list, &dev->namespaces);
2224 }
2225 list_for_each_entry(ns, &dev->namespaces, list)
2226 add_disk(ns->disk);
422ef0c7 2227 res = 0;
b60503ba 2228
bc5fc7e4 2229 out:
684f5c20 2230 dma_free_coherent(&dev->pci_dev->dev, 8192, mem, dma_addr);
b60503ba
MW		 2231 return res;
2232}
2233
0877cb0d
KB		 2234static int nvme_dev_map(struct nvme_dev *dev)
2235{
42f61420 2236 u64 cap;
0877cb0d
KB		 2237 int bars, result = -ENOMEM;
2238 struct pci_dev *pdev = dev->pci_dev;
2239
2240 if (pci_enable_device_mem(pdev))
2241 return result;
2242
2243 dev->entry[0].vector = pdev->irq;
2244 pci_set_master(pdev);
2245 bars = pci_select_bars(pdev, IORESOURCE_MEM);
2246 if (pci_request_selected_regions(pdev, bars, "nvme"))
2247 goto disable_pci;
2248
052d0efa
RK		 2249 if (dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)) &&
2250 dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32)))
2251 goto disable;
0877cb0d 2252
0877cb0d
KB		 2253 dev->bar = ioremap(pci_resource_start(pdev, 0), 8192);
2254 if (!dev->bar)
2255 goto disable;
0e53d180
KB		 2256 if (readl(&dev->bar->csts) == -1) {
2257 result = -ENODEV;
2258 goto unmap;
2259 }
42f61420
KB		 2260 cap = readq(&dev->bar->cap);
2261 dev->q_depth = min_t(int, NVME_CAP_MQES(cap) + 1, NVME_Q_DEPTH);
2262 dev->db_stride = 1 << NVME_CAP_STRIDE(cap);
0877cb0d
KB		 2263 dev->dbs = ((void __iomem *)dev->bar) + 4096;
2264
2265 return 0;
2266
0e53d180
KB		 2267 unmap:
2268 iounmap(dev->bar);
2269 dev->bar = NULL;
0877cb0d
KB		 2270 disable:
2271 pci_release_regions(pdev);
2272 disable_pci:
2273 pci_disable_device(pdev);
2274 return result;
2275}
2276
2277static void nvme_dev_unmap(struct nvme_dev *dev)
2278{
2279 if (dev->pci_dev->msi_enabled)
2280 pci_disable_msi(dev->pci_dev);
2281 else if (dev->pci_dev->msix_enabled)
2282 pci_disable_msix(dev->pci_dev);
2283
2284 if (dev->bar) {
2285 iounmap(dev->bar);
2286 dev->bar = NULL;
9a6b9458 2287 pci_release_regions(dev->pci_dev);
0877cb0d
KB		 2288 }
2289
0877cb0d
KB		 2290 if (pci_is_enabled(dev->pci_dev))
2291 pci_disable_device(dev->pci_dev);
2292}
2293
4d115420
KB		 2294struct nvme_delq_ctx {
2295 struct task_struct *waiter;
2296 struct kthread_worker *worker;
2297 atomic_t refcount;
2298};
2299
2300static void nvme_wait_dq(struct nvme_delq_ctx *dq, struct nvme_dev *dev)
2301{
2302 dq->waiter = current;
2303 mb();
2304
2305 for (;;) {
2306 set_current_state(TASK_KILLABLE);
2307 if (!atomic_read(&dq->refcount))
2308 break;
2309 if (!schedule_timeout(ADMIN_TIMEOUT) ||
2310 fatal_signal_pending(current)) {
2311 set_current_state(TASK_RUNNING);
2312
2313 nvme_disable_ctrl(dev, readq(&dev->bar->cap));
2314 nvme_disable_queue(dev, 0);
2315
2316 send_sig(SIGKILL, dq->worker->task, 1);
2317 flush_kthread_worker(dq->worker);
2318 return;
2319 }
2320 }
2321 set_current_state(TASK_RUNNING);
2322}
2323
2324static void nvme_put_dq(struct nvme_delq_ctx *dq)
2325{
2326 atomic_dec(&dq->refcount);
2327 if (dq->waiter)
2328 wake_up_process(dq->waiter);
2329}
2330
2331static struct nvme_delq_ctx *nvme_get_dq(struct nvme_delq_ctx *dq)
2332{
2333 atomic_inc(&dq->refcount);
2334 return dq;
2335}
2336
2337static void nvme_del_queue_end(struct nvme_queue *nvmeq)
2338{
2339 struct nvme_delq_ctx *dq = nvmeq->cmdinfo.ctx;
2340
2341 nvme_clear_queue(nvmeq);
2342 nvme_put_dq(dq);
2343}
2344
2345static int adapter_async_del_queue(struct nvme_queue *nvmeq, u8 opcode,
2346 kthread_work_func_t fn)
2347{
2348 struct nvme_command c;
2349
2350 memset(&c, 0, sizeof(c));
2351 c.delete_queue.opcode = opcode;
2352 c.delete_queue.qid = cpu_to_le16(nvmeq->qid);
2353
2354 init_kthread_work(&nvmeq->cmdinfo.work, fn);
2355 return nvme_submit_admin_cmd_async(nvmeq->dev, &c, &nvmeq->cmdinfo);
2356}
2357
2358static void nvme_del_cq_work_handler(struct kthread_work *work)
2359{
2360 struct nvme_queue *nvmeq = container_of(work, struct nvme_queue,
2361 cmdinfo.work);
2362 nvme_del_queue_end(nvmeq);
2363}
2364
2365static int nvme_delete_cq(struct nvme_queue *nvmeq)
2366{
2367 return adapter_async_del_queue(nvmeq, nvme_admin_delete_cq,
2368 nvme_del_cq_work_handler);
2369}
2370
2371static void nvme_del_sq_work_handler(struct kthread_work *work)
2372{
2373 struct nvme_queue *nvmeq = container_of(work, struct nvme_queue,
2374 cmdinfo.work);
2375 int status = nvmeq->cmdinfo.status;
2376
2377 if (!status)
2378 status = nvme_delete_cq(nvmeq);
2379 if (status)
2380 nvme_del_queue_end(nvmeq);
2381}
2382
2383static int nvme_delete_sq(struct nvme_queue *nvmeq)
2384{
2385 return adapter_async_del_queue(nvmeq, nvme_admin_delete_sq,
2386 nvme_del_sq_work_handler);
2387}
2388
2389static void nvme_del_queue_start(struct kthread_work *work)
2390{
2391 struct nvme_queue *nvmeq = container_of(work, struct nvme_queue,
2392 cmdinfo.work);
2393 allow_signal(SIGKILL);
2394 if (nvme_delete_sq(nvmeq))
2395 nvme_del_queue_end(nvmeq);
2396}
2397
2398static void nvme_disable_io_queues(struct nvme_dev *dev)
2399{
2400 int i;
2401 DEFINE_KTHREAD_WORKER_ONSTACK(worker);
2402 struct nvme_delq_ctx dq;
2403 struct task_struct *kworker_task = kthread_run(kthread_worker_fn,
2404 &worker, "nvme%d", dev->instance);
2405
2406 if (IS_ERR(kworker_task)) {
2407 dev_err(&dev->pci_dev->dev,
2408 "Failed to create queue del task\n");
2409 for (i = dev->queue_count - 1; i > 0; i--)
2410 nvme_disable_queue(dev, i);
2411 return;
2412 }
2413
2414 dq.waiter = NULL;
2415 atomic_set(&dq.refcount, 0);
2416 dq.worker = &worker;
2417 for (i = dev->queue_count - 1; i > 0; i--) {
5a92e700 2418 struct nvme_queue *nvmeq = raw_nvmeq(dev, i);
4d115420
KB		 2419
2420 if (nvme_suspend_queue(nvmeq))
2421 continue;
2422 nvmeq->cmdinfo.ctx = nvme_get_dq(&dq);
2423 nvmeq->cmdinfo.worker = dq.worker;
2424 init_kthread_work(&nvmeq->cmdinfo.work, nvme_del_queue_start);
2425 queue_kthread_work(dq.worker, &nvmeq->cmdinfo.work);
2426 }
2427 nvme_wait_dq(&dq, dev);
2428 kthread_stop(kworker_task);
2429}
2430
b9afca3e
DM		 2431/*
2432* Remove the node from the device list and check
2433* for whether or not we need to stop the nvme_thread.
2434*/
2435static void nvme_dev_list_remove(struct nvme_dev *dev)
2436{
2437 struct task_struct *tmp = NULL;
2438
2439 spin_lock(&dev_list_lock);
2440 list_del_init(&dev->node);
2441 if (list_empty(&dev_list) && !IS_ERR_OR_NULL(nvme_thread)) {
2442 tmp = nvme_thread;
2443 nvme_thread = NULL;
2444 }
2445 spin_unlock(&dev_list_lock);
2446
2447 if (tmp)
2448 kthread_stop(tmp);
2449}
2450
f0b50732 2451static void nvme_dev_shutdown(struct nvme_dev *dev)
b60503ba 2452{
22404274
KB		 2453 int i;
2454
d4b4ff8e 2455 dev->initialized = 0;
33b1e95c 2456 unregister_hotcpu_notifier(&dev->nb);
b60503ba 2457
b9afca3e 2458 nvme_dev_list_remove(dev);
1fa6aead 2459
4d115420
KB		 2460 if (!dev->bar || (dev->bar && readl(&dev->bar->csts) == -1)) {
2461 for (i = dev->queue_count - 1; i >= 0; i--) {
5a92e700 2462 struct nvme_queue *nvmeq = raw_nvmeq(dev, i);
4d115420
KB		 2463 nvme_suspend_queue(nvmeq);
2464 nvme_clear_queue(nvmeq);
2465 }
2466 } else {
2467 nvme_disable_io_queues(dev);
1894d8f1 2468 nvme_shutdown_ctrl(dev);
4d115420
KB		 2469 nvme_disable_queue(dev, 0);
2470 }
f0b50732
KB		 2471 nvme_dev_unmap(dev);
2472}
2473
2474static void nvme_dev_remove(struct nvme_dev *dev)
2475{
9ac27090 2476 struct nvme_ns *ns;
f0b50732 2477
9ac27090
KB		 2478 list_for_each_entry(ns, &dev->namespaces, list) {
2479 if (ns->disk->flags & GENHD_FL_UP)
2480 del_gendisk(ns->disk);
2481 if (!blk_queue_dying(ns->queue))
2482 blk_cleanup_queue(ns->queue);
b60503ba 2483 }
b60503ba
MW		 2484}
2485
091b6092
MW		 2486static int nvme_setup_prp_pools(struct nvme_dev *dev)
2487{
2488 struct device *dmadev = &dev->pci_dev->dev;
2489 dev->prp_page_pool = dma_pool_create("prp list page", dmadev,
2490 PAGE_SIZE, PAGE_SIZE, 0);
2491 if (!dev->prp_page_pool)
2492 return -ENOMEM;
2493
99802a7a
MW		 2494 /* Optimisation for I/Os between 4k and 128k */
2495 dev->prp_small_pool = dma_pool_create("prp list 256", dmadev,
2496 256, 256, 0);
2497 if (!dev->prp_small_pool) {
2498 dma_pool_destroy(dev->prp_page_pool);
2499 return -ENOMEM;
2500 }
091b6092
MW		 2501 return 0;
2502}
2503
2504static void nvme_release_prp_pools(struct nvme_dev *dev)
2505{
2506 dma_pool_destroy(dev->prp_page_pool);
99802a7a 2507 dma_pool_destroy(dev->prp_small_pool);
091b6092
MW		 2508}
2509
cd58ad7d
QSA		 2510static DEFINE_IDA(nvme_instance_ida);
2511
2512static int nvme_set_instance(struct nvme_dev *dev)
b60503ba 2513{
cd58ad7d
QSA		 2514 int instance, error;
2515
2516 do {
2517 if (!ida_pre_get(&nvme_instance_ida, GFP_KERNEL))
2518 return -ENODEV;
2519
2520 spin_lock(&dev_list_lock);
2521 error = ida_get_new(&nvme_instance_ida, &instance);
2522 spin_unlock(&dev_list_lock);
2523 } while (error == -EAGAIN);
2524
2525 if (error)
2526 return -ENODEV;
2527
2528 dev->instance = instance;
2529 return 0;
b60503ba
MW		 2530}
2531
2532static void nvme_release_instance(struct nvme_dev *dev)
2533{
cd58ad7d
QSA		 2534 spin_lock(&dev_list_lock);
2535 ida_remove(&nvme_instance_ida, dev->instance);
2536 spin_unlock(&dev_list_lock);
b60503ba
MW		 2537}
2538
9ac27090
KB		 2539static void nvme_free_namespaces(struct nvme_dev *dev)
2540{
2541 struct nvme_ns *ns, *next;
2542
2543 list_for_each_entry_safe(ns, next, &dev->namespaces, list) {
2544 list_del(&ns->list);
2545 put_disk(ns->disk);
2546 kfree(ns);
2547 }
2548}
2549
5e82e952
KB		 2550static void nvme_free_dev(struct kref *kref)
2551{
2552 struct nvme_dev *dev = container_of(kref, struct nvme_dev, kref);
9ac27090
KB		 2553
2554 nvme_free_namespaces(dev);
42f61420 2555 free_percpu(dev->io_queue);
5e82e952
KB		 2556 kfree(dev->queues);
2557 kfree(dev->entry);
2558 kfree(dev);
2559}
2560
2561static int nvme_dev_open(struct inode *inode, struct file *f)
2562{
2563 struct nvme_dev *dev = container_of(f->private_data, struct nvme_dev,
2564 miscdev);
2565 kref_get(&dev->kref);
2566 f->private_data = dev;
2567 return 0;
2568}
2569
2570static int nvme_dev_release(struct inode *inode, struct file *f)
2571{
2572 struct nvme_dev *dev = f->private_data;
2573 kref_put(&dev->kref, nvme_free_dev);
2574 return 0;
2575}
2576
2577static long nvme_dev_ioctl(struct file *f, unsigned int cmd, unsigned long arg)
2578{
2579 struct nvme_dev *dev = f->private_data;
2580 switch (cmd) {
2581 case NVME_IOCTL_ADMIN_CMD:
2582 return nvme_user_admin_cmd(dev, (void __user *)arg);
2583 default:
2584 return -ENOTTY;
2585 }
2586}
2587
2588static const struct file_operations nvme_dev_fops = {
2589 .owner = THIS_MODULE,
2590 .open = nvme_dev_open,
2591 .release = nvme_dev_release,
2592 .unlocked_ioctl = nvme_dev_ioctl,
2593 .compat_ioctl = nvme_dev_ioctl,
2594};
2595
f0b50732
KB		 2596static int nvme_dev_start(struct nvme_dev *dev)
2597{
2598 int result;
b9afca3e 2599 bool start_thread = false;
f0b50732
KB		 2600
2601 result = nvme_dev_map(dev);
2602 if (result)
2603 return result;
2604
2605 result = nvme_configure_admin_queue(dev);
2606 if (result)
2607 goto unmap;
2608
2609 spin_lock(&dev_list_lock);
b9afca3e
DM		 2610 if (list_empty(&dev_list) && IS_ERR_OR_NULL(nvme_thread)) {
2611 start_thread = true;
2612 nvme_thread = NULL;
2613 }
f0b50732
KB		 2614 list_add(&dev->node, &dev_list);
2615 spin_unlock(&dev_list_lock);
2616
b9afca3e
DM		 2617 if (start_thread) {
2618 nvme_thread = kthread_run(nvme_kthread, NULL, "nvme");
2619 wake_up(&nvme_kthread_wait);
2620 } else
2621 wait_event_killable(nvme_kthread_wait, nvme_thread);
2622
2623 if (IS_ERR_OR_NULL(nvme_thread)) {
2624 result = nvme_thread ? PTR_ERR(nvme_thread) : -EINTR;
2625 goto disable;
2626 }
2627
f0b50732 2628 result = nvme_setup_io_queues(dev);
d82e8bfd 2629 if (result && result != -EBUSY)
f0b50732
KB		 2630 goto disable;
2631
d82e8bfd 2632 return result;
f0b50732
KB		 2633
2634 disable:
a1a5ef99 2635 nvme_disable_queue(dev, 0);
b9afca3e 2636 nvme_dev_list_remove(dev);
f0b50732
KB		 2637 unmap:
2638 nvme_dev_unmap(dev);
2639 return result;
2640}
2641
9a6b9458
KB		 2642static int nvme_remove_dead_ctrl(void *arg)
2643{
2644 struct nvme_dev *dev = (struct nvme_dev *)arg;
2645 struct pci_dev *pdev = dev->pci_dev;
2646
2647 if (pci_get_drvdata(pdev))
2648 pci_stop_and_remove_bus_device(pdev);
2649 kref_put(&dev->kref, nvme_free_dev);
2650 return 0;
2651}
2652
2653static void nvme_remove_disks(struct work_struct *ws)
2654{
9a6b9458
KB		 2655 struct nvme_dev *dev = container_of(ws, struct nvme_dev, reset_work);
2656
2657 nvme_dev_remove(dev);
5a92e700 2658 nvme_free_queues(dev, 1);
9a6b9458
KB		 2659}
2660
2661static int nvme_dev_resume(struct nvme_dev *dev)
2662{
2663 int ret;
2664
2665 ret = nvme_dev_start(dev);
2666 if (ret && ret != -EBUSY)
2667 return ret;
2668 if (ret == -EBUSY) {
2669 spin_lock(&dev_list_lock);
9ca97374 2670 dev->reset_workfn = nvme_remove_disks;
9a6b9458
KB		 2671 queue_work(nvme_workq, &dev->reset_work);
2672 spin_unlock(&dev_list_lock);
2673 }
d4b4ff8e 2674 dev->initialized = 1;
9a6b9458
KB		 2675 return 0;
2676}
2677
2678static void nvme_dev_reset(struct nvme_dev *dev)
2679{
2680 nvme_dev_shutdown(dev);
2681 if (nvme_dev_resume(dev)) {
2682 dev_err(&dev->pci_dev->dev, "Device failed to resume\n");
2683 kref_get(&dev->kref);
2684 if (IS_ERR(kthread_run(nvme_remove_dead_ctrl, dev, "nvme%d",
2685 dev->instance))) {
2686 dev_err(&dev->pci_dev->dev,
2687 "Failed to start controller remove task\n");
2688 kref_put(&dev->kref, nvme_free_dev);
2689 }
2690 }
2691}
2692
2693static void nvme_reset_failed_dev(struct work_struct *ws)
2694{
2695 struct nvme_dev *dev = container_of(ws, struct nvme_dev, reset_work);
2696 nvme_dev_reset(dev);
2697}
2698
9ca97374
TH		 2699static void nvme_reset_workfn(struct work_struct *work)
2700{
2701 struct nvme_dev *dev = container_of(work, struct nvme_dev, reset_work);
2702 dev->reset_workfn(work);
2703}
2704
8d85fce7 2705static int nvme_probe(struct pci_dev *pdev, const struct pci_device_id *id)
b60503ba 2706{
0877cb0d 2707 int result = -ENOMEM;
b60503ba
MW		 2708 struct nvme_dev *dev;
2709
2710 dev = kzalloc(sizeof(*dev), GFP_KERNEL);
2711 if (!dev)
2712 return -ENOMEM;
2713 dev->entry = kcalloc(num_possible_cpus(), sizeof(*dev->entry),
2714 GFP_KERNEL);
2715 if (!dev->entry)
2716 goto free;
1b23484b
MW		 2717 dev->queues = kcalloc(num_possible_cpus() + 1, sizeof(void *),
2718 GFP_KERNEL);
b60503ba
MW		 2719 if (!dev->queues)
2720 goto free;
42f61420
KB		 2721 dev->io_queue = alloc_percpu(unsigned short);
2722 if (!dev->io_queue)
2723 goto free;
b60503ba
MW		 2724
2725 INIT_LIST_HEAD(&dev->namespaces);
9ca97374
TH		 2726 dev->reset_workfn = nvme_reset_failed_dev;
2727 INIT_WORK(&dev->reset_work, nvme_reset_workfn);
b60503ba 2728 dev->pci_dev = pdev;
9a6b9458 2729 pci_set_drvdata(pdev, dev);
cd58ad7d
QSA		 2730 result = nvme_set_instance(dev);
2731 if (result)
0877cb0d 2732 goto free;
b60503ba 2733
091b6092
MW		 2734 result = nvme_setup_prp_pools(dev);
2735 if (result)
0877cb0d 2736 goto release;
091b6092 2737
fb35e914 2738 kref_init(&dev->kref);
f0b50732 2739 result = nvme_dev_start(dev);
d82e8bfd
KB		 2740 if (result) {
2741 if (result == -EBUSY)
2742 goto create_cdev;
0877cb0d 2743 goto release_pools;
d82e8bfd 2744 }
b60503ba 2745
740216fc 2746 result = nvme_dev_add(dev);
d82e8bfd 2747 if (result)
f0b50732 2748 goto shutdown;
740216fc 2749
d82e8bfd 2750 create_cdev:
5e82e952
KB		 2751 scnprintf(dev->name, sizeof(dev->name), "nvme%d", dev->instance);
2752 dev->miscdev.minor = MISC_DYNAMIC_MINOR;
2753 dev->miscdev.parent = &pdev->dev;
2754 dev->miscdev.name = dev->name;
2755 dev->miscdev.fops = &nvme_dev_fops;
2756 result = misc_register(&dev->miscdev);
2757 if (result)
2758 goto remove;
2759
d4b4ff8e 2760 dev->initialized = 1;
b60503ba
MW		 2761 return 0;
2762
5e82e952
KB		 2763 remove:
2764 nvme_dev_remove(dev);
9ac27090 2765 nvme_free_namespaces(dev);
f0b50732
KB		 2766 shutdown:
2767 nvme_dev_shutdown(dev);
0877cb0d 2768 release_pools:
a1a5ef99 2769 nvme_free_queues(dev, 0);
091b6092 2770 nvme_release_prp_pools(dev);
0877cb0d
KB		 2771 release:
2772 nvme_release_instance(dev);
b60503ba 2773 free:
42f61420 2774 free_percpu(dev->io_queue);
b60503ba
MW		 2775 kfree(dev->queues);
2776 kfree(dev->entry);
2777 kfree(dev);
2778 return result;
2779}
2780
09ece142
KB		 2781static void nvme_shutdown(struct pci_dev *pdev)
2782{
2783 struct nvme_dev *dev = pci_get_drvdata(pdev);
2784 nvme_dev_shutdown(dev);
2785}
2786
8d85fce7 2787static void nvme_remove(struct pci_dev *pdev)
b60503ba
MW		 2788{
2789 struct nvme_dev *dev = pci_get_drvdata(pdev);
9a6b9458
KB		 2790
2791 spin_lock(&dev_list_lock);
2792 list_del_init(&dev->node);
2793 spin_unlock(&dev_list_lock);
2794
2795 pci_set_drvdata(pdev, NULL);
2796 flush_work(&dev->reset_work);
5e82e952 2797 misc_deregister(&dev->miscdev);
9a6b9458
KB		 2798 nvme_dev_remove(dev);
2799 nvme_dev_shutdown(dev);
a1a5ef99 2800 nvme_free_queues(dev, 0);
5a92e700 2801 rcu_barrier();
9a6b9458
KB		 2802 nvme_release_instance(dev);
2803 nvme_release_prp_pools(dev);
5e82e952 2804 kref_put(&dev->kref, nvme_free_dev);
b60503ba
MW		 2805}
2806
2807/* These functions are yet to be implemented */
2808#define nvme_error_detected NULL
2809#define nvme_dump_registers NULL
2810#define nvme_link_reset NULL
2811#define nvme_slot_reset NULL
2812#define nvme_error_resume NULL
cd638946 2813
671a6018 2814#ifdef CONFIG_PM_SLEEP
cd638946
KB		 2815static int nvme_suspend(struct device *dev)
2816{
2817 struct pci_dev *pdev = to_pci_dev(dev);
2818 struct nvme_dev *ndev = pci_get_drvdata(pdev);
2819
2820 nvme_dev_shutdown(ndev);
2821 return 0;
2822}
2823
2824static int nvme_resume(struct device *dev)
2825{
2826 struct pci_dev *pdev = to_pci_dev(dev);
2827 struct nvme_dev *ndev = pci_get_drvdata(pdev);
cd638946 2828
9a6b9458 2829 if (nvme_dev_resume(ndev) && !work_busy(&ndev->reset_work)) {
9ca97374 2830 ndev->reset_workfn = nvme_reset_failed_dev;
9a6b9458
KB		 2831 queue_work(nvme_workq, &ndev->reset_work);
2832 }
2833 return 0;
cd638946 2834}
671a6018 2835#endif
cd638946
KB		 2836
2837static SIMPLE_DEV_PM_OPS(nvme_dev_pm_ops, nvme_suspend, nvme_resume);
b60503ba 2838
1d352035 2839static const struct pci_error_handlers nvme_err_handler = {
b60503ba
MW		 2840 .error_detected = nvme_error_detected,
2841 .mmio_enabled = nvme_dump_registers,
2842 .link_reset = nvme_link_reset,
2843 .slot_reset = nvme_slot_reset,
2844 .resume = nvme_error_resume,
2845};
2846
2847/* Move to pci_ids.h later */
2848#define PCI_CLASS_STORAGE_EXPRESS 0x010802
2849
6eb0d698 2850static const struct pci_device_id nvme_id_table[] = {
b60503ba
MW		 2851 { PCI_DEVICE_CLASS(PCI_CLASS_STORAGE_EXPRESS, 0xffffff) },
2852 { 0, }
2853};
2854MODULE_DEVICE_TABLE(pci, nvme_id_table);
2855
2856static struct pci_driver nvme_driver = {
2857 .name = "nvme",
2858 .id_table = nvme_id_table,
2859 .probe = nvme_probe,
8d85fce7 2860 .remove = nvme_remove,
09ece142 2861 .shutdown = nvme_shutdown,
cd638946
KB		 2862 .driver = {
2863 .pm = &nvme_dev_pm_ops,
2864 },
b60503ba
MW		 2865 .err_handler = &nvme_err_handler,
2866};
2867
2868static int __init nvme_init(void)
2869{
0ac13140 2870 int result;
1fa6aead 2871
b9afca3e 2872 init_waitqueue_head(&nvme_kthread_wait);
b60503ba 2873
9a6b9458
KB		 2874 nvme_workq = create_singlethread_workqueue("nvme");
2875 if (!nvme_workq)
b9afca3e 2876 return -ENOMEM;
9a6b9458 2877
5c42ea16
KB		 2878 result = register_blkdev(nvme_major, "nvme");
2879 if (result < 0)
9a6b9458 2880 goto kill_workq;
5c42ea16 2881 else if (result > 0)
0ac13140 2882 nvme_major = result;
b60503ba
MW		 2883
2884 result = pci_register_driver(&nvme_driver);
1fa6aead
MW		 2885 if (result)
2886 goto unregister_blkdev;
2887 return 0;
b60503ba 2888
1fa6aead 2889 unregister_blkdev:
b60503ba 2890 unregister_blkdev(nvme_major, "nvme");
9a6b9458
KB		 2891 kill_workq:
2892 destroy_workqueue(nvme_workq);
b60503ba
MW		 2893 return result;
2894}
2895
2896static void __exit nvme_exit(void)
2897{
2898 pci_unregister_driver(&nvme_driver);
2899 unregister_blkdev(nvme_major, "nvme");
9a6b9458 2900 destroy_workqueue(nvme_workq);
b9afca3e 2901 BUG_ON(nvme_thread && !IS_ERR(nvme_thread));
b60503ba
MW		 2902}
2903
2904MODULE_AUTHOR("Matthew Wilcox <willy@linux.intel.com>");
2905MODULE_LICENSE("GPL");
6eb0d698 2906MODULE_VERSION("0.9");
b60503ba
MW		 2907module_init(nvme_init);
2908module_exit(nvme_exit);
Linux 6.x block layer and io_uring tree(s)