[linux-2.6-block.git] / drivers / bcma / scan.c

/*
 * Broadcom specific AMBA
 * Bus scanning
 *
 * Licensed under the GNU/GPL. See COPYING for details.
 */

#include "scan.h"
#include "bcma_private.h"

#include <linux/bcma/bcma.h>
#include <linux/bcma/bcma_regs.h>
#include <linux/pci.h>
#include <linux/io.h>
#include <linux/dma-mapping.h>
#include <linux/slab.h>

struct bcma_device_id_name {
	u16 id;
	const char *name;
};
struct bcma_device_id_name bcma_device_names[] = {
	{ BCMA_CORE_OOB_ROUTER, "OOB Router" },
	{ BCMA_CORE_INVALID, "Invalid" },
	{ BCMA_CORE_CHIPCOMMON, "ChipCommon" },
	{ BCMA_CORE_ILINE20, "ILine 20" },
	{ BCMA_CORE_SRAM, "SRAM" },
	{ BCMA_CORE_SDRAM, "SDRAM" },
	{ BCMA_CORE_PCI, "PCI" },
	{ BCMA_CORE_MIPS, "MIPS" },
	{ BCMA_CORE_ETHERNET, "Fast Ethernet" },
	{ BCMA_CORE_V90, "V90" },
	{ BCMA_CORE_USB11_HOSTDEV, "USB 1.1 Hostdev" },
	{ BCMA_CORE_ADSL, "ADSL" },
	{ BCMA_CORE_ILINE100, "ILine 100" },
	{ BCMA_CORE_IPSEC, "IPSEC" },
	{ BCMA_CORE_UTOPIA, "UTOPIA" },
	{ BCMA_CORE_PCMCIA, "PCMCIA" },
	{ BCMA_CORE_INTERNAL_MEM, "Internal Memory" },
	{ BCMA_CORE_MEMC_SDRAM, "MEMC SDRAM" },
	{ BCMA_CORE_OFDM, "OFDM" },
	{ BCMA_CORE_EXTIF, "EXTIF" },
	{ BCMA_CORE_80211, "IEEE 802.11" },
	{ BCMA_CORE_PHY_A, "PHY A" },
	{ BCMA_CORE_PHY_B, "PHY B" },
	{ BCMA_CORE_PHY_G, "PHY G" },
	{ BCMA_CORE_MIPS_3302, "MIPS 3302" },
	{ BCMA_CORE_USB11_HOST, "USB 1.1 Host" },
	{ BCMA_CORE_USB11_DEV, "USB 1.1 Device" },
	{ BCMA_CORE_USB20_HOST, "USB 2.0 Host" },
	{ BCMA_CORE_USB20_DEV, "USB 2.0 Device" },
	{ BCMA_CORE_SDIO_HOST, "SDIO Host" },
	{ BCMA_CORE_ROBOSWITCH, "Roboswitch" },
	{ BCMA_CORE_PARA_ATA, "PATA" },
	{ BCMA_CORE_SATA_XORDMA, "SATA XOR-DMA" },
	{ BCMA_CORE_ETHERNET_GBIT, "GBit Ethernet" },
	{ BCMA_CORE_PCIE, "PCIe" },
	{ BCMA_CORE_PHY_N, "PHY N" },
	{ BCMA_CORE_SRAM_CTL, "SRAM Controller" },
	{ BCMA_CORE_MINI_MACPHY, "Mini MACPHY" },
	{ BCMA_CORE_ARM_1176, "ARM 1176" },
	{ BCMA_CORE_ARM_7TDMI, "ARM 7TDMI" },
	{ BCMA_CORE_PHY_LP, "PHY LP" },
	{ BCMA_CORE_PMU, "PMU" },
	{ BCMA_CORE_PHY_SSN, "PHY SSN" },
	{ BCMA_CORE_SDIO_DEV, "SDIO Device" },
	{ BCMA_CORE_ARM_CM3, "ARM CM3" },
	{ BCMA_CORE_PHY_HT, "PHY HT" },
	{ BCMA_CORE_MIPS_74K, "MIPS 74K" },
	{ BCMA_CORE_MAC_GBIT, "GBit MAC" },
	{ BCMA_CORE_DDR12_MEM_CTL, "DDR1/DDR2 Memory Controller" },
	{ BCMA_CORE_PCIE_RC, "PCIe Root Complex" },
	{ BCMA_CORE_OCP_OCP_BRIDGE, "OCP to OCP Bridge" },
	{ BCMA_CORE_SHARED_COMMON, "Common Shared" },
	{ BCMA_CORE_OCP_AHB_BRIDGE, "OCP to AHB Bridge" },
	{ BCMA_CORE_SPI_HOST, "SPI Host" },
	{ BCMA_CORE_I2S, "I2S" },
	{ BCMA_CORE_SDR_DDR1_MEM_CTL, "SDR/DDR1 Memory Controller" },
	{ BCMA_CORE_SHIM, "SHIM" },
	{ BCMA_CORE_DEFAULT, "Default" },
};
const char *bcma_device_name(struct bcma_device_id *id)
{
	int i;

	if (id->manuf == BCMA_MANUF_BCM) {
		for (i = 0; i < ARRAY_SIZE(bcma_device_names); i++) {
			if (bcma_device_names[i].id == id->id)
				return bcma_device_names[i].name;
		}
	}
	return "UNKNOWN";
}

static u32 bcma_scan_read32(struct bcma_bus *bus, u8 current_coreidx,
		       u16 offset)
{
	return readl(bus->mmio + offset);
}

static void bcma_scan_switch_core(struct bcma_bus *bus, u32 addr)
{
	if (bus->hosttype == BCMA_HOSTTYPE_PCI)
		pci_write_config_dword(bus->host_pci, BCMA_PCI_BAR0_WIN,
				       addr);
}

static u32 bcma_erom_get_ent(struct bcma_bus *bus, u32 **eromptr)
{
	u32 ent = readl(*eromptr);
	(*eromptr)++;
	return ent;
}

static void bcma_erom_push_ent(u32 **eromptr)
{
	(*eromptr)--;
}

static s32 bcma_erom_get_ci(struct bcma_bus *bus, u32 **eromptr)
{
	u32 ent = bcma_erom_get_ent(bus, eromptr);
	if (!(ent & SCAN_ER_VALID))
		return -ENOENT;
	if ((ent & SCAN_ER_TAG) != SCAN_ER_TAG_CI)
		return -ENOENT;
	return ent;
}

static bool bcma_erom_is_end(struct bcma_bus *bus, u32 **eromptr)
{
	u32 ent = bcma_erom_get_ent(bus, eromptr);
	bcma_erom_push_ent(eromptr);
	return (ent == (SCAN_ER_TAG_END | SCAN_ER_VALID));
}

static bool bcma_erom_is_bridge(struct bcma_bus *bus, u32 **eromptr)
{
	u32 ent = bcma_erom_get_ent(bus, eromptr);
	bcma_erom_push_ent(eromptr);
	return (((ent & SCAN_ER_VALID)) &&
		((ent & SCAN_ER_TAGX) == SCAN_ER_TAG_ADDR) &&
		((ent & SCAN_ADDR_TYPE) == SCAN_ADDR_TYPE_BRIDGE));
}

static void bcma_erom_skip_component(struct bcma_bus *bus, u32 **eromptr)
{
	u32 ent;
	while (1) {
		ent = bcma_erom_get_ent(bus, eromptr);
		if ((ent & SCAN_ER_VALID) &&
		    ((ent & SCAN_ER_TAG) == SCAN_ER_TAG_CI))
			break;
		if (ent == (SCAN_ER_TAG_END | SCAN_ER_VALID))
			break;
	}
	bcma_erom_push_ent(eromptr);
}

static s32 bcma_erom_get_mst_port(struct bcma_bus *bus, u32 **eromptr)
{
	u32 ent = bcma_erom_get_ent(bus, eromptr);
	if (!(ent & SCAN_ER_VALID))
		return -ENOENT;
	if ((ent & SCAN_ER_TAG) != SCAN_ER_TAG_MP)
		return -ENOENT;
	return ent;
}

static s32 bcma_erom_get_addr_desc(struct bcma_bus *bus, u32 **eromptr,
				  u32 type, u8 port)
{
	u32 addrl, addrh, sizel, sizeh = 0;
	u32 size;

	u32 ent = bcma_erom_get_ent(bus, eromptr);
	if ((!(ent & SCAN_ER_VALID)) ||
	    ((ent & SCAN_ER_TAGX) != SCAN_ER_TAG_ADDR) ||
	    ((ent & SCAN_ADDR_TYPE) != type) ||
	    (((ent & SCAN_ADDR_PORT) >> SCAN_ADDR_PORT_SHIFT) != port)) {
		bcma_erom_push_ent(eromptr);
		return -EINVAL;
	}

	addrl = ent & SCAN_ADDR_ADDR;
	if (ent & SCAN_ADDR_AG32)
		addrh = bcma_erom_get_ent(bus, eromptr);
	else
		addrh = 0;

	if ((ent & SCAN_ADDR_SZ) == SCAN_ADDR_SZ_SZD) {
		size = bcma_erom_get_ent(bus, eromptr);
		sizel = size & SCAN_SIZE_SZ;
		if (size & SCAN_SIZE_SG32)
			sizeh = bcma_erom_get_ent(bus, eromptr);
	} else
		sizel = SCAN_ADDR_SZ_BASE <<
				((ent & SCAN_ADDR_SZ) >> SCAN_ADDR_SZ_SHIFT);

	return addrl;
}

static int bcma_get_next_core(struct bcma_bus *bus, u32 __iomem **eromptr,
			      struct bcma_device *core)
{
	s32 tmp;
	u8 i, j;
	s32 cia, cib;
	u8 ports[2], wrappers[2];

	/* get CIs */
	cia = bcma_erom_get_ci(bus, eromptr);
	if (cia < 0) {
		bcma_erom_push_ent(eromptr);
		if (bcma_erom_is_end(bus, eromptr))
			return -ESPIPE;
		return -EILSEQ;
	}
	cib = bcma_erom_get_ci(bus, eromptr);
	if (cib < 0)
		return -EILSEQ;

	/* parse CIs */
	core->id.class = (cia & SCAN_CIA_CLASS) >> SCAN_CIA_CLASS_SHIFT;
	core->id.id = (cia & SCAN_CIA_ID) >> SCAN_CIA_ID_SHIFT;
	core->id.manuf = (cia & SCAN_CIA_MANUF) >> SCAN_CIA_MANUF_SHIFT;
	ports[0] = (cib & SCAN_CIB_NMP) >> SCAN_CIB_NMP_SHIFT;
	ports[1] = (cib & SCAN_CIB_NSP) >> SCAN_CIB_NSP_SHIFT;
	wrappers[0] = (cib & SCAN_CIB_NMW) >> SCAN_CIB_NMW_SHIFT;
	wrappers[1] = (cib & SCAN_CIB_NSW) >> SCAN_CIB_NSW_SHIFT;
	core->id.rev = (cib & SCAN_CIB_REV) >> SCAN_CIB_REV_SHIFT;

	if (((core->id.manuf == BCMA_MANUF_ARM) &&
	     (core->id.id == 0xFFF)) ||
	    (ports[1] == 0)) {
		bcma_erom_skip_component(bus, eromptr);
		return -ENXIO;
	}

	/* check if component is a core at all */
	if (wrappers[0] + wrappers[1] == 0) {
		/* we could save addrl of the router
		if (cid == BCMA_CORE_OOB_ROUTER)
		 */
		bcma_erom_skip_component(bus, eromptr);
		return -ENXIO;
	}

	if (bcma_erom_is_bridge(bus, eromptr)) {
		bcma_erom_skip_component(bus, eromptr);
		return -ENXIO;
	}

	/* get & parse master ports */
	for (i = 0; i < ports[0]; i++) {
		u32 mst_port_d = bcma_erom_get_mst_port(bus, eromptr);
		if (mst_port_d < 0)
			return -EILSEQ;
	}

	/* get & parse slave ports */
	for (i = 0; i < ports[1]; i++) {
		for (j = 0; ; j++) {
			tmp = bcma_erom_get_addr_desc(bus, eromptr,
				SCAN_ADDR_TYPE_SLAVE, i);
			if (tmp < 0) {
				/* no more entries for port _i_ */
				/* pr_debug("erom: slave port %d "
				 * "has %d descriptors\n", i, j); */
				break;
			} else {
				if (i == 0 && j == 0)
					core->addr = tmp;
			}
		}
	}

	/* get & parse master wrappers */
	for (i = 0; i < wrappers[0]; i++) {
		for (j = 0; ; j++) {
			tmp = bcma_erom_get_addr_desc(bus, eromptr,
				SCAN_ADDR_TYPE_MWRAP, i);
			if (tmp < 0) {
				/* no more entries for port _i_ */
				/* pr_debug("erom: master wrapper %d "
				 * "has %d descriptors\n", i, j); */
				break;
			} else {
				if (i == 0 && j == 0)
					core->wrap = tmp;
			}
		}
	}

	/* get & parse slave wrappers */
	for (i = 0; i < wrappers[1]; i++) {
		u8 hack = (ports[1] == 1) ? 0 : 1;
		for (j = 0; ; j++) {
			tmp = bcma_erom_get_addr_desc(bus, eromptr,
				SCAN_ADDR_TYPE_SWRAP, i + hack);
			if (tmp < 0) {
				/* no more entries for port _i_ */
				/* pr_debug("erom: master wrapper %d "
				 * has %d descriptors\n", i, j); */
				break;
			} else {
				if (wrappers[0] == 0 && !i && !j)
					core->wrap = tmp;
			}
		}
	}
	return 0;
}

static void bcma_init_bus(struct bcma_bus *bus)
{
	s32 tmp;

	INIT_LIST_HEAD(&bus->cores);
	bus->nr_cores = 0;

	bcma_scan_switch_core(bus, BCMA_ADDR_BASE);

	tmp = bcma_scan_read32(bus, 0, BCMA_CC_ID);
	bus->chipinfo.id = (tmp & BCMA_CC_ID_ID) >> BCMA_CC_ID_ID_SHIFT;
	bus->chipinfo.rev = (tmp & BCMA_CC_ID_REV) >> BCMA_CC_ID_REV_SHIFT;
	bus->chipinfo.pkg = (tmp & BCMA_CC_ID_PKG) >> BCMA_CC_ID_PKG_SHIFT;
}

int bcma_bus_scan(struct bcma_bus *bus)
{
	u32 erombase;
	u32 __iomem *eromptr, *eromend;

	int err;

	bcma_init_bus(bus);

	erombase = bcma_scan_read32(bus, 0, BCMA_CC_EROM);
	eromptr = bus->mmio;
	eromend = eromptr + BCMA_CORE_SIZE / sizeof(u32);

	bcma_scan_switch_core(bus, erombase);

	while (eromptr < eromend) {
		struct bcma_device *core = kzalloc(sizeof(*core), GFP_KERNEL);
		if (!core)
			return -ENOMEM;
		INIT_LIST_HEAD(&core->list);
		core->bus = bus;

		err = bcma_get_next_core(bus, &eromptr, core);
		if (err == -ENXIO)
			continue;
		else if (err == -ESPIPE)
			break;
		else if (err < 0)
			return err;

		pr_info("Core %d found: %s "
			"(manuf 0x%03X, id 0x%03X, rev 0x%02X, class 0x%X)\n",
			bus->nr_cores, bcma_device_name(&core->id),
			core->id.manuf, core->id.id, core->id.rev,
			core->id.class);

		core->core_index = bus->nr_cores++;
		list_add(&core->list, &bus->cores);
	}

	return 0;
}
Commit	Line	Data
8369ae33 RM	1	/*
	2	* Broadcom specific AMBA
	3	* Bus scanning
	4	*
	5	* Licensed under the GNU/GPL. See COPYING for details.
	6	*/
	7
	8	#include "scan.h"
	9	#include "bcma_private.h"
	10
	11	#include <linux/bcma/bcma.h>
	12	#include <linux/bcma/bcma_regs.h>
	13	#include <linux/pci.h>
	14	#include <linux/io.h>
	15	#include <linux/dma-mapping.h>
	16	#include <linux/slab.h>
	17
	18	struct bcma_device_id_name {
	19	u16 id;
	20	const char *name;
	21	};
	22	struct bcma_device_id_name bcma_device_names[] = {
	23	{ BCMA_CORE_OOB_ROUTER, "OOB Router" },
	24	{ BCMA_CORE_INVALID, "Invalid" },
	25	{ BCMA_CORE_CHIPCOMMON, "ChipCommon" },
	26	{ BCMA_CORE_ILINE20, "ILine 20" },
	27	{ BCMA_CORE_SRAM, "SRAM" },
	28	{ BCMA_CORE_SDRAM, "SDRAM" },
	29	{ BCMA_CORE_PCI, "PCI" },
	30	{ BCMA_CORE_MIPS, "MIPS" },
	31	{ BCMA_CORE_ETHERNET, "Fast Ethernet" },
	32	{ BCMA_CORE_V90, "V90" },
	33	{ BCMA_CORE_USB11_HOSTDEV, "USB 1.1 Hostdev" },
	34	{ BCMA_CORE_ADSL, "ADSL" },
	35	{ BCMA_CORE_ILINE100, "ILine 100" },
	36	{ BCMA_CORE_IPSEC, "IPSEC" },
	37	{ BCMA_CORE_UTOPIA, "UTOPIA" },
	38	{ BCMA_CORE_PCMCIA, "PCMCIA" },
	39	{ BCMA_CORE_INTERNAL_MEM, "Internal Memory" },
	40	{ BCMA_CORE_MEMC_SDRAM, "MEMC SDRAM" },
	41	{ BCMA_CORE_OFDM, "OFDM" },
	42	{ BCMA_CORE_EXTIF, "EXTIF" },
	43	{ BCMA_CORE_80211, "IEEE 802.11" },
	44	{ BCMA_CORE_PHY_A, "PHY A" },
	45	{ BCMA_CORE_PHY_B, "PHY B" },
	46	{ BCMA_CORE_PHY_G, "PHY G" },
	47	{ BCMA_CORE_MIPS_3302, "MIPS 3302" },
	48	{ BCMA_CORE_USB11_HOST, "USB 1.1 Host" },
	49	{ BCMA_CORE_USB11_DEV, "USB 1.1 Device" },
	50	{ BCMA_CORE_USB20_HOST, "USB 2.0 Host" },
	51	{ BCMA_CORE_USB20_DEV, "USB 2.0 Device" },
	52	{ BCMA_CORE_SDIO_HOST, "SDIO Host" },
	53	{ BCMA_CORE_ROBOSWITCH, "Roboswitch" },
	54	{ BCMA_CORE_PARA_ATA, "PATA" },
	55	{ BCMA_CORE_SATA_XORDMA, "SATA XOR-DMA" },
	56	{ BCMA_CORE_ETHERNET_GBIT, "GBit Ethernet" },
	57	{ BCMA_CORE_PCIE, "PCIe" },
	58	{ BCMA_CORE_PHY_N, "PHY N" },
	59	{ BCMA_CORE_SRAM_CTL, "SRAM Controller" },
	60	{ BCMA_CORE_MINI_MACPHY, "Mini MACPHY" },
	61	{ BCMA_CORE_ARM_1176, "ARM 1176" },
	62	{ BCMA_CORE_ARM_7TDMI, "ARM 7TDMI" },
	63	{ BCMA_CORE_PHY_LP, "PHY LP" },
	64	{ BCMA_CORE_PMU, "PMU" },
65	{ BCMA_CORE_PHY_SSN, "PHY SSN" },
66	{ BCMA_CORE_SDIO_DEV, "SDIO Device" },
67	{ BCMA_CORE_ARM_CM3, "ARM CM3" },
68	{ BCMA_CORE_PHY_HT, "PHY HT" },
69	{ BCMA_CORE_MIPS_74K, "MIPS 74K" },
70	{ BCMA_CORE_MAC_GBIT, "GBit MAC" },
71	{ BCMA_CORE_DDR12_MEM_CTL, "DDR1/DDR2 Memory Controller" },
72	{ BCMA_CORE_PCIE_RC, "PCIe Root Complex" },
73	{ BCMA_CORE_OCP_OCP_BRIDGE, "OCP to OCP Bridge" },
74	{ BCMA_CORE_SHARED_COMMON, "Common Shared" },
75	{ BCMA_CORE_OCP_AHB_BRIDGE, "OCP to AHB Bridge" },
76	{ BCMA_CORE_SPI_HOST, "SPI Host" },
77	{ BCMA_CORE_I2S, "I2S" },
78	{ BCMA_CORE_SDR_DDR1_MEM_CTL, "SDR/DDR1 Memory Controller" },
79	{ BCMA_CORE_SHIM, "SHIM" },
80	{ BCMA_CORE_DEFAULT, "Default" },
81	};
82	const char bcma_device_name(struct bcma_device_id id)
83	{
84	int i;
85
86	if (id->manuf == BCMA_MANUF_BCM) {
87	for (i = 0; i < ARRAY_SIZE(bcma_device_names); i++) {
88	if (bcma_device_names[i].id == id->id)
89	return bcma_device_names[i].name;
90	}
91	}
92	return "UNKNOWN";
93	}
94
95	static u32 bcma_scan_read32(struct bcma_bus *bus, u8 current_coreidx,
96	u16 offset)
97	{
98	return readl(bus->mmio + offset);
99	}
100
101	static void bcma_scan_switch_core(struct bcma_bus *bus, u32 addr)
102	{
103	if (bus->hosttype == BCMA_HOSTTYPE_PCI)
104	pci_write_config_dword(bus->host_pci, BCMA_PCI_BAR0_WIN,
105	addr);
106	}
107
108	static u32 bcma_erom_get_ent(struct bcma_bus bus, u32 *eromptr)
109	{
110	u32 ent = readl(*eromptr);
111	(*eromptr)++;
112	return ent;
113	}
114
115	static void bcma_erom_push_ent(u32 **eromptr)
116	{
117	(*eromptr)--;
118	}
119
120	static s32 bcma_erom_get_ci(struct bcma_bus bus, u32 *eromptr)
121	{
122	u32 ent = bcma_erom_get_ent(bus, eromptr);
123	if (!(ent & SCAN_ER_VALID))
124	return -ENOENT;
125	if ((ent & SCAN_ER_TAG) != SCAN_ER_TAG_CI)
126	return -ENOENT;
127	return ent;
128	}
129
130	static bool bcma_erom_is_end(struct bcma_bus bus, u32 *eromptr)
131	{
132	u32 ent = bcma_erom_get_ent(bus, eromptr);
133	bcma_erom_push_ent(eromptr);
134	return (ent == (SCAN_ER_TAG_END \| SCAN_ER_VALID));
135	}
136
137	static bool bcma_erom_is_bridge(struct bcma_bus bus, u32 *eromptr)
138	{
139	u32 ent = bcma_erom_get_ent(bus, eromptr);
140	bcma_erom_push_ent(eromptr);
141	return (((ent & SCAN_ER_VALID)) &&
142	((ent & SCAN_ER_TAGX) == SCAN_ER_TAG_ADDR) &&
143	((ent & SCAN_ADDR_TYPE) == SCAN_ADDR_TYPE_BRIDGE));
144	}
145
146	static void bcma_erom_skip_component(struct bcma_bus bus, u32 *eromptr)
147	{
148	u32 ent;
149	while (1) {
150	ent = bcma_erom_get_ent(bus, eromptr);
151	if ((ent & SCAN_ER_VALID) &&
152	((ent & SCAN_ER_TAG) == SCAN_ER_TAG_CI))
153	break;
154	if (ent == (SCAN_ER_TAG_END \| SCAN_ER_VALID))
155	break;
156	}
157	bcma_erom_push_ent(eromptr);
158	}
159
160	static s32 bcma_erom_get_mst_port(struct bcma_bus bus, u32 *eromptr)
161	{
162	u32 ent = bcma_erom_get_ent(bus, eromptr);
163	if (!(ent & SCAN_ER_VALID))
164	return -ENOENT;
165	if ((ent & SCAN_ER_TAG) != SCAN_ER_TAG_MP)
166	return -ENOENT;
167	return ent;
168	}
169
170	static s32 bcma_erom_get_addr_desc(struct bcma_bus bus, u32 *eromptr,
171	u32 type, u8 port)
172	{
173	u32 addrl, addrh, sizel, sizeh = 0;
174	u32 size;
175
176	u32 ent = bcma_erom_get_ent(bus, eromptr);
177	if ((!(ent & SCAN_ER_VALID)) \|\|
178	((ent & SCAN_ER_TAGX) != SCAN_ER_TAG_ADDR) \|\|
179	((ent & SCAN_ADDR_TYPE) != type) \|\|
180	(((ent & SCAN_ADDR_PORT) >> SCAN_ADDR_PORT_SHIFT) != port)) {
181	bcma_erom_push_ent(eromptr);
182	return -EINVAL;
183	}
184
185	addrl = ent & SCAN_ADDR_ADDR;
186	if (ent & SCAN_ADDR_AG32)
187	addrh = bcma_erom_get_ent(bus, eromptr);
188	else
189	addrh = 0;
190
191	if ((ent & SCAN_ADDR_SZ) == SCAN_ADDR_SZ_SZD) {
192	size = bcma_erom_get_ent(bus, eromptr);
193	sizel = size & SCAN_SIZE_SZ;
194	if (size & SCAN_SIZE_SG32)
195	sizeh = bcma_erom_get_ent(bus, eromptr);
196	} else
197	sizel = SCAN_ADDR_SZ_BASE <<
198	((ent & SCAN_ADDR_SZ) >> SCAN_ADDR_SZ_SHIFT);
199
200	return addrl;
201	}
202
982eee67 HM	203	static int bcma_get_next_core(struct bcma_bus bus, u32 __iomem *eromptr,
	204	struct bcma_device *core)
	205	{
	206	s32 tmp;
	207	u8 i, j;
	208	s32 cia, cib;
	209	u8 ports[2], wrappers[2];
	210
	211	/* get CIs */
	212	cia = bcma_erom_get_ci(bus, eromptr);
	213	if (cia < 0) {
	214	bcma_erom_push_ent(eromptr);
	215	if (bcma_erom_is_end(bus, eromptr))
	216	return -ESPIPE;
	217	return -EILSEQ;
	218	}
	219	cib = bcma_erom_get_ci(bus, eromptr);
	220	if (cib < 0)
	221	return -EILSEQ;
	222
	223	/* parse CIs */
	224	core->id.class = (cia & SCAN_CIA_CLASS) >> SCAN_CIA_CLASS_SHIFT;
	225	core->id.id = (cia & SCAN_CIA_ID) >> SCAN_CIA_ID_SHIFT;
	226	core->id.manuf = (cia & SCAN_CIA_MANUF) >> SCAN_CIA_MANUF_SHIFT;
	227	ports[0] = (cib & SCAN_CIB_NMP) >> SCAN_CIB_NMP_SHIFT;
	228	ports[1] = (cib & SCAN_CIB_NSP) >> SCAN_CIB_NSP_SHIFT;
	229	wrappers[0] = (cib & SCAN_CIB_NMW) >> SCAN_CIB_NMW_SHIFT;
	230	wrappers[1] = (cib & SCAN_CIB_NSW) >> SCAN_CIB_NSW_SHIFT;
	231	core->id.rev = (cib & SCAN_CIB_REV) >> SCAN_CIB_REV_SHIFT;
	232
	233	if (((core->id.manuf == BCMA_MANUF_ARM) &&
	234	(core->id.id == 0xFFF)) \|\|
	235	(ports[1] == 0)) {
	236	bcma_erom_skip_component(bus, eromptr);
	237	return -ENXIO;
	238	}
	239
	240	/* check if component is a core at all */
	241	if (wrappers[0] + wrappers[1] == 0) {
	242	/* we could save addrl of the router
	243	if (cid == BCMA_CORE_OOB_ROUTER)
	244	*/
	245	bcma_erom_skip_component(bus, eromptr);
	246	return -ENXIO;
	247	}
	248
	249	if (bcma_erom_is_bridge(bus, eromptr)) {
	250	bcma_erom_skip_component(bus, eromptr);
	251	return -ENXIO;
	252	}
	253
	254	/* get & parse master ports */
	255	for (i = 0; i < ports[0]; i++) {
	256	u32 mst_port_d = bcma_erom_get_mst_port(bus, eromptr);
	257	if (mst_port_d < 0)
	258	return -EILSEQ;
	259	}
	260
	261	/* get & parse slave ports */
	262	for (i = 0; i < ports[1]; i++) {
	263	for (j = 0; ; j++) {
	264	tmp = bcma_erom_get_addr_desc(bus, eromptr,
	265	SCAN_ADDR_TYPE_SLAVE, i);
	266	if (tmp < 0) {
267	/* no more entries for port _i_ */
268	/* pr_debug("erom: slave port %d "
269	* "has %d descriptors\n", i, j); */
270	break;
271	} else {
272	if (i == 0 && j == 0)
273	core->addr = tmp;
274	}
275	}
276	}
277
278	/* get & parse master wrappers */
279	for (i = 0; i < wrappers[0]; i++) {
280	for (j = 0; ; j++) {
281	tmp = bcma_erom_get_addr_desc(bus, eromptr,
282	SCAN_ADDR_TYPE_MWRAP, i);
283	if (tmp < 0) {
284	/* no more entries for port _i_ */
285	/* pr_debug("erom: master wrapper %d "
286	* "has %d descriptors\n", i, j); */
287	break;
288	} else {
289	if (i == 0 && j == 0)
290	core->wrap = tmp;
291	}
292	}
293	}
294
295	/* get & parse slave wrappers */
296	for (i = 0; i < wrappers[1]; i++) {
297	u8 hack = (ports[1] == 1) ? 0 : 1;
298	for (j = 0; ; j++) {
299	tmp = bcma_erom_get_addr_desc(bus, eromptr,
300	SCAN_ADDR_TYPE_SWRAP, i + hack);
301	if (tmp < 0) {
302	/* no more entries for port _i_ */
303	/* pr_debug("erom: master wrapper %d "
304	* has %d descriptors\n", i, j); */
305	break;
306	} else {
307	if (wrappers[0] == 0 && !i && !j)
308	core->wrap = tmp;
309	}
310	}
311	}
312	return 0;
313	}
314
67a5c29e	315	static void bcma_init_bus(struct bcma_bus *bus)
8369ae33	316	{
8369ae33	317	s32 tmp;
8369ae33	318
8369ae33 RM	319	INIT_LIST_HEAD(&bus->cores);
	320	bus->nr_cores = 0;
	321
	322	bcma_scan_switch_core(bus, BCMA_ADDR_BASE);
	323
	324	tmp = bcma_scan_read32(bus, 0, BCMA_CC_ID);
	325	bus->chipinfo.id = (tmp & BCMA_CC_ID_ID) >> BCMA_CC_ID_ID_SHIFT;
	326	bus->chipinfo.rev = (tmp & BCMA_CC_ID_REV) >> BCMA_CC_ID_REV_SHIFT;
	327	bus->chipinfo.pkg = (tmp & BCMA_CC_ID_PKG) >> BCMA_CC_ID_PKG_SHIFT;
67a5c29e HM	328	}
	329
	330	int bcma_bus_scan(struct bcma_bus *bus)
	331	{
	332	u32 erombase;
	333	u32 __iomem eromptr, eromend;
	334
	335	int err;
	336
	337	bcma_init_bus(bus);
8369ae33 RM	338
	339	erombase = bcma_scan_read32(bus, 0, BCMA_CC_EROM);
	340	eromptr = bus->mmio;
	341	eromend = eromptr + BCMA_CORE_SIZE / sizeof(u32);
	342
	343	bcma_scan_switch_core(bus, erombase);
	344
	345	while (eromptr < eromend) {
	346	struct bcma_device core = kzalloc(sizeof(core), GFP_KERNEL);
	347	if (!core)
	348	return -ENOMEM;
	349	INIT_LIST_HEAD(&core->list);
	350	core->bus = bus;
	351
982eee67 HM	352	err = bcma_get_next_core(bus, &eromptr, core);
982eee67 HM	353	if (err == -ENXIO)
8369ae33	354	continue;
982eee67 HM	355	else if (err == -ESPIPE)
	356	break;
	357	else if (err < 0)
	358	return err;
8369ae33 RM	359
	360	pr_info("Core %d found: %s "
	361	"(manuf 0x%03X, id 0x%03X, rev 0x%02X, class 0x%X)\n",
	362	bus->nr_cores, bcma_device_name(&core->id),
	363	core->id.manuf, core->id.id, core->id.rev,
	364	core->id.class);
	365
	366	core->core_index = bus->nr_cores++;
	367	list_add(&core->list, &bus->cores);
8369ae33 RM	368	}
	369
	370	return 0;
	371	}