Commit | Line | Data |
---|---|---|
8369ae33 RM |
1 | /* |
2 | * Broadcom specific AMBA | |
3 | * PCI Core | |
4 | * | |
49dc9577 | 5 | * Copyright 2005, 2011, Broadcom Corporation |
eb032b98 | 6 | * Copyright 2006, 2007, Michael Buesch <m@bues.ch> |
2be25cac | 7 | * Copyright 2011, 2012, Hauke Mehrtens <hauke@hauke-m.de> |
8369ae33 RM |
8 | * |
9 | * Licensed under the GNU/GPL. See COPYING for details. | |
10 | */ | |
11 | ||
12 | #include "bcma_private.h" | |
44a8e377 | 13 | #include <linux/export.h> |
8369ae33 RM |
14 | #include <linux/bcma/bcma.h> |
15 | ||
16 | /************************************************** | |
17 | * R/W ops. | |
18 | **************************************************/ | |
19 | ||
4b259a5c | 20 | u32 bcma_pcie_read(struct bcma_drv_pci *pc, u32 address) |
8369ae33 | 21 | { |
2be25cac HM |
22 | pcicore_write32(pc, BCMA_CORE_PCI_PCIEIND_ADDR, address); |
23 | pcicore_read32(pc, BCMA_CORE_PCI_PCIEIND_ADDR); | |
24 | return pcicore_read32(pc, BCMA_CORE_PCI_PCIEIND_DATA); | |
8369ae33 RM |
25 | } |
26 | ||
8369ae33 RM |
27 | static void bcma_pcie_write(struct bcma_drv_pci *pc, u32 address, u32 data) |
28 | { | |
2be25cac HM |
29 | pcicore_write32(pc, BCMA_CORE_PCI_PCIEIND_ADDR, address); |
30 | pcicore_read32(pc, BCMA_CORE_PCI_PCIEIND_ADDR); | |
31 | pcicore_write32(pc, BCMA_CORE_PCI_PCIEIND_DATA, data); | |
8369ae33 | 32 | } |
8369ae33 RM |
33 | |
34 | static void bcma_pcie_mdio_set_phy(struct bcma_drv_pci *pc, u8 phy) | |
35 | { | |
8369ae33 RM |
36 | u32 v; |
37 | int i; | |
38 | ||
2be25cac HM |
39 | v = BCMA_CORE_PCI_MDIODATA_START; |
40 | v |= BCMA_CORE_PCI_MDIODATA_WRITE; | |
41 | v |= (BCMA_CORE_PCI_MDIODATA_DEV_ADDR << | |
42 | BCMA_CORE_PCI_MDIODATA_DEVADDR_SHF); | |
43 | v |= (BCMA_CORE_PCI_MDIODATA_BLK_ADDR << | |
44 | BCMA_CORE_PCI_MDIODATA_REGADDR_SHF); | |
45 | v |= BCMA_CORE_PCI_MDIODATA_TA; | |
8369ae33 | 46 | v |= (phy << 4); |
2be25cac | 47 | pcicore_write32(pc, BCMA_CORE_PCI_MDIO_DATA, v); |
8369ae33 RM |
48 | |
49 | udelay(10); | |
50 | for (i = 0; i < 200; i++) { | |
2be25cac HM |
51 | v = pcicore_read32(pc, BCMA_CORE_PCI_MDIO_CONTROL); |
52 | if (v & BCMA_CORE_PCI_MDIOCTL_ACCESS_DONE) | |
8369ae33 RM |
53 | break; |
54 | msleep(1); | |
55 | } | |
56 | } | |
57 | ||
58 | static u16 bcma_pcie_mdio_read(struct bcma_drv_pci *pc, u8 device, u8 address) | |
59 | { | |
8369ae33 RM |
60 | int max_retries = 10; |
61 | u16 ret = 0; | |
62 | u32 v; | |
63 | int i; | |
64 | ||
2be25cac HM |
65 | /* enable mdio access to SERDES */ |
66 | v = BCMA_CORE_PCI_MDIOCTL_PREAM_EN; | |
67 | v |= BCMA_CORE_PCI_MDIOCTL_DIVISOR_VAL; | |
68 | pcicore_write32(pc, BCMA_CORE_PCI_MDIO_CONTROL, v); | |
8369ae33 RM |
69 | |
70 | if (pc->core->id.rev >= 10) { | |
71 | max_retries = 200; | |
72 | bcma_pcie_mdio_set_phy(pc, device); | |
2be25cac HM |
73 | v = (BCMA_CORE_PCI_MDIODATA_DEV_ADDR << |
74 | BCMA_CORE_PCI_MDIODATA_DEVADDR_SHF); | |
75 | v |= (address << BCMA_CORE_PCI_MDIODATA_REGADDR_SHF); | |
76 | } else { | |
77 | v = (device << BCMA_CORE_PCI_MDIODATA_DEVADDR_SHF_OLD); | |
78 | v |= (address << BCMA_CORE_PCI_MDIODATA_REGADDR_SHF_OLD); | |
8369ae33 RM |
79 | } |
80 | ||
2be25cac HM |
81 | v = BCMA_CORE_PCI_MDIODATA_START; |
82 | v |= BCMA_CORE_PCI_MDIODATA_READ; | |
83 | v |= BCMA_CORE_PCI_MDIODATA_TA; | |
84 | ||
85 | pcicore_write32(pc, BCMA_CORE_PCI_MDIO_DATA, v); | |
8369ae33 RM |
86 | /* Wait for the device to complete the transaction */ |
87 | udelay(10); | |
f1a9c1e6 | 88 | for (i = 0; i < max_retries; i++) { |
2be25cac HM |
89 | v = pcicore_read32(pc, BCMA_CORE_PCI_MDIO_CONTROL); |
90 | if (v & BCMA_CORE_PCI_MDIOCTL_ACCESS_DONE) { | |
8369ae33 | 91 | udelay(10); |
2be25cac | 92 | ret = pcicore_read32(pc, BCMA_CORE_PCI_MDIO_DATA); |
8369ae33 RM |
93 | break; |
94 | } | |
95 | msleep(1); | |
96 | } | |
2be25cac | 97 | pcicore_write32(pc, BCMA_CORE_PCI_MDIO_CONTROL, 0); |
8369ae33 RM |
98 | return ret; |
99 | } | |
100 | ||
101 | static void bcma_pcie_mdio_write(struct bcma_drv_pci *pc, u8 device, | |
102 | u8 address, u16 data) | |
103 | { | |
8369ae33 RM |
104 | int max_retries = 10; |
105 | u32 v; | |
106 | int i; | |
107 | ||
2be25cac HM |
108 | /* enable mdio access to SERDES */ |
109 | v = BCMA_CORE_PCI_MDIOCTL_PREAM_EN; | |
110 | v |= BCMA_CORE_PCI_MDIOCTL_DIVISOR_VAL; | |
111 | pcicore_write32(pc, BCMA_CORE_PCI_MDIO_CONTROL, v); | |
8369ae33 RM |
112 | |
113 | if (pc->core->id.rev >= 10) { | |
114 | max_retries = 200; | |
115 | bcma_pcie_mdio_set_phy(pc, device); | |
2be25cac HM |
116 | v = (BCMA_CORE_PCI_MDIODATA_DEV_ADDR << |
117 | BCMA_CORE_PCI_MDIODATA_DEVADDR_SHF); | |
118 | v |= (address << BCMA_CORE_PCI_MDIODATA_REGADDR_SHF); | |
119 | } else { | |
120 | v = (device << BCMA_CORE_PCI_MDIODATA_DEVADDR_SHF_OLD); | |
121 | v |= (address << BCMA_CORE_PCI_MDIODATA_REGADDR_SHF_OLD); | |
8369ae33 RM |
122 | } |
123 | ||
2be25cac HM |
124 | v = BCMA_CORE_PCI_MDIODATA_START; |
125 | v |= BCMA_CORE_PCI_MDIODATA_WRITE; | |
126 | v |= BCMA_CORE_PCI_MDIODATA_TA; | |
8369ae33 | 127 | v |= data; |
2be25cac | 128 | pcicore_write32(pc, BCMA_CORE_PCI_MDIO_DATA, v); |
8369ae33 RM |
129 | /* Wait for the device to complete the transaction */ |
130 | udelay(10); | |
131 | for (i = 0; i < max_retries; i++) { | |
2be25cac HM |
132 | v = pcicore_read32(pc, BCMA_CORE_PCI_MDIO_CONTROL); |
133 | if (v & BCMA_CORE_PCI_MDIOCTL_ACCESS_DONE) | |
8369ae33 RM |
134 | break; |
135 | msleep(1); | |
136 | } | |
2be25cac | 137 | pcicore_write32(pc, BCMA_CORE_PCI_MDIO_CONTROL, 0); |
8369ae33 RM |
138 | } |
139 | ||
140 | /************************************************** | |
141 | * Workarounds. | |
142 | **************************************************/ | |
143 | ||
144 | static u8 bcma_pcicore_polarity_workaround(struct bcma_drv_pci *pc) | |
145 | { | |
2be25cac HM |
146 | u32 tmp; |
147 | ||
148 | tmp = bcma_pcie_read(pc, BCMA_CORE_PCI_PLP_STATUSREG); | |
149 | if (tmp & BCMA_CORE_PCI_PLP_POLARITYINV_STAT) | |
150 | return BCMA_CORE_PCI_SERDES_RX_CTRL_FORCE | | |
151 | BCMA_CORE_PCI_SERDES_RX_CTRL_POLARITY; | |
152 | else | |
153 | return BCMA_CORE_PCI_SERDES_RX_CTRL_FORCE; | |
8369ae33 RM |
154 | } |
155 | ||
156 | static void bcma_pcicore_serdes_workaround(struct bcma_drv_pci *pc) | |
157 | { | |
8369ae33 RM |
158 | u16 tmp; |
159 | ||
2be25cac HM |
160 | bcma_pcie_mdio_write(pc, BCMA_CORE_PCI_MDIODATA_DEV_RX, |
161 | BCMA_CORE_PCI_SERDES_RX_CTRL, | |
162 | bcma_pcicore_polarity_workaround(pc)); | |
163 | tmp = bcma_pcie_mdio_read(pc, BCMA_CORE_PCI_MDIODATA_DEV_PLL, | |
164 | BCMA_CORE_PCI_SERDES_PLL_CTRL); | |
165 | if (tmp & BCMA_CORE_PCI_PLL_CTRL_FREQDET_EN) | |
166 | bcma_pcie_mdio_write(pc, BCMA_CORE_PCI_MDIODATA_DEV_PLL, | |
167 | BCMA_CORE_PCI_SERDES_PLL_CTRL, | |
168 | tmp & ~BCMA_CORE_PCI_PLL_CTRL_FREQDET_EN); | |
8369ae33 RM |
169 | } |
170 | ||
ec00f373 HM |
171 | static void bcma_core_pci_fixcfg(struct bcma_drv_pci *pc) |
172 | { | |
173 | struct bcma_device *core = pc->core; | |
174 | u16 val16, core_index; | |
175 | uint regoff; | |
176 | ||
177 | regoff = BCMA_CORE_PCI_SPROM(BCMA_CORE_PCI_SPROM_PI_OFFSET); | |
178 | core_index = (u16)core->core_index; | |
179 | ||
180 | val16 = pcicore_read16(pc, regoff); | |
181 | if (((val16 & BCMA_CORE_PCI_SPROM_PI_MASK) >> BCMA_CORE_PCI_SPROM_PI_SHIFT) | |
182 | != core_index) { | |
183 | val16 = (core_index << BCMA_CORE_PCI_SPROM_PI_SHIFT) | | |
184 | (val16 & ~BCMA_CORE_PCI_SPROM_PI_MASK); | |
185 | pcicore_write16(pc, regoff, val16); | |
186 | } | |
187 | } | |
188 | ||
8369ae33 RM |
189 | /************************************************** |
190 | * Init. | |
191 | **************************************************/ | |
192 | ||
d1a7a8e1 | 193 | static void __devinit bcma_core_pci_clientmode_init(struct bcma_drv_pci *pc) |
8369ae33 | 194 | { |
ec00f373 | 195 | bcma_core_pci_fixcfg(pc); |
8369ae33 RM |
196 | bcma_pcicore_serdes_workaround(pc); |
197 | } | |
1de520f4 | 198 | |
d1a7a8e1 | 199 | void __devinit bcma_core_pci_init(struct bcma_drv_pci *pc) |
9352f69c | 200 | { |
517f43e5 HM |
201 | if (pc->setup_done) |
202 | return; | |
203 | ||
9352f69c | 204 | #ifdef CONFIG_BCMA_DRIVER_PCI_HOSTMODE |
49dc9577 HM |
205 | pc->hostmode = bcma_core_pci_is_in_hostmode(pc); |
206 | if (pc->hostmode) | |
9352f69c | 207 | bcma_core_pci_hostmode_init(pc); |
9352f69c | 208 | #endif /* CONFIG_BCMA_DRIVER_PCI_HOSTMODE */ |
517f43e5 | 209 | |
49dc9577 HM |
210 | if (!pc->hostmode) |
211 | bcma_core_pci_clientmode_init(pc); | |
9352f69c RM |
212 | } |
213 | ||
1de520f4 RM |
214 | int bcma_core_pci_irq_ctl(struct bcma_drv_pci *pc, struct bcma_device *core, |
215 | bool enable) | |
216 | { | |
217 | struct pci_dev *pdev = pc->core->bus->host_pci; | |
218 | u32 coremask, tmp; | |
ecd177c2 HM |
219 | int err = 0; |
220 | ||
221 | if (core->bus->hosttype != BCMA_HOSTTYPE_PCI) { | |
222 | /* This bcma device is not on a PCI host-bus. So the IRQs are | |
223 | * not routed through the PCI core. | |
224 | * So we must not enable routing through the PCI core. */ | |
225 | goto out; | |
226 | } | |
1de520f4 RM |
227 | |
228 | err = pci_read_config_dword(pdev, BCMA_PCI_IRQMASK, &tmp); | |
229 | if (err) | |
230 | goto out; | |
231 | ||
232 | coremask = BIT(core->core_index) << 8; | |
233 | if (enable) | |
234 | tmp |= coremask; | |
235 | else | |
236 | tmp &= ~coremask; | |
237 | ||
238 | err = pci_write_config_dword(pdev, BCMA_PCI_IRQMASK, tmp); | |
239 | ||
240 | out: | |
241 | return err; | |
242 | } | |
440ca98f | 243 | EXPORT_SYMBOL_GPL(bcma_core_pci_irq_ctl); |
29f6b3d8 HM |
244 | |
245 | void bcma_core_pci_extend_L1timer(struct bcma_drv_pci *pc, bool extend) | |
246 | { | |
247 | u32 w; | |
248 | ||
249 | w = bcma_pcie_read(pc, BCMA_CORE_PCI_DLLP_PMTHRESHREG); | |
250 | if (extend) | |
251 | w |= BCMA_CORE_PCI_ASPMTIMER_EXTEND; | |
252 | else | |
253 | w &= ~BCMA_CORE_PCI_ASPMTIMER_EXTEND; | |
254 | bcma_pcie_write(pc, BCMA_CORE_PCI_DLLP_PMTHRESHREG, w); | |
255 | bcma_pcie_read(pc, BCMA_CORE_PCI_DLLP_PMTHRESHREG); | |
256 | } | |
257 | EXPORT_SYMBOL_GPL(bcma_core_pci_extend_L1timer); |