Commit | Line | Data |
---|---|---|
8369ae33 RM |
1 | /* |
2 | * Broadcom specific AMBA | |
3 | * PCI Core | |
4 | * | |
5 | * Copyright 2005, Broadcom Corporation | |
eb032b98 | 6 | * Copyright 2006, 2007, Michael Buesch <m@bues.ch> |
2be25cac | 7 | * Copyright 2011, 2012, Hauke Mehrtens <hauke@hauke-m.de> |
8369ae33 RM |
8 | * |
9 | * Licensed under the GNU/GPL. See COPYING for details. | |
10 | */ | |
11 | ||
12 | #include "bcma_private.h" | |
44a8e377 | 13 | #include <linux/export.h> |
8369ae33 RM |
14 | #include <linux/bcma/bcma.h> |
15 | ||
16 | /************************************************** | |
17 | * R/W ops. | |
18 | **************************************************/ | |
19 | ||
4b259a5c | 20 | u32 bcma_pcie_read(struct bcma_drv_pci *pc, u32 address) |
8369ae33 | 21 | { |
2be25cac HM |
22 | pcicore_write32(pc, BCMA_CORE_PCI_PCIEIND_ADDR, address); |
23 | pcicore_read32(pc, BCMA_CORE_PCI_PCIEIND_ADDR); | |
24 | return pcicore_read32(pc, BCMA_CORE_PCI_PCIEIND_DATA); | |
8369ae33 RM |
25 | } |
26 | ||
27 | #if 0 | |
28 | static void bcma_pcie_write(struct bcma_drv_pci *pc, u32 address, u32 data) | |
29 | { | |
2be25cac HM |
30 | pcicore_write32(pc, BCMA_CORE_PCI_PCIEIND_ADDR, address); |
31 | pcicore_read32(pc, BCMA_CORE_PCI_PCIEIND_ADDR); | |
32 | pcicore_write32(pc, BCMA_CORE_PCI_PCIEIND_DATA, data); | |
8369ae33 RM |
33 | } |
34 | #endif | |
35 | ||
36 | static void bcma_pcie_mdio_set_phy(struct bcma_drv_pci *pc, u8 phy) | |
37 | { | |
8369ae33 RM |
38 | u32 v; |
39 | int i; | |
40 | ||
2be25cac HM |
41 | v = BCMA_CORE_PCI_MDIODATA_START; |
42 | v |= BCMA_CORE_PCI_MDIODATA_WRITE; | |
43 | v |= (BCMA_CORE_PCI_MDIODATA_DEV_ADDR << | |
44 | BCMA_CORE_PCI_MDIODATA_DEVADDR_SHF); | |
45 | v |= (BCMA_CORE_PCI_MDIODATA_BLK_ADDR << | |
46 | BCMA_CORE_PCI_MDIODATA_REGADDR_SHF); | |
47 | v |= BCMA_CORE_PCI_MDIODATA_TA; | |
8369ae33 | 48 | v |= (phy << 4); |
2be25cac | 49 | pcicore_write32(pc, BCMA_CORE_PCI_MDIO_DATA, v); |
8369ae33 RM |
50 | |
51 | udelay(10); | |
52 | for (i = 0; i < 200; i++) { | |
2be25cac HM |
53 | v = pcicore_read32(pc, BCMA_CORE_PCI_MDIO_CONTROL); |
54 | if (v & BCMA_CORE_PCI_MDIOCTL_ACCESS_DONE) | |
8369ae33 RM |
55 | break; |
56 | msleep(1); | |
57 | } | |
58 | } | |
59 | ||
60 | static u16 bcma_pcie_mdio_read(struct bcma_drv_pci *pc, u8 device, u8 address) | |
61 | { | |
8369ae33 RM |
62 | int max_retries = 10; |
63 | u16 ret = 0; | |
64 | u32 v; | |
65 | int i; | |
66 | ||
2be25cac HM |
67 | /* enable mdio access to SERDES */ |
68 | v = BCMA_CORE_PCI_MDIOCTL_PREAM_EN; | |
69 | v |= BCMA_CORE_PCI_MDIOCTL_DIVISOR_VAL; | |
70 | pcicore_write32(pc, BCMA_CORE_PCI_MDIO_CONTROL, v); | |
8369ae33 RM |
71 | |
72 | if (pc->core->id.rev >= 10) { | |
73 | max_retries = 200; | |
74 | bcma_pcie_mdio_set_phy(pc, device); | |
2be25cac HM |
75 | v = (BCMA_CORE_PCI_MDIODATA_DEV_ADDR << |
76 | BCMA_CORE_PCI_MDIODATA_DEVADDR_SHF); | |
77 | v |= (address << BCMA_CORE_PCI_MDIODATA_REGADDR_SHF); | |
78 | } else { | |
79 | v = (device << BCMA_CORE_PCI_MDIODATA_DEVADDR_SHF_OLD); | |
80 | v |= (address << BCMA_CORE_PCI_MDIODATA_REGADDR_SHF_OLD); | |
8369ae33 RM |
81 | } |
82 | ||
2be25cac HM |
83 | v = BCMA_CORE_PCI_MDIODATA_START; |
84 | v |= BCMA_CORE_PCI_MDIODATA_READ; | |
85 | v |= BCMA_CORE_PCI_MDIODATA_TA; | |
86 | ||
87 | pcicore_write32(pc, BCMA_CORE_PCI_MDIO_DATA, v); | |
8369ae33 RM |
88 | /* Wait for the device to complete the transaction */ |
89 | udelay(10); | |
f1a9c1e6 | 90 | for (i = 0; i < max_retries; i++) { |
2be25cac HM |
91 | v = pcicore_read32(pc, BCMA_CORE_PCI_MDIO_CONTROL); |
92 | if (v & BCMA_CORE_PCI_MDIOCTL_ACCESS_DONE) { | |
8369ae33 | 93 | udelay(10); |
2be25cac | 94 | ret = pcicore_read32(pc, BCMA_CORE_PCI_MDIO_DATA); |
8369ae33 RM |
95 | break; |
96 | } | |
97 | msleep(1); | |
98 | } | |
2be25cac | 99 | pcicore_write32(pc, BCMA_CORE_PCI_MDIO_CONTROL, 0); |
8369ae33 RM |
100 | return ret; |
101 | } | |
102 | ||
103 | static void bcma_pcie_mdio_write(struct bcma_drv_pci *pc, u8 device, | |
104 | u8 address, u16 data) | |
105 | { | |
8369ae33 RM |
106 | int max_retries = 10; |
107 | u32 v; | |
108 | int i; | |
109 | ||
2be25cac HM |
110 | /* enable mdio access to SERDES */ |
111 | v = BCMA_CORE_PCI_MDIOCTL_PREAM_EN; | |
112 | v |= BCMA_CORE_PCI_MDIOCTL_DIVISOR_VAL; | |
113 | pcicore_write32(pc, BCMA_CORE_PCI_MDIO_CONTROL, v); | |
8369ae33 RM |
114 | |
115 | if (pc->core->id.rev >= 10) { | |
116 | max_retries = 200; | |
117 | bcma_pcie_mdio_set_phy(pc, device); | |
2be25cac HM |
118 | v = (BCMA_CORE_PCI_MDIODATA_DEV_ADDR << |
119 | BCMA_CORE_PCI_MDIODATA_DEVADDR_SHF); | |
120 | v |= (address << BCMA_CORE_PCI_MDIODATA_REGADDR_SHF); | |
121 | } else { | |
122 | v = (device << BCMA_CORE_PCI_MDIODATA_DEVADDR_SHF_OLD); | |
123 | v |= (address << BCMA_CORE_PCI_MDIODATA_REGADDR_SHF_OLD); | |
8369ae33 RM |
124 | } |
125 | ||
2be25cac HM |
126 | v = BCMA_CORE_PCI_MDIODATA_START; |
127 | v |= BCMA_CORE_PCI_MDIODATA_WRITE; | |
128 | v |= BCMA_CORE_PCI_MDIODATA_TA; | |
8369ae33 | 129 | v |= data; |
2be25cac | 130 | pcicore_write32(pc, BCMA_CORE_PCI_MDIO_DATA, v); |
8369ae33 RM |
131 | /* Wait for the device to complete the transaction */ |
132 | udelay(10); | |
133 | for (i = 0; i < max_retries; i++) { | |
2be25cac HM |
134 | v = pcicore_read32(pc, BCMA_CORE_PCI_MDIO_CONTROL); |
135 | if (v & BCMA_CORE_PCI_MDIOCTL_ACCESS_DONE) | |
8369ae33 RM |
136 | break; |
137 | msleep(1); | |
138 | } | |
2be25cac | 139 | pcicore_write32(pc, BCMA_CORE_PCI_MDIO_CONTROL, 0); |
8369ae33 RM |
140 | } |
141 | ||
142 | /************************************************** | |
143 | * Workarounds. | |
144 | **************************************************/ | |
145 | ||
146 | static u8 bcma_pcicore_polarity_workaround(struct bcma_drv_pci *pc) | |
147 | { | |
2be25cac HM |
148 | u32 tmp; |
149 | ||
150 | tmp = bcma_pcie_read(pc, BCMA_CORE_PCI_PLP_STATUSREG); | |
151 | if (tmp & BCMA_CORE_PCI_PLP_POLARITYINV_STAT) | |
152 | return BCMA_CORE_PCI_SERDES_RX_CTRL_FORCE | | |
153 | BCMA_CORE_PCI_SERDES_RX_CTRL_POLARITY; | |
154 | else | |
155 | return BCMA_CORE_PCI_SERDES_RX_CTRL_FORCE; | |
8369ae33 RM |
156 | } |
157 | ||
158 | static void bcma_pcicore_serdes_workaround(struct bcma_drv_pci *pc) | |
159 | { | |
8369ae33 RM |
160 | u16 tmp; |
161 | ||
2be25cac HM |
162 | bcma_pcie_mdio_write(pc, BCMA_CORE_PCI_MDIODATA_DEV_RX, |
163 | BCMA_CORE_PCI_SERDES_RX_CTRL, | |
164 | bcma_pcicore_polarity_workaround(pc)); | |
165 | tmp = bcma_pcie_mdio_read(pc, BCMA_CORE_PCI_MDIODATA_DEV_PLL, | |
166 | BCMA_CORE_PCI_SERDES_PLL_CTRL); | |
167 | if (tmp & BCMA_CORE_PCI_PLL_CTRL_FREQDET_EN) | |
168 | bcma_pcie_mdio_write(pc, BCMA_CORE_PCI_MDIODATA_DEV_PLL, | |
169 | BCMA_CORE_PCI_SERDES_PLL_CTRL, | |
170 | tmp & ~BCMA_CORE_PCI_PLL_CTRL_FREQDET_EN); | |
8369ae33 RM |
171 | } |
172 | ||
173 | /************************************************** | |
174 | * Init. | |
175 | **************************************************/ | |
176 | ||
d1a7a8e1 | 177 | static void __devinit bcma_core_pci_clientmode_init(struct bcma_drv_pci *pc) |
8369ae33 RM |
178 | { |
179 | bcma_pcicore_serdes_workaround(pc); | |
180 | } | |
1de520f4 | 181 | |
d1a7a8e1 | 182 | static bool __devinit bcma_core_pci_is_in_hostmode(struct bcma_drv_pci *pc) |
9352f69c RM |
183 | { |
184 | struct bcma_bus *bus = pc->core->bus; | |
185 | u16 chipid_top; | |
186 | ||
187 | chipid_top = (bus->chipinfo.id & 0xFF00); | |
188 | if (chipid_top != 0x4700 && | |
189 | chipid_top != 0x5300) | |
190 | return false; | |
191 | ||
6e6e8c51 | 192 | #ifdef CONFIG_SSB_DRIVER_PCICORE |
26f2622e | 193 | if (bus->sprom.boardflags_lo & SSB_BFL_NOPCI) |
9352f69c | 194 | return false; |
6e6e8c51 | 195 | #endif /* CONFIG_SSB_DRIVER_PCICORE */ |
9352f69c RM |
196 | |
197 | #if 0 | |
198 | /* TODO: on BCMA we use address from EROM instead of magic formula */ | |
199 | u32 tmp; | |
200 | return !mips_busprobe32(tmp, (bus->mmio + | |
201 | (pc->core->core_index * BCMA_CORE_SIZE))); | |
202 | #endif | |
203 | ||
204 | return true; | |
205 | } | |
206 | ||
d1a7a8e1 | 207 | void __devinit bcma_core_pci_init(struct bcma_drv_pci *pc) |
9352f69c | 208 | { |
517f43e5 HM |
209 | if (pc->setup_done) |
210 | return; | |
211 | ||
9352f69c RM |
212 | if (bcma_core_pci_is_in_hostmode(pc)) { |
213 | #ifdef CONFIG_BCMA_DRIVER_PCI_HOSTMODE | |
214 | bcma_core_pci_hostmode_init(pc); | |
215 | #else | |
216 | pr_err("Driver compiled without support for hostmode PCI\n"); | |
217 | #endif /* CONFIG_BCMA_DRIVER_PCI_HOSTMODE */ | |
218 | } else { | |
219 | bcma_core_pci_clientmode_init(pc); | |
220 | } | |
517f43e5 HM |
221 | |
222 | pc->setup_done = true; | |
9352f69c RM |
223 | } |
224 | ||
1de520f4 RM |
225 | int bcma_core_pci_irq_ctl(struct bcma_drv_pci *pc, struct bcma_device *core, |
226 | bool enable) | |
227 | { | |
228 | struct pci_dev *pdev = pc->core->bus->host_pci; | |
229 | u32 coremask, tmp; | |
ecd177c2 HM |
230 | int err = 0; |
231 | ||
232 | if (core->bus->hosttype != BCMA_HOSTTYPE_PCI) { | |
233 | /* This bcma device is not on a PCI host-bus. So the IRQs are | |
234 | * not routed through the PCI core. | |
235 | * So we must not enable routing through the PCI core. */ | |
236 | goto out; | |
237 | } | |
1de520f4 RM |
238 | |
239 | err = pci_read_config_dword(pdev, BCMA_PCI_IRQMASK, &tmp); | |
240 | if (err) | |
241 | goto out; | |
242 | ||
243 | coremask = BIT(core->core_index) << 8; | |
244 | if (enable) | |
245 | tmp |= coremask; | |
246 | else | |
247 | tmp &= ~coremask; | |
248 | ||
249 | err = pci_write_config_dword(pdev, BCMA_PCI_IRQMASK, tmp); | |
250 | ||
251 | out: | |
252 | return err; | |
253 | } | |
440ca98f | 254 | EXPORT_SYMBOL_GPL(bcma_core_pci_irq_ctl); |