[linux-block.git] / drivers / bcma / driver_gpio.c

/*
 * Broadcom specific AMBA
 * GPIO driver
 *
 * Copyright 2011, Broadcom Corporation
 * Copyright 2012, Hauke Mehrtens <hauke@hauke-m.de>
 *
 * Licensed under the GNU/GPL. See COPYING for details.
 */

#include <linux/gpio/driver.h>
#include <linux/interrupt.h>
#include <linux/export.h>
#include <linux/bcma/bcma.h>

#include "bcma_private.h"

#define BCMA_GPIO_MAX_PINS	32

static int bcma_gpio_get_value(struct gpio_chip *chip, unsigned gpio)
{
	struct bcma_drv_cc *cc = gpiochip_get_data(chip);

	return !!bcma_chipco_gpio_in(cc, 1 << gpio);
}

static void bcma_gpio_set_value(struct gpio_chip *chip, unsigned gpio,
				int value)
{
	struct bcma_drv_cc *cc = gpiochip_get_data(chip);

	bcma_chipco_gpio_out(cc, 1 << gpio, value ? 1 << gpio : 0);
}

static int bcma_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
{
	struct bcma_drv_cc *cc = gpiochip_get_data(chip);

	bcma_chipco_gpio_outen(cc, 1 << gpio, 0);
	return 0;
}

static int bcma_gpio_direction_output(struct gpio_chip *chip, unsigned gpio,
				      int value)
{
	struct bcma_drv_cc *cc = gpiochip_get_data(chip);

	bcma_chipco_gpio_outen(cc, 1 << gpio, 1 << gpio);
	bcma_chipco_gpio_out(cc, 1 << gpio, value ? 1 << gpio : 0);
	return 0;
}

static int bcma_gpio_request(struct gpio_chip *chip, unsigned gpio)
{
	struct bcma_drv_cc *cc = gpiochip_get_data(chip);

	bcma_chipco_gpio_control(cc, 1 << gpio, 0);
	/* clear pulldown */
	bcma_chipco_gpio_pulldown(cc, 1 << gpio, 0);
	/* Set pullup */
	bcma_chipco_gpio_pullup(cc, 1 << gpio, 1 << gpio);

	return 0;
}

static void bcma_gpio_free(struct gpio_chip *chip, unsigned gpio)
{
	struct bcma_drv_cc *cc = gpiochip_get_data(chip);

	/* clear pullup */
	bcma_chipco_gpio_pullup(cc, 1 << gpio, 0);
}

#if IS_BUILTIN(CONFIG_BCM47XX) || IS_BUILTIN(CONFIG_ARCH_BCM_5301X)

static void bcma_gpio_irq_unmask(struct irq_data *d)
{
	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
	struct bcma_drv_cc *cc = gpiochip_get_data(gc);
	int gpio = irqd_to_hwirq(d);
	u32 val = bcma_chipco_gpio_in(cc, BIT(gpio));

	bcma_chipco_gpio_polarity(cc, BIT(gpio), val);
	bcma_chipco_gpio_intmask(cc, BIT(gpio), BIT(gpio));
}

static void bcma_gpio_irq_mask(struct irq_data *d)
{
	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
	struct bcma_drv_cc *cc = gpiochip_get_data(gc);
	int gpio = irqd_to_hwirq(d);

	bcma_chipco_gpio_intmask(cc, BIT(gpio), 0);
}

static struct irq_chip bcma_gpio_irq_chip = {
	.name		= "BCMA-GPIO",
	.irq_mask	= bcma_gpio_irq_mask,
	.irq_unmask	= bcma_gpio_irq_unmask,
};

static irqreturn_t bcma_gpio_irq_handler(int irq, void *dev_id)
{
	struct bcma_drv_cc *cc = dev_id;
	struct gpio_chip *gc = &cc->gpio;
	u32 val = bcma_cc_read32(cc, BCMA_CC_GPIOIN);
	u32 mask = bcma_cc_read32(cc, BCMA_CC_GPIOIRQ);
	u32 pol = bcma_cc_read32(cc, BCMA_CC_GPIOPOL);
	unsigned long irqs = (val ^ pol) & mask;
	int gpio;

	if (!irqs)
		return IRQ_NONE;

	for_each_set_bit(gpio, &irqs, gc->ngpio)
		generic_handle_irq(irq_find_mapping(gc->irq.domain, gpio));
	bcma_chipco_gpio_polarity(cc, irqs, val & irqs);

	return IRQ_HANDLED;
}

static int bcma_gpio_irq_init(struct bcma_drv_cc *cc)
{
	struct gpio_chip *chip = &cc->gpio;
	struct gpio_irq_chip *girq = &chip->irq;
	int hwirq, err;

	if (cc->core->bus->hosttype != BCMA_HOSTTYPE_SOC)
		return 0;

	hwirq = bcma_core_irq(cc->core, 0);
	err = request_irq(hwirq, bcma_gpio_irq_handler, IRQF_SHARED, "gpio",
			  cc);
	if (err)
		return err;

	bcma_chipco_gpio_intmask(cc, ~0, 0);
	bcma_cc_set32(cc, BCMA_CC_IRQMASK, BCMA_CC_IRQ_GPIO);

	girq->chip = &bcma_gpio_irq_chip;
	/* This will let us handle the parent IRQ in the driver */
	girq->parent_handler = NULL;
	girq->num_parents = 0;
	girq->parents = NULL;
	girq->default_type = IRQ_TYPE_NONE;
	girq->handler = handle_simple_irq;

	return 0;
}

static void bcma_gpio_irq_exit(struct bcma_drv_cc *cc)
{
	if (cc->core->bus->hosttype != BCMA_HOSTTYPE_SOC)
		return;

	bcma_cc_mask32(cc, BCMA_CC_IRQMASK, ~BCMA_CC_IRQ_GPIO);
	free_irq(bcma_core_irq(cc->core, 0), cc);
}
#else
static int bcma_gpio_irq_init(struct bcma_drv_cc *cc)
{
	return 0;
}

static void bcma_gpio_irq_exit(struct bcma_drv_cc *cc)
{
}
#endif

int bcma_gpio_init(struct bcma_drv_cc *cc)
{
	struct bcma_bus *bus = cc->core->bus;
	struct gpio_chip *chip = &cc->gpio;
	int err;

	chip->label		= "bcma_gpio";
	chip->owner		= THIS_MODULE;
	chip->request		= bcma_gpio_request;
	chip->free		= bcma_gpio_free;
	chip->get		= bcma_gpio_get_value;
	chip->set		= bcma_gpio_set_value;
	chip->direction_input	= bcma_gpio_direction_input;
	chip->direction_output	= bcma_gpio_direction_output;
	chip->owner		= THIS_MODULE;
	chip->parent		= bus->dev;
#if IS_BUILTIN(CONFIG_OF)
	chip->of_node		= cc->core->dev.of_node;
#endif
	switch (bus->chipinfo.id) {
	case BCMA_CHIP_ID_BCM4707:
	case BCMA_CHIP_ID_BCM5357:
	case BCMA_CHIP_ID_BCM53572:
	case BCMA_CHIP_ID_BCM53573:
	case BCMA_CHIP_ID_BCM47094:
		chip->ngpio	= 32;
		break;
	default:
		chip->ngpio	= 16;
	}

	/*
	 * Register SoC GPIO devices with absolute GPIO pin base.
	 * On MIPS, we don't have Device Tree and we can't use relative (per chip)
	 * GPIO numbers.
	 * On some ARM devices, user space may want to access some system GPIO
	 * pins directly, which is easier to do with a predictable GPIO base.
	 */
	if (IS_BUILTIN(CONFIG_BCM47XX) ||
	    cc->core->bus->hosttype == BCMA_HOSTTYPE_SOC)
		chip->base		= bus->num * BCMA_GPIO_MAX_PINS;
	else
		chip->base		= -1;

	err = bcma_gpio_irq_init(cc);
	if (err)
		return err;

	err = gpiochip_add_data(chip, cc);
	if (err) {
		bcma_gpio_irq_exit(cc);
		return err;
	}

	return 0;
}

int bcma_gpio_unregister(struct bcma_drv_cc *cc)
{
	bcma_gpio_irq_exit(cc);
	gpiochip_remove(&cc->gpio);
	return 0;
}
Commit	Line	Data
cf0936b0 HM	1	/*
	2	* Broadcom specific AMBA
	3	* GPIO driver
	4	*
	5	* Copyright 2011, Broadcom Corporation
	6	* Copyright 2012, Hauke Mehrtens <hauke@hauke-m.de>
	7	*
	8	* Licensed under the GNU/GPL. See COPYING for details.
	9	*/
	10
74f4e0cc	11	#include <linux/gpio/driver.h>
2997609e	12	#include <linux/interrupt.h>
cf0936b0 HM	13	#include <linux/export.h>
	14	#include <linux/bcma/bcma.h>
	15
	16	#include "bcma_private.h"
	17
057fcd42 RM	18	#define BCMA_GPIO_MAX_PINS 32
057fcd42 RM	19
cf0936b0 HM	20	static int bcma_gpio_get_value(struct gpio_chip *chip, unsigned gpio)
cf0936b0 HM	21	{
78d455a2	22	struct bcma_drv_cc *cc = gpiochip_get_data(chip);
cf0936b0 HM	23
	24	return !!bcma_chipco_gpio_in(cc, 1 << gpio);
	25	}
	26
	27	static void bcma_gpio_set_value(struct gpio_chip *chip, unsigned gpio,
	28	int value)
	29	{
78d455a2	30	struct bcma_drv_cc *cc = gpiochip_get_data(chip);
cf0936b0 HM	31
	32	bcma_chipco_gpio_out(cc, 1 << gpio, value ? 1 << gpio : 0);
	33	}
	34
	35	static int bcma_gpio_direction_input(struct gpio_chip *chip, unsigned gpio)
	36	{
78d455a2	37	struct bcma_drv_cc *cc = gpiochip_get_data(chip);
cf0936b0 HM	38
	39	bcma_chipco_gpio_outen(cc, 1 << gpio, 0);
	40	return 0;
	41	}
	42
	43	static int bcma_gpio_direction_output(struct gpio_chip *chip, unsigned gpio,
	44	int value)
	45	{
78d455a2	46	struct bcma_drv_cc *cc = gpiochip_get_data(chip);
cf0936b0 HM	47
	48	bcma_chipco_gpio_outen(cc, 1 << gpio, 1 << gpio);
	49	bcma_chipco_gpio_out(cc, 1 << gpio, value ? 1 << gpio : 0);
	50	return 0;
	51	}
	52
	53	static int bcma_gpio_request(struct gpio_chip *chip, unsigned gpio)
	54	{
78d455a2	55	struct bcma_drv_cc *cc = gpiochip_get_data(chip);
cf0936b0 HM	56
	57	bcma_chipco_gpio_control(cc, 1 << gpio, 0);
	58	/* clear pulldown */
	59	bcma_chipco_gpio_pulldown(cc, 1 << gpio, 0);
	60	/* Set pullup */
	61	bcma_chipco_gpio_pullup(cc, 1 << gpio, 1 << gpio);
	62
	63	return 0;
	64	}
	65
	66	static void bcma_gpio_free(struct gpio_chip *chip, unsigned gpio)
	67	{
78d455a2	68	struct bcma_drv_cc *cc = gpiochip_get_data(chip);
cf0936b0 HM	69
	70	/* clear pullup */
	71	bcma_chipco_gpio_pullup(cc, 1 << gpio, 0);
	72	}
	73
0cbfc065	74	#if IS_BUILTIN(CONFIG_BCM47XX) \|\| IS_BUILTIN(CONFIG_ARCH_BCM_5301X)
8f1ca268	75
2997609e RM	76	static void bcma_gpio_irq_unmask(struct irq_data *d)
2997609e RM	77	{
74f4e0cc	78	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
78d455a2	79	struct bcma_drv_cc *cc = gpiochip_get_data(gc);
2997609e	80	int gpio = irqd_to_hwirq(d);
978e55d2	81	u32 val = bcma_chipco_gpio_in(cc, BIT(gpio));
2997609e	82
978e55d2	83	bcma_chipco_gpio_polarity(cc, BIT(gpio), val);
2997609e RM	84	bcma_chipco_gpio_intmask(cc, BIT(gpio), BIT(gpio));
	85	}
	86
	87	static void bcma_gpio_irq_mask(struct irq_data *d)
	88	{
74f4e0cc	89	struct gpio_chip *gc = irq_data_get_irq_chip_data(d);
78d455a2	90	struct bcma_drv_cc *cc = gpiochip_get_data(gc);
2997609e RM	91	int gpio = irqd_to_hwirq(d);
	92
	93	bcma_chipco_gpio_intmask(cc, BIT(gpio), 0);
	94	}
	95
	96	static struct irq_chip bcma_gpio_irq_chip = {
	97	.name = "BCMA-GPIO",
	98	.irq_mask = bcma_gpio_irq_mask,
	99	.irq_unmask = bcma_gpio_irq_unmask,
	100	};
	101
	102	static irqreturn_t bcma_gpio_irq_handler(int irq, void *dev_id)
	103	{
	104	struct bcma_drv_cc *cc = dev_id;
74f4e0cc	105	struct gpio_chip *gc = &cc->gpio;
2997609e RM	106	u32 val = bcma_cc_read32(cc, BCMA_CC_GPIOIN);
	107	u32 mask = bcma_cc_read32(cc, BCMA_CC_GPIOIRQ);
	108	u32 pol = bcma_cc_read32(cc, BCMA_CC_GPIOPOL);
d5ab2adb	109	unsigned long irqs = (val ^ pol) & mask;
2997609e RM	110	int gpio;
	111
	112	if (!irqs)
	113	return IRQ_NONE;
	114
74f4e0cc	115	for_each_set_bit(gpio, &irqs, gc->ngpio)
f0fbe7bc	116	generic_handle_irq(irq_find_mapping(gc->irq.domain, gpio));
2997609e RM	117	bcma_chipco_gpio_polarity(cc, irqs, val & irqs);
	118
	119	return IRQ_HANDLED;
	120	}
	121
74f4e0cc	122	static int bcma_gpio_irq_init(struct bcma_drv_cc *cc)
2997609e RM	123	{
2997609e RM	124	struct gpio_chip *chip = &cc->gpio;
a080ecb1	125	struct gpio_irq_chip *girq = &chip->irq;
74f4e0cc	126	int hwirq, err;
2997609e RM	127
	128	if (cc->core->bus->hosttype != BCMA_HOSTTYPE_SOC)
	129	return 0;
	130
85eb92e8	131	hwirq = bcma_core_irq(cc->core, 0);
2997609e RM	132	err = request_irq(hwirq, bcma_gpio_irq_handler, IRQF_SHARED, "gpio",
	133	cc);
	134	if (err)
74f4e0cc	135	return err;
2997609e	136
978e55d2	137	bcma_chipco_gpio_intmask(cc, ~0, 0);
2997609e RM	138	bcma_cc_set32(cc, BCMA_CC_IRQMASK, BCMA_CC_IRQ_GPIO);
2997609e RM	139
a080ecb1 LW	140	girq->chip = &bcma_gpio_irq_chip;
	141	/* This will let us handle the parent IRQ in the driver */
	142	girq->parent_handler = NULL;
	143	girq->num_parents = 0;
	144	girq->parents = NULL;
	145	girq->default_type = IRQ_TYPE_NONE;
	146	girq->handler = handle_simple_irq;
74f4e0cc LW	147
74f4e0cc LW	148	return 0;
2997609e RM	149	}
2997609e RM	150
74f4e0cc	151	static void bcma_gpio_irq_exit(struct bcma_drv_cc *cc)
2997609e	152	{
2997609e RM	153	if (cc->core->bus->hosttype != BCMA_HOSTTYPE_SOC)
	154	return;
	155
	156	bcma_cc_mask32(cc, BCMA_CC_IRQMASK, ~BCMA_CC_IRQ_GPIO);
85eb92e8	157	free_irq(bcma_core_irq(cc->core, 0), cc);
2997609e RM	158	}
2997609e RM	159	#else
74f4e0cc	160	static int bcma_gpio_irq_init(struct bcma_drv_cc *cc)
2997609e RM	161	{
	162	return 0;
	163	}
	164
74f4e0cc	165	static void bcma_gpio_irq_exit(struct bcma_drv_cc *cc)
2997609e RM	166	{
	167	}
	168	#endif
	169
cf0936b0 HM	170	int bcma_gpio_init(struct bcma_drv_cc *cc)
cf0936b0 HM	171	{
057fcd42	172	struct bcma_bus *bus = cc->core->bus;
cf0936b0	173	struct gpio_chip *chip = &cc->gpio;
2997609e	174	int err;
cf0936b0 HM	175
	176	chip->label = "bcma_gpio";
	177	chip->owner = THIS_MODULE;
	178	chip->request = bcma_gpio_request;
	179	chip->free = bcma_gpio_free;
	180	chip->get = bcma_gpio_get_value;
	181	chip->set = bcma_gpio_set_value;
	182	chip->direction_input = bcma_gpio_direction_input;
	183	chip->direction_output = bcma_gpio_direction_output;
74f4e0cc	184	chip->owner = THIS_MODULE;
5a1c18b7	185	chip->parent = bus->dev;
a0196d11	186	#if IS_BUILTIN(CONFIG_OF)
a4bb5b1b	187	chip->of_node = cc->core->dev.of_node;
2997609e	188	#endif
057fcd42	189	switch (bus->chipinfo.id) {
f022ea52	190	case BCMA_CHIP_ID_BCM4707:
0f8ca014	191	case BCMA_CHIP_ID_BCM5357:
f0db59e1	192	case BCMA_CHIP_ID_BCM53572:
459c3514	193	case BCMA_CHIP_ID_BCM53573:
61dba73c	194	case BCMA_CHIP_ID_BCM47094:
0f8ca014 RM	195	chip->ngpio = 32;
	196	break;
	197	default:
	198	chip->ngpio = 16;
	199	}
	200
057fcd42	201	/*
2d57b712 FF	202	* Register SoC GPIO devices with absolute GPIO pin base.
	203	* On MIPS, we don't have Device Tree and we can't use relative (per chip)
	204	* GPIO numbers.
	205	* On some ARM devices, user space may want to access some system GPIO
	206	* pins directly, which is easier to do with a predictable GPIO base.
057fcd42	207	*/
2d57b712 FF	208	if (IS_BUILTIN(CONFIG_BCM47XX) \|\|
	209	cc->core->bus->hosttype == BCMA_HOSTTYPE_SOC)
	210	chip->base = bus->num * BCMA_GPIO_MAX_PINS;
	211	else
	212	chip->base = -1;
cf0936b0	213
a080ecb1	214	err = bcma_gpio_irq_init(cc);
2997609e RM	215	if (err)
	216	return err;
	217
a080ecb1	218	err = gpiochip_add_data(chip, cc);
2997609e	219	if (err) {
a080ecb1	220	bcma_gpio_irq_exit(cc);
2997609e RM	221	return err;
	222	}
	223
	224	return 0;
cf0936b0	225	}
c50ae947 HM	226
	227	int bcma_gpio_unregister(struct bcma_drv_cc *cc)
	228	{
74f4e0cc	229	bcma_gpio_irq_exit(cc);
88d5e520	230	gpiochip_remove(&cc->gpio);
88d5e520	231	return 0;
c50ae947	232	}