[linux-2.6-block.git] / drivers / bcma / driver_chipcommon_pmu.c

/*
 * Broadcom specific AMBA
 * ChipCommon Power Management Unit driver
 *
 * Copyright 2009, Michael Buesch <m@bues.ch>
 * Copyright 2007, 2011, Broadcom Corporation
 * Copyright 2011, 2012, Hauke Mehrtens <hauke@hauke-m.de>
 *
 * Licensed under the GNU/GPL. See COPYING for details.
 */

#include "bcma_private.h"
#include <linux/export.h>
#include <linux/bcma/bcma.h>

static u32 bcma_chipco_pll_read(struct bcma_drv_cc *cc, u32 offset)
{
	bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR, offset);
	bcma_cc_read32(cc, BCMA_CC_PLLCTL_ADDR);
	return bcma_cc_read32(cc, BCMA_CC_PLLCTL_DATA);
}

void bcma_chipco_pll_write(struct bcma_drv_cc *cc, u32 offset, u32 value)
{
	bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR, offset);
	bcma_cc_read32(cc, BCMA_CC_PLLCTL_ADDR);
	bcma_cc_write32(cc, BCMA_CC_PLLCTL_DATA, value);
}
EXPORT_SYMBOL_GPL(bcma_chipco_pll_write);

void bcma_chipco_pll_maskset(struct bcma_drv_cc *cc, u32 offset, u32 mask,
			     u32 set)
{
	bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR, offset);
	bcma_cc_read32(cc, BCMA_CC_PLLCTL_ADDR);
	bcma_cc_maskset32(cc, BCMA_CC_PLLCTL_DATA, mask, set);
}
EXPORT_SYMBOL_GPL(bcma_chipco_pll_maskset);

void bcma_chipco_chipctl_maskset(struct bcma_drv_cc *cc,
				 u32 offset, u32 mask, u32 set)
{
	bcma_cc_write32(cc, BCMA_CC_CHIPCTL_ADDR, offset);
	bcma_cc_read32(cc, BCMA_CC_CHIPCTL_ADDR);
	bcma_cc_maskset32(cc, BCMA_CC_CHIPCTL_DATA, mask, set);
}
EXPORT_SYMBOL_GPL(bcma_chipco_chipctl_maskset);

void bcma_chipco_regctl_maskset(struct bcma_drv_cc *cc, u32 offset, u32 mask,
				u32 set)
{
	bcma_cc_write32(cc, BCMA_CC_REGCTL_ADDR, offset);
	bcma_cc_read32(cc, BCMA_CC_REGCTL_ADDR);
	bcma_cc_maskset32(cc, BCMA_CC_REGCTL_DATA, mask, set);
}
EXPORT_SYMBOL_GPL(bcma_chipco_regctl_maskset);

static void bcma_pmu_resources_init(struct bcma_drv_cc *cc)
{
	struct bcma_bus *bus = cc->core->bus;
	u32 min_msk = 0, max_msk = 0;

	switch (bus->chipinfo.id) {
	case BCMA_CHIP_ID_BCM4313:
		min_msk = 0x200D;
		max_msk = 0xFFFF;
		break;
	default:
		bcma_debug(bus, "PMU resource config unknown or not needed for device 0x%04X\n",
			   bus->chipinfo.id);
	}

	/* Set the resource masks. */
	if (min_msk)
		bcma_cc_write32(cc, BCMA_CC_PMU_MINRES_MSK, min_msk);
	if (max_msk)
		bcma_cc_write32(cc, BCMA_CC_PMU_MAXRES_MSK, max_msk);

	/*
	 * Add some delay; allow resources to come up and settle.
	 * Delay is required for SoC (early init).
	 */
	mdelay(2);
}

/* Disable to allow reading SPROM. Don't know the adventages of enabling it. */
void bcma_chipco_bcm4331_ext_pa_lines_ctl(struct bcma_drv_cc *cc, bool enable)
{
	struct bcma_bus *bus = cc->core->bus;
	u32 val;

	val = bcma_cc_read32(cc, BCMA_CC_CHIPCTL);
	if (enable) {
		val |= BCMA_CHIPCTL_4331_EXTPA_EN;
		if (bus->chipinfo.pkg == 9 || bus->chipinfo.pkg == 11)
			val |= BCMA_CHIPCTL_4331_EXTPA_ON_GPIO2_5;
		else if (bus->chipinfo.rev > 0)
			val |= BCMA_CHIPCTL_4331_EXTPA_EN2;
	} else {
		val &= ~BCMA_CHIPCTL_4331_EXTPA_EN;
		val &= ~BCMA_CHIPCTL_4331_EXTPA_EN2;
		val &= ~BCMA_CHIPCTL_4331_EXTPA_ON_GPIO2_5;
	}
	bcma_cc_write32(cc, BCMA_CC_CHIPCTL, val);
}

static void bcma_pmu_workarounds(struct bcma_drv_cc *cc)
{
	struct bcma_bus *bus = cc->core->bus;

	switch (bus->chipinfo.id) {
	case BCMA_CHIP_ID_BCM4313:
		/* enable 12 mA drive strenth for 4313 and set chipControl
		   register bit 1 */
		bcma_chipco_chipctl_maskset(cc, 0,
					    ~BCMA_CCTRL_4313_12MA_LED_DRIVE,
					    BCMA_CCTRL_4313_12MA_LED_DRIVE);
		break;
	case BCMA_CHIP_ID_BCM4331:
	case BCMA_CHIP_ID_BCM43431:
		/* Ext PA lines must be enabled for tx on BCM4331 */
		bcma_chipco_bcm4331_ext_pa_lines_ctl(cc, true);
		break;
	case BCMA_CHIP_ID_BCM43224:
	case BCMA_CHIP_ID_BCM43421:
		/* enable 12 mA drive strenth for 43224 and set chipControl
		   register bit 15 */
		if (bus->chipinfo.rev == 0) {
			bcma_cc_maskset32(cc, BCMA_CC_CHIPCTL,
					  ~BCMA_CCTRL_43224_GPIO_TOGGLE,
					  BCMA_CCTRL_43224_GPIO_TOGGLE);
			bcma_chipco_chipctl_maskset(cc, 0,
						    ~BCMA_CCTRL_43224A0_12MA_LED_DRIVE,
						    BCMA_CCTRL_43224A0_12MA_LED_DRIVE);
		} else {
			bcma_chipco_chipctl_maskset(cc, 0,
						    ~BCMA_CCTRL_43224B0_12MA_LED_DRIVE,
						    BCMA_CCTRL_43224B0_12MA_LED_DRIVE);
		}
		break;
	default:
		bcma_debug(bus, "Workarounds unknown or not needed for device 0x%04X\n",
			   bus->chipinfo.id);
	}
}

void bcma_pmu_early_init(struct bcma_drv_cc *cc)
{
	u32 pmucap;

	pmucap = bcma_cc_read32(cc, BCMA_CC_PMU_CAP);
	cc->pmu.rev = (pmucap & BCMA_CC_PMU_CAP_REVISION);

	bcma_debug(cc->core->bus, "Found rev %u PMU (capabilities 0x%08X)\n",
		   cc->pmu.rev, pmucap);
}

void bcma_pmu_init(struct bcma_drv_cc *cc)
{
	if (cc->pmu.rev == 1)
		bcma_cc_mask32(cc, BCMA_CC_PMU_CTL,
			      ~BCMA_CC_PMU_CTL_NOILPONW);
	else
		bcma_cc_set32(cc, BCMA_CC_PMU_CTL,
			     BCMA_CC_PMU_CTL_NOILPONW);

	bcma_pmu_resources_init(cc);
	bcma_pmu_workarounds(cc);
}

u32 bcma_pmu_get_alp_clock(struct bcma_drv_cc *cc)
{
	struct bcma_bus *bus = cc->core->bus;

	switch (bus->chipinfo.id) {
	case BCMA_CHIP_ID_BCM4716:
	case BCMA_CHIP_ID_BCM4748:
	case BCMA_CHIP_ID_BCM47162:
	case BCMA_CHIP_ID_BCM4313:
	case BCMA_CHIP_ID_BCM5357:
	case BCMA_CHIP_ID_BCM4749:
	case BCMA_CHIP_ID_BCM53572:
		/* always 20Mhz */
		return 20000 * 1000;
	case BCMA_CHIP_ID_BCM5356:
	case BCMA_CHIP_ID_BCM4706:
		/* always 25Mhz */
		return 25000 * 1000;
	default:
		bcma_warn(bus, "No ALP clock specified for %04X device, pmu rev. %d, using default %d Hz\n",
			  bus->chipinfo.id, cc->pmu.rev, BCMA_CC_PMU_ALP_CLOCK);
	}
	return BCMA_CC_PMU_ALP_CLOCK;
}

/* Find the output of the "m" pll divider given pll controls that start with
 * pllreg "pll0" i.e. 12 for main 6 for phy, 0 for misc.
 */
static u32 bcma_pmu_pll_clock(struct bcma_drv_cc *cc, u32 pll0, u32 m)
{
	u32 tmp, div, ndiv, p1, p2, fc;
	struct bcma_bus *bus = cc->core->bus;

	BUG_ON((pll0 & 3) || (pll0 > BCMA_CC_PMU4716_MAINPLL_PLL0));

	BUG_ON(!m || m > 4);

	if (bus->chipinfo.id == BCMA_CHIP_ID_BCM5357 ||
	    bus->chipinfo.id == BCMA_CHIP_ID_BCM4749) {
		/* Detect failure in clock setting */
		tmp = bcma_cc_read32(cc, BCMA_CC_CHIPSTAT);
		if (tmp & 0x40000)
			return 133 * 1000000;
	}

	tmp = bcma_chipco_pll_read(cc, pll0 + BCMA_CC_PPL_P1P2_OFF);
	p1 = (tmp & BCMA_CC_PPL_P1_MASK) >> BCMA_CC_PPL_P1_SHIFT;
	p2 = (tmp & BCMA_CC_PPL_P2_MASK) >> BCMA_CC_PPL_P2_SHIFT;

	tmp = bcma_chipco_pll_read(cc, pll0 + BCMA_CC_PPL_M14_OFF);
	div = (tmp >> ((m - 1) * BCMA_CC_PPL_MDIV_WIDTH)) &
		BCMA_CC_PPL_MDIV_MASK;

	tmp = bcma_chipco_pll_read(cc, pll0 + BCMA_CC_PPL_NM5_OFF);
	ndiv = (tmp & BCMA_CC_PPL_NDIV_MASK) >> BCMA_CC_PPL_NDIV_SHIFT;

	/* Do calculation in Mhz */
	fc = bcma_pmu_get_alp_clock(cc) / 1000000;
	fc = (p1 * ndiv * fc) / p2;

	/* Return clock in Hertz */
	return (fc / div) * 1000000;
}

static u32 bcma_pmu_pll_clock_bcm4706(struct bcma_drv_cc *cc, u32 pll0, u32 m)
{
	u32 tmp, ndiv, p1div, p2div;
	u32 clock;

	BUG_ON(!m || m > 4);

	/* Get N, P1 and P2 dividers to determine CPU clock */
	tmp = bcma_chipco_pll_read(cc, pll0 + BCMA_CC_PMU6_4706_PROCPLL_OFF);
	ndiv = (tmp & BCMA_CC_PMU6_4706_PROC_NDIV_INT_MASK)
		>> BCMA_CC_PMU6_4706_PROC_NDIV_INT_SHIFT;
	p1div = (tmp & BCMA_CC_PMU6_4706_PROC_P1DIV_MASK)
		>> BCMA_CC_PMU6_4706_PROC_P1DIV_SHIFT;
	p2div = (tmp & BCMA_CC_PMU6_4706_PROC_P2DIV_MASK)
		>> BCMA_CC_PMU6_4706_PROC_P2DIV_SHIFT;

	tmp = bcma_cc_read32(cc, BCMA_CC_CHIPSTAT);
	if (tmp & BCMA_CC_CHIPST_4706_PKG_OPTION)
		/* Low cost bonding: Fixed reference clock 25MHz and m = 4 */
		clock = (25000000 / 4) * ndiv * p2div / p1div;
	else
		/* Fixed reference clock 25MHz and m = 2 */
		clock = (25000000 / 2) * ndiv * p2div / p1div;

	if (m == BCMA_CC_PMU5_MAINPLL_SSB)
		clock = clock / 4;

	return clock;
}

/* query bus clock frequency for PMU-enabled chipcommon */
static u32 bcma_pmu_get_bus_clock(struct bcma_drv_cc *cc)
{
	struct bcma_bus *bus = cc->core->bus;

	switch (bus->chipinfo.id) {
	case BCMA_CHIP_ID_BCM4716:
	case BCMA_CHIP_ID_BCM4748:
	case BCMA_CHIP_ID_BCM47162:
		return bcma_pmu_pll_clock(cc, BCMA_CC_PMU4716_MAINPLL_PLL0,
					  BCMA_CC_PMU5_MAINPLL_SSB);
	case BCMA_CHIP_ID_BCM5356:
		return bcma_pmu_pll_clock(cc, BCMA_CC_PMU5356_MAINPLL_PLL0,
					  BCMA_CC_PMU5_MAINPLL_SSB);
	case BCMA_CHIP_ID_BCM5357:
	case BCMA_CHIP_ID_BCM4749:
		return bcma_pmu_pll_clock(cc, BCMA_CC_PMU5357_MAINPLL_PLL0,
					  BCMA_CC_PMU5_MAINPLL_SSB);
	case BCMA_CHIP_ID_BCM4706:
		return bcma_pmu_pll_clock_bcm4706(cc,
						  BCMA_CC_PMU4706_MAINPLL_PLL0,
						  BCMA_CC_PMU5_MAINPLL_SSB);
	case BCMA_CHIP_ID_BCM53572:
		return 75000000;
	default:
		bcma_warn(bus, "No bus clock specified for %04X device, pmu rev. %d, using default %d Hz\n",
			  bus->chipinfo.id, cc->pmu.rev, BCMA_CC_PMU_HT_CLOCK);
	}
	return BCMA_CC_PMU_HT_CLOCK;
}

/* query cpu clock frequency for PMU-enabled chipcommon */
u32 bcma_pmu_get_cpu_clock(struct bcma_drv_cc *cc)
{
	struct bcma_bus *bus = cc->core->bus;

	if (bus->chipinfo.id == BCMA_CHIP_ID_BCM53572)
		return 300000000;

	/* New PMUs can have different clock for bus and CPU */
	if (cc->pmu.rev >= 5) {
		u32 pll;
		switch (bus->chipinfo.id) {
		case BCMA_CHIP_ID_BCM4706:
			return bcma_pmu_pll_clock_bcm4706(cc,
						BCMA_CC_PMU4706_MAINPLL_PLL0,
						BCMA_CC_PMU5_MAINPLL_CPU);
		case BCMA_CHIP_ID_BCM5356:
			pll = BCMA_CC_PMU5356_MAINPLL_PLL0;
			break;
		case BCMA_CHIP_ID_BCM5357:
		case BCMA_CHIP_ID_BCM4749:
			pll = BCMA_CC_PMU5357_MAINPLL_PLL0;
			break;
		default:
			pll = BCMA_CC_PMU4716_MAINPLL_PLL0;
			break;
		}

		return bcma_pmu_pll_clock(cc, pll, BCMA_CC_PMU5_MAINPLL_CPU);
	}

	/* On old PMUs CPU has the same clock as the bus */
	return bcma_pmu_get_bus_clock(cc);
}

static void bcma_pmu_spuravoid_pll_write(struct bcma_drv_cc *cc, u32 offset,
					 u32 value)
{
	bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR, offset);
	bcma_cc_write32(cc, BCMA_CC_PLLCTL_DATA, value);
}

void bcma_pmu_spuravoid_pllupdate(struct bcma_drv_cc *cc, int spuravoid)
{
	u32 tmp = 0;
	u8 phypll_offset = 0;
	u8 bcm5357_bcm43236_p1div[] = {0x1, 0x5, 0x5};
	u8 bcm5357_bcm43236_ndiv[] = {0x30, 0xf6, 0xfc};
	struct bcma_bus *bus = cc->core->bus;

	switch (bus->chipinfo.id) {
	case BCMA_CHIP_ID_BCM5357:
	case BCMA_CHIP_ID_BCM4749:
	case BCMA_CHIP_ID_BCM53572:
		/* 5357[ab]0, 43236[ab]0, and 6362b0 */

		/* BCM5357 needs to touch PLL1_PLLCTL[02],
		   so offset PLL0_PLLCTL[02] by 6 */
		phypll_offset = (bus->chipinfo.id == BCMA_CHIP_ID_BCM5357 ||
		       bus->chipinfo.id == BCMA_CHIP_ID_BCM4749 ||
		       bus->chipinfo.id == BCMA_CHIP_ID_BCM53572) ? 6 : 0;

		/* RMW only the P1 divider */
		bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR,
				BCMA_CC_PMU_PLL_CTL0 + phypll_offset);
		tmp = bcma_cc_read32(cc, BCMA_CC_PLLCTL_DATA);
		tmp &= (~(BCMA_CC_PMU1_PLL0_PC0_P1DIV_MASK));
		tmp |= (bcm5357_bcm43236_p1div[spuravoid] << BCMA_CC_PMU1_PLL0_PC0_P1DIV_SHIFT);
		bcma_cc_write32(cc, BCMA_CC_PLLCTL_DATA, tmp);

		/* RMW only the int feedback divider */
		bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR,
				BCMA_CC_PMU_PLL_CTL2 + phypll_offset);
		tmp = bcma_cc_read32(cc, BCMA_CC_PLLCTL_DATA);
		tmp &= ~(BCMA_CC_PMU1_PLL0_PC2_NDIV_INT_MASK);
		tmp |= (bcm5357_bcm43236_ndiv[spuravoid]) << BCMA_CC_PMU1_PLL0_PC2_NDIV_INT_SHIFT;
		bcma_cc_write32(cc, BCMA_CC_PLLCTL_DATA, tmp);

		tmp = 1 << 10;
		break;

	case BCMA_CHIP_ID_BCM4331:
	case BCMA_CHIP_ID_BCM43431:
		if (spuravoid == 2) {
			bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0,
						     0x11500014);
			bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
						     0x0FC00a08);
		} else if (spuravoid == 1) {
			bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0,
						     0x11500014);
			bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
						     0x0F600a08);
		} else {
			bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0,
						     0x11100014);
			bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
						     0x03000a08);
		}
		tmp = 1 << 10;
		break;

	case BCMA_CHIP_ID_BCM43224:
	case BCMA_CHIP_ID_BCM43225:
	case BCMA_CHIP_ID_BCM43421:
		if (spuravoid == 1) {
			bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0,
						     0x11500010);
			bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL1,
						     0x000C0C06);
			bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
						     0x0F600a08);
			bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL3,
						     0x00000000);
			bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL4,
						     0x2001E920);
			bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5,
						     0x88888815);
		} else {
			bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0,
						     0x11100010);
			bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL1,
						     0x000c0c06);
			bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
						     0x03000a08);
			bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL3,
						     0x00000000);
			bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL4,
						     0x200005c0);
			bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5,
						     0x88888815);
		}
		tmp = 1 << 10;
		break;

	case BCMA_CHIP_ID_BCM4716:
	case BCMA_CHIP_ID_BCM4748:
	case BCMA_CHIP_ID_BCM47162:
		if (spuravoid == 1) {
			bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0,
						     0x11500060);
			bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL1,
						     0x080C0C06);
			bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
						     0x0F600000);
			bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL3,
						     0x00000000);
			bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL4,
						     0x2001E924);
			bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5,
						     0x88888815);
		} else {
			bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0,
						     0x11100060);
			bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL1,
						     0x080c0c06);
			bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
						     0x03000000);
			bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL3,
						     0x00000000);
			bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL4,
						     0x200005c0);
			bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5,
						     0x88888815);
		}

		tmp = 3 << 9;
		break;

	case BCMA_CHIP_ID_BCM43227:
	case BCMA_CHIP_ID_BCM43228:
	case BCMA_CHIP_ID_BCM43428:
		/* LCNXN */
		/* PLL Settings for spur avoidance on/off mode,
		   no on2 support for 43228A0 */
		if (spuravoid == 1) {
			bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0,
						     0x01100014);
			bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL1,
						     0x040C0C06);
			bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
						     0x03140A08);
			bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL3,
						     0x00333333);
			bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL4,
						     0x202C2820);
			bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5,
						     0x88888815);
		} else {
			bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0,
						     0x11100014);
			bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL1,
						     0x040c0c06);
			bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
						     0x03000a08);
			bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL3,
						     0x00000000);
			bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL4,
						     0x200005c0);
			bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5,
						     0x88888815);
		}
		tmp = 1 << 10;
		break;
	default:
		bcma_err(bus, "Unknown spuravoidance settings for chip 0x%04X, not changing PLL\n",
			 bus->chipinfo.id);
		break;
	}

	tmp |= bcma_cc_read32(cc, BCMA_CC_PMU_CTL);
	bcma_cc_write32(cc, BCMA_CC_PMU_CTL, tmp);
}
EXPORT_SYMBOL_GPL(bcma_pmu_spuravoid_pllupdate);
Commit	Line	Data
8369ae33 RM	1	/*
	2	* Broadcom specific AMBA
	3	* ChipCommon Power Management Unit driver
	4	*
eb032b98	5	* Copyright 2009, Michael Buesch <m@bues.ch>
c586e109 HM	6	* Copyright 2007, 2011, Broadcom Corporation
c586e109 HM	7	* Copyright 2011, 2012, Hauke Mehrtens <hauke@hauke-m.de>
8369ae33 RM	8	*
	9	* Licensed under the GNU/GPL. See COPYING for details.
	10	*/
	11
	12	#include "bcma_private.h"
44a8e377	13	#include <linux/export.h>
8369ae33 RM	14	#include <linux/bcma/bcma.h>
8369ae33 RM	15
908debc8 HM	16	static u32 bcma_chipco_pll_read(struct bcma_drv_cc *cc, u32 offset)
	17	{
	18	bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR, offset);
	19	bcma_cc_read32(cc, BCMA_CC_PLLCTL_ADDR);
	20	return bcma_cc_read32(cc, BCMA_CC_PLLCTL_DATA);
	21	}
	22
3861b2c5	23	void bcma_chipco_pll_write(struct bcma_drv_cc *cc, u32 offset, u32 value)
8369ae33	24	{
3861b2c5 RM	25	bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR, offset);
	26	bcma_cc_read32(cc, BCMA_CC_PLLCTL_ADDR);
	27	bcma_cc_write32(cc, BCMA_CC_PLLCTL_DATA, value);
	28	}
	29	EXPORT_SYMBOL_GPL(bcma_chipco_pll_write);
8369ae33	30
3861b2c5 RM	31	void bcma_chipco_pll_maskset(struct bcma_drv_cc *cc, u32 offset, u32 mask,
	32	u32 set)
	33	{
	34	bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR, offset);
	35	bcma_cc_read32(cc, BCMA_CC_PLLCTL_ADDR);
	36	bcma_cc_maskset32(cc, BCMA_CC_PLLCTL_DATA, mask, set);
	37	}
	38	EXPORT_SYMBOL_GPL(bcma_chipco_pll_maskset);
	39
	40	void bcma_chipco_chipctl_maskset(struct bcma_drv_cc *cc,
	41	u32 offset, u32 mask, u32 set)
	42	{
8369ae33 RM	43	bcma_cc_write32(cc, BCMA_CC_CHIPCTL_ADDR, offset);
8369ae33 RM	44	bcma_cc_read32(cc, BCMA_CC_CHIPCTL_ADDR);
3861b2c5 RM	45	bcma_cc_maskset32(cc, BCMA_CC_CHIPCTL_DATA, mask, set);
	46	}
	47	EXPORT_SYMBOL_GPL(bcma_chipco_chipctl_maskset);
	48
	49	void bcma_chipco_regctl_maskset(struct bcma_drv_cc *cc, u32 offset, u32 mask,
	50	u32 set)
	51	{
	52	bcma_cc_write32(cc, BCMA_CC_REGCTL_ADDR, offset);
	53	bcma_cc_read32(cc, BCMA_CC_REGCTL_ADDR);
	54	bcma_cc_maskset32(cc, BCMA_CC_REGCTL_DATA, mask, set);
8369ae33	55	}
3861b2c5	56	EXPORT_SYMBOL_GPL(bcma_chipco_regctl_maskset);
8369ae33	57
8369ae33 RM	58	static void bcma_pmu_resources_init(struct bcma_drv_cc *cc)
	59	{
	60	struct bcma_bus *bus = cc->core->bus;
	61	u32 min_msk = 0, max_msk = 0;
	62
	63	switch (bus->chipinfo.id) {
4b4f5be2	64	case BCMA_CHIP_ID_BCM4313:
8369ae33 RM	65	min_msk = 0x200D;
	66	max_msk = 0xFFFF;
	67	break;
8369ae33	68	default:
3d9d8af3 RM	69	bcma_debug(bus, "PMU resource config unknown or not needed for device 0x%04X\n",
3d9d8af3 RM	70	bus->chipinfo.id);
8369ae33 RM	71	}
	72
	73	/* Set the resource masks. */
	74	if (min_msk)
	75	bcma_cc_write32(cc, BCMA_CC_PMU_MINRES_MSK, min_msk);
	76	if (max_msk)
	77	bcma_cc_write32(cc, BCMA_CC_PMU_MAXRES_MSK, max_msk);
4795f096	78
1fd41a65 RM	79	/*
	80	* Add some delay; allow resources to come up and settle.
	81	* Delay is required for SoC (early init).
	82	*/
4795f096	83	mdelay(2);
8369ae33 RM	84	}
8369ae33 RM	85
984e5bef RM	86	/* Disable to allow reading SPROM. Don't know the adventages of enabling it. */
	87	void bcma_chipco_bcm4331_ext_pa_lines_ctl(struct bcma_drv_cc *cc, bool enable)
	88	{
	89	struct bcma_bus *bus = cc->core->bus;
	90	u32 val;
	91
	92	val = bcma_cc_read32(cc, BCMA_CC_CHIPCTL);
	93	if (enable) {
	94	val \|= BCMA_CHIPCTL_4331_EXTPA_EN;
	95	if (bus->chipinfo.pkg == 9 \|\| bus->chipinfo.pkg == 11)
	96	val \|= BCMA_CHIPCTL_4331_EXTPA_ON_GPIO2_5;
00eeedcf HM	97	else if (bus->chipinfo.rev > 0)
00eeedcf HM	98	val \|= BCMA_CHIPCTL_4331_EXTPA_EN2;
984e5bef RM	99	} else {
984e5bef RM	100	val &= ~BCMA_CHIPCTL_4331_EXTPA_EN;
00eeedcf	101	val &= ~BCMA_CHIPCTL_4331_EXTPA_EN2;
984e5bef RM	102	val &= ~BCMA_CHIPCTL_4331_EXTPA_ON_GPIO2_5;
	103	}
	104	bcma_cc_write32(cc, BCMA_CC_CHIPCTL, val);
	105	}
	106
94f3457f	107	static void bcma_pmu_workarounds(struct bcma_drv_cc *cc)
8369ae33 RM	108	{
	109	struct bcma_bus *bus = cc->core->bus;
	110
	111	switch (bus->chipinfo.id) {
4b4f5be2	112	case BCMA_CHIP_ID_BCM4313:
b9562545 HM	113	/* enable 12 mA drive strenth for 4313 and set chipControl
	114	register bit 1 */
	115	bcma_chipco_chipctl_maskset(cc, 0,
1f03bf06	116	~BCMA_CCTRL_4313_12MA_LED_DRIVE,
b9562545	117	BCMA_CCTRL_4313_12MA_LED_DRIVE);
8369ae33	118	break;
4b4f5be2 HM	119	case BCMA_CHIP_ID_BCM4331:
4b4f5be2 HM	120	case BCMA_CHIP_ID_BCM43431:
69aaedd3 SF	121	/* Ext PA lines must be enabled for tx on BCM4331 */
69aaedd3 SF	122	bcma_chipco_bcm4331_ext_pa_lines_ctl(cc, true);
8369ae33	123	break;
4b4f5be2	124	case BCMA_CHIP_ID_BCM43224:
b9562545 HM	125	case BCMA_CHIP_ID_BCM43421:
	126	/* enable 12 mA drive strenth for 43224 and set chipControl
	127	register bit 15 */
8369ae33	128	if (bus->chipinfo.rev == 0) {
b9562545	129	bcma_cc_maskset32(cc, BCMA_CC_CHIPCTL,
1f03bf06	130	~BCMA_CCTRL_43224_GPIO_TOGGLE,
b9562545 HM	131	BCMA_CCTRL_43224_GPIO_TOGGLE);
b9562545 HM	132	bcma_chipco_chipctl_maskset(cc, 0,
1f03bf06	133	~BCMA_CCTRL_43224A0_12MA_LED_DRIVE,
b9562545	134	BCMA_CCTRL_43224A0_12MA_LED_DRIVE);
8369ae33	135	} else {
b9562545	136	bcma_chipco_chipctl_maskset(cc, 0,
1f03bf06	137	~BCMA_CCTRL_43224B0_12MA_LED_DRIVE,
b9562545	138	BCMA_CCTRL_43224B0_12MA_LED_DRIVE);
8369ae33 RM	139	}
	140	break;
	141	default:
3d9d8af3 RM	142	bcma_debug(bus, "Workarounds unknown or not needed for device 0x%04X\n",
3d9d8af3 RM	143	bus->chipinfo.id);
8369ae33 RM	144	}
	145	}
	146
49655bb8	147	void bcma_pmu_early_init(struct bcma_drv_cc *cc)
8369ae33 RM	148	{
	149	u32 pmucap;
	150
	151	pmucap = bcma_cc_read32(cc, BCMA_CC_PMU_CAP);
	152	cc->pmu.rev = (pmucap & BCMA_CC_PMU_CAP_REVISION);
	153
3d9d8af3 RM	154	bcma_debug(cc->core->bus, "Found rev %u PMU (capabilities 0x%08X)\n",
3d9d8af3 RM	155	cc->pmu.rev, pmucap);
49655bb8	156	}
8369ae33	157
49655bb8 HM	158	void bcma_pmu_init(struct bcma_drv_cc *cc)
49655bb8 HM	159	{
8369ae33 RM	160	if (cc->pmu.rev == 1)
	161	bcma_cc_mask32(cc, BCMA_CC_PMU_CTL,
	162	~BCMA_CC_PMU_CTL_NOILPONW);
	163	else
	164	bcma_cc_set32(cc, BCMA_CC_PMU_CTL,
	165	BCMA_CC_PMU_CTL_NOILPONW);
	166
8369ae33	167	bcma_pmu_resources_init(cc);
8369ae33 RM	168	bcma_pmu_workarounds(cc);
8369ae33 RM	169	}
e3afe0e5	170
5b5ac414	171	u32 bcma_pmu_get_alp_clock(struct bcma_drv_cc *cc)
e3afe0e5 HM	172	{
	173	struct bcma_bus *bus = cc->core->bus;
	174
	175	switch (bus->chipinfo.id) {
4b4f5be2 HM	176	case BCMA_CHIP_ID_BCM4716:
	177	case BCMA_CHIP_ID_BCM4748:
	178	case BCMA_CHIP_ID_BCM47162:
	179	case BCMA_CHIP_ID_BCM4313:
	180	case BCMA_CHIP_ID_BCM5357:
	181	case BCMA_CHIP_ID_BCM4749:
	182	case BCMA_CHIP_ID_BCM53572:
e3afe0e5 HM	183	/* always 20Mhz */
e3afe0e5 HM	184	return 20000 * 1000;
4b4f5be2 HM	185	case BCMA_CHIP_ID_BCM5356:
4b4f5be2 HM	186	case BCMA_CHIP_ID_BCM4706:
e3afe0e5 HM	187	/* always 25Mhz */
	188	return 25000 * 1000;
	189	default:
3d9d8af3 RM	190	bcma_warn(bus, "No ALP clock specified for %04X device, pmu rev. %d, using default %d Hz\n",
3d9d8af3 RM	191	bus->chipinfo.id, cc->pmu.rev, BCMA_CC_PMU_ALP_CLOCK);
e3afe0e5 HM	192	}
	193	return BCMA_CC_PMU_ALP_CLOCK;
	194	}
908debc8 HM	195
	196	/* Find the output of the "m" pll divider given pll controls that start with
	197	* pllreg "pll0" i.e. 12 for main 6 for phy, 0 for misc.
	198	*/
5b5ac414	199	static u32 bcma_pmu_pll_clock(struct bcma_drv_cc *cc, u32 pll0, u32 m)
908debc8 HM	200	{
	201	u32 tmp, div, ndiv, p1, p2, fc;
	202	struct bcma_bus *bus = cc->core->bus;
	203
	204	BUG_ON((pll0 & 3) \|\| (pll0 > BCMA_CC_PMU4716_MAINPLL_PLL0));
	205
	206	BUG_ON(!m \|\| m > 4);
	207
4b4f5be2 HM	208	if (bus->chipinfo.id == BCMA_CHIP_ID_BCM5357 \|\|
4b4f5be2 HM	209	bus->chipinfo.id == BCMA_CHIP_ID_BCM4749) {
908debc8 HM	210	/* Detect failure in clock setting */
	211	tmp = bcma_cc_read32(cc, BCMA_CC_CHIPSTAT);
	212	if (tmp & 0x40000)
	213	return 133 * 1000000;
	214	}
	215
	216	tmp = bcma_chipco_pll_read(cc, pll0 + BCMA_CC_PPL_P1P2_OFF);
	217	p1 = (tmp & BCMA_CC_PPL_P1_MASK) >> BCMA_CC_PPL_P1_SHIFT;
	218	p2 = (tmp & BCMA_CC_PPL_P2_MASK) >> BCMA_CC_PPL_P2_SHIFT;
	219
	220	tmp = bcma_chipco_pll_read(cc, pll0 + BCMA_CC_PPL_M14_OFF);
	221	div = (tmp >> ((m - 1) * BCMA_CC_PPL_MDIV_WIDTH)) &
	222	BCMA_CC_PPL_MDIV_MASK;
	223
	224	tmp = bcma_chipco_pll_read(cc, pll0 + BCMA_CC_PPL_NM5_OFF);
	225	ndiv = (tmp & BCMA_CC_PPL_NDIV_MASK) >> BCMA_CC_PPL_NDIV_SHIFT;
	226
	227	/* Do calculation in Mhz */
5b5ac414	228	fc = bcma_pmu_get_alp_clock(cc) / 1000000;
908debc8 HM	229	fc = (p1 * ndiv * fc) / p2;
	230
	231	/* Return clock in Hertz */
	232	return (fc / div) * 1000000;
	233	}
	234
5b5ac414	235	static u32 bcma_pmu_pll_clock_bcm4706(struct bcma_drv_cc *cc, u32 pll0, u32 m)
650cef38 HM	236	{
	237	u32 tmp, ndiv, p1div, p2div;
	238	u32 clock;
	239
	240	BUG_ON(!m \|\| m > 4);
	241
	242	/* Get N, P1 and P2 dividers to determine CPU clock */
	243	tmp = bcma_chipco_pll_read(cc, pll0 + BCMA_CC_PMU6_4706_PROCPLL_OFF);
	244	ndiv = (tmp & BCMA_CC_PMU6_4706_PROC_NDIV_INT_MASK)
	245	>> BCMA_CC_PMU6_4706_PROC_NDIV_INT_SHIFT;
	246	p1div = (tmp & BCMA_CC_PMU6_4706_PROC_P1DIV_MASK)
	247	>> BCMA_CC_PMU6_4706_PROC_P1DIV_SHIFT;
	248	p2div = (tmp & BCMA_CC_PMU6_4706_PROC_P2DIV_MASK)
	249	>> BCMA_CC_PMU6_4706_PROC_P2DIV_SHIFT;
	250
	251	tmp = bcma_cc_read32(cc, BCMA_CC_CHIPSTAT);
	252	if (tmp & BCMA_CC_CHIPST_4706_PKG_OPTION)
	253	/* Low cost bonding: Fixed reference clock 25MHz and m = 4 */
	254	clock = (25000000 / 4) * ndiv * p2div / p1div;
	255	else
	256	/* Fixed reference clock 25MHz and m = 2 */
	257	clock = (25000000 / 2) * ndiv * p2div / p1div;
	258
	259	if (m == BCMA_CC_PMU5_MAINPLL_SSB)
	260	clock = clock / 4;
	261
	262	return clock;
	263	}
	264
908debc8	265	/* query bus clock frequency for PMU-enabled chipcommon */
5b5ac414	266	static u32 bcma_pmu_get_bus_clock(struct bcma_drv_cc *cc)
908debc8 HM	267	{
	268	struct bcma_bus *bus = cc->core->bus;
	269
	270	switch (bus->chipinfo.id) {
4b4f5be2 HM	271	case BCMA_CHIP_ID_BCM4716:
	272	case BCMA_CHIP_ID_BCM4748:
	273	case BCMA_CHIP_ID_BCM47162:
5b5ac414 RM	274	return bcma_pmu_pll_clock(cc, BCMA_CC_PMU4716_MAINPLL_PLL0,
5b5ac414 RM	275	BCMA_CC_PMU5_MAINPLL_SSB);
4b4f5be2	276	case BCMA_CHIP_ID_BCM5356:
5b5ac414 RM	277	return bcma_pmu_pll_clock(cc, BCMA_CC_PMU5356_MAINPLL_PLL0,
5b5ac414 RM	278	BCMA_CC_PMU5_MAINPLL_SSB);
4b4f5be2 HM	279	case BCMA_CHIP_ID_BCM5357:
4b4f5be2 HM	280	case BCMA_CHIP_ID_BCM4749:
5b5ac414 RM	281	return bcma_pmu_pll_clock(cc, BCMA_CC_PMU5357_MAINPLL_PLL0,
5b5ac414 RM	282	BCMA_CC_PMU5_MAINPLL_SSB);
4b4f5be2	283	case BCMA_CHIP_ID_BCM4706:
5b5ac414 RM	284	return bcma_pmu_pll_clock_bcm4706(cc,
	285	BCMA_CC_PMU4706_MAINPLL_PLL0,
	286	BCMA_CC_PMU5_MAINPLL_SSB);
4b4f5be2	287	case BCMA_CHIP_ID_BCM53572:
908debc8 HM	288	return 75000000;
908debc8 HM	289	default:
5b5ac414	290	bcma_warn(bus, "No bus clock specified for %04X device, pmu rev. %d, using default %d Hz\n",
3d9d8af3	291	bus->chipinfo.id, cc->pmu.rev, BCMA_CC_PMU_HT_CLOCK);
908debc8 HM	292	}
	293	return BCMA_CC_PMU_HT_CLOCK;
	294	}
	295
	296	/* query cpu clock frequency for PMU-enabled chipcommon */
5b5ac414	297	u32 bcma_pmu_get_cpu_clock(struct bcma_drv_cc *cc)
908debc8 HM	298	{
	299	struct bcma_bus *bus = cc->core->bus;
	300
4b4f5be2	301	if (bus->chipinfo.id == BCMA_CHIP_ID_BCM53572)
908debc8 HM	302	return 300000000;
908debc8 HM	303
5b5ac414	304	/* New PMUs can have different clock for bus and CPU */
908debc8 HM	305	if (cc->pmu.rev >= 5) {
	306	u32 pll;
	307	switch (bus->chipinfo.id) {
650cef38	308	case BCMA_CHIP_ID_BCM4706:
5b5ac414	309	return bcma_pmu_pll_clock_bcm4706(cc,
650cef38 HM	310	BCMA_CC_PMU4706_MAINPLL_PLL0,
650cef38 HM	311	BCMA_CC_PMU5_MAINPLL_CPU);
4b4f5be2	312	case BCMA_CHIP_ID_BCM5356:
908debc8 HM	313	pll = BCMA_CC_PMU5356_MAINPLL_PLL0;
908debc8 HM	314	break;
4b4f5be2 HM	315	case BCMA_CHIP_ID_BCM5357:
4b4f5be2 HM	316	case BCMA_CHIP_ID_BCM4749:
908debc8 HM	317	pll = BCMA_CC_PMU5357_MAINPLL_PLL0;
	318	break;
	319	default:
	320	pll = BCMA_CC_PMU4716_MAINPLL_PLL0;
	321	break;
	322	}
	323
5b5ac414	324	return bcma_pmu_pll_clock(cc, pll, BCMA_CC_PMU5_MAINPLL_CPU);
908debc8 HM	325	}
908debc8 HM	326
5b5ac414 RM	327	/* On old PMUs CPU has the same clock as the bus */
5b5ac414 RM	328	return bcma_pmu_get_bus_clock(cc);
908debc8	329	}
c586e109 HM	330
	331	static void bcma_pmu_spuravoid_pll_write(struct bcma_drv_cc *cc, u32 offset,
	332	u32 value)
	333	{
	334	bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR, offset);
	335	bcma_cc_write32(cc, BCMA_CC_PLLCTL_DATA, value);
	336	}
	337
	338	void bcma_pmu_spuravoid_pllupdate(struct bcma_drv_cc *cc, int spuravoid)
	339	{
	340	u32 tmp = 0;
	341	u8 phypll_offset = 0;
	342	u8 bcm5357_bcm43236_p1div[] = {0x1, 0x5, 0x5};
	343	u8 bcm5357_bcm43236_ndiv[] = {0x30, 0xf6, 0xfc};
	344	struct bcma_bus *bus = cc->core->bus;
	345
	346	switch (bus->chipinfo.id) {
	347	case BCMA_CHIP_ID_BCM5357:
	348	case BCMA_CHIP_ID_BCM4749:
	349	case BCMA_CHIP_ID_BCM53572:
	350	/* 5357[ab]0, 43236[ab]0, and 6362b0 */
	351
	352	/* BCM5357 needs to touch PLL1_PLLCTL[02],
	353	so offset PLL0_PLLCTL[02] by 6 */
	354	phypll_offset = (bus->chipinfo.id == BCMA_CHIP_ID_BCM5357 \|\|
	355	bus->chipinfo.id == BCMA_CHIP_ID_BCM4749 \|\|
	356	bus->chipinfo.id == BCMA_CHIP_ID_BCM53572) ? 6 : 0;
	357
	358	/* RMW only the P1 divider */
	359	bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR,
	360	BCMA_CC_PMU_PLL_CTL0 + phypll_offset);
	361	tmp = bcma_cc_read32(cc, BCMA_CC_PLLCTL_DATA);
	362	tmp &= (~(BCMA_CC_PMU1_PLL0_PC0_P1DIV_MASK));
	363	tmp \|= (bcm5357_bcm43236_p1div[spuravoid] << BCMA_CC_PMU1_PLL0_PC0_P1DIV_SHIFT);
	364	bcma_cc_write32(cc, BCMA_CC_PLLCTL_DATA, tmp);
	365
	366	/* RMW only the int feedback divider */
	367	bcma_cc_write32(cc, BCMA_CC_PLLCTL_ADDR,
	368	BCMA_CC_PMU_PLL_CTL2 + phypll_offset);
	369	tmp = bcma_cc_read32(cc, BCMA_CC_PLLCTL_DATA);
	370	tmp &= ~(BCMA_CC_PMU1_PLL0_PC2_NDIV_INT_MASK);
	371	tmp \|= (bcm5357_bcm43236_ndiv[spuravoid]) << BCMA_CC_PMU1_PLL0_PC2_NDIV_INT_SHIFT;
	372	bcma_cc_write32(cc, BCMA_CC_PLLCTL_DATA, tmp);
	373
	374	tmp = 1 << 10;
	375	break;
	376
	377	case BCMA_CHIP_ID_BCM4331:
	378	case BCMA_CHIP_ID_BCM43431:
	379	if (spuravoid == 2) {
	380	bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0,
	381	0x11500014);
	382	bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
	383	0x0FC00a08);
	384	} else if (spuravoid == 1) {
	385	bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0,
	386	0x11500014);
	387	bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
	388	0x0F600a08);
	389	} else {
	390	bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0,
	391	0x11100014);
	392	bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
	393	0x03000a08);
394	}
395	tmp = 1 << 10;
396	break;
397
398	case BCMA_CHIP_ID_BCM43224:
399	case BCMA_CHIP_ID_BCM43225:
400	case BCMA_CHIP_ID_BCM43421:
401	if (spuravoid == 1) {
402	bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0,
403	0x11500010);
404	bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL1,
405	0x000C0C06);
406	bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
407	0x0F600a08);
408	bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL3,
409	0x00000000);
410	bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL4,
411	0x2001E920);
412	bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5,
413	0x88888815);
414	} else {
415	bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0,
416	0x11100010);
417	bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL1,
418	0x000c0c06);
419	bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
420	0x03000a08);
421	bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL3,
422	0x00000000);
423	bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL4,
424	0x200005c0);
425	bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5,
426	0x88888815);
427	}
428	tmp = 1 << 10;
429	break;
430
431	case BCMA_CHIP_ID_BCM4716:
432	case BCMA_CHIP_ID_BCM4748:
433	case BCMA_CHIP_ID_BCM47162:
434	if (spuravoid == 1) {
435	bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0,
436	0x11500060);
437	bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL1,
438	0x080C0C06);
439	bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
440	0x0F600000);
441	bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL3,
442	0x00000000);
443	bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL4,
444	0x2001E924);
445	bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5,
446	0x88888815);
447	} else {
448	bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0,
449	0x11100060);
450	bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL1,
451	0x080c0c06);
452	bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
453	0x03000000);
454	bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL3,
455	0x00000000);
456	bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL4,
457	0x200005c0);
458	bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5,
459	0x88888815);
460	}
461
462	tmp = 3 << 9;
463	break;
464
465	case BCMA_CHIP_ID_BCM43227:
466	case BCMA_CHIP_ID_BCM43228:
467	case BCMA_CHIP_ID_BCM43428:
468	/* LCNXN */
469	/* PLL Settings for spur avoidance on/off mode,
470	no on2 support for 43228A0 */
471	if (spuravoid == 1) {
472	bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0,
473	0x01100014);
474	bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL1,
475	0x040C0C06);
476	bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
477	0x03140A08);
478	bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL3,
479	0x00333333);
480	bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL4,
481	0x202C2820);
482	bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5,
483	0x88888815);
484	} else {
485	bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL0,
486	0x11100014);
487	bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL1,
488	0x040c0c06);
489	bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL2,
490	0x03000a08);
491	bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL3,
492	0x00000000);
493	bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL4,
494	0x200005c0);
495	bcma_pmu_spuravoid_pll_write(cc, BCMA_CC_PMU_PLL_CTL5,
496	0x88888815);
497	}
498	tmp = 1 << 10;
499	break;
500	default:
3d9d8af3 RM	501	bcma_err(bus, "Unknown spuravoidance settings for chip 0x%04X, not changing PLL\n",
3d9d8af3 RM	502	bus->chipinfo.id);
c586e109 HM	503	break;
	504	}
	505
	506	tmp \|= bcma_cc_read32(cc, BCMA_CC_PMU_CTL);
	507	bcma_cc_write32(cc, BCMA_CC_PMU_CTL, tmp);
	508	}
	509	EXPORT_SYMBOL_GPL(bcma_pmu_spuravoid_pllupdate);