[linux-2.6-block.git] / drivers / bcma / core.c

/*
 * Broadcom specific AMBA
 * Core ops
 *
 * Licensed under the GNU/GPL. See COPYING for details.
 */

#include "bcma_private.h"
#include <linux/export.h>
#include <linux/bcma/bcma.h>

bool bcma_core_is_enabled(struct bcma_device *core)
{
	if ((bcma_aread32(core, BCMA_IOCTL) & (BCMA_IOCTL_CLK | BCMA_IOCTL_FGC))
	    != BCMA_IOCTL_CLK)
		return false;
	if (bcma_aread32(core, BCMA_RESET_CTL) & BCMA_RESET_CTL_RESET)
		return false;
	return true;
}
EXPORT_SYMBOL_GPL(bcma_core_is_enabled);

void bcma_core_disable(struct bcma_device *core, u32 flags)
{
	if (bcma_aread32(core, BCMA_RESET_CTL) & BCMA_RESET_CTL_RESET)
		return;

	bcma_awrite32(core, BCMA_IOCTL, flags);
	bcma_aread32(core, BCMA_IOCTL);
	udelay(10);

	bcma_awrite32(core, BCMA_RESET_CTL, BCMA_RESET_CTL_RESET);
	bcma_aread32(core, BCMA_RESET_CTL);
	udelay(1);
}
EXPORT_SYMBOL_GPL(bcma_core_disable);

int bcma_core_enable(struct bcma_device *core, u32 flags)
{
	bcma_core_disable(core, flags);

	bcma_awrite32(core, BCMA_IOCTL, (BCMA_IOCTL_CLK | BCMA_IOCTL_FGC | flags));
	bcma_aread32(core, BCMA_IOCTL);

	bcma_awrite32(core, BCMA_RESET_CTL, 0);
	udelay(1);

	bcma_awrite32(core, BCMA_IOCTL, (BCMA_IOCTL_CLK | flags));
	bcma_aread32(core, BCMA_IOCTL);
	udelay(1);

	return 0;
}
EXPORT_SYMBOL_GPL(bcma_core_enable);

void bcma_core_set_clockmode(struct bcma_device *core,
			     enum bcma_clkmode clkmode)
{
	u16 i;

	WARN_ON(core->id.id != BCMA_CORE_CHIPCOMMON &&
		core->id.id != BCMA_CORE_PCIE &&
		core->id.id != BCMA_CORE_80211);

	switch (clkmode) {
	case BCMA_CLKMODE_FAST:
		bcma_set32(core, BCMA_CLKCTLST, BCMA_CLKCTLST_FORCEHT);
		usleep_range(64, 300);
		for (i = 0; i < 1500; i++) {
			if (bcma_read32(core, BCMA_CLKCTLST) &
			    BCMA_CLKCTLST_HAVEHT) {
				i = 0;
				break;
			}
			udelay(10);
		}
		if (i)
			bcma_err(core->bus, "HT force timeout\n");
		break;
	case BCMA_CLKMODE_DYNAMIC:
		bcma_set32(core, BCMA_CLKCTLST, ~BCMA_CLKCTLST_FORCEHT);
		break;
	}
}
EXPORT_SYMBOL_GPL(bcma_core_set_clockmode);

void bcma_core_pll_ctl(struct bcma_device *core, u32 req, u32 status, bool on)
{
	u16 i;

	WARN_ON(req & ~BCMA_CLKCTLST_EXTRESREQ);
	WARN_ON(status & ~BCMA_CLKCTLST_EXTRESST);

	if (on) {
		bcma_set32(core, BCMA_CLKCTLST, req);
		for (i = 0; i < 10000; i++) {
			if ((bcma_read32(core, BCMA_CLKCTLST) & status) ==
			    status) {
				i = 0;
				break;
			}
			udelay(10);
		}
		if (i)
			bcma_err(core->bus, "PLL enable timeout\n");
	} else {
		/*
		 * Mask the PLL but don't wait for it to be disabled. PLL may be
		 * shared between cores and will be still up if there is another
		 * core using it.
		 */
		bcma_mask32(core, BCMA_CLKCTLST, ~req);
		bcma_read32(core, BCMA_CLKCTLST);
	}
}
EXPORT_SYMBOL_GPL(bcma_core_pll_ctl);

u32 bcma_core_dma_translation(struct bcma_device *core)
{
	switch (core->bus->hosttype) {
	case BCMA_HOSTTYPE_SOC:
		return 0;
	case BCMA_HOSTTYPE_PCI:
		if (bcma_aread32(core, BCMA_IOST) & BCMA_IOST_DMA64)
			return BCMA_DMA_TRANSLATION_DMA64_CMT;
		else
			return BCMA_DMA_TRANSLATION_DMA32_CMT;
	default:
		bcma_err(core->bus, "DMA translation unknown for host %d\n",
			 core->bus->hosttype);
	}
	return BCMA_DMA_TRANSLATION_NONE;
}
EXPORT_SYMBOL(bcma_core_dma_translation);
Commit	Line	Data
8369ae33 RM	1	/*
	2	* Broadcom specific AMBA
	3	* Core ops
	4	*
	5	* Licensed under the GNU/GPL. See COPYING for details.
	6	*/
	7
	8	#include "bcma_private.h"
44a8e377	9	#include <linux/export.h>
8369ae33 RM	10	#include <linux/bcma/bcma.h>
	11
	12	bool bcma_core_is_enabled(struct bcma_device *core)
	13	{
	14	if ((bcma_aread32(core, BCMA_IOCTL) & (BCMA_IOCTL_CLK \| BCMA_IOCTL_FGC))
	15	!= BCMA_IOCTL_CLK)
	16	return false;
	17	if (bcma_aread32(core, BCMA_RESET_CTL) & BCMA_RESET_CTL_RESET)
	18	return false;
	19	return true;
	20	}
	21	EXPORT_SYMBOL_GPL(bcma_core_is_enabled);
	22
e3ae0cac	23	void bcma_core_disable(struct bcma_device *core, u32 flags)
8369ae33 RM	24	{
	25	if (bcma_aread32(core, BCMA_RESET_CTL) & BCMA_RESET_CTL_RESET)
	26	return;
	27
	28	bcma_awrite32(core, BCMA_IOCTL, flags);
	29	bcma_aread32(core, BCMA_IOCTL);
	30	udelay(10);
	31
	32	bcma_awrite32(core, BCMA_RESET_CTL, BCMA_RESET_CTL_RESET);
044e68c0	33	bcma_aread32(core, BCMA_RESET_CTL);
8369ae33 RM	34	udelay(1);
8369ae33 RM	35	}
e3ae0cac	36	EXPORT_SYMBOL_GPL(bcma_core_disable);
8369ae33 RM	37
	38	int bcma_core_enable(struct bcma_device *core, u32 flags)
	39	{
	40	bcma_core_disable(core, flags);
	41
	42	bcma_awrite32(core, BCMA_IOCTL, (BCMA_IOCTL_CLK \| BCMA_IOCTL_FGC \| flags));
	43	bcma_aread32(core, BCMA_IOCTL);
	44
	45	bcma_awrite32(core, BCMA_RESET_CTL, 0);
	46	udelay(1);
	47
	48	bcma_awrite32(core, BCMA_IOCTL, (BCMA_IOCTL_CLK \| flags));
	49	bcma_aread32(core, BCMA_IOCTL);
	50	udelay(1);
	51
	52	return 0;
	53	}
	54	EXPORT_SYMBOL_GPL(bcma_core_enable);
7424dd0d RM	55
	56	void bcma_core_set_clockmode(struct bcma_device *core,
	57	enum bcma_clkmode clkmode)
	58	{
	59	u16 i;
	60
	61	WARN_ON(core->id.id != BCMA_CORE_CHIPCOMMON &&
	62	core->id.id != BCMA_CORE_PCIE &&
	63	core->id.id != BCMA_CORE_80211);
	64
	65	switch (clkmode) {
	66	case BCMA_CLKMODE_FAST:
	67	bcma_set32(core, BCMA_CLKCTLST, BCMA_CLKCTLST_FORCEHT);
1fd41a65	68	usleep_range(64, 300);
7424dd0d RM	69	for (i = 0; i < 1500; i++) {
	70	if (bcma_read32(core, BCMA_CLKCTLST) &
	71	BCMA_CLKCTLST_HAVEHT) {
	72	i = 0;
	73	break;
	74	}
	75	udelay(10);
	76	}
	77	if (i)
3d9d8af3	78	bcma_err(core->bus, "HT force timeout\n");
7424dd0d RM	79	break;
7424dd0d RM	80	case BCMA_CLKMODE_DYNAMIC:
0b2948ee	81	bcma_set32(core, BCMA_CLKCTLST, ~BCMA_CLKCTLST_FORCEHT);
7424dd0d RM	82	break;
	83	}
	84	}
	85	EXPORT_SYMBOL_GPL(bcma_core_set_clockmode);
6f53912f RM	86
	87	void bcma_core_pll_ctl(struct bcma_device *core, u32 req, u32 status, bool on)
	88	{
	89	u16 i;
	90
	91	WARN_ON(req & ~BCMA_CLKCTLST_EXTRESREQ);
	92	WARN_ON(status & ~BCMA_CLKCTLST_EXTRESST);
	93
	94	if (on) {
	95	bcma_set32(core, BCMA_CLKCTLST, req);
	96	for (i = 0; i < 10000; i++) {
	97	if ((bcma_read32(core, BCMA_CLKCTLST) & status) ==
	98	status) {
	99	i = 0;
	100	break;
	101	}
	102	udelay(10);
	103	}
	104	if (i)
3d9d8af3	105	bcma_err(core->bus, "PLL enable timeout\n");
6f53912f	106	} else {
c722839c RM	107	/*
	108	* Mask the PLL but don't wait for it to be disabled. PLL may be
	109	* shared between cores and will be still up if there is another
	110	* core using it.
	111	*/
	112	bcma_mask32(core, BCMA_CLKCTLST, ~req);
	113	bcma_read32(core, BCMA_CLKCTLST);
6f53912f RM	114	}
	115	}
	116	EXPORT_SYMBOL_GPL(bcma_core_pll_ctl);
05aec233 RM	117
	118	u32 bcma_core_dma_translation(struct bcma_device *core)
	119	{
	120	switch (core->bus->hosttype) {
ecd177c2 HM	121	case BCMA_HOSTTYPE_SOC:
ecd177c2 HM	122	return 0;
05aec233 RM	123	case BCMA_HOSTTYPE_PCI:
	124	if (bcma_aread32(core, BCMA_IOST) & BCMA_IOST_DMA64)
	125	return BCMA_DMA_TRANSLATION_DMA64_CMT;
	126	else
	127	return BCMA_DMA_TRANSLATION_DMA32_CMT;
	128	default:
3d9d8af3 RM	129	bcma_err(core->bus, "DMA translation unknown for host %d\n",
3d9d8af3 RM	130	core->bus->hosttype);
05aec233 RM	131	}
	132	return BCMA_DMA_TRANSLATION_NONE;
	133	}
	134	EXPORT_SYMBOL(bcma_core_dma_translation);