[linux-2.6-block.git] / drivers / base / regmap / regmap-mmio.c

// SPDX-License-Identifier: GPL-2.0
//
// Register map access API - MMIO support
//
// Copyright (c) 2012, NVIDIA CORPORATION.  All rights reserved.

#include <linux/clk.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/regmap.h>
#include <linux/slab.h>
#include <linux/swab.h>

#include "internal.h"

struct regmap_mmio_context {
	void __iomem *regs;
	unsigned int val_bytes;
	bool big_endian;

	bool attached_clk;
	struct clk *clk;

	void (*reg_write)(struct regmap_mmio_context *ctx,
			  unsigned int reg, unsigned int val);
	unsigned int (*reg_read)(struct regmap_mmio_context *ctx,
			         unsigned int reg);
};

static int regmap_mmio_regbits_check(size_t reg_bits)
{
	switch (reg_bits) {
	case 8:
	case 16:
	case 32:
		return 0;
	default:
		return -EINVAL;
	}
}

static int regmap_mmio_get_min_stride(size_t val_bits)
{
	int min_stride;

	switch (val_bits) {
	case 8:
		/* The core treats 0 as 1 */
		min_stride = 0;
		break;
	case 16:
		min_stride = 2;
		break;
	case 32:
		min_stride = 4;
		break;
	default:
		return -EINVAL;
	}

	return min_stride;
}

static void regmap_mmio_write8(struct regmap_mmio_context *ctx,
				unsigned int reg,
				unsigned int val)
{
	writeb(val, ctx->regs + reg);
}

static void regmap_mmio_write8_relaxed(struct regmap_mmio_context *ctx,
				unsigned int reg,
				unsigned int val)
{
	writeb_relaxed(val, ctx->regs + reg);
}

static void regmap_mmio_iowrite8(struct regmap_mmio_context *ctx,
				 unsigned int reg, unsigned int val)
{
	iowrite8(val, ctx->regs + reg);
}

static void regmap_mmio_write16le(struct regmap_mmio_context *ctx,
				  unsigned int reg,
				  unsigned int val)
{
	writew(val, ctx->regs + reg);
}

static void regmap_mmio_write16le_relaxed(struct regmap_mmio_context *ctx,
				  unsigned int reg,
				  unsigned int val)
{
	writew_relaxed(val, ctx->regs + reg);
}

static void regmap_mmio_iowrite16le(struct regmap_mmio_context *ctx,
				    unsigned int reg, unsigned int val)
{
	iowrite16(val, ctx->regs + reg);
}

static void regmap_mmio_write16be(struct regmap_mmio_context *ctx,
				  unsigned int reg,
				  unsigned int val)
{
	writew(swab16(val), ctx->regs + reg);
}

static void regmap_mmio_iowrite16be(struct regmap_mmio_context *ctx,
				    unsigned int reg, unsigned int val)
{
	iowrite16be(val, ctx->regs + reg);
}

static void regmap_mmio_write32le(struct regmap_mmio_context *ctx,
				  unsigned int reg,
				  unsigned int val)
{
	writel(val, ctx->regs + reg);
}

static void regmap_mmio_write32le_relaxed(struct regmap_mmio_context *ctx,
				  unsigned int reg,
				  unsigned int val)
{
	writel_relaxed(val, ctx->regs + reg);
}

static void regmap_mmio_iowrite32le(struct regmap_mmio_context *ctx,
				    unsigned int reg, unsigned int val)
{
	iowrite32(val, ctx->regs + reg);
}

static void regmap_mmio_write32be(struct regmap_mmio_context *ctx,
				  unsigned int reg,
				  unsigned int val)
{
	writel(swab32(val), ctx->regs + reg);
}

static void regmap_mmio_iowrite32be(struct regmap_mmio_context *ctx,
				    unsigned int reg, unsigned int val)
{
	iowrite32be(val, ctx->regs + reg);
}

static int regmap_mmio_write(void *context, unsigned int reg, unsigned int val)
{
	struct regmap_mmio_context *ctx = context;
	int ret;

	if (!IS_ERR(ctx->clk)) {
		ret = clk_enable(ctx->clk);
		if (ret < 0)
			return ret;
	}

	ctx->reg_write(ctx, reg, val);

	if (!IS_ERR(ctx->clk))
		clk_disable(ctx->clk);

	return 0;
}

static int regmap_mmio_noinc_write(void *context, unsigned int reg,
				   const void *val, size_t val_count)
{
	struct regmap_mmio_context *ctx = context;
	int ret = 0;
	int i;

	if (!IS_ERR(ctx->clk)) {
		ret = clk_enable(ctx->clk);
		if (ret < 0)
			return ret;
	}

	/*
	 * There are no native, assembly-optimized write single register
	 * operations for big endian, so fall back to emulation if this
	 * is needed. (Single bytes are fine, they are not affected by
	 * endianness.)
	 */
	if (ctx->big_endian && (ctx->val_bytes > 1)) {
		switch (ctx->val_bytes) {
		case 2:
		{
			const u16 *valp = (const u16 *)val;
			for (i = 0; i < val_count; i++)
				writew(swab16(valp[i]), ctx->regs + reg);
			goto out_clk;
		}
		case 4:
		{
			const u32 *valp = (const u32 *)val;
			for (i = 0; i < val_count; i++)
				writel(swab32(valp[i]), ctx->regs + reg);
			goto out_clk;
		}
		default:
			ret = -EINVAL;
			goto out_clk;
		}
	}

	switch (ctx->val_bytes) {
	case 1:
		writesb(ctx->regs + reg, (const u8 *)val, val_count);
		break;
	case 2:
		writesw(ctx->regs + reg, (const u16 *)val, val_count);
		break;
	case 4:
		writesl(ctx->regs + reg, (const u32 *)val, val_count);
		break;
	default:
		ret = -EINVAL;
		break;
	}

out_clk:
	if (!IS_ERR(ctx->clk))
		clk_disable(ctx->clk);

	return ret;
}

static unsigned int regmap_mmio_read8(struct regmap_mmio_context *ctx,
				      unsigned int reg)
{
	return readb(ctx->regs + reg);
}

static unsigned int regmap_mmio_read8_relaxed(struct regmap_mmio_context *ctx,
				      unsigned int reg)
{
	return readb_relaxed(ctx->regs + reg);
}

static unsigned int regmap_mmio_ioread8(struct regmap_mmio_context *ctx,
					unsigned int reg)
{
	return ioread8(ctx->regs + reg);
}

static unsigned int regmap_mmio_read16le(struct regmap_mmio_context *ctx,
				         unsigned int reg)
{
	return readw(ctx->regs + reg);
}

static unsigned int regmap_mmio_read16le_relaxed(struct regmap_mmio_context *ctx,
						 unsigned int reg)
{
	return readw_relaxed(ctx->regs + reg);
}

static unsigned int regmap_mmio_ioread16le(struct regmap_mmio_context *ctx,
					   unsigned int reg)
{
	return ioread16(ctx->regs + reg);
}

static unsigned int regmap_mmio_read16be(struct regmap_mmio_context *ctx,
				         unsigned int reg)
{
	return swab16(readw(ctx->regs + reg));
}

static unsigned int regmap_mmio_ioread16be(struct regmap_mmio_context *ctx,
					   unsigned int reg)
{
	return ioread16be(ctx->regs + reg);
}

static unsigned int regmap_mmio_read32le(struct regmap_mmio_context *ctx,
				         unsigned int reg)
{
	return readl(ctx->regs + reg);
}

static unsigned int regmap_mmio_read32le_relaxed(struct regmap_mmio_context *ctx,
						 unsigned int reg)
{
	return readl_relaxed(ctx->regs + reg);
}

static unsigned int regmap_mmio_ioread32le(struct regmap_mmio_context *ctx,
					   unsigned int reg)
{
	return ioread32(ctx->regs + reg);
}

static unsigned int regmap_mmio_read32be(struct regmap_mmio_context *ctx,
				         unsigned int reg)
{
	return swab32(readl(ctx->regs + reg));
}

static unsigned int regmap_mmio_ioread32be(struct regmap_mmio_context *ctx,
					   unsigned int reg)
{
	return ioread32be(ctx->regs + reg);
}

static int regmap_mmio_read(void *context, unsigned int reg, unsigned int *val)
{
	struct regmap_mmio_context *ctx = context;
	int ret;

	if (!IS_ERR(ctx->clk)) {
		ret = clk_enable(ctx->clk);
		if (ret < 0)
			return ret;
	}

	*val = ctx->reg_read(ctx, reg);

	if (!IS_ERR(ctx->clk))
		clk_disable(ctx->clk);

	return 0;
}

static int regmap_mmio_noinc_read(void *context, unsigned int reg,
				  void *val, size_t val_count)
{
	struct regmap_mmio_context *ctx = context;
	int ret = 0;

	if (!IS_ERR(ctx->clk)) {
		ret = clk_enable(ctx->clk);
		if (ret < 0)
			return ret;
	}

	switch (ctx->val_bytes) {
	case 1:
		readsb(ctx->regs + reg, (u8 *)val, val_count);
		break;
	case 2:
		readsw(ctx->regs + reg, (u16 *)val, val_count);
		break;
	case 4:
		readsl(ctx->regs + reg, (u32 *)val, val_count);
		break;
	default:
		ret = -EINVAL;
		goto out_clk;
	}

	/*
	 * There are no native, assembly-optimized write single register
	 * operations for big endian, so fall back to emulation if this
	 * is needed. (Single bytes are fine, they are not affected by
	 * endianness.)
	 */
	if (ctx->big_endian && (ctx->val_bytes > 1)) {
		switch (ctx->val_bytes) {
		case 2:
			swab16_array(val, val_count);
			break;
		case 4:
			swab32_array(val, val_count);
			break;
		default:
			ret = -EINVAL;
			break;
		}
	}

out_clk:
	if (!IS_ERR(ctx->clk))
		clk_disable(ctx->clk);

	return ret;
}


static void regmap_mmio_free_context(void *context)
{
	struct regmap_mmio_context *ctx = context;

	if (!IS_ERR(ctx->clk)) {
		clk_unprepare(ctx->clk);
		if (!ctx->attached_clk)
			clk_put(ctx->clk);
	}
	kfree(context);
}

static const struct regmap_bus regmap_mmio = {
	.fast_io = true,
	.reg_write = regmap_mmio_write,
	.reg_read = regmap_mmio_read,
	.reg_noinc_write = regmap_mmio_noinc_write,
	.reg_noinc_read = regmap_mmio_noinc_read,
	.free_context = regmap_mmio_free_context,
	.val_format_endian_default = REGMAP_ENDIAN_LITTLE,
};

static struct regmap_mmio_context *regmap_mmio_gen_context(struct device *dev,
					const char *clk_id,
					void __iomem *regs,
					const struct regmap_config *config)
{
	struct regmap_mmio_context *ctx;
	int min_stride;
	int ret;

	ret = regmap_mmio_regbits_check(config->reg_bits);
	if (ret)
		return ERR_PTR(ret);

	if (config->pad_bits)
		return ERR_PTR(-EINVAL);

	min_stride = regmap_mmio_get_min_stride(config->val_bits);
	if (min_stride < 0)
		return ERR_PTR(min_stride);

	if (config->reg_stride && config->reg_stride < min_stride)
		return ERR_PTR(-EINVAL);

	if (config->use_relaxed_mmio && config->io_port)
		return ERR_PTR(-EINVAL);

	ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
	if (!ctx)
		return ERR_PTR(-ENOMEM);

	ctx->regs = regs;
	ctx->val_bytes = config->val_bits / 8;
	ctx->clk = ERR_PTR(-ENODEV);

	switch (regmap_get_val_endian(dev, &regmap_mmio, config)) {
	case REGMAP_ENDIAN_DEFAULT:
	case REGMAP_ENDIAN_LITTLE:
#ifdef __LITTLE_ENDIAN
	case REGMAP_ENDIAN_NATIVE:
#endif
		switch (config->val_bits) {
		case 8:
			if (config->io_port) {
				ctx->reg_read = regmap_mmio_ioread8;
				ctx->reg_write = regmap_mmio_iowrite8;
			} else if (config->use_relaxed_mmio) {
				ctx->reg_read = regmap_mmio_read8_relaxed;
				ctx->reg_write = regmap_mmio_write8_relaxed;
			} else {
				ctx->reg_read = regmap_mmio_read8;
				ctx->reg_write = regmap_mmio_write8;
			}
			break;
		case 16:
			if (config->io_port) {
				ctx->reg_read = regmap_mmio_ioread16le;
				ctx->reg_write = regmap_mmio_iowrite16le;
			} else if (config->use_relaxed_mmio) {
				ctx->reg_read = regmap_mmio_read16le_relaxed;
				ctx->reg_write = regmap_mmio_write16le_relaxed;
			} else {
				ctx->reg_read = regmap_mmio_read16le;
				ctx->reg_write = regmap_mmio_write16le;
			}
			break;
		case 32:
			if (config->io_port) {
				ctx->reg_read = regmap_mmio_ioread32le;
				ctx->reg_write = regmap_mmio_iowrite32le;
			} else if (config->use_relaxed_mmio) {
				ctx->reg_read = regmap_mmio_read32le_relaxed;
				ctx->reg_write = regmap_mmio_write32le_relaxed;
			} else {
				ctx->reg_read = regmap_mmio_read32le;
				ctx->reg_write = regmap_mmio_write32le;
			}
			break;
		default:
			ret = -EINVAL;
			goto err_free;
		}
		break;
	case REGMAP_ENDIAN_BIG:
#ifdef __BIG_ENDIAN
	case REGMAP_ENDIAN_NATIVE:
#endif
		ctx->big_endian = true;
		switch (config->val_bits) {
		case 8:
			if (config->io_port) {
				ctx->reg_read = regmap_mmio_ioread8;
				ctx->reg_write = regmap_mmio_iowrite8;
			} else {
				ctx->reg_read = regmap_mmio_read8;
				ctx->reg_write = regmap_mmio_write8;
			}
			break;
		case 16:
			if (config->io_port) {
				ctx->reg_read = regmap_mmio_ioread16be;
				ctx->reg_write = regmap_mmio_iowrite16be;
			} else {
				ctx->reg_read = regmap_mmio_read16be;
				ctx->reg_write = regmap_mmio_write16be;
			}
			break;
		case 32:
			if (config->io_port) {
				ctx->reg_read = regmap_mmio_ioread32be;
				ctx->reg_write = regmap_mmio_iowrite32be;
			} else {
				ctx->reg_read = regmap_mmio_read32be;
				ctx->reg_write = regmap_mmio_write32be;
			}
			break;
		default:
			ret = -EINVAL;
			goto err_free;
		}
		break;
	default:
		ret = -EINVAL;
		goto err_free;
	}

	if (clk_id == NULL)
		return ctx;

	ctx->clk = clk_get(dev, clk_id);
	if (IS_ERR(ctx->clk)) {
		ret = PTR_ERR(ctx->clk);
		goto err_free;
	}

	ret = clk_prepare(ctx->clk);
	if (ret < 0) {
		clk_put(ctx->clk);
		goto err_free;
	}

	return ctx;

err_free:
	kfree(ctx);

	return ERR_PTR(ret);
}

struct regmap *__regmap_init_mmio_clk(struct device *dev, const char *clk_id,
				      void __iomem *regs,
				      const struct regmap_config *config,
				      struct lock_class_key *lock_key,
				      const char *lock_name)
{
	struct regmap_mmio_context *ctx;

	ctx = regmap_mmio_gen_context(dev, clk_id, regs, config);
	if (IS_ERR(ctx))
		return ERR_CAST(ctx);

	return __regmap_init(dev, &regmap_mmio, ctx, config,
			     lock_key, lock_name);
}
EXPORT_SYMBOL_GPL(__regmap_init_mmio_clk);

struct regmap *__devm_regmap_init_mmio_clk(struct device *dev,
					   const char *clk_id,
					   void __iomem *regs,
					   const struct regmap_config *config,
					   struct lock_class_key *lock_key,
					   const char *lock_name)
{
	struct regmap_mmio_context *ctx;

	ctx = regmap_mmio_gen_context(dev, clk_id, regs, config);
	if (IS_ERR(ctx))
		return ERR_CAST(ctx);

	return __devm_regmap_init(dev, &regmap_mmio, ctx, config,
				  lock_key, lock_name);
}
EXPORT_SYMBOL_GPL(__devm_regmap_init_mmio_clk);

int regmap_mmio_attach_clk(struct regmap *map, struct clk *clk)
{
	struct regmap_mmio_context *ctx = map->bus_context;

	ctx->clk = clk;
	ctx->attached_clk = true;

	return clk_prepare(ctx->clk);
}
EXPORT_SYMBOL_GPL(regmap_mmio_attach_clk);

void regmap_mmio_detach_clk(struct regmap *map)
{
	struct regmap_mmio_context *ctx = map->bus_context;

	clk_unprepare(ctx->clk);

	ctx->attached_clk = false;
	ctx->clk = NULL;
}
EXPORT_SYMBOL_GPL(regmap_mmio_detach_clk);

MODULE_LICENSE("GPL v2");
Commit	Line	Data
37613fa5 GKH	1	// SPDX-License-Identifier: GPL-2.0
	2	//
	3	// Register map access API - MMIO support
	4	//
	5	// Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
45f5ff81	6
878ec67b	7	#include <linux/clk.h>
45f5ff81	8	#include <linux/err.h>
45f5ff81 SW	9	#include <linux/io.h>
	10	#include <linux/module.h>
	11	#include <linux/regmap.h>
	12	#include <linux/slab.h>
400dceb6	13	#include <linux/swab.h>
45f5ff81	14
0dbdb76c MB	15	#include "internal.h"
0dbdb76c MB	16
45f5ff81 SW	17	struct regmap_mmio_context {
45f5ff81 SW	18	void __iomem *regs;
d63aa09f	19	unsigned int val_bytes;
81c0386c	20	bool big_endian;
31895662 MR	21
31895662 MR	22	bool attached_clk;
878ec67b	23	struct clk *clk;
45f5ff81	24
922a9f93 MB	25	void (reg_write)(struct regmap_mmio_context ctx,
	26	unsigned int reg, unsigned int val);
	27	unsigned int (reg_read)(struct regmap_mmio_context ctx,
	28	unsigned int reg);
	29	};
41b0c2c9	30
451485ba XL	31	static int regmap_mmio_regbits_check(size_t reg_bits)
	32	{
	33	switch (reg_bits) {
	34	case 8:
	35	case 16:
	36	case 32:
451485ba XL	37	return 0;
	38	default:
	39	return -EINVAL;
	40	}
	41	}
	42
75fb0aae XL	43	static int regmap_mmio_get_min_stride(size_t val_bits)
	44	{
	45	int min_stride;
	46
	47	switch (val_bits) {
	48	case 8:
	49	/* The core treats 0 as 1 */
	50	min_stride = 0;
01ed2307	51	break;
75fb0aae XL	52	case 16:
	53	min_stride = 2;
	54	break;
	55	case 32:
	56	min_stride = 4;
	57	break;
75fb0aae XL	58	default:
	59	return -EINVAL;
	60	}
	61
	62	return min_stride;
	63	}
	64
922a9f93 MB	65	static void regmap_mmio_write8(struct regmap_mmio_context *ctx,
	66	unsigned int reg,
	67	unsigned int val)
	68	{
	69	writeb(val, ctx->regs + reg);
	70	}
	71
6e1e90ec AR	72	static void regmap_mmio_write8_relaxed(struct regmap_mmio_context *ctx,
	73	unsigned int reg,
	74	unsigned int val)
	75	{
	76	writeb_relaxed(val, ctx->regs + reg);
	77	}
	78
93ce5576 AS	79	static void regmap_mmio_iowrite8(struct regmap_mmio_context *ctx,
	80	unsigned int reg, unsigned int val)
	81	{
	82	iowrite8(val, ctx->regs + reg);
	83	}
	84
922a9f93 MB	85	static void regmap_mmio_write16le(struct regmap_mmio_context *ctx,
	86	unsigned int reg,
	87	unsigned int val)
41b0c2c9	88	{
922a9f93	89	writew(val, ctx->regs + reg);
41b0c2c9 XL	90	}
41b0c2c9 XL	91
6e1e90ec AR	92	static void regmap_mmio_write16le_relaxed(struct regmap_mmio_context *ctx,
	93	unsigned int reg,
	94	unsigned int val)
	95	{
	96	writew_relaxed(val, ctx->regs + reg);
	97	}
	98
93ce5576 AS	99	static void regmap_mmio_iowrite16le(struct regmap_mmio_context *ctx,
	100	unsigned int reg, unsigned int val)
	101	{
	102	iowrite16(val, ctx->regs + reg);
	103	}
	104
922a9f93 MB	105	static void regmap_mmio_write16be(struct regmap_mmio_context *ctx,
	106	unsigned int reg,
	107	unsigned int val)
88cb32c6	108	{
7e7ba58c	109	writew(swab16(val), ctx->regs + reg);
922a9f93 MB	110	}
922a9f93 MB	111
93ce5576 AS	112	static void regmap_mmio_iowrite16be(struct regmap_mmio_context *ctx,
	113	unsigned int reg, unsigned int val)
	114	{
	115	iowrite16be(val, ctx->regs + reg);
	116	}
	117
922a9f93 MB	118	static void regmap_mmio_write32le(struct regmap_mmio_context *ctx,
	119	unsigned int reg,
	120	unsigned int val)
	121	{
	122	writel(val, ctx->regs + reg);
	123	}
	124
6e1e90ec AR	125	static void regmap_mmio_write32le_relaxed(struct regmap_mmio_context *ctx,
	126	unsigned int reg,
	127	unsigned int val)
	128	{
	129	writel_relaxed(val, ctx->regs + reg);
	130	}
	131
93ce5576 AS	132	static void regmap_mmio_iowrite32le(struct regmap_mmio_context *ctx,
	133	unsigned int reg, unsigned int val)
	134	{
	135	iowrite32(val, ctx->regs + reg);
	136	}
	137
922a9f93 MB	138	static void regmap_mmio_write32be(struct regmap_mmio_context *ctx,
	139	unsigned int reg,
	140	unsigned int val)
	141	{
7e7ba58c	142	writel(swab32(val), ctx->regs + reg);
922a9f93 MB	143	}
922a9f93 MB	144
93ce5576 AS	145	static void regmap_mmio_iowrite32be(struct regmap_mmio_context *ctx,
	146	unsigned int reg, unsigned int val)
	147	{
	148	iowrite32be(val, ctx->regs + reg);
	149	}
	150
922a9f93	151	static int regmap_mmio_write(void *context, unsigned int reg, unsigned int val)
45f5ff81 SW	152	{
45f5ff81 SW	153	struct regmap_mmio_context *ctx = context;
878ec67b	154	int ret;
45f5ff81	155
6b8e090e	156	if (!IS_ERR(ctx->clk)) {
878ec67b PZ	157	ret = clk_enable(ctx->clk);
	158	if (ret < 0)
	159	return ret;
	160	}
	161
922a9f93	162	ctx->reg_write(ctx, reg, val);
45f5ff81	163
6b8e090e	164	if (!IS_ERR(ctx->clk))
878ec67b PZ	165	clk_disable(ctx->clk);
878ec67b PZ	166
45f5ff81 SW	167	return 0;
	168	}
	169
81c0386c LW	170	static int regmap_mmio_noinc_write(void *context, unsigned int reg,
	171	const void *val, size_t val_count)
	172	{
	173	struct regmap_mmio_context *ctx = context;
	174	int ret = 0;
	175	int i;
	176
	177	if (!IS_ERR(ctx->clk)) {
	178	ret = clk_enable(ctx->clk);
	179	if (ret < 0)
	180	return ret;
	181	}
	182
	183	/*
	184	* There are no native, assembly-optimized write single register
	185	* operations for big endian, so fall back to emulation if this
	186	* is needed. (Single bytes are fine, they are not affected by
	187	* endianness.)
	188	*/
	189	if (ctx->big_endian && (ctx->val_bytes > 1)) {
	190	switch (ctx->val_bytes) {
	191	case 2:
	192	{
	193	const u16 valp = (const u16 )val;
	194	for (i = 0; i < val_count; i++)
	195	writew(swab16(valp[i]), ctx->regs + reg);
	196	goto out_clk;
	197	}
	198	case 4:
	199	{
	200	const u32 valp = (const u32 )val;
	201	for (i = 0; i < val_count; i++)
	202	writel(swab32(valp[i]), ctx->regs + reg);
	203	goto out_clk;
	204	}
81c0386c LW	205	default:
	206	ret = -EINVAL;
	207	goto out_clk;
	208	}
	209	}
	210
	211	switch (ctx->val_bytes) {
	212	case 1:
	213	writesb(ctx->regs + reg, (const u8 *)val, val_count);
	214	break;
	215	case 2:
	216	writesw(ctx->regs + reg, (const u16 *)val, val_count);
	217	break;
	218	case 4:
	219	writesl(ctx->regs + reg, (const u32 *)val, val_count);
	220	break;
81c0386c LW	221	default:
	222	ret = -EINVAL;
	223	break;
	224	}
	225
	226	out_clk:
	227	if (!IS_ERR(ctx->clk))
	228	clk_disable(ctx->clk);
	229
	230	return ret;
	231	}
	232
922a9f93 MB	233	static unsigned int regmap_mmio_read8(struct regmap_mmio_context *ctx,
922a9f93 MB	234	unsigned int reg)
45f5ff81	235	{
922a9f93 MB	236	return readb(ctx->regs + reg);
	237	}
	238
6e1e90ec AR	239	static unsigned int regmap_mmio_read8_relaxed(struct regmap_mmio_context *ctx,
	240	unsigned int reg)
	241	{
	242	return readb_relaxed(ctx->regs + reg);
	243	}
	244
93ce5576 AS	245	static unsigned int regmap_mmio_ioread8(struct regmap_mmio_context *ctx,
	246	unsigned int reg)
	247	{
	248	return ioread8(ctx->regs + reg);
	249	}
	250
922a9f93 MB	251	static unsigned int regmap_mmio_read16le(struct regmap_mmio_context *ctx,
	252	unsigned int reg)
	253	{
	254	return readw(ctx->regs + reg);
	255	}
	256
6e1e90ec AR	257	static unsigned int regmap_mmio_read16le_relaxed(struct regmap_mmio_context *ctx,
	258	unsigned int reg)
	259	{
	260	return readw_relaxed(ctx->regs + reg);
	261	}
	262
93ce5576 AS	263	static unsigned int regmap_mmio_ioread16le(struct regmap_mmio_context *ctx,
	264	unsigned int reg)
	265	{
	266	return ioread16(ctx->regs + reg);
	267	}
	268
922a9f93 MB	269	static unsigned int regmap_mmio_read16be(struct regmap_mmio_context *ctx,
	270	unsigned int reg)
	271	{
7e7ba58c	272	return swab16(readw(ctx->regs + reg));
922a9f93 MB	273	}
922a9f93 MB	274
93ce5576 AS	275	static unsigned int regmap_mmio_ioread16be(struct regmap_mmio_context *ctx,
	276	unsigned int reg)
	277	{
	278	return ioread16be(ctx->regs + reg);
	279	}
	280
922a9f93 MB	281	static unsigned int regmap_mmio_read32le(struct regmap_mmio_context *ctx,
	282	unsigned int reg)
	283	{
	284	return readl(ctx->regs + reg);
	285	}
93258040	286
6e1e90ec AR	287	static unsigned int regmap_mmio_read32le_relaxed(struct regmap_mmio_context *ctx,
	288	unsigned int reg)
	289	{
	290	return readl_relaxed(ctx->regs + reg);
	291	}
	292
93ce5576 AS	293	static unsigned int regmap_mmio_ioread32le(struct regmap_mmio_context *ctx,
	294	unsigned int reg)
	295	{
	296	return ioread32(ctx->regs + reg);
	297	}
	298
922a9f93 MB	299	static unsigned int regmap_mmio_read32be(struct regmap_mmio_context *ctx,
	300	unsigned int reg)
	301	{
7e7ba58c	302	return swab32(readl(ctx->regs + reg));
922a9f93	303	}
40606dba	304
93ce5576 AS	305	static unsigned int regmap_mmio_ioread32be(struct regmap_mmio_context *ctx,
	306	unsigned int reg)
	307	{
	308	return ioread32be(ctx->regs + reg);
	309	}
	310
922a9f93	311	static int regmap_mmio_read(void context, unsigned int reg, unsigned int val)
45f5ff81 SW	312	{
45f5ff81 SW	313	struct regmap_mmio_context *ctx = context;
878ec67b	314	int ret;
45f5ff81	315
6b8e090e	316	if (!IS_ERR(ctx->clk)) {
878ec67b PZ	317	ret = clk_enable(ctx->clk);
	318	if (ret < 0)
	319	return ret;
	320	}
	321
922a9f93	322	*val = ctx->reg_read(ctx, reg);
45f5ff81	323
6b8e090e	324	if (!IS_ERR(ctx->clk))
878ec67b PZ	325	clk_disable(ctx->clk);
878ec67b PZ	326
45f5ff81 SW	327	return 0;
	328	}
	329
81c0386c LW	330	static int regmap_mmio_noinc_read(void *context, unsigned int reg,
	331	void *val, size_t val_count)
	332	{
	333	struct regmap_mmio_context *ctx = context;
	334	int ret = 0;
81c0386c LW	335
	336	if (!IS_ERR(ctx->clk)) {
	337	ret = clk_enable(ctx->clk);
	338	if (ret < 0)
	339	return ret;
	340	}
	341
	342	switch (ctx->val_bytes) {
	343	case 1:
	344	readsb(ctx->regs + reg, (u8 *)val, val_count);
	345	break;
	346	case 2:
	347	readsw(ctx->regs + reg, (u16 *)val, val_count);
	348	break;
	349	case 4:
	350	readsl(ctx->regs + reg, (u32 *)val, val_count);
	351	break;
81c0386c LW	352	default:
	353	ret = -EINVAL;
	354	goto out_clk;
	355	}
	356
	357	/*
	358	* There are no native, assembly-optimized write single register
	359	* operations for big endian, so fall back to emulation if this
	360	* is needed. (Single bytes are fine, they are not affected by
	361	* endianness.)
	362	*/
	363	if (ctx->big_endian && (ctx->val_bytes > 1)) {
	364	switch (ctx->val_bytes) {
	365	case 2:
400dceb6	366	swab16_array(val, val_count);
81c0386c	367	break;
81c0386c	368	case 4:
400dceb6	369	swab32_array(val, val_count);
81c0386c	370	break;
81c0386c LW	371	default:
	372	ret = -EINVAL;
	373	break;
	374	}
	375	}
	376
81c0386c LW	377	out_clk:
	378	if (!IS_ERR(ctx->clk))
	379	clk_disable(ctx->clk);
	380
	381	return ret;
81c0386c LW	382	}
	383
	384
45f5ff81 SW	385	static void regmap_mmio_free_context(void *context)
45f5ff81 SW	386	{
878ec67b PZ	387	struct regmap_mmio_context *ctx = context;
878ec67b PZ	388
6b8e090e	389	if (!IS_ERR(ctx->clk)) {
878ec67b	390	clk_unprepare(ctx->clk);
eb4a219d JK	391	if (!ctx->attached_clk)
eb4a219d JK	392	clk_put(ctx->clk);
878ec67b	393	}
45f5ff81 SW	394	kfree(context);
	395	}
	396
922a9f93	397	static const struct regmap_bus regmap_mmio = {
45f5ff81	398	.fast_io = true,
922a9f93 MB	399	.reg_write = regmap_mmio_write,
922a9f93 MB	400	.reg_read = regmap_mmio_read,
81c0386c LW	401	.reg_noinc_write = regmap_mmio_noinc_write,
81c0386c LW	402	.reg_noinc_read = regmap_mmio_noinc_read,
45f5ff81	403	.free_context = regmap_mmio_free_context,
2ed94f6f	404	.val_format_endian_default = REGMAP_ENDIAN_LITTLE,
45f5ff81 SW	405	};
45f5ff81 SW	406
878ec67b PZ	407	static struct regmap_mmio_context regmap_mmio_gen_context(struct device dev,
	408	const char *clk_id,
	409	void __iomem *regs,
45f5ff81 SW	410	const struct regmap_config *config)
	411	{
	412	struct regmap_mmio_context *ctx;
f01ee60f	413	int min_stride;
878ec67b	414	int ret;
45f5ff81	415
451485ba XL	416	ret = regmap_mmio_regbits_check(config->reg_bits);
	417	if (ret)
	418	return ERR_PTR(ret);
45f5ff81 SW	419
	420	if (config->pad_bits)
	421	return ERR_PTR(-EINVAL);
	422
75fb0aae XL	423	min_stride = regmap_mmio_get_min_stride(config->val_bits);
	424	if (min_stride < 0)
	425	return ERR_PTR(min_stride);
45f5ff81	426
e12ff287	427	if (config->reg_stride && config->reg_stride < min_stride)
f01ee60f SW	428	return ERR_PTR(-EINVAL);
f01ee60f SW	429
93ce5576 AS	430	if (config->use_relaxed_mmio && config->io_port)
	431	return ERR_PTR(-EINVAL);
	432
46335119	433	ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
45f5ff81 SW	434	if (!ctx)
	435	return ERR_PTR(-ENOMEM);
	436
	437	ctx->regs = regs;
	438	ctx->val_bytes = config->val_bits / 8;
6b8e090e	439	ctx->clk = ERR_PTR(-ENODEV);
45f5ff81	440
0dbdb76c	441	switch (regmap_get_val_endian(dev, &regmap_mmio, config)) {
922a9f93 MB	442	case REGMAP_ENDIAN_DEFAULT:
	443	case REGMAP_ENDIAN_LITTLE:
	444	#ifdef __LITTLE_ENDIAN
	445	case REGMAP_ENDIAN_NATIVE:
	446	#endif
	447	switch (config->val_bits) {
	448	case 8:
93ce5576 AS	449	if (config->io_port) {
	450	ctx->reg_read = regmap_mmio_ioread8;
	451	ctx->reg_write = regmap_mmio_iowrite8;
	452	} else if (config->use_relaxed_mmio) {
6e1e90ec AR	453	ctx->reg_read = regmap_mmio_read8_relaxed;
	454	ctx->reg_write = regmap_mmio_write8_relaxed;
	455	} else {
	456	ctx->reg_read = regmap_mmio_read8;
	457	ctx->reg_write = regmap_mmio_write8;
	458	}
922a9f93 MB	459	break;
922a9f93 MB	460	case 16:
93ce5576 AS	461	if (config->io_port) {
	462	ctx->reg_read = regmap_mmio_ioread16le;
	463	ctx->reg_write = regmap_mmio_iowrite16le;
	464	} else if (config->use_relaxed_mmio) {
6e1e90ec AR	465	ctx->reg_read = regmap_mmio_read16le_relaxed;
	466	ctx->reg_write = regmap_mmio_write16le_relaxed;
	467	} else {
	468	ctx->reg_read = regmap_mmio_read16le;
	469	ctx->reg_write = regmap_mmio_write16le;
	470	}
922a9f93 MB	471	break;
922a9f93 MB	472	case 32:
93ce5576 AS	473	if (config->io_port) {
	474	ctx->reg_read = regmap_mmio_ioread32le;
	475	ctx->reg_write = regmap_mmio_iowrite32le;
	476	} else if (config->use_relaxed_mmio) {
6e1e90ec AR	477	ctx->reg_read = regmap_mmio_read32le_relaxed;
	478	ctx->reg_write = regmap_mmio_write32le_relaxed;
	479	} else {
	480	ctx->reg_read = regmap_mmio_read32le;
	481	ctx->reg_write = regmap_mmio_write32le;
	482	}
922a9f93	483	break;
922a9f93 MB	484	default:
	485	ret = -EINVAL;
	486	goto err_free;
	487	}
	488	break;
	489	case REGMAP_ENDIAN_BIG:
	490	#ifdef __BIG_ENDIAN
	491	case REGMAP_ENDIAN_NATIVE:
	492	#endif
81c0386c	493	ctx->big_endian = true;
922a9f93 MB	494	switch (config->val_bits) {
922a9f93 MB	495	case 8:
93ce5576 AS	496	if (config->io_port) {
	497	ctx->reg_read = regmap_mmio_ioread8;
	498	ctx->reg_write = regmap_mmio_iowrite8;
	499	} else {
	500	ctx->reg_read = regmap_mmio_read8;
	501	ctx->reg_write = regmap_mmio_write8;
	502	}
922a9f93 MB	503	break;
922a9f93 MB	504	case 16:
93ce5576 AS	505	if (config->io_port) {
	506	ctx->reg_read = regmap_mmio_ioread16be;
	507	ctx->reg_write = regmap_mmio_iowrite16be;
	508	} else {
	509	ctx->reg_read = regmap_mmio_read16be;
	510	ctx->reg_write = regmap_mmio_write16be;
	511	}
922a9f93 MB	512	break;
922a9f93 MB	513	case 32:
93ce5576 AS	514	if (config->io_port) {
	515	ctx->reg_read = regmap_mmio_ioread32be;
	516	ctx->reg_write = regmap_mmio_iowrite32be;
	517	} else {
	518	ctx->reg_read = regmap_mmio_read32be;
	519	ctx->reg_write = regmap_mmio_write32be;
	520	}
922a9f93 MB	521	break;
	522	default:
	523	ret = -EINVAL;
	524	goto err_free;
	525	}
	526	break;
	527	default:
	528	ret = -EINVAL;
	529	goto err_free;
	530	}
	531
878ec67b PZ	532	if (clk_id == NULL)
	533	return ctx;
	534
	535	ctx->clk = clk_get(dev, clk_id);
	536	if (IS_ERR(ctx->clk)) {
	537	ret = PTR_ERR(ctx->clk);
	538	goto err_free;
	539	}
	540
	541	ret = clk_prepare(ctx->clk);
	542	if (ret < 0) {
	543	clk_put(ctx->clk);
	544	goto err_free;
	545	}
	546
45f5ff81	547	return ctx;
878ec67b PZ	548
	549	err_free:
	550	kfree(ctx);
	551
	552	return ERR_PTR(ret);
45f5ff81 SW	553	}
45f5ff81 SW	554
3cfe7a74 NB	555	struct regmap __regmap_init_mmio_clk(struct device dev, const char *clk_id,
	556	void __iomem *regs,
	557	const struct regmap_config *config,
	558	struct lock_class_key *lock_key,
	559	const char *lock_name)
45f5ff81 SW	560	{
	561	struct regmap_mmio_context *ctx;
	562
878ec67b	563	ctx = regmap_mmio_gen_context(dev, clk_id, regs, config);
45f5ff81 SW	564	if (IS_ERR(ctx))
	565	return ERR_CAST(ctx);
	566
3cfe7a74 NB	567	return __regmap_init(dev, &regmap_mmio, ctx, config,
3cfe7a74 NB	568	lock_key, lock_name);
45f5ff81	569	}
3cfe7a74	570	EXPORT_SYMBOL_GPL(__regmap_init_mmio_clk);
45f5ff81	571
3cfe7a74 NB	572	struct regmap __devm_regmap_init_mmio_clk(struct device dev,
	573	const char *clk_id,
	574	void __iomem *regs,
	575	const struct regmap_config *config,
	576	struct lock_class_key *lock_key,
	577	const char *lock_name)
45f5ff81 SW	578	{
	579	struct regmap_mmio_context *ctx;
	580
878ec67b	581	ctx = regmap_mmio_gen_context(dev, clk_id, regs, config);
45f5ff81 SW	582	if (IS_ERR(ctx))
	583	return ERR_CAST(ctx);
	584
3cfe7a74 NB	585	return __devm_regmap_init(dev, &regmap_mmio, ctx, config,
3cfe7a74 NB	586	lock_key, lock_name);
45f5ff81	587	}
3cfe7a74	588	EXPORT_SYMBOL_GPL(__devm_regmap_init_mmio_clk);
45f5ff81	589
31895662 MR	590	int regmap_mmio_attach_clk(struct regmap map, struct clk clk)
	591	{
	592	struct regmap_mmio_context *ctx = map->bus_context;
	593
	594	ctx->clk = clk;
	595	ctx->attached_clk = true;
	596
	597	return clk_prepare(ctx->clk);
	598	}
	599	EXPORT_SYMBOL_GPL(regmap_mmio_attach_clk);
	600
	601	void regmap_mmio_detach_clk(struct regmap *map)
	602	{
	603	struct regmap_mmio_context *ctx = map->bus_context;
	604
	605	clk_unprepare(ctx->clk);
	606
	607	ctx->attached_clk = false;
	608	ctx->clk = NULL;
	609	}
	610	EXPORT_SYMBOL_GPL(regmap_mmio_detach_clk);
	611
45f5ff81	612	MODULE_LICENSE("GPL v2");