[linux-2.6-block.git] / drivers / base / regmap / regmap-mmio.c

/*
 * Register map access API - MMIO support
 *
 * Copyright (c) 2012, NVIDIA CORPORATION.  All rights reserved.
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
 * version 2, as published by the Free Software Foundation.
 *
 * This program is distributed in the hope it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License
 * along with this program.  If not, see <http://www.gnu.org/licenses/>.
 */

#include <linux/clk.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/module.h>
#include <linux/regmap.h>
#include <linux/slab.h>

struct regmap_mmio_context {
	void __iomem *regs;
	unsigned val_bytes;
	struct clk *clk;

	void (*reg_write)(struct regmap_mmio_context *ctx,
			  unsigned int reg, unsigned int val);
	unsigned int (*reg_read)(struct regmap_mmio_context *ctx,
			         unsigned int reg);
};

static int regmap_mmio_regbits_check(size_t reg_bits)
{
	switch (reg_bits) {
	case 8:
	case 16:
	case 32:
#ifdef CONFIG_64BIT
	case 64:
#endif
		return 0;
	default:
		return -EINVAL;
	}
}

static int regmap_mmio_get_min_stride(size_t val_bits)
{
	int min_stride;

	switch (val_bits) {
	case 8:
		/* The core treats 0 as 1 */
		min_stride = 0;
		return 0;
	case 16:
		min_stride = 2;
		break;
	case 32:
		min_stride = 4;
		break;
#ifdef CONFIG_64BIT
	case 64:
		min_stride = 8;
		break;
#endif
	default:
		return -EINVAL;
	}

	return min_stride;
}

static void regmap_mmio_write8(struct regmap_mmio_context *ctx,
				unsigned int reg,
				unsigned int val)
{
	writeb(val, ctx->regs + reg);
}

static void regmap_mmio_write16le(struct regmap_mmio_context *ctx,
				  unsigned int reg,
				  unsigned int val)
{
	writew(val, ctx->regs + reg);
}

static void regmap_mmio_write16be(struct regmap_mmio_context *ctx,
				  unsigned int reg,
				  unsigned int val)
{
	iowrite16be(val, ctx->regs + reg);
}

static void regmap_mmio_write32le(struct regmap_mmio_context *ctx,
				  unsigned int reg,
				  unsigned int val)
{
	writel(val, ctx->regs + reg);
}

static void regmap_mmio_write32be(struct regmap_mmio_context *ctx,
				  unsigned int reg,
				  unsigned int val)
{
	iowrite32be(val, ctx->regs + reg);
}

#ifdef CONFIG_64BIT
static void regmap_mmio_write64le(struct regmap_mmio_context *ctx,
				  unsigned int reg,
				  unsigned int val)
{
	writeq(val, ctx->regs + reg);
}
#endif

static int regmap_mmio_write(void *context, unsigned int reg, unsigned int val)
{
	struct regmap_mmio_context *ctx = context;
	int ret;

	if (!IS_ERR(ctx->clk)) {
		ret = clk_enable(ctx->clk);
		if (ret < 0)
			return ret;
	}

	ctx->reg_write(ctx, reg, val);

	if (!IS_ERR(ctx->clk))
		clk_disable(ctx->clk);

	return 0;
}

static unsigned int regmap_mmio_read8(struct regmap_mmio_context *ctx,
				      unsigned int reg)
{
	return readb(ctx->regs + reg);
}

static unsigned int regmap_mmio_read16le(struct regmap_mmio_context *ctx,
				         unsigned int reg)
{
	return readw(ctx->regs + reg);
}

static unsigned int regmap_mmio_read16be(struct regmap_mmio_context *ctx,
				         unsigned int reg)
{
	return ioread16be(ctx->regs + reg);
}

static unsigned int regmap_mmio_read32le(struct regmap_mmio_context *ctx,
				         unsigned int reg)
{
	return readl(ctx->regs + reg);
}

static unsigned int regmap_mmio_read32be(struct regmap_mmio_context *ctx,
				         unsigned int reg)
{
	return ioread32be(ctx->regs + reg);
}

#ifdef CONFIG_64BIT
static unsigned int regmap_mmio_read64le(struct regmap_mmio_context *ctx,
				         unsigned int reg)
{
	return readq(ctx->regs + reg);
}
#endif

static int regmap_mmio_read(void *context, unsigned int reg, unsigned int *val)
{
	struct regmap_mmio_context *ctx = context;
	int ret;

	if (!IS_ERR(ctx->clk)) {
		ret = clk_enable(ctx->clk);
		if (ret < 0)
			return ret;
	}

	*val = ctx->reg_read(ctx, reg);

	if (!IS_ERR(ctx->clk))
		clk_disable(ctx->clk);

	return 0;
}

static void regmap_mmio_free_context(void *context)
{
	struct regmap_mmio_context *ctx = context;

	if (!IS_ERR(ctx->clk)) {
		clk_unprepare(ctx->clk);
		clk_put(ctx->clk);
	}
	kfree(context);
}

static const struct regmap_bus regmap_mmio = {
	.fast_io = true,
	.reg_write = regmap_mmio_write,
	.reg_read = regmap_mmio_read,
	.free_context = regmap_mmio_free_context,
};

static struct regmap_mmio_context *regmap_mmio_gen_context(struct device *dev,
					const char *clk_id,
					void __iomem *regs,
					const struct regmap_config *config)
{
	struct regmap_mmio_context *ctx;
	int min_stride;
	int ret;

	ret = regmap_mmio_regbits_check(config->reg_bits);
	if (ret)
		return ERR_PTR(ret);

	if (config->pad_bits)
		return ERR_PTR(-EINVAL);

	min_stride = regmap_mmio_get_min_stride(config->val_bits);
	if (min_stride < 0)
		return ERR_PTR(min_stride);

	if (config->reg_stride < min_stride)
		return ERR_PTR(-EINVAL);

	ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
	if (!ctx)
		return ERR_PTR(-ENOMEM);

	ctx->regs = regs;
	ctx->val_bytes = config->val_bits / 8;
	ctx->clk = ERR_PTR(-ENODEV);

	switch (config->reg_format_endian) {
	case REGMAP_ENDIAN_DEFAULT:
	case REGMAP_ENDIAN_LITTLE:
#ifdef __LITTLE_ENDIAN
	case REGMAP_ENDIAN_NATIVE:
#endif
		switch (config->val_bits) {
		case 8:
			ctx->reg_read = regmap_mmio_read8;
			ctx->reg_write = regmap_mmio_write8;
			break;
		case 16:
			ctx->reg_read = regmap_mmio_read16le;
			ctx->reg_write = regmap_mmio_write16le;
			break;
		case 32:
			ctx->reg_read = regmap_mmio_read32le;
			ctx->reg_write = regmap_mmio_write32le;
			break;
#ifdef CONFIG_64BIT
		case 64:
			ctx->reg_read = regmap_mmio_read64le;
			ctx->reg_write = regmap_mmio_write64le;
			break;
#endif
		default:
			ret = -EINVAL;
			goto err_free;
		}
		break;
	case REGMAP_ENDIAN_BIG:
#ifdef __BIG_ENDIAN
	case REGMAP_ENDIAN_NATIVE:
#endif
		switch (config->val_bits) {
		case 8:
			ctx->reg_read = regmap_mmio_read8;
			ctx->reg_write = regmap_mmio_write8;
			break;
		case 16:
			ctx->reg_read = regmap_mmio_read16be;
			ctx->reg_write = regmap_mmio_write16be;
			break;
		case 32:
			ctx->reg_read = regmap_mmio_read32be;
			ctx->reg_write = regmap_mmio_write32be;
			break;
		default:
			ret = -EINVAL;
			goto err_free;
		}
		break;
	default:
		ret = -EINVAL;
		goto err_free;
	}

	if (clk_id == NULL)
		return ctx;

	ctx->clk = clk_get(dev, clk_id);
	if (IS_ERR(ctx->clk)) {
		ret = PTR_ERR(ctx->clk);
		goto err_free;
	}

	ret = clk_prepare(ctx->clk);
	if (ret < 0) {
		clk_put(ctx->clk);
		goto err_free;
	}

	return ctx;

err_free:
	kfree(ctx);

	return ERR_PTR(ret);
}

struct regmap *__regmap_init_mmio_clk(struct device *dev, const char *clk_id,
				      void __iomem *regs,
				      const struct regmap_config *config,
				      struct lock_class_key *lock_key,
				      const char *lock_name)
{
	struct regmap_mmio_context *ctx;

	ctx = regmap_mmio_gen_context(dev, clk_id, regs, config);
	if (IS_ERR(ctx))
		return ERR_CAST(ctx);

	return __regmap_init(dev, &regmap_mmio, ctx, config,
			     lock_key, lock_name);
}
EXPORT_SYMBOL_GPL(__regmap_init_mmio_clk);

struct regmap *__devm_regmap_init_mmio_clk(struct device *dev,
					   const char *clk_id,
					   void __iomem *regs,
					   const struct regmap_config *config,
					   struct lock_class_key *lock_key,
					   const char *lock_name)
{
	struct regmap_mmio_context *ctx;

	ctx = regmap_mmio_gen_context(dev, clk_id, regs, config);
	if (IS_ERR(ctx))
		return ERR_CAST(ctx);

	return __devm_regmap_init(dev, &regmap_mmio, ctx, config,
				  lock_key, lock_name);
}
EXPORT_SYMBOL_GPL(__devm_regmap_init_mmio_clk);

MODULE_LICENSE("GPL v2");
Commit	Line	Data
45f5ff81 SW	1	/*
	2	* Register map access API - MMIO support
	3	*
	4	* Copyright (c) 2012, NVIDIA CORPORATION. All rights reserved.
	5	*
	6	* This program is free software; you can redistribute it and/or modify it
	7	* under the terms and conditions of the GNU General Public License,
	8	* version 2, as published by the Free Software Foundation.
	9	*
	10	* This program is distributed in the hope it will be useful, but WITHOUT
	11	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	12	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	13	* more details.
	14	*
	15	* You should have received a copy of the GNU General Public License
	16	* along with this program. If not, see <http://www.gnu.org/licenses/>.
	17	*/
	18
878ec67b	19	#include <linux/clk.h>
45f5ff81	20	#include <linux/err.h>
45f5ff81 SW	21	#include <linux/io.h>
	22	#include <linux/module.h>
	23	#include <linux/regmap.h>
	24	#include <linux/slab.h>
	25
	26	struct regmap_mmio_context {
	27	void __iomem *regs;
	28	unsigned val_bytes;
878ec67b	29	struct clk *clk;
45f5ff81	30
922a9f93 MB	31	void (reg_write)(struct regmap_mmio_context ctx,
	32	unsigned int reg, unsigned int val);
	33	unsigned int (reg_read)(struct regmap_mmio_context ctx,
	34	unsigned int reg);
	35	};
41b0c2c9	36
451485ba XL	37	static int regmap_mmio_regbits_check(size_t reg_bits)
	38	{
	39	switch (reg_bits) {
	40	case 8:
	41	case 16:
	42	case 32:
	43	#ifdef CONFIG_64BIT
	44	case 64:
	45	#endif
	46	return 0;
	47	default:
	48	return -EINVAL;
	49	}
	50	}
	51
75fb0aae XL	52	static int regmap_mmio_get_min_stride(size_t val_bits)
	53	{
	54	int min_stride;
	55
	56	switch (val_bits) {
	57	case 8:
	58	/* The core treats 0 as 1 */
	59	min_stride = 0;
	60	return 0;
	61	case 16:
	62	min_stride = 2;
	63	break;
	64	case 32:
	65	min_stride = 4;
	66	break;
	67	#ifdef CONFIG_64BIT
	68	case 64:
	69	min_stride = 8;
	70	break;
	71	#endif
	72	default:
	73	return -EINVAL;
	74	}
	75
	76	return min_stride;
	77	}
	78
922a9f93 MB	79	static void regmap_mmio_write8(struct regmap_mmio_context *ctx,
	80	unsigned int reg,
	81	unsigned int val)
	82	{
	83	writeb(val, ctx->regs + reg);
	84	}
	85
	86	static void regmap_mmio_write16le(struct regmap_mmio_context *ctx,
	87	unsigned int reg,
	88	unsigned int val)
41b0c2c9	89	{
922a9f93	90	writew(val, ctx->regs + reg);
41b0c2c9 XL	91	}
41b0c2c9 XL	92
922a9f93 MB	93	static void regmap_mmio_write16be(struct regmap_mmio_context *ctx,
	94	unsigned int reg,
	95	unsigned int val)
88cb32c6	96	{
922a9f93 MB	97	iowrite16be(val, ctx->regs + reg);
	98	}
	99
	100	static void regmap_mmio_write32le(struct regmap_mmio_context *ctx,
	101	unsigned int reg,
	102	unsigned int val)
	103	{
	104	writel(val, ctx->regs + reg);
	105	}
	106
	107	static void regmap_mmio_write32be(struct regmap_mmio_context *ctx,
	108	unsigned int reg,
	109	unsigned int val)
	110	{
	111	iowrite32be(val, ctx->regs + reg);
	112	}
	113
88cb32c6	114	#ifdef CONFIG_64BIT
922a9f93 MB	115	static void regmap_mmio_write64le(struct regmap_mmio_context *ctx,
	116	unsigned int reg,
	117	unsigned int val)
	118	{
	119	writeq(val, ctx->regs + reg);
41b0c2c9	120	}
922a9f93	121	#endif
41b0c2c9	122
922a9f93	123	static int regmap_mmio_write(void *context, unsigned int reg, unsigned int val)
45f5ff81 SW	124	{
45f5ff81 SW	125	struct regmap_mmio_context *ctx = context;
878ec67b	126	int ret;
45f5ff81	127
6b8e090e	128	if (!IS_ERR(ctx->clk)) {
878ec67b PZ	129	ret = clk_enable(ctx->clk);
	130	if (ret < 0)
	131	return ret;
	132	}
	133
922a9f93	134	ctx->reg_write(ctx, reg, val);
45f5ff81	135
6b8e090e	136	if (!IS_ERR(ctx->clk))
878ec67b PZ	137	clk_disable(ctx->clk);
878ec67b PZ	138
45f5ff81 SW	139	return 0;
	140	}
	141
922a9f93 MB	142	static unsigned int regmap_mmio_read8(struct regmap_mmio_context *ctx,
922a9f93 MB	143	unsigned int reg)
45f5ff81	144	{
922a9f93 MB	145	return readb(ctx->regs + reg);
	146	}
	147
	148	static unsigned int regmap_mmio_read16le(struct regmap_mmio_context *ctx,
	149	unsigned int reg)
	150	{
	151	return readw(ctx->regs + reg);
	152	}
	153
	154	static unsigned int regmap_mmio_read16be(struct regmap_mmio_context *ctx,
	155	unsigned int reg)
	156	{
	157	return ioread16be(ctx->regs + reg);
	158	}
	159
	160	static unsigned int regmap_mmio_read32le(struct regmap_mmio_context *ctx,
	161	unsigned int reg)
	162	{
	163	return readl(ctx->regs + reg);
	164	}
93258040	165
922a9f93 MB	166	static unsigned int regmap_mmio_read32be(struct regmap_mmio_context *ctx,
	167	unsigned int reg)
	168	{
	169	return ioread32be(ctx->regs + reg);
	170	}
40606dba	171
922a9f93 MB	172	#ifdef CONFIG_64BIT
	173	static unsigned int regmap_mmio_read64le(struct regmap_mmio_context *ctx,
	174	unsigned int reg)
	175	{
	176	return readq(ctx->regs + reg);
45f5ff81	177	}
922a9f93	178	#endif
45f5ff81	179
922a9f93	180	static int regmap_mmio_read(void context, unsigned int reg, unsigned int val)
45f5ff81 SW	181	{
45f5ff81 SW	182	struct regmap_mmio_context *ctx = context;
878ec67b	183	int ret;
45f5ff81	184
6b8e090e	185	if (!IS_ERR(ctx->clk)) {
878ec67b PZ	186	ret = clk_enable(ctx->clk);
	187	if (ret < 0)
	188	return ret;
	189	}
	190
922a9f93	191	*val = ctx->reg_read(ctx, reg);
45f5ff81	192
6b8e090e	193	if (!IS_ERR(ctx->clk))
878ec67b PZ	194	clk_disable(ctx->clk);
878ec67b PZ	195
45f5ff81 SW	196	return 0;
	197	}
	198
	199	static void regmap_mmio_free_context(void *context)
	200	{
878ec67b PZ	201	struct regmap_mmio_context *ctx = context;
878ec67b PZ	202
6b8e090e	203	if (!IS_ERR(ctx->clk)) {
878ec67b PZ	204	clk_unprepare(ctx->clk);
	205	clk_put(ctx->clk);
	206	}
45f5ff81 SW	207	kfree(context);
	208	}
	209
922a9f93	210	static const struct regmap_bus regmap_mmio = {
45f5ff81	211	.fast_io = true,
922a9f93 MB	212	.reg_write = regmap_mmio_write,
922a9f93 MB	213	.reg_read = regmap_mmio_read,
45f5ff81 SW	214	.free_context = regmap_mmio_free_context,
	215	};
	216
878ec67b PZ	217	static struct regmap_mmio_context regmap_mmio_gen_context(struct device dev,
	218	const char *clk_id,
	219	void __iomem *regs,
45f5ff81 SW	220	const struct regmap_config *config)
	221	{
	222	struct regmap_mmio_context *ctx;
f01ee60f	223	int min_stride;
878ec67b	224	int ret;
45f5ff81	225
451485ba XL	226	ret = regmap_mmio_regbits_check(config->reg_bits);
	227	if (ret)
	228	return ERR_PTR(ret);
45f5ff81 SW	229
	230	if (config->pad_bits)
	231	return ERR_PTR(-EINVAL);
	232
75fb0aae XL	233	min_stride = regmap_mmio_get_min_stride(config->val_bits);
	234	if (min_stride < 0)
	235	return ERR_PTR(min_stride);
45f5ff81	236
f01ee60f SW	237	if (config->reg_stride < min_stride)
	238	return ERR_PTR(-EINVAL);
	239
46335119	240	ctx = kzalloc(sizeof(*ctx), GFP_KERNEL);
45f5ff81 SW	241	if (!ctx)
	242	return ERR_PTR(-ENOMEM);
	243
	244	ctx->regs = regs;
	245	ctx->val_bytes = config->val_bits / 8;
6b8e090e	246	ctx->clk = ERR_PTR(-ENODEV);
45f5ff81	247
922a9f93 MB	248	switch (config->reg_format_endian) {
	249	case REGMAP_ENDIAN_DEFAULT:
	250	case REGMAP_ENDIAN_LITTLE:
	251	#ifdef __LITTLE_ENDIAN
	252	case REGMAP_ENDIAN_NATIVE:
	253	#endif
	254	switch (config->val_bits) {
	255	case 8:
	256	ctx->reg_read = regmap_mmio_read8;
	257	ctx->reg_write = regmap_mmio_write8;
	258	break;
	259	case 16:
	260	ctx->reg_read = regmap_mmio_read16le;
	261	ctx->reg_write = regmap_mmio_write16le;
	262	break;
	263	case 32:
	264	ctx->reg_read = regmap_mmio_read32le;
	265	ctx->reg_write = regmap_mmio_write32le;
	266	break;
	267	#ifdef CONFIG_64BIT
	268	case 64:
	269	ctx->reg_read = regmap_mmio_read64le;
	270	ctx->reg_write = regmap_mmio_write64le;
	271	break;
	272	#endif
	273	default:
	274	ret = -EINVAL;
	275	goto err_free;
	276	}
	277	break;
	278	case REGMAP_ENDIAN_BIG:
	279	#ifdef __BIG_ENDIAN
	280	case REGMAP_ENDIAN_NATIVE:
	281	#endif
	282	switch (config->val_bits) {
	283	case 8:
	284	ctx->reg_read = regmap_mmio_read8;
	285	ctx->reg_write = regmap_mmio_write8;
	286	break;
	287	case 16:
	288	ctx->reg_read = regmap_mmio_read16be;
	289	ctx->reg_write = regmap_mmio_write16be;
	290	break;
	291	case 32:
	292	ctx->reg_read = regmap_mmio_read32be;
	293	ctx->reg_write = regmap_mmio_write32be;
	294	break;
	295	default:
	296	ret = -EINVAL;
	297	goto err_free;
	298	}
	299	break;
	300	default:
	301	ret = -EINVAL;
	302	goto err_free;
	303	}
	304
878ec67b PZ	305	if (clk_id == NULL)
	306	return ctx;
	307
	308	ctx->clk = clk_get(dev, clk_id);
	309	if (IS_ERR(ctx->clk)) {
	310	ret = PTR_ERR(ctx->clk);
	311	goto err_free;
	312	}
	313
	314	ret = clk_prepare(ctx->clk);
	315	if (ret < 0) {
	316	clk_put(ctx->clk);
	317	goto err_free;
	318	}
	319
45f5ff81	320	return ctx;
878ec67b PZ	321
	322	err_free:
	323	kfree(ctx);
	324
	325	return ERR_PTR(ret);
45f5ff81 SW	326	}
45f5ff81 SW	327
3cfe7a74 NB	328	struct regmap __regmap_init_mmio_clk(struct device dev, const char *clk_id,
	329	void __iomem *regs,
	330	const struct regmap_config *config,
	331	struct lock_class_key *lock_key,
	332	const char *lock_name)
45f5ff81 SW	333	{
	334	struct regmap_mmio_context *ctx;
	335
878ec67b	336	ctx = regmap_mmio_gen_context(dev, clk_id, regs, config);
45f5ff81 SW	337	if (IS_ERR(ctx))
	338	return ERR_CAST(ctx);
	339
3cfe7a74 NB	340	return __regmap_init(dev, &regmap_mmio, ctx, config,
3cfe7a74 NB	341	lock_key, lock_name);
45f5ff81	342	}
3cfe7a74	343	EXPORT_SYMBOL_GPL(__regmap_init_mmio_clk);
45f5ff81	344
3cfe7a74 NB	345	struct regmap __devm_regmap_init_mmio_clk(struct device dev,
	346	const char *clk_id,
	347	void __iomem *regs,
	348	const struct regmap_config *config,
	349	struct lock_class_key *lock_key,
	350	const char *lock_name)
45f5ff81 SW	351	{
	352	struct regmap_mmio_context *ctx;
	353
878ec67b	354	ctx = regmap_mmio_gen_context(dev, clk_id, regs, config);
45f5ff81 SW	355	if (IS_ERR(ctx))
	356	return ERR_CAST(ctx);
	357
3cfe7a74 NB	358	return __devm_regmap_init(dev, &regmap_mmio, ctx, config,
3cfe7a74 NB	359	lock_key, lock_name);
45f5ff81	360	}
3cfe7a74	361	EXPORT_SYMBOL_GPL(__devm_regmap_init_mmio_clk);
45f5ff81 SW	362
45f5ff81 SW	363	MODULE_LICENSE("GPL v2");