Commit | Line | Data |
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9fabe24e DP |
1 | /* |
2 | * Register cache access API | |
3 | * | |
4 | * Copyright 2011 Wolfson Microelectronics plc | |
5 | * | |
6 | * Author: Dimitris Papastamos <dp@opensource.wolfsonmicro.com> | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | */ | |
12 | ||
f094fea6 | 13 | #include <linux/bsearch.h> |
e39be3a3 XL |
14 | #include <linux/device.h> |
15 | #include <linux/export.h> | |
16 | #include <linux/slab.h> | |
c08604b8 | 17 | #include <linux/sort.h> |
e39be3a3 | 18 | #include <trace/events/regmap.h> |
9fabe24e DP |
19 | |
20 | #include "internal.h" | |
21 | ||
22 | static const struct regcache_ops *cache_types[] = { | |
28644c80 | 23 | ®cache_rbtree_ops, |
2cbbb579 | 24 | ®cache_lzo_ops, |
2ac902ce | 25 | ®cache_flat_ops, |
9fabe24e DP |
26 | }; |
27 | ||
28 | static int regcache_hw_init(struct regmap *map) | |
29 | { | |
30 | int i, j; | |
31 | int ret; | |
32 | int count; | |
33 | unsigned int val; | |
34 | void *tmp_buf; | |
35 | ||
36 | if (!map->num_reg_defaults_raw) | |
37 | return -EINVAL; | |
38 | ||
fb70067e XL |
39 | /* calculate the size of reg_defaults */ |
40 | for (count = 0, i = 0; i < map->num_reg_defaults_raw; i++) | |
41 | if (!regmap_volatile(map, i * map->reg_stride)) | |
42 | count++; | |
43 | ||
44 | /* all registers are volatile, so just bypass */ | |
45 | if (!count) { | |
46 | map->cache_bypass = true; | |
47 | return 0; | |
48 | } | |
49 | ||
50 | map->num_reg_defaults = count; | |
51 | map->reg_defaults = kmalloc_array(count, sizeof(struct reg_default), | |
52 | GFP_KERNEL); | |
53 | if (!map->reg_defaults) | |
54 | return -ENOMEM; | |
55 | ||
9fabe24e | 56 | if (!map->reg_defaults_raw) { |
df00c79f | 57 | u32 cache_bypass = map->cache_bypass; |
9fabe24e | 58 | dev_warn(map->dev, "No cache defaults, reading back from HW\n"); |
df00c79f LD |
59 | |
60 | /* Bypass the cache access till data read from HW*/ | |
61 | map->cache_bypass = 1; | |
9fabe24e | 62 | tmp_buf = kmalloc(map->cache_size_raw, GFP_KERNEL); |
fb70067e XL |
63 | if (!tmp_buf) { |
64 | ret = -ENOMEM; | |
65 | goto err_free; | |
66 | } | |
eb4cb76f MB |
67 | ret = regmap_raw_read(map, 0, tmp_buf, |
68 | map->num_reg_defaults_raw); | |
df00c79f | 69 | map->cache_bypass = cache_bypass; |
fb70067e XL |
70 | if (ret < 0) |
71 | goto err_cache_free; | |
72 | ||
9fabe24e DP |
73 | map->reg_defaults_raw = tmp_buf; |
74 | map->cache_free = 1; | |
75 | } | |
76 | ||
9fabe24e | 77 | /* fill the reg_defaults */ |
9fabe24e | 78 | for (i = 0, j = 0; i < map->num_reg_defaults_raw; i++) { |
f01ee60f | 79 | if (regmap_volatile(map, i * map->reg_stride)) |
9fabe24e | 80 | continue; |
fbba43c5 | 81 | val = regcache_get_val(map, map->reg_defaults_raw, i); |
f01ee60f | 82 | map->reg_defaults[j].reg = i * map->reg_stride; |
9fabe24e DP |
83 | map->reg_defaults[j].def = val; |
84 | j++; | |
85 | } | |
86 | ||
87 | return 0; | |
021cd616 | 88 | |
fb70067e XL |
89 | err_cache_free: |
90 | kfree(tmp_buf); | |
021cd616 | 91 | err_free: |
fb70067e | 92 | kfree(map->reg_defaults); |
021cd616 LPC |
93 | |
94 | return ret; | |
9fabe24e DP |
95 | } |
96 | ||
e5e3b8ab | 97 | int regcache_init(struct regmap *map, const struct regmap_config *config) |
9fabe24e DP |
98 | { |
99 | int ret; | |
100 | int i; | |
101 | void *tmp_buf; | |
102 | ||
f01ee60f SW |
103 | for (i = 0; i < config->num_reg_defaults; i++) |
104 | if (config->reg_defaults[i].reg % map->reg_stride) | |
105 | return -EINVAL; | |
106 | ||
e7a6db30 MB |
107 | if (map->cache_type == REGCACHE_NONE) { |
108 | map->cache_bypass = true; | |
9fabe24e | 109 | return 0; |
e7a6db30 | 110 | } |
9fabe24e DP |
111 | |
112 | for (i = 0; i < ARRAY_SIZE(cache_types); i++) | |
113 | if (cache_types[i]->type == map->cache_type) | |
114 | break; | |
115 | ||
116 | if (i == ARRAY_SIZE(cache_types)) { | |
117 | dev_err(map->dev, "Could not match compress type: %d\n", | |
118 | map->cache_type); | |
119 | return -EINVAL; | |
120 | } | |
121 | ||
e5e3b8ab LPC |
122 | map->num_reg_defaults = config->num_reg_defaults; |
123 | map->num_reg_defaults_raw = config->num_reg_defaults_raw; | |
124 | map->reg_defaults_raw = config->reg_defaults_raw; | |
064d4db1 LPC |
125 | map->cache_word_size = DIV_ROUND_UP(config->val_bits, 8); |
126 | map->cache_size_raw = map->cache_word_size * config->num_reg_defaults_raw; | |
e5e3b8ab | 127 | |
9fabe24e DP |
128 | map->cache = NULL; |
129 | map->cache_ops = cache_types[i]; | |
130 | ||
131 | if (!map->cache_ops->read || | |
132 | !map->cache_ops->write || | |
133 | !map->cache_ops->name) | |
134 | return -EINVAL; | |
135 | ||
136 | /* We still need to ensure that the reg_defaults | |
137 | * won't vanish from under us. We'll need to make | |
138 | * a copy of it. | |
139 | */ | |
720e4616 | 140 | if (config->reg_defaults) { |
9fabe24e DP |
141 | if (!map->num_reg_defaults) |
142 | return -EINVAL; | |
720e4616 | 143 | tmp_buf = kmemdup(config->reg_defaults, map->num_reg_defaults * |
9fabe24e DP |
144 | sizeof(struct reg_default), GFP_KERNEL); |
145 | if (!tmp_buf) | |
146 | return -ENOMEM; | |
147 | map->reg_defaults = tmp_buf; | |
8528bdd4 | 148 | } else if (map->num_reg_defaults_raw) { |
5fcd2560 | 149 | /* Some devices such as PMICs don't have cache defaults, |
9fabe24e DP |
150 | * we cope with this by reading back the HW registers and |
151 | * crafting the cache defaults by hand. | |
152 | */ | |
153 | ret = regcache_hw_init(map); | |
154 | if (ret < 0) | |
155 | return ret; | |
fb70067e XL |
156 | if (map->cache_bypass) |
157 | return 0; | |
9fabe24e DP |
158 | } |
159 | ||
160 | if (!map->max_register) | |
161 | map->max_register = map->num_reg_defaults_raw; | |
162 | ||
163 | if (map->cache_ops->init) { | |
164 | dev_dbg(map->dev, "Initializing %s cache\n", | |
165 | map->cache_ops->name); | |
bd061c78 LPC |
166 | ret = map->cache_ops->init(map); |
167 | if (ret) | |
168 | goto err_free; | |
9fabe24e DP |
169 | } |
170 | return 0; | |
bd061c78 LPC |
171 | |
172 | err_free: | |
173 | kfree(map->reg_defaults); | |
174 | if (map->cache_free) | |
175 | kfree(map->reg_defaults_raw); | |
176 | ||
177 | return ret; | |
9fabe24e DP |
178 | } |
179 | ||
180 | void regcache_exit(struct regmap *map) | |
181 | { | |
182 | if (map->cache_type == REGCACHE_NONE) | |
183 | return; | |
184 | ||
185 | BUG_ON(!map->cache_ops); | |
186 | ||
187 | kfree(map->reg_defaults); | |
188 | if (map->cache_free) | |
189 | kfree(map->reg_defaults_raw); | |
190 | ||
191 | if (map->cache_ops->exit) { | |
192 | dev_dbg(map->dev, "Destroying %s cache\n", | |
193 | map->cache_ops->name); | |
194 | map->cache_ops->exit(map); | |
195 | } | |
196 | } | |
197 | ||
198 | /** | |
199 | * regcache_read: Fetch the value of a given register from the cache. | |
200 | * | |
201 | * @map: map to configure. | |
202 | * @reg: The register index. | |
203 | * @value: The value to be returned. | |
204 | * | |
205 | * Return a negative value on failure, 0 on success. | |
206 | */ | |
207 | int regcache_read(struct regmap *map, | |
208 | unsigned int reg, unsigned int *value) | |
209 | { | |
bc7ee556 MB |
210 | int ret; |
211 | ||
9fabe24e DP |
212 | if (map->cache_type == REGCACHE_NONE) |
213 | return -ENOSYS; | |
214 | ||
215 | BUG_ON(!map->cache_ops); | |
216 | ||
bc7ee556 MB |
217 | if (!regmap_volatile(map, reg)) { |
218 | ret = map->cache_ops->read(map, reg, value); | |
219 | ||
220 | if (ret == 0) | |
221 | trace_regmap_reg_read_cache(map->dev, reg, *value); | |
222 | ||
223 | return ret; | |
224 | } | |
9fabe24e DP |
225 | |
226 | return -EINVAL; | |
227 | } | |
9fabe24e DP |
228 | |
229 | /** | |
230 | * regcache_write: Set the value of a given register in the cache. | |
231 | * | |
232 | * @map: map to configure. | |
233 | * @reg: The register index. | |
234 | * @value: The new register value. | |
235 | * | |
236 | * Return a negative value on failure, 0 on success. | |
237 | */ | |
238 | int regcache_write(struct regmap *map, | |
239 | unsigned int reg, unsigned int value) | |
240 | { | |
241 | if (map->cache_type == REGCACHE_NONE) | |
242 | return 0; | |
243 | ||
244 | BUG_ON(!map->cache_ops); | |
245 | ||
9fabe24e DP |
246 | if (!regmap_volatile(map, reg)) |
247 | return map->cache_ops->write(map, reg, value); | |
248 | ||
249 | return 0; | |
250 | } | |
9fabe24e | 251 | |
d856fce4 MH |
252 | static int regcache_default_sync(struct regmap *map, unsigned int min, |
253 | unsigned int max) | |
254 | { | |
255 | unsigned int reg; | |
256 | ||
75617328 | 257 | for (reg = min; reg <= max; reg += map->reg_stride) { |
d856fce4 MH |
258 | unsigned int val; |
259 | int ret; | |
260 | ||
83f8475c DR |
261 | if (regmap_volatile(map, reg) || |
262 | !regmap_writeable(map, reg)) | |
d856fce4 MH |
263 | continue; |
264 | ||
265 | ret = regcache_read(map, reg, &val); | |
266 | if (ret) | |
267 | return ret; | |
268 | ||
269 | /* Is this the hardware default? If so skip. */ | |
270 | ret = regcache_lookup_reg(map, reg); | |
271 | if (ret >= 0 && val == map->reg_defaults[ret].def) | |
272 | continue; | |
273 | ||
274 | map->cache_bypass = 1; | |
275 | ret = _regmap_write(map, reg, val); | |
276 | map->cache_bypass = 0; | |
f29a4320 JN |
277 | if (ret) { |
278 | dev_err(map->dev, "Unable to sync register %#x. %d\n", | |
279 | reg, ret); | |
d856fce4 | 280 | return ret; |
f29a4320 | 281 | } |
d856fce4 MH |
282 | dev_dbg(map->dev, "Synced register %#x, value %#x\n", reg, val); |
283 | } | |
284 | ||
285 | return 0; | |
286 | } | |
287 | ||
9fabe24e DP |
288 | /** |
289 | * regcache_sync: Sync the register cache with the hardware. | |
290 | * | |
291 | * @map: map to configure. | |
292 | * | |
293 | * Any registers that should not be synced should be marked as | |
294 | * volatile. In general drivers can choose not to use the provided | |
295 | * syncing functionality if they so require. | |
296 | * | |
297 | * Return a negative value on failure, 0 on success. | |
298 | */ | |
299 | int regcache_sync(struct regmap *map) | |
300 | { | |
954757d7 | 301 | int ret = 0; |
954757d7 | 302 | unsigned int i; |
59360089 | 303 | const char *name; |
beb1a10f | 304 | unsigned int bypass; |
59360089 | 305 | |
d856fce4 | 306 | BUG_ON(!map->cache_ops); |
9fabe24e | 307 | |
81485f52 | 308 | map->lock(map->lock_arg); |
beb1a10f DP |
309 | /* Remember the initial bypass state */ |
310 | bypass = map->cache_bypass; | |
954757d7 DP |
311 | dev_dbg(map->dev, "Syncing %s cache\n", |
312 | map->cache_ops->name); | |
313 | name = map->cache_ops->name; | |
314 | trace_regcache_sync(map->dev, name, "start"); | |
22f0d90a | 315 | |
8ae0d7e8 MB |
316 | if (!map->cache_dirty) |
317 | goto out; | |
d9db7627 | 318 | |
affbe886 MB |
319 | map->async = true; |
320 | ||
22f0d90a | 321 | /* Apply any patch first */ |
8a892d69 | 322 | map->cache_bypass = 1; |
22f0d90a MB |
323 | for (i = 0; i < map->patch_regs; i++) { |
324 | ret = _regmap_write(map, map->patch[i].reg, map->patch[i].def); | |
325 | if (ret != 0) { | |
326 | dev_err(map->dev, "Failed to write %x = %x: %d\n", | |
327 | map->patch[i].reg, map->patch[i].def, ret); | |
328 | goto out; | |
329 | } | |
330 | } | |
8a892d69 | 331 | map->cache_bypass = 0; |
22f0d90a | 332 | |
d856fce4 MH |
333 | if (map->cache_ops->sync) |
334 | ret = map->cache_ops->sync(map, 0, map->max_register); | |
335 | else | |
336 | ret = regcache_default_sync(map, 0, map->max_register); | |
954757d7 | 337 | |
6ff73738 MB |
338 | if (ret == 0) |
339 | map->cache_dirty = false; | |
954757d7 | 340 | |
954757d7 | 341 | out: |
beb1a10f | 342 | /* Restore the bypass state */ |
affbe886 | 343 | map->async = false; |
beb1a10f | 344 | map->cache_bypass = bypass; |
81485f52 | 345 | map->unlock(map->lock_arg); |
954757d7 | 346 | |
affbe886 MB |
347 | regmap_async_complete(map); |
348 | ||
349 | trace_regcache_sync(map->dev, name, "stop"); | |
350 | ||
954757d7 | 351 | return ret; |
9fabe24e DP |
352 | } |
353 | EXPORT_SYMBOL_GPL(regcache_sync); | |
354 | ||
4d4cfd16 MB |
355 | /** |
356 | * regcache_sync_region: Sync part of the register cache with the hardware. | |
357 | * | |
358 | * @map: map to sync. | |
359 | * @min: first register to sync | |
360 | * @max: last register to sync | |
361 | * | |
362 | * Write all non-default register values in the specified region to | |
363 | * the hardware. | |
364 | * | |
365 | * Return a negative value on failure, 0 on success. | |
366 | */ | |
367 | int regcache_sync_region(struct regmap *map, unsigned int min, | |
368 | unsigned int max) | |
369 | { | |
370 | int ret = 0; | |
371 | const char *name; | |
372 | unsigned int bypass; | |
373 | ||
d856fce4 | 374 | BUG_ON(!map->cache_ops); |
4d4cfd16 | 375 | |
81485f52 | 376 | map->lock(map->lock_arg); |
4d4cfd16 MB |
377 | |
378 | /* Remember the initial bypass state */ | |
379 | bypass = map->cache_bypass; | |
380 | ||
381 | name = map->cache_ops->name; | |
382 | dev_dbg(map->dev, "Syncing %s cache from %d-%d\n", name, min, max); | |
383 | ||
384 | trace_regcache_sync(map->dev, name, "start region"); | |
385 | ||
386 | if (!map->cache_dirty) | |
387 | goto out; | |
388 | ||
affbe886 MB |
389 | map->async = true; |
390 | ||
d856fce4 MH |
391 | if (map->cache_ops->sync) |
392 | ret = map->cache_ops->sync(map, min, max); | |
393 | else | |
394 | ret = regcache_default_sync(map, min, max); | |
4d4cfd16 MB |
395 | |
396 | out: | |
4d4cfd16 MB |
397 | /* Restore the bypass state */ |
398 | map->cache_bypass = bypass; | |
affbe886 | 399 | map->async = false; |
81485f52 | 400 | map->unlock(map->lock_arg); |
4d4cfd16 | 401 | |
affbe886 MB |
402 | regmap_async_complete(map); |
403 | ||
404 | trace_regcache_sync(map->dev, name, "stop region"); | |
405 | ||
4d4cfd16 MB |
406 | return ret; |
407 | } | |
e466de05 | 408 | EXPORT_SYMBOL_GPL(regcache_sync_region); |
4d4cfd16 | 409 | |
697e85bc MB |
410 | /** |
411 | * regcache_drop_region: Discard part of the register cache | |
412 | * | |
413 | * @map: map to operate on | |
414 | * @min: first register to discard | |
415 | * @max: last register to discard | |
416 | * | |
417 | * Discard part of the register cache. | |
418 | * | |
419 | * Return a negative value on failure, 0 on success. | |
420 | */ | |
421 | int regcache_drop_region(struct regmap *map, unsigned int min, | |
422 | unsigned int max) | |
423 | { | |
697e85bc MB |
424 | int ret = 0; |
425 | ||
3f4ff561 | 426 | if (!map->cache_ops || !map->cache_ops->drop) |
697e85bc MB |
427 | return -EINVAL; |
428 | ||
81485f52 | 429 | map->lock(map->lock_arg); |
697e85bc MB |
430 | |
431 | trace_regcache_drop_region(map->dev, min, max); | |
432 | ||
3f4ff561 | 433 | ret = map->cache_ops->drop(map, min, max); |
697e85bc | 434 | |
81485f52 | 435 | map->unlock(map->lock_arg); |
697e85bc MB |
436 | |
437 | return ret; | |
438 | } | |
439 | EXPORT_SYMBOL_GPL(regcache_drop_region); | |
440 | ||
92afb286 MB |
441 | /** |
442 | * regcache_cache_only: Put a register map into cache only mode | |
443 | * | |
444 | * @map: map to configure | |
445 | * @cache_only: flag if changes should be written to the hardware | |
446 | * | |
447 | * When a register map is marked as cache only writes to the register | |
448 | * map API will only update the register cache, they will not cause | |
449 | * any hardware changes. This is useful for allowing portions of | |
450 | * drivers to act as though the device were functioning as normal when | |
451 | * it is disabled for power saving reasons. | |
452 | */ | |
453 | void regcache_cache_only(struct regmap *map, bool enable) | |
454 | { | |
81485f52 | 455 | map->lock(map->lock_arg); |
ac77a765 | 456 | WARN_ON(map->cache_bypass && enable); |
92afb286 | 457 | map->cache_only = enable; |
5d5b7d4f | 458 | trace_regmap_cache_only(map->dev, enable); |
81485f52 | 459 | map->unlock(map->lock_arg); |
92afb286 MB |
460 | } |
461 | EXPORT_SYMBOL_GPL(regcache_cache_only); | |
462 | ||
8ae0d7e8 MB |
463 | /** |
464 | * regcache_mark_dirty: Mark the register cache as dirty | |
465 | * | |
466 | * @map: map to mark | |
467 | * | |
468 | * Mark the register cache as dirty, for example due to the device | |
469 | * having been powered down for suspend. If the cache is not marked | |
470 | * as dirty then the cache sync will be suppressed. | |
471 | */ | |
472 | void regcache_mark_dirty(struct regmap *map) | |
473 | { | |
81485f52 | 474 | map->lock(map->lock_arg); |
8ae0d7e8 | 475 | map->cache_dirty = true; |
81485f52 | 476 | map->unlock(map->lock_arg); |
8ae0d7e8 MB |
477 | } |
478 | EXPORT_SYMBOL_GPL(regcache_mark_dirty); | |
479 | ||
6eb0f5e0 DP |
480 | /** |
481 | * regcache_cache_bypass: Put a register map into cache bypass mode | |
482 | * | |
483 | * @map: map to configure | |
0eef6b04 | 484 | * @cache_bypass: flag if changes should not be written to the hardware |
6eb0f5e0 DP |
485 | * |
486 | * When a register map is marked with the cache bypass option, writes | |
487 | * to the register map API will only update the hardware and not the | |
488 | * the cache directly. This is useful when syncing the cache back to | |
489 | * the hardware. | |
490 | */ | |
491 | void regcache_cache_bypass(struct regmap *map, bool enable) | |
492 | { | |
81485f52 | 493 | map->lock(map->lock_arg); |
ac77a765 | 494 | WARN_ON(map->cache_only && enable); |
6eb0f5e0 | 495 | map->cache_bypass = enable; |
5d5b7d4f | 496 | trace_regmap_cache_bypass(map->dev, enable); |
81485f52 | 497 | map->unlock(map->lock_arg); |
6eb0f5e0 DP |
498 | } |
499 | EXPORT_SYMBOL_GPL(regcache_cache_bypass); | |
500 | ||
879082c9 MB |
501 | bool regcache_set_val(struct regmap *map, void *base, unsigned int idx, |
502 | unsigned int val) | |
9fabe24e | 503 | { |
325acab4 MB |
504 | if (regcache_get_val(map, base, idx) == val) |
505 | return true; | |
506 | ||
eb4cb76f MB |
507 | /* Use device native format if possible */ |
508 | if (map->format.format_val) { | |
509 | map->format.format_val(base + (map->cache_word_size * idx), | |
510 | val, 0); | |
511 | return false; | |
512 | } | |
513 | ||
879082c9 | 514 | switch (map->cache_word_size) { |
9fabe24e DP |
515 | case 1: { |
516 | u8 *cache = base; | |
9fabe24e DP |
517 | cache[idx] = val; |
518 | break; | |
519 | } | |
520 | case 2: { | |
521 | u16 *cache = base; | |
9fabe24e DP |
522 | cache[idx] = val; |
523 | break; | |
524 | } | |
7d5e525b MB |
525 | case 4: { |
526 | u32 *cache = base; | |
7d5e525b MB |
527 | cache[idx] = val; |
528 | break; | |
529 | } | |
9fabe24e DP |
530 | default: |
531 | BUG(); | |
532 | } | |
9fabe24e DP |
533 | return false; |
534 | } | |
535 | ||
879082c9 MB |
536 | unsigned int regcache_get_val(struct regmap *map, const void *base, |
537 | unsigned int idx) | |
9fabe24e DP |
538 | { |
539 | if (!base) | |
540 | return -EINVAL; | |
541 | ||
eb4cb76f MB |
542 | /* Use device native format if possible */ |
543 | if (map->format.parse_val) | |
8817796b MB |
544 | return map->format.parse_val(regcache_get_val_addr(map, base, |
545 | idx)); | |
eb4cb76f | 546 | |
879082c9 | 547 | switch (map->cache_word_size) { |
9fabe24e DP |
548 | case 1: { |
549 | const u8 *cache = base; | |
550 | return cache[idx]; | |
551 | } | |
552 | case 2: { | |
553 | const u16 *cache = base; | |
554 | return cache[idx]; | |
555 | } | |
7d5e525b MB |
556 | case 4: { |
557 | const u32 *cache = base; | |
558 | return cache[idx]; | |
559 | } | |
9fabe24e DP |
560 | default: |
561 | BUG(); | |
562 | } | |
563 | /* unreachable */ | |
564 | return -1; | |
565 | } | |
566 | ||
f094fea6 | 567 | static int regcache_default_cmp(const void *a, const void *b) |
c08604b8 DP |
568 | { |
569 | const struct reg_default *_a = a; | |
570 | const struct reg_default *_b = b; | |
571 | ||
572 | return _a->reg - _b->reg; | |
573 | } | |
574 | ||
f094fea6 MB |
575 | int regcache_lookup_reg(struct regmap *map, unsigned int reg) |
576 | { | |
577 | struct reg_default key; | |
578 | struct reg_default *r; | |
579 | ||
580 | key.reg = reg; | |
581 | key.def = 0; | |
582 | ||
583 | r = bsearch(&key, map->reg_defaults, map->num_reg_defaults, | |
584 | sizeof(struct reg_default), regcache_default_cmp); | |
585 | ||
586 | if (r) | |
587 | return r - map->reg_defaults; | |
588 | else | |
6e6ace00 | 589 | return -ENOENT; |
f094fea6 | 590 | } |
f8bd822c | 591 | |
3f4ff561 LPC |
592 | static bool regcache_reg_present(unsigned long *cache_present, unsigned int idx) |
593 | { | |
594 | if (!cache_present) | |
595 | return true; | |
596 | ||
597 | return test_bit(idx, cache_present); | |
598 | } | |
599 | ||
cfdeb8c3 | 600 | static int regcache_sync_block_single(struct regmap *map, void *block, |
3f4ff561 | 601 | unsigned long *cache_present, |
cfdeb8c3 MB |
602 | unsigned int block_base, |
603 | unsigned int start, unsigned int end) | |
604 | { | |
605 | unsigned int i, regtmp, val; | |
606 | int ret; | |
607 | ||
608 | for (i = start; i < end; i++) { | |
609 | regtmp = block_base + (i * map->reg_stride); | |
610 | ||
3f4ff561 | 611 | if (!regcache_reg_present(cache_present, i)) |
cfdeb8c3 MB |
612 | continue; |
613 | ||
614 | val = regcache_get_val(map, block, i); | |
615 | ||
616 | /* Is this the hardware default? If so skip. */ | |
617 | ret = regcache_lookup_reg(map, regtmp); | |
618 | if (ret >= 0 && val == map->reg_defaults[ret].def) | |
619 | continue; | |
620 | ||
621 | map->cache_bypass = 1; | |
622 | ||
623 | ret = _regmap_write(map, regtmp, val); | |
624 | ||
625 | map->cache_bypass = 0; | |
f29a4320 JN |
626 | if (ret != 0) { |
627 | dev_err(map->dev, "Unable to sync register %#x. %d\n", | |
628 | regtmp, ret); | |
cfdeb8c3 | 629 | return ret; |
f29a4320 | 630 | } |
cfdeb8c3 MB |
631 | dev_dbg(map->dev, "Synced register %#x, value %#x\n", |
632 | regtmp, val); | |
633 | } | |
634 | ||
635 | return 0; | |
636 | } | |
637 | ||
75a5f89f MB |
638 | static int regcache_sync_block_raw_flush(struct regmap *map, const void **data, |
639 | unsigned int base, unsigned int cur) | |
640 | { | |
641 | size_t val_bytes = map->format.val_bytes; | |
642 | int ret, count; | |
643 | ||
644 | if (*data == NULL) | |
645 | return 0; | |
646 | ||
78ba73ee | 647 | count = (cur - base) / map->reg_stride; |
75a5f89f | 648 | |
9659293c | 649 | dev_dbg(map->dev, "Writing %zu bytes for %d registers from 0x%x-0x%x\n", |
78ba73ee | 650 | count * val_bytes, count, base, cur - map->reg_stride); |
75a5f89f MB |
651 | |
652 | map->cache_bypass = 1; | |
653 | ||
0a819809 | 654 | ret = _regmap_raw_write(map, base, *data, count * val_bytes); |
f29a4320 JN |
655 | if (ret) |
656 | dev_err(map->dev, "Unable to sync registers %#x-%#x. %d\n", | |
657 | base, cur - map->reg_stride, ret); | |
75a5f89f MB |
658 | |
659 | map->cache_bypass = 0; | |
660 | ||
661 | *data = NULL; | |
662 | ||
663 | return ret; | |
664 | } | |
665 | ||
f52687af | 666 | static int regcache_sync_block_raw(struct regmap *map, void *block, |
3f4ff561 | 667 | unsigned long *cache_present, |
cfdeb8c3 MB |
668 | unsigned int block_base, unsigned int start, |
669 | unsigned int end) | |
f8bd822c | 670 | { |
75a5f89f MB |
671 | unsigned int i, val; |
672 | unsigned int regtmp = 0; | |
673 | unsigned int base = 0; | |
674 | const void *data = NULL; | |
f8bd822c MB |
675 | int ret; |
676 | ||
677 | for (i = start; i < end; i++) { | |
678 | regtmp = block_base + (i * map->reg_stride); | |
679 | ||
3f4ff561 | 680 | if (!regcache_reg_present(cache_present, i)) { |
75a5f89f MB |
681 | ret = regcache_sync_block_raw_flush(map, &data, |
682 | base, regtmp); | |
683 | if (ret != 0) | |
684 | return ret; | |
f8bd822c | 685 | continue; |
75a5f89f | 686 | } |
f8bd822c MB |
687 | |
688 | val = regcache_get_val(map, block, i); | |
689 | ||
690 | /* Is this the hardware default? If so skip. */ | |
691 | ret = regcache_lookup_reg(map, regtmp); | |
75a5f89f MB |
692 | if (ret >= 0 && val == map->reg_defaults[ret].def) { |
693 | ret = regcache_sync_block_raw_flush(map, &data, | |
694 | base, regtmp); | |
695 | if (ret != 0) | |
696 | return ret; | |
f8bd822c | 697 | continue; |
75a5f89f | 698 | } |
f8bd822c | 699 | |
75a5f89f MB |
700 | if (!data) { |
701 | data = regcache_get_val_addr(map, block, i); | |
702 | base = regtmp; | |
703 | } | |
f8bd822c MB |
704 | } |
705 | ||
2d49b598 LPC |
706 | return regcache_sync_block_raw_flush(map, &data, base, regtmp + |
707 | map->reg_stride); | |
f8bd822c | 708 | } |
cfdeb8c3 MB |
709 | |
710 | int regcache_sync_block(struct regmap *map, void *block, | |
3f4ff561 | 711 | unsigned long *cache_present, |
cfdeb8c3 MB |
712 | unsigned int block_base, unsigned int start, |
713 | unsigned int end) | |
714 | { | |
5c1ebe7f | 715 | if (regmap_can_raw_write(map) && !map->use_single_rw) |
3f4ff561 LPC |
716 | return regcache_sync_block_raw(map, block, cache_present, |
717 | block_base, start, end); | |
cfdeb8c3 | 718 | else |
3f4ff561 LPC |
719 | return regcache_sync_block_single(map, block, cache_present, |
720 | block_base, start, end); | |
cfdeb8c3 | 721 | } |