Commit | Line | Data |
---|---|---|
9fabe24e DP |
1 | /* |
2 | * Register cache access API | |
3 | * | |
4 | * Copyright 2011 Wolfson Microelectronics plc | |
5 | * | |
6 | * Author: Dimitris Papastamos <dp@opensource.wolfsonmicro.com> | |
7 | * | |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License version 2 as | |
10 | * published by the Free Software Foundation. | |
11 | */ | |
12 | ||
f094fea6 | 13 | #include <linux/bsearch.h> |
e39be3a3 XL |
14 | #include <linux/device.h> |
15 | #include <linux/export.h> | |
16 | #include <linux/slab.h> | |
c08604b8 | 17 | #include <linux/sort.h> |
9fabe24e | 18 | |
f58078da | 19 | #include "trace.h" |
9fabe24e DP |
20 | #include "internal.h" |
21 | ||
22 | static const struct regcache_ops *cache_types[] = { | |
28644c80 | 23 | ®cache_rbtree_ops, |
2cbbb579 | 24 | ®cache_lzo_ops, |
2ac902ce | 25 | ®cache_flat_ops, |
9fabe24e DP |
26 | }; |
27 | ||
28 | static int regcache_hw_init(struct regmap *map) | |
29 | { | |
30 | int i, j; | |
31 | int ret; | |
32 | int count; | |
33 | unsigned int val; | |
34 | void *tmp_buf; | |
35 | ||
36 | if (!map->num_reg_defaults_raw) | |
37 | return -EINVAL; | |
38 | ||
fb70067e XL |
39 | /* calculate the size of reg_defaults */ |
40 | for (count = 0, i = 0; i < map->num_reg_defaults_raw; i++) | |
41 | if (!regmap_volatile(map, i * map->reg_stride)) | |
42 | count++; | |
43 | ||
44 | /* all registers are volatile, so just bypass */ | |
45 | if (!count) { | |
46 | map->cache_bypass = true; | |
47 | return 0; | |
48 | } | |
49 | ||
50 | map->num_reg_defaults = count; | |
51 | map->reg_defaults = kmalloc_array(count, sizeof(struct reg_default), | |
52 | GFP_KERNEL); | |
53 | if (!map->reg_defaults) | |
54 | return -ENOMEM; | |
55 | ||
9fabe24e | 56 | if (!map->reg_defaults_raw) { |
621a5f7a | 57 | bool cache_bypass = map->cache_bypass; |
9fabe24e | 58 | dev_warn(map->dev, "No cache defaults, reading back from HW\n"); |
df00c79f LD |
59 | |
60 | /* Bypass the cache access till data read from HW*/ | |
621a5f7a | 61 | map->cache_bypass = true; |
9fabe24e | 62 | tmp_buf = kmalloc(map->cache_size_raw, GFP_KERNEL); |
fb70067e XL |
63 | if (!tmp_buf) { |
64 | ret = -ENOMEM; | |
65 | goto err_free; | |
66 | } | |
eb4cb76f MB |
67 | ret = regmap_raw_read(map, 0, tmp_buf, |
68 | map->num_reg_defaults_raw); | |
df00c79f | 69 | map->cache_bypass = cache_bypass; |
fb70067e XL |
70 | if (ret < 0) |
71 | goto err_cache_free; | |
72 | ||
9fabe24e DP |
73 | map->reg_defaults_raw = tmp_buf; |
74 | map->cache_free = 1; | |
75 | } | |
76 | ||
9fabe24e | 77 | /* fill the reg_defaults */ |
9fabe24e | 78 | for (i = 0, j = 0; i < map->num_reg_defaults_raw; i++) { |
f01ee60f | 79 | if (regmap_volatile(map, i * map->reg_stride)) |
9fabe24e | 80 | continue; |
fbba43c5 | 81 | val = regcache_get_val(map, map->reg_defaults_raw, i); |
f01ee60f | 82 | map->reg_defaults[j].reg = i * map->reg_stride; |
9fabe24e DP |
83 | map->reg_defaults[j].def = val; |
84 | j++; | |
85 | } | |
86 | ||
87 | return 0; | |
021cd616 | 88 | |
fb70067e XL |
89 | err_cache_free: |
90 | kfree(tmp_buf); | |
021cd616 | 91 | err_free: |
fb70067e | 92 | kfree(map->reg_defaults); |
021cd616 LPC |
93 | |
94 | return ret; | |
9fabe24e DP |
95 | } |
96 | ||
e5e3b8ab | 97 | int regcache_init(struct regmap *map, const struct regmap_config *config) |
9fabe24e DP |
98 | { |
99 | int ret; | |
100 | int i; | |
101 | void *tmp_buf; | |
102 | ||
e7a6db30 | 103 | if (map->cache_type == REGCACHE_NONE) { |
8cfe2fd3 XL |
104 | if (config->reg_defaults || config->num_reg_defaults_raw) |
105 | dev_warn(map->dev, | |
106 | "No cache used with register defaults set!\n"); | |
107 | ||
e7a6db30 | 108 | map->cache_bypass = true; |
9fabe24e | 109 | return 0; |
e7a6db30 | 110 | } |
9fabe24e | 111 | |
167f7066 XL |
112 | if (config->reg_defaults && !config->num_reg_defaults) { |
113 | dev_err(map->dev, | |
114 | "Register defaults are set without the number!\n"); | |
115 | return -EINVAL; | |
116 | } | |
117 | ||
8cfe2fd3 XL |
118 | for (i = 0; i < config->num_reg_defaults; i++) |
119 | if (config->reg_defaults[i].reg % map->reg_stride) | |
120 | return -EINVAL; | |
121 | ||
9fabe24e DP |
122 | for (i = 0; i < ARRAY_SIZE(cache_types); i++) |
123 | if (cache_types[i]->type == map->cache_type) | |
124 | break; | |
125 | ||
126 | if (i == ARRAY_SIZE(cache_types)) { | |
127 | dev_err(map->dev, "Could not match compress type: %d\n", | |
128 | map->cache_type); | |
129 | return -EINVAL; | |
130 | } | |
131 | ||
e5e3b8ab LPC |
132 | map->num_reg_defaults = config->num_reg_defaults; |
133 | map->num_reg_defaults_raw = config->num_reg_defaults_raw; | |
134 | map->reg_defaults_raw = config->reg_defaults_raw; | |
064d4db1 LPC |
135 | map->cache_word_size = DIV_ROUND_UP(config->val_bits, 8); |
136 | map->cache_size_raw = map->cache_word_size * config->num_reg_defaults_raw; | |
e5e3b8ab | 137 | |
9fabe24e DP |
138 | map->cache = NULL; |
139 | map->cache_ops = cache_types[i]; | |
140 | ||
141 | if (!map->cache_ops->read || | |
142 | !map->cache_ops->write || | |
143 | !map->cache_ops->name) | |
144 | return -EINVAL; | |
145 | ||
146 | /* We still need to ensure that the reg_defaults | |
147 | * won't vanish from under us. We'll need to make | |
148 | * a copy of it. | |
149 | */ | |
720e4616 | 150 | if (config->reg_defaults) { |
720e4616 | 151 | tmp_buf = kmemdup(config->reg_defaults, map->num_reg_defaults * |
9fabe24e DP |
152 | sizeof(struct reg_default), GFP_KERNEL); |
153 | if (!tmp_buf) | |
154 | return -ENOMEM; | |
155 | map->reg_defaults = tmp_buf; | |
8528bdd4 | 156 | } else if (map->num_reg_defaults_raw) { |
5fcd2560 | 157 | /* Some devices such as PMICs don't have cache defaults, |
9fabe24e DP |
158 | * we cope with this by reading back the HW registers and |
159 | * crafting the cache defaults by hand. | |
160 | */ | |
161 | ret = regcache_hw_init(map); | |
162 | if (ret < 0) | |
163 | return ret; | |
fb70067e XL |
164 | if (map->cache_bypass) |
165 | return 0; | |
9fabe24e DP |
166 | } |
167 | ||
168 | if (!map->max_register) | |
169 | map->max_register = map->num_reg_defaults_raw; | |
170 | ||
171 | if (map->cache_ops->init) { | |
172 | dev_dbg(map->dev, "Initializing %s cache\n", | |
173 | map->cache_ops->name); | |
bd061c78 LPC |
174 | ret = map->cache_ops->init(map); |
175 | if (ret) | |
176 | goto err_free; | |
9fabe24e DP |
177 | } |
178 | return 0; | |
bd061c78 LPC |
179 | |
180 | err_free: | |
181 | kfree(map->reg_defaults); | |
182 | if (map->cache_free) | |
183 | kfree(map->reg_defaults_raw); | |
184 | ||
185 | return ret; | |
9fabe24e DP |
186 | } |
187 | ||
188 | void regcache_exit(struct regmap *map) | |
189 | { | |
190 | if (map->cache_type == REGCACHE_NONE) | |
191 | return; | |
192 | ||
193 | BUG_ON(!map->cache_ops); | |
194 | ||
195 | kfree(map->reg_defaults); | |
196 | if (map->cache_free) | |
197 | kfree(map->reg_defaults_raw); | |
198 | ||
199 | if (map->cache_ops->exit) { | |
200 | dev_dbg(map->dev, "Destroying %s cache\n", | |
201 | map->cache_ops->name); | |
202 | map->cache_ops->exit(map); | |
203 | } | |
204 | } | |
205 | ||
206 | /** | |
207 | * regcache_read: Fetch the value of a given register from the cache. | |
208 | * | |
209 | * @map: map to configure. | |
210 | * @reg: The register index. | |
211 | * @value: The value to be returned. | |
212 | * | |
213 | * Return a negative value on failure, 0 on success. | |
214 | */ | |
215 | int regcache_read(struct regmap *map, | |
216 | unsigned int reg, unsigned int *value) | |
217 | { | |
bc7ee556 MB |
218 | int ret; |
219 | ||
9fabe24e DP |
220 | if (map->cache_type == REGCACHE_NONE) |
221 | return -ENOSYS; | |
222 | ||
223 | BUG_ON(!map->cache_ops); | |
224 | ||
bc7ee556 MB |
225 | if (!regmap_volatile(map, reg)) { |
226 | ret = map->cache_ops->read(map, reg, value); | |
227 | ||
228 | if (ret == 0) | |
c6b570d9 | 229 | trace_regmap_reg_read_cache(map, reg, *value); |
bc7ee556 MB |
230 | |
231 | return ret; | |
232 | } | |
9fabe24e DP |
233 | |
234 | return -EINVAL; | |
235 | } | |
9fabe24e DP |
236 | |
237 | /** | |
238 | * regcache_write: Set the value of a given register in the cache. | |
239 | * | |
240 | * @map: map to configure. | |
241 | * @reg: The register index. | |
242 | * @value: The new register value. | |
243 | * | |
244 | * Return a negative value on failure, 0 on success. | |
245 | */ | |
246 | int regcache_write(struct regmap *map, | |
247 | unsigned int reg, unsigned int value) | |
248 | { | |
249 | if (map->cache_type == REGCACHE_NONE) | |
250 | return 0; | |
251 | ||
252 | BUG_ON(!map->cache_ops); | |
253 | ||
9fabe24e DP |
254 | if (!regmap_volatile(map, reg)) |
255 | return map->cache_ops->write(map, reg, value); | |
256 | ||
257 | return 0; | |
258 | } | |
9fabe24e | 259 | |
3969fa08 KC |
260 | static bool regcache_reg_needs_sync(struct regmap *map, unsigned int reg, |
261 | unsigned int val) | |
262 | { | |
263 | int ret; | |
264 | ||
1c79771a KC |
265 | /* If we don't know the chip just got reset, then sync everything. */ |
266 | if (!map->no_sync_defaults) | |
267 | return true; | |
268 | ||
3969fa08 KC |
269 | /* Is this the hardware default? If so skip. */ |
270 | ret = regcache_lookup_reg(map, reg); | |
271 | if (ret >= 0 && val == map->reg_defaults[ret].def) | |
272 | return false; | |
273 | return true; | |
274 | } | |
275 | ||
d856fce4 MH |
276 | static int regcache_default_sync(struct regmap *map, unsigned int min, |
277 | unsigned int max) | |
278 | { | |
279 | unsigned int reg; | |
280 | ||
75617328 | 281 | for (reg = min; reg <= max; reg += map->reg_stride) { |
d856fce4 MH |
282 | unsigned int val; |
283 | int ret; | |
284 | ||
83f8475c DR |
285 | if (regmap_volatile(map, reg) || |
286 | !regmap_writeable(map, reg)) | |
d856fce4 MH |
287 | continue; |
288 | ||
289 | ret = regcache_read(map, reg, &val); | |
290 | if (ret) | |
291 | return ret; | |
292 | ||
3969fa08 | 293 | if (!regcache_reg_needs_sync(map, reg, val)) |
d856fce4 MH |
294 | continue; |
295 | ||
621a5f7a | 296 | map->cache_bypass = true; |
d856fce4 | 297 | ret = _regmap_write(map, reg, val); |
621a5f7a | 298 | map->cache_bypass = false; |
f29a4320 JN |
299 | if (ret) { |
300 | dev_err(map->dev, "Unable to sync register %#x. %d\n", | |
301 | reg, ret); | |
d856fce4 | 302 | return ret; |
f29a4320 | 303 | } |
d856fce4 MH |
304 | dev_dbg(map->dev, "Synced register %#x, value %#x\n", reg, val); |
305 | } | |
306 | ||
307 | return 0; | |
308 | } | |
309 | ||
9fabe24e DP |
310 | /** |
311 | * regcache_sync: Sync the register cache with the hardware. | |
312 | * | |
313 | * @map: map to configure. | |
314 | * | |
315 | * Any registers that should not be synced should be marked as | |
316 | * volatile. In general drivers can choose not to use the provided | |
317 | * syncing functionality if they so require. | |
318 | * | |
319 | * Return a negative value on failure, 0 on success. | |
320 | */ | |
321 | int regcache_sync(struct regmap *map) | |
322 | { | |
954757d7 | 323 | int ret = 0; |
954757d7 | 324 | unsigned int i; |
59360089 | 325 | const char *name; |
621a5f7a | 326 | bool bypass; |
59360089 | 327 | |
d856fce4 | 328 | BUG_ON(!map->cache_ops); |
9fabe24e | 329 | |
81485f52 | 330 | map->lock(map->lock_arg); |
beb1a10f DP |
331 | /* Remember the initial bypass state */ |
332 | bypass = map->cache_bypass; | |
954757d7 DP |
333 | dev_dbg(map->dev, "Syncing %s cache\n", |
334 | map->cache_ops->name); | |
335 | name = map->cache_ops->name; | |
c6b570d9 | 336 | trace_regcache_sync(map, name, "start"); |
22f0d90a | 337 | |
8ae0d7e8 MB |
338 | if (!map->cache_dirty) |
339 | goto out; | |
d9db7627 | 340 | |
affbe886 MB |
341 | map->async = true; |
342 | ||
22f0d90a | 343 | /* Apply any patch first */ |
621a5f7a | 344 | map->cache_bypass = true; |
22f0d90a MB |
345 | for (i = 0; i < map->patch_regs; i++) { |
346 | ret = _regmap_write(map, map->patch[i].reg, map->patch[i].def); | |
347 | if (ret != 0) { | |
348 | dev_err(map->dev, "Failed to write %x = %x: %d\n", | |
349 | map->patch[i].reg, map->patch[i].def, ret); | |
350 | goto out; | |
351 | } | |
352 | } | |
621a5f7a | 353 | map->cache_bypass = false; |
22f0d90a | 354 | |
d856fce4 MH |
355 | if (map->cache_ops->sync) |
356 | ret = map->cache_ops->sync(map, 0, map->max_register); | |
357 | else | |
358 | ret = regcache_default_sync(map, 0, map->max_register); | |
954757d7 | 359 | |
6ff73738 MB |
360 | if (ret == 0) |
361 | map->cache_dirty = false; | |
954757d7 | 362 | |
954757d7 | 363 | out: |
beb1a10f | 364 | /* Restore the bypass state */ |
affbe886 | 365 | map->async = false; |
beb1a10f | 366 | map->cache_bypass = bypass; |
1c79771a | 367 | map->no_sync_defaults = false; |
81485f52 | 368 | map->unlock(map->lock_arg); |
954757d7 | 369 | |
affbe886 MB |
370 | regmap_async_complete(map); |
371 | ||
c6b570d9 | 372 | trace_regcache_sync(map, name, "stop"); |
affbe886 | 373 | |
954757d7 | 374 | return ret; |
9fabe24e DP |
375 | } |
376 | EXPORT_SYMBOL_GPL(regcache_sync); | |
377 | ||
4d4cfd16 MB |
378 | /** |
379 | * regcache_sync_region: Sync part of the register cache with the hardware. | |
380 | * | |
381 | * @map: map to sync. | |
382 | * @min: first register to sync | |
383 | * @max: last register to sync | |
384 | * | |
385 | * Write all non-default register values in the specified region to | |
386 | * the hardware. | |
387 | * | |
388 | * Return a negative value on failure, 0 on success. | |
389 | */ | |
390 | int regcache_sync_region(struct regmap *map, unsigned int min, | |
391 | unsigned int max) | |
392 | { | |
393 | int ret = 0; | |
394 | const char *name; | |
621a5f7a | 395 | bool bypass; |
4d4cfd16 | 396 | |
d856fce4 | 397 | BUG_ON(!map->cache_ops); |
4d4cfd16 | 398 | |
81485f52 | 399 | map->lock(map->lock_arg); |
4d4cfd16 MB |
400 | |
401 | /* Remember the initial bypass state */ | |
402 | bypass = map->cache_bypass; | |
403 | ||
404 | name = map->cache_ops->name; | |
405 | dev_dbg(map->dev, "Syncing %s cache from %d-%d\n", name, min, max); | |
406 | ||
c6b570d9 | 407 | trace_regcache_sync(map, name, "start region"); |
4d4cfd16 MB |
408 | |
409 | if (!map->cache_dirty) | |
410 | goto out; | |
411 | ||
affbe886 MB |
412 | map->async = true; |
413 | ||
d856fce4 MH |
414 | if (map->cache_ops->sync) |
415 | ret = map->cache_ops->sync(map, min, max); | |
416 | else | |
417 | ret = regcache_default_sync(map, min, max); | |
4d4cfd16 MB |
418 | |
419 | out: | |
4d4cfd16 MB |
420 | /* Restore the bypass state */ |
421 | map->cache_bypass = bypass; | |
affbe886 | 422 | map->async = false; |
1c79771a | 423 | map->no_sync_defaults = false; |
81485f52 | 424 | map->unlock(map->lock_arg); |
4d4cfd16 | 425 | |
affbe886 MB |
426 | regmap_async_complete(map); |
427 | ||
c6b570d9 | 428 | trace_regcache_sync(map, name, "stop region"); |
affbe886 | 429 | |
4d4cfd16 MB |
430 | return ret; |
431 | } | |
e466de05 | 432 | EXPORT_SYMBOL_GPL(regcache_sync_region); |
4d4cfd16 | 433 | |
697e85bc MB |
434 | /** |
435 | * regcache_drop_region: Discard part of the register cache | |
436 | * | |
437 | * @map: map to operate on | |
438 | * @min: first register to discard | |
439 | * @max: last register to discard | |
440 | * | |
441 | * Discard part of the register cache. | |
442 | * | |
443 | * Return a negative value on failure, 0 on success. | |
444 | */ | |
445 | int regcache_drop_region(struct regmap *map, unsigned int min, | |
446 | unsigned int max) | |
447 | { | |
697e85bc MB |
448 | int ret = 0; |
449 | ||
3f4ff561 | 450 | if (!map->cache_ops || !map->cache_ops->drop) |
697e85bc MB |
451 | return -EINVAL; |
452 | ||
81485f52 | 453 | map->lock(map->lock_arg); |
697e85bc | 454 | |
c6b570d9 | 455 | trace_regcache_drop_region(map, min, max); |
697e85bc | 456 | |
3f4ff561 | 457 | ret = map->cache_ops->drop(map, min, max); |
697e85bc | 458 | |
81485f52 | 459 | map->unlock(map->lock_arg); |
697e85bc MB |
460 | |
461 | return ret; | |
462 | } | |
463 | EXPORT_SYMBOL_GPL(regcache_drop_region); | |
464 | ||
92afb286 MB |
465 | /** |
466 | * regcache_cache_only: Put a register map into cache only mode | |
467 | * | |
468 | * @map: map to configure | |
469 | * @cache_only: flag if changes should be written to the hardware | |
470 | * | |
471 | * When a register map is marked as cache only writes to the register | |
472 | * map API will only update the register cache, they will not cause | |
473 | * any hardware changes. This is useful for allowing portions of | |
474 | * drivers to act as though the device were functioning as normal when | |
475 | * it is disabled for power saving reasons. | |
476 | */ | |
477 | void regcache_cache_only(struct regmap *map, bool enable) | |
478 | { | |
81485f52 | 479 | map->lock(map->lock_arg); |
ac77a765 | 480 | WARN_ON(map->cache_bypass && enable); |
92afb286 | 481 | map->cache_only = enable; |
c6b570d9 | 482 | trace_regmap_cache_only(map, enable); |
81485f52 | 483 | map->unlock(map->lock_arg); |
92afb286 MB |
484 | } |
485 | EXPORT_SYMBOL_GPL(regcache_cache_only); | |
486 | ||
8ae0d7e8 | 487 | /** |
1c79771a | 488 | * regcache_mark_dirty: Indicate that HW registers were reset to default values |
8ae0d7e8 MB |
489 | * |
490 | * @map: map to mark | |
491 | * | |
1c79771a KC |
492 | * Inform regcache that the device has been powered down or reset, so that |
493 | * on resume, regcache_sync() knows to write out all non-default values | |
494 | * stored in the cache. | |
495 | * | |
496 | * If this function is not called, regcache_sync() will assume that | |
497 | * the hardware state still matches the cache state, modulo any writes that | |
498 | * happened when cache_only was true. | |
8ae0d7e8 MB |
499 | */ |
500 | void regcache_mark_dirty(struct regmap *map) | |
501 | { | |
81485f52 | 502 | map->lock(map->lock_arg); |
8ae0d7e8 | 503 | map->cache_dirty = true; |
1c79771a | 504 | map->no_sync_defaults = true; |
81485f52 | 505 | map->unlock(map->lock_arg); |
8ae0d7e8 MB |
506 | } |
507 | EXPORT_SYMBOL_GPL(regcache_mark_dirty); | |
508 | ||
6eb0f5e0 DP |
509 | /** |
510 | * regcache_cache_bypass: Put a register map into cache bypass mode | |
511 | * | |
512 | * @map: map to configure | |
0eef6b04 | 513 | * @cache_bypass: flag if changes should not be written to the hardware |
6eb0f5e0 DP |
514 | * |
515 | * When a register map is marked with the cache bypass option, writes | |
516 | * to the register map API will only update the hardware and not the | |
517 | * the cache directly. This is useful when syncing the cache back to | |
518 | * the hardware. | |
519 | */ | |
520 | void regcache_cache_bypass(struct regmap *map, bool enable) | |
521 | { | |
81485f52 | 522 | map->lock(map->lock_arg); |
ac77a765 | 523 | WARN_ON(map->cache_only && enable); |
6eb0f5e0 | 524 | map->cache_bypass = enable; |
c6b570d9 | 525 | trace_regmap_cache_bypass(map, enable); |
81485f52 | 526 | map->unlock(map->lock_arg); |
6eb0f5e0 DP |
527 | } |
528 | EXPORT_SYMBOL_GPL(regcache_cache_bypass); | |
529 | ||
879082c9 MB |
530 | bool regcache_set_val(struct regmap *map, void *base, unsigned int idx, |
531 | unsigned int val) | |
9fabe24e | 532 | { |
325acab4 MB |
533 | if (regcache_get_val(map, base, idx) == val) |
534 | return true; | |
535 | ||
eb4cb76f MB |
536 | /* Use device native format if possible */ |
537 | if (map->format.format_val) { | |
538 | map->format.format_val(base + (map->cache_word_size * idx), | |
539 | val, 0); | |
540 | return false; | |
541 | } | |
542 | ||
879082c9 | 543 | switch (map->cache_word_size) { |
9fabe24e DP |
544 | case 1: { |
545 | u8 *cache = base; | |
2fd6902e | 546 | |
9fabe24e DP |
547 | cache[idx] = val; |
548 | break; | |
549 | } | |
550 | case 2: { | |
551 | u16 *cache = base; | |
2fd6902e | 552 | |
9fabe24e DP |
553 | cache[idx] = val; |
554 | break; | |
555 | } | |
7d5e525b MB |
556 | case 4: { |
557 | u32 *cache = base; | |
2fd6902e | 558 | |
7d5e525b MB |
559 | cache[idx] = val; |
560 | break; | |
561 | } | |
8b7663de XL |
562 | #ifdef CONFIG_64BIT |
563 | case 8: { | |
564 | u64 *cache = base; | |
565 | ||
7d5e525b MB |
566 | cache[idx] = val; |
567 | break; | |
568 | } | |
8b7663de | 569 | #endif |
9fabe24e DP |
570 | default: |
571 | BUG(); | |
572 | } | |
9fabe24e DP |
573 | return false; |
574 | } | |
575 | ||
879082c9 MB |
576 | unsigned int regcache_get_val(struct regmap *map, const void *base, |
577 | unsigned int idx) | |
9fabe24e DP |
578 | { |
579 | if (!base) | |
580 | return -EINVAL; | |
581 | ||
eb4cb76f MB |
582 | /* Use device native format if possible */ |
583 | if (map->format.parse_val) | |
8817796b MB |
584 | return map->format.parse_val(regcache_get_val_addr(map, base, |
585 | idx)); | |
eb4cb76f | 586 | |
879082c9 | 587 | switch (map->cache_word_size) { |
9fabe24e DP |
588 | case 1: { |
589 | const u8 *cache = base; | |
2fd6902e | 590 | |
9fabe24e DP |
591 | return cache[idx]; |
592 | } | |
593 | case 2: { | |
594 | const u16 *cache = base; | |
2fd6902e | 595 | |
9fabe24e DP |
596 | return cache[idx]; |
597 | } | |
7d5e525b MB |
598 | case 4: { |
599 | const u32 *cache = base; | |
2fd6902e | 600 | |
7d5e525b MB |
601 | return cache[idx]; |
602 | } | |
8b7663de XL |
603 | #ifdef CONFIG_64BIT |
604 | case 8: { | |
605 | const u64 *cache = base; | |
606 | ||
7d5e525b MB |
607 | return cache[idx]; |
608 | } | |
8b7663de | 609 | #endif |
9fabe24e DP |
610 | default: |
611 | BUG(); | |
612 | } | |
613 | /* unreachable */ | |
614 | return -1; | |
615 | } | |
616 | ||
f094fea6 | 617 | static int regcache_default_cmp(const void *a, const void *b) |
c08604b8 DP |
618 | { |
619 | const struct reg_default *_a = a; | |
620 | const struct reg_default *_b = b; | |
621 | ||
622 | return _a->reg - _b->reg; | |
623 | } | |
624 | ||
f094fea6 MB |
625 | int regcache_lookup_reg(struct regmap *map, unsigned int reg) |
626 | { | |
627 | struct reg_default key; | |
628 | struct reg_default *r; | |
629 | ||
630 | key.reg = reg; | |
631 | key.def = 0; | |
632 | ||
633 | r = bsearch(&key, map->reg_defaults, map->num_reg_defaults, | |
634 | sizeof(struct reg_default), regcache_default_cmp); | |
635 | ||
636 | if (r) | |
637 | return r - map->reg_defaults; | |
638 | else | |
6e6ace00 | 639 | return -ENOENT; |
f094fea6 | 640 | } |
f8bd822c | 641 | |
3f4ff561 LPC |
642 | static bool regcache_reg_present(unsigned long *cache_present, unsigned int idx) |
643 | { | |
644 | if (!cache_present) | |
645 | return true; | |
646 | ||
647 | return test_bit(idx, cache_present); | |
648 | } | |
649 | ||
cfdeb8c3 | 650 | static int regcache_sync_block_single(struct regmap *map, void *block, |
3f4ff561 | 651 | unsigned long *cache_present, |
cfdeb8c3 MB |
652 | unsigned int block_base, |
653 | unsigned int start, unsigned int end) | |
654 | { | |
655 | unsigned int i, regtmp, val; | |
656 | int ret; | |
657 | ||
658 | for (i = start; i < end; i++) { | |
659 | regtmp = block_base + (i * map->reg_stride); | |
660 | ||
4ceba98d TI |
661 | if (!regcache_reg_present(cache_present, i) || |
662 | !regmap_writeable(map, regtmp)) | |
cfdeb8c3 MB |
663 | continue; |
664 | ||
665 | val = regcache_get_val(map, block, i); | |
3969fa08 | 666 | if (!regcache_reg_needs_sync(map, regtmp, val)) |
cfdeb8c3 MB |
667 | continue; |
668 | ||
621a5f7a | 669 | map->cache_bypass = true; |
cfdeb8c3 MB |
670 | |
671 | ret = _regmap_write(map, regtmp, val); | |
672 | ||
621a5f7a | 673 | map->cache_bypass = false; |
f29a4320 JN |
674 | if (ret != 0) { |
675 | dev_err(map->dev, "Unable to sync register %#x. %d\n", | |
676 | regtmp, ret); | |
cfdeb8c3 | 677 | return ret; |
f29a4320 | 678 | } |
cfdeb8c3 MB |
679 | dev_dbg(map->dev, "Synced register %#x, value %#x\n", |
680 | regtmp, val); | |
681 | } | |
682 | ||
683 | return 0; | |
684 | } | |
685 | ||
75a5f89f MB |
686 | static int regcache_sync_block_raw_flush(struct regmap *map, const void **data, |
687 | unsigned int base, unsigned int cur) | |
688 | { | |
689 | size_t val_bytes = map->format.val_bytes; | |
690 | int ret, count; | |
691 | ||
692 | if (*data == NULL) | |
693 | return 0; | |
694 | ||
78ba73ee | 695 | count = (cur - base) / map->reg_stride; |
75a5f89f | 696 | |
9659293c | 697 | dev_dbg(map->dev, "Writing %zu bytes for %d registers from 0x%x-0x%x\n", |
78ba73ee | 698 | count * val_bytes, count, base, cur - map->reg_stride); |
75a5f89f | 699 | |
621a5f7a | 700 | map->cache_bypass = true; |
75a5f89f | 701 | |
0a819809 | 702 | ret = _regmap_raw_write(map, base, *data, count * val_bytes); |
f29a4320 JN |
703 | if (ret) |
704 | dev_err(map->dev, "Unable to sync registers %#x-%#x. %d\n", | |
705 | base, cur - map->reg_stride, ret); | |
75a5f89f | 706 | |
621a5f7a | 707 | map->cache_bypass = false; |
75a5f89f MB |
708 | |
709 | *data = NULL; | |
710 | ||
711 | return ret; | |
712 | } | |
713 | ||
f52687af | 714 | static int regcache_sync_block_raw(struct regmap *map, void *block, |
3f4ff561 | 715 | unsigned long *cache_present, |
cfdeb8c3 MB |
716 | unsigned int block_base, unsigned int start, |
717 | unsigned int end) | |
f8bd822c | 718 | { |
75a5f89f MB |
719 | unsigned int i, val; |
720 | unsigned int regtmp = 0; | |
721 | unsigned int base = 0; | |
722 | const void *data = NULL; | |
f8bd822c MB |
723 | int ret; |
724 | ||
725 | for (i = start; i < end; i++) { | |
726 | regtmp = block_base + (i * map->reg_stride); | |
727 | ||
4ceba98d TI |
728 | if (!regcache_reg_present(cache_present, i) || |
729 | !regmap_writeable(map, regtmp)) { | |
75a5f89f MB |
730 | ret = regcache_sync_block_raw_flush(map, &data, |
731 | base, regtmp); | |
732 | if (ret != 0) | |
733 | return ret; | |
f8bd822c | 734 | continue; |
75a5f89f | 735 | } |
f8bd822c MB |
736 | |
737 | val = regcache_get_val(map, block, i); | |
3969fa08 | 738 | if (!regcache_reg_needs_sync(map, regtmp, val)) { |
75a5f89f MB |
739 | ret = regcache_sync_block_raw_flush(map, &data, |
740 | base, regtmp); | |
741 | if (ret != 0) | |
742 | return ret; | |
f8bd822c | 743 | continue; |
75a5f89f | 744 | } |
f8bd822c | 745 | |
75a5f89f MB |
746 | if (!data) { |
747 | data = regcache_get_val_addr(map, block, i); | |
748 | base = regtmp; | |
749 | } | |
f8bd822c MB |
750 | } |
751 | ||
2d49b598 LPC |
752 | return regcache_sync_block_raw_flush(map, &data, base, regtmp + |
753 | map->reg_stride); | |
f8bd822c | 754 | } |
cfdeb8c3 MB |
755 | |
756 | int regcache_sync_block(struct regmap *map, void *block, | |
3f4ff561 | 757 | unsigned long *cache_present, |
cfdeb8c3 MB |
758 | unsigned int block_base, unsigned int start, |
759 | unsigned int end) | |
760 | { | |
67921a1a | 761 | if (regmap_can_raw_write(map) && !map->use_single_write) |
3f4ff561 LPC |
762 | return regcache_sync_block_raw(map, block, cache_present, |
763 | block_base, start, end); | |
cfdeb8c3 | 764 | else |
3f4ff561 LPC |
765 | return regcache_sync_block_single(map, block, cache_present, |
766 | block_base, start, end); | |
cfdeb8c3 | 767 | } |