Commit | Line | Data |
---|---|---|
098fde11 | 1 | /* |
1da177e4 LT |
2 | * nicstar.h |
3 | * | |
4 | * Header file for the nicstar device driver. | |
5 | * | |
6 | * Author: Rui Prior (rprior@inescn.pt) | |
7 | * PowerPC support by Jay Talbott (jay_talbott@mcg.mot.com) April 1999 | |
8 | * | |
9 | * (C) INESC 1998 | |
098fde11 | 10 | */ |
1da177e4 LT |
11 | |
12 | #ifndef _LINUX_NICSTAR_H_ | |
13 | #define _LINUX_NICSTAR_H_ | |
14 | ||
098fde11 | 15 | /* Includes */ |
1da177e4 LT |
16 | |
17 | #include <linux/types.h> | |
18 | #include <linux/pci.h> | |
19 | #include <linux/uio.h> | |
20 | #include <linux/skbuff.h> | |
21 | #include <linux/atmdev.h> | |
22 | #include <linux/atm_nicstar.h> | |
23 | ||
098fde11 | 24 | /* Options */ |
1da177e4 | 25 | |
1da177e4 LT |
26 | #define NS_MAX_CARDS 4 /* Maximum number of NICStAR based cards |
27 | controlled by the device driver. Must | |
098fde11 | 28 | be <= 5 */ |
1da177e4 LT |
29 | |
30 | #undef RCQ_SUPPORT /* Do not define this for now */ | |
31 | ||
32 | #define NS_TST_NUM_ENTRIES 2340 /* + 1 for return */ | |
33 | #define NS_TST_RESERVED 340 /* N. entries reserved for UBR/ABR/VBR */ | |
34 | ||
35 | #define NS_SMBUFSIZE 48 /* 48, 96, 240 or 2048 */ | |
36 | #define NS_LGBUFSIZE 16384 /* 2048, 4096, 8192 or 16384 */ | |
37 | #define NS_RSQSIZE 8192 /* 2048, 4096 or 8192 */ | |
38 | #define NS_VPIBITS 2 /* 0, 1, 2, or 8 */ | |
39 | ||
40 | #define NS_MAX_RCTSIZE 4096 /* Number of entries. 4096 or 16384. | |
098fde11 | 41 | Define 4096 only if (all) your card(s) |
1da177e4 LT |
42 | have 32K x 32bit SRAM, in which case |
43 | setting this to 16384 will just waste a | |
44 | lot of memory. | |
45 | Setting this to 4096 for a card with | |
46 | 128K x 32bit SRAM will limit the maximum | |
47 | VCI. */ | |
48 | ||
098fde11 | 49 | /*#define NS_PCI_LATENCY 64*//* Must be a multiple of 32 */ |
1da177e4 LT |
50 | |
51 | /* Number of buffers initially allocated */ | |
098fde11 C |
52 | #define NUM_SB 32 /* Must be even */ |
53 | #define NUM_LB 24 /* Must be even */ | |
54 | #define NUM_HB 8 /* Pre-allocated huge buffers */ | |
55 | #define NUM_IOVB 48 /* Iovec buffers */ | |
1da177e4 LT |
56 | |
57 | /* Lower level for count of buffers */ | |
098fde11 C |
58 | #define MIN_SB 8 /* Must be even */ |
59 | #define MIN_LB 8 /* Must be even */ | |
1da177e4 LT |
60 | #define MIN_HB 6 |
61 | #define MIN_IOVB 8 | |
62 | ||
63 | /* Upper level for count of buffers */ | |
098fde11 C |
64 | #define MAX_SB 64 /* Must be even, <= 508 */ |
65 | #define MAX_LB 48 /* Must be even, <= 508 */ | |
1da177e4 LT |
66 | #define MAX_HB 10 |
67 | #define MAX_IOVB 80 | |
68 | ||
69 | /* These are the absolute maximum allowed for the ioctl() */ | |
098fde11 C |
70 | #define TOP_SB 256 /* Must be even, <= 508 */ |
71 | #define TOP_LB 128 /* Must be even, <= 508 */ | |
1da177e4 LT |
72 | #define TOP_HB 64 |
73 | #define TOP_IOVB 256 | |
74 | ||
1da177e4 LT |
75 | #define MAX_TBD_PER_VC 1 /* Number of TBDs before a TSR */ |
76 | #define MAX_TBD_PER_SCQ 10 /* Only meaningful for variable rate SCQs */ | |
77 | ||
78 | #undef ENABLE_TSQFIE | |
79 | ||
80 | #define SCQFULL_TIMEOUT (5 * HZ) | |
81 | ||
82 | #define NS_POLL_PERIOD (HZ) | |
83 | ||
84 | #define PCR_TOLERANCE (1.0001) | |
85 | ||
098fde11 | 86 | /* ESI stuff */ |
1da177e4 LT |
87 | |
88 | #define NICSTAR_EPROM_MAC_ADDR_OFFSET 0x6C | |
89 | #define NICSTAR_EPROM_MAC_ADDR_OFFSET_ALT 0xF6 | |
90 | ||
098fde11 | 91 | /* #defines */ |
1da177e4 LT |
92 | |
93 | #define NS_IOREMAP_SIZE 4096 | |
94 | ||
8728b834 DM |
95 | /* |
96 | * BUF_XX distinguish the Rx buffers depending on their (small/large) size. | |
97 | * BUG_SM and BUG_LG are both used by the driver and the device. | |
98 | * BUF_NONE is only used by the driver. | |
99 | */ | |
100 | #define BUF_SM 0x00000000 /* These two are used for push_rxbufs() */ | |
101 | #define BUF_LG 0x00000001 /* CMD, Write_FreeBufQ, LBUF bit */ | |
102 | #define BUF_NONE 0xffffffff /* Software only: */ | |
1da177e4 LT |
103 | |
104 | #define NS_HBUFSIZE 65568 /* Size of max. AAL5 PDU */ | |
105 | #define NS_MAX_IOVECS (2 + (65568 - NS_SMBUFSIZE) / \ | |
106 | (NS_LGBUFSIZE - (NS_LGBUFSIZE % 48))) | |
107 | #define NS_IOVBUFSIZE (NS_MAX_IOVECS * (sizeof(struct iovec))) | |
108 | ||
109 | #define NS_SMBUFSIZE_USABLE (NS_SMBUFSIZE - NS_SMBUFSIZE % 48) | |
110 | #define NS_LGBUFSIZE_USABLE (NS_LGBUFSIZE - NS_LGBUFSIZE % 48) | |
111 | ||
112 | #define NS_AAL0_HEADER (ATM_AAL0_SDU - ATM_CELL_PAYLOAD) /* 4 bytes */ | |
113 | ||
114 | #define NS_SMSKBSIZE (NS_SMBUFSIZE + NS_AAL0_HEADER) | |
115 | #define NS_LGSKBSIZE (NS_SMBUFSIZE + NS_LGBUFSIZE) | |
116 | ||
098fde11 | 117 | /* NICStAR structures located in host memory */ |
1da177e4 | 118 | |
098fde11 C |
119 | /* |
120 | * RSQ - Receive Status Queue | |
1da177e4 LT |
121 | * |
122 | * Written by the NICStAR, read by the device driver. | |
123 | */ | |
124 | ||
098fde11 C |
125 | typedef struct ns_rsqe { |
126 | u32 word_1; | |
127 | u32 buffer_handle; | |
128 | u32 final_aal5_crc32; | |
129 | u32 word_4; | |
1da177e4 LT |
130 | } ns_rsqe; |
131 | ||
132 | #define ns_rsqe_vpi(ns_rsqep) \ | |
133 | ((le32_to_cpu((ns_rsqep)->word_1) & 0x00FF0000) >> 16) | |
134 | #define ns_rsqe_vci(ns_rsqep) \ | |
135 | (le32_to_cpu((ns_rsqep)->word_1) & 0x0000FFFF) | |
136 | ||
137 | #define NS_RSQE_VALID 0x80000000 | |
138 | #define NS_RSQE_NZGFC 0x00004000 | |
139 | #define NS_RSQE_EOPDU 0x00002000 | |
140 | #define NS_RSQE_BUFSIZE 0x00001000 | |
141 | #define NS_RSQE_CONGESTION 0x00000800 | |
142 | #define NS_RSQE_CLP 0x00000400 | |
143 | #define NS_RSQE_CRCERR 0x00000200 | |
144 | ||
145 | #define NS_RSQE_BUFSIZE_SM 0x00000000 | |
146 | #define NS_RSQE_BUFSIZE_LG 0x00001000 | |
147 | ||
148 | #define ns_rsqe_valid(ns_rsqep) \ | |
149 | (le32_to_cpu((ns_rsqep)->word_4) & NS_RSQE_VALID) | |
150 | #define ns_rsqe_nzgfc(ns_rsqep) \ | |
151 | (le32_to_cpu((ns_rsqep)->word_4) & NS_RSQE_NZGFC) | |
152 | #define ns_rsqe_eopdu(ns_rsqep) \ | |
153 | (le32_to_cpu((ns_rsqep)->word_4) & NS_RSQE_EOPDU) | |
154 | #define ns_rsqe_bufsize(ns_rsqep) \ | |
155 | (le32_to_cpu((ns_rsqep)->word_4) & NS_RSQE_BUFSIZE) | |
156 | #define ns_rsqe_congestion(ns_rsqep) \ | |
157 | (le32_to_cpu((ns_rsqep)->word_4) & NS_RSQE_CONGESTION) | |
158 | #define ns_rsqe_clp(ns_rsqep) \ | |
159 | (le32_to_cpu((ns_rsqep)->word_4) & NS_RSQE_CLP) | |
160 | #define ns_rsqe_crcerr(ns_rsqep) \ | |
161 | (le32_to_cpu((ns_rsqep)->word_4) & NS_RSQE_CRCERR) | |
162 | ||
163 | #define ns_rsqe_cellcount(ns_rsqep) \ | |
164 | (le32_to_cpu((ns_rsqep)->word_4) & 0x000001FF) | |
165 | #define ns_rsqe_init(ns_rsqep) \ | |
098fde11 | 166 | ((ns_rsqep)->word_4 = cpu_to_le32(0x00000000)) |
1da177e4 LT |
167 | |
168 | #define NS_RSQ_NUM_ENTRIES (NS_RSQSIZE / 16) | |
169 | #define NS_RSQ_ALIGNMENT NS_RSQSIZE | |
170 | ||
098fde11 C |
171 | /* |
172 | * RCQ - Raw Cell Queue | |
1da177e4 LT |
173 | * |
174 | * Written by the NICStAR, read by the device driver. | |
175 | */ | |
176 | ||
098fde11 C |
177 | typedef struct cell_payload { |
178 | u32 word[12]; | |
1da177e4 LT |
179 | } cell_payload; |
180 | ||
098fde11 C |
181 | typedef struct ns_rcqe { |
182 | u32 word_1; | |
183 | u32 word_2; | |
184 | u32 word_3; | |
185 | u32 word_4; | |
186 | cell_payload payload; | |
1da177e4 LT |
187 | } ns_rcqe; |
188 | ||
189 | #define NS_RCQE_SIZE 64 /* bytes */ | |
190 | ||
191 | #define ns_rcqe_islast(ns_rcqep) \ | |
192 | (le32_to_cpu((ns_rcqep)->word_2) != 0x00000000) | |
193 | #define ns_rcqe_cellheader(ns_rcqep) \ | |
194 | (le32_to_cpu((ns_rcqep)->word_1)) | |
195 | #define ns_rcqe_nextbufhandle(ns_rcqep) \ | |
196 | (le32_to_cpu((ns_rcqep)->word_2)) | |
197 | ||
098fde11 C |
198 | /* |
199 | * SCQ - Segmentation Channel Queue | |
1da177e4 LT |
200 | * |
201 | * Written by the device driver, read by the NICStAR. | |
202 | */ | |
203 | ||
098fde11 C |
204 | typedef struct ns_scqe { |
205 | u32 word_1; | |
206 | u32 word_2; | |
207 | u32 word_3; | |
208 | u32 word_4; | |
1da177e4 LT |
209 | } ns_scqe; |
210 | ||
211 | /* NOTE: SCQ entries can be either a TBD (Transmit Buffer Descriptors) | |
098fde11 | 212 | or TSR (Transmit Status Requests) */ |
1da177e4 LT |
213 | |
214 | #define NS_SCQE_TYPE_TBD 0x00000000 | |
215 | #define NS_SCQE_TYPE_TSR 0x80000000 | |
216 | ||
1da177e4 LT |
217 | #define NS_TBD_EOPDU 0x40000000 |
218 | #define NS_TBD_AAL0 0x00000000 | |
219 | #define NS_TBD_AAL34 0x04000000 | |
220 | #define NS_TBD_AAL5 0x08000000 | |
221 | ||
222 | #define NS_TBD_VPI_MASK 0x0FF00000 | |
223 | #define NS_TBD_VCI_MASK 0x000FFFF0 | |
224 | #define NS_TBD_VC_MASK (NS_TBD_VPI_MASK | NS_TBD_VCI_MASK) | |
225 | ||
226 | #define NS_TBD_VPI_SHIFT 20 | |
227 | #define NS_TBD_VCI_SHIFT 4 | |
228 | ||
229 | #define ns_tbd_mkword_1(flags, m, n, buflen) \ | |
230 | (cpu_to_le32((flags) | (m) << 23 | (n) << 16 | (buflen))) | |
231 | #define ns_tbd_mkword_1_novbr(flags, buflen) \ | |
232 | (cpu_to_le32((flags) | (buflen) | 0x00810000)) | |
233 | #define ns_tbd_mkword_3(control, pdulen) \ | |
234 | (cpu_to_le32((control) << 16 | (pdulen))) | |
235 | #define ns_tbd_mkword_4(gfc, vpi, vci, pt, clp) \ | |
236 | (cpu_to_le32((gfc) << 28 | (vpi) << 20 | (vci) << 4 | (pt) << 1 | (clp))) | |
237 | ||
1da177e4 LT |
238 | #define NS_TSR_INTENABLE 0x20000000 |
239 | ||
098fde11 | 240 | #define NS_TSR_SCDISVBR 0xFFFF /* Use as scdi for VBR SCD */ |
1da177e4 LT |
241 | |
242 | #define ns_tsr_mkword_1(flags) \ | |
243 | (cpu_to_le32(NS_SCQE_TYPE_TSR | (flags))) | |
244 | #define ns_tsr_mkword_2(scdi, scqi) \ | |
245 | (cpu_to_le32((scdi) << 16 | 0x00008000 | (scqi))) | |
246 | ||
247 | #define ns_scqe_is_tsr(ns_scqep) \ | |
248 | (le32_to_cpu((ns_scqep)->word_1) & NS_SCQE_TYPE_TSR) | |
249 | ||
250 | #define VBR_SCQ_NUM_ENTRIES 512 | |
251 | #define VBR_SCQSIZE 8192 | |
252 | #define CBR_SCQ_NUM_ENTRIES 64 | |
253 | #define CBR_SCQSIZE 1024 | |
254 | ||
255 | #define NS_SCQE_SIZE 16 | |
256 | ||
098fde11 C |
257 | /* |
258 | * TSQ - Transmit Status Queue | |
1da177e4 LT |
259 | * |
260 | * Written by the NICStAR, read by the device driver. | |
261 | */ | |
262 | ||
098fde11 C |
263 | typedef struct ns_tsi { |
264 | u32 word_1; | |
265 | u32 word_2; | |
1da177e4 LT |
266 | } ns_tsi; |
267 | ||
268 | /* NOTE: The first word can be a status word copied from the TSR which | |
098fde11 C |
269 | originated the TSI, or a timer overflow indicator. In this last |
270 | case, the value of the first word is all zeroes. */ | |
1da177e4 LT |
271 | |
272 | #define NS_TSI_EMPTY 0x80000000 | |
273 | #define NS_TSI_TIMESTAMP_MASK 0x00FFFFFF | |
274 | ||
275 | #define ns_tsi_isempty(ns_tsip) \ | |
276 | (le32_to_cpu((ns_tsip)->word_2) & NS_TSI_EMPTY) | |
277 | #define ns_tsi_gettimestamp(ns_tsip) \ | |
278 | (le32_to_cpu((ns_tsip)->word_2) & NS_TSI_TIMESTAMP_MASK) | |
279 | ||
280 | #define ns_tsi_init(ns_tsip) \ | |
281 | ((ns_tsip)->word_2 = cpu_to_le32(NS_TSI_EMPTY)) | |
282 | ||
1da177e4 LT |
283 | #define NS_TSQSIZE 8192 |
284 | #define NS_TSQ_NUM_ENTRIES 1024 | |
285 | #define NS_TSQ_ALIGNMENT 8192 | |
286 | ||
1da177e4 LT |
287 | #define NS_TSI_SCDISVBR NS_TSR_SCDISVBR |
288 | ||
289 | #define ns_tsi_tmrof(ns_tsip) \ | |
290 | (le32_to_cpu((ns_tsip)->word_1) == 0x00000000) | |
291 | #define ns_tsi_getscdindex(ns_tsip) \ | |
292 | ((le32_to_cpu((ns_tsip)->word_1) & 0xFFFF0000) >> 16) | |
293 | #define ns_tsi_getscqpos(ns_tsip) \ | |
294 | (le32_to_cpu((ns_tsip)->word_1) & 0x00007FFF) | |
295 | ||
098fde11 | 296 | /* NICStAR structures located in local SRAM */ |
1da177e4 | 297 | |
098fde11 C |
298 | /* |
299 | * RCT - Receive Connection Table | |
1da177e4 LT |
300 | * |
301 | * Written by both the NICStAR and the device driver. | |
302 | */ | |
303 | ||
098fde11 C |
304 | typedef struct ns_rcte { |
305 | u32 word_1; | |
306 | u32 buffer_handle; | |
307 | u32 dma_address; | |
308 | u32 aal5_crc32; | |
1da177e4 LT |
309 | } ns_rcte; |
310 | ||
098fde11 | 311 | #define NS_RCTE_BSFB 0x00200000 /* Rev. D only */ |
1da177e4 LT |
312 | #define NS_RCTE_NZGFC 0x00100000 |
313 | #define NS_RCTE_CONNECTOPEN 0x00080000 | |
314 | #define NS_RCTE_AALMASK 0x00070000 | |
315 | #define NS_RCTE_AAL0 0x00000000 | |
316 | #define NS_RCTE_AAL34 0x00010000 | |
317 | #define NS_RCTE_AAL5 0x00020000 | |
318 | #define NS_RCTE_RCQ 0x00030000 | |
319 | #define NS_RCTE_RAWCELLINTEN 0x00008000 | |
320 | #define NS_RCTE_RXCONSTCELLADDR 0x00004000 | |
321 | #define NS_RCTE_BUFFVALID 0x00002000 | |
322 | #define NS_RCTE_FBDSIZE 0x00001000 | |
323 | #define NS_RCTE_EFCI 0x00000800 | |
324 | #define NS_RCTE_CLP 0x00000400 | |
325 | #define NS_RCTE_CRCERROR 0x00000200 | |
326 | #define NS_RCTE_CELLCOUNT_MASK 0x000001FF | |
327 | ||
328 | #define NS_RCTE_FBDSIZE_SM 0x00000000 | |
329 | #define NS_RCTE_FBDSIZE_LG 0x00001000 | |
330 | ||
331 | #define NS_RCT_ENTRY_SIZE 4 /* Number of dwords */ | |
332 | ||
333 | /* NOTE: We could make macros to contruct the first word of the RCTE, | |
098fde11 | 334 | but that doesn't seem to make much sense... */ |
1da177e4 | 335 | |
098fde11 C |
336 | /* |
337 | * FBD - Free Buffer Descriptor | |
1da177e4 LT |
338 | * |
339 | * Written by the device driver using via the command register. | |
340 | */ | |
341 | ||
098fde11 C |
342 | typedef struct ns_fbd { |
343 | u32 buffer_handle; | |
344 | u32 dma_address; | |
1da177e4 LT |
345 | } ns_fbd; |
346 | ||
098fde11 C |
347 | /* |
348 | * TST - Transmit Schedule Table | |
1da177e4 LT |
349 | * |
350 | * Written by the device driver. | |
351 | */ | |
352 | ||
353 | typedef u32 ns_tste; | |
354 | ||
355 | #define NS_TST_OPCODE_MASK 0x60000000 | |
356 | ||
098fde11 C |
357 | #define NS_TST_OPCODE_NULL 0x00000000 /* Insert null cell */ |
358 | #define NS_TST_OPCODE_FIXED 0x20000000 /* Cell from a fixed rate channel */ | |
1da177e4 | 359 | #define NS_TST_OPCODE_VARIABLE 0x40000000 |
098fde11 | 360 | #define NS_TST_OPCODE_END 0x60000000 /* Jump */ |
1da177e4 LT |
361 | |
362 | #define ns_tste_make(opcode, sramad) (opcode | sramad) | |
363 | ||
364 | /* NOTE: | |
365 | ||
366 | - When the opcode is FIXED, sramad specifies the SRAM address of the | |
098fde11 | 367 | SCD for that fixed rate channel. |
1da177e4 | 368 | - When the opcode is END, sramad specifies the SRAM address of the |
098fde11 | 369 | location of the next TST entry to read. |
1da177e4 LT |
370 | */ |
371 | ||
098fde11 C |
372 | /* |
373 | * SCD - Segmentation Channel Descriptor | |
1da177e4 LT |
374 | * |
375 | * Written by both the device driver and the NICStAR | |
376 | */ | |
377 | ||
098fde11 C |
378 | typedef struct ns_scd { |
379 | u32 word_1; | |
380 | u32 word_2; | |
381 | u32 partial_aal5_crc; | |
382 | u32 reserved; | |
383 | ns_scqe cache_a; | |
384 | ns_scqe cache_b; | |
1da177e4 LT |
385 | } ns_scd; |
386 | ||
098fde11 C |
387 | #define NS_SCD_BASE_MASK_VAR 0xFFFFE000 /* Variable rate */ |
388 | #define NS_SCD_BASE_MASK_FIX 0xFFFFFC00 /* Fixed rate */ | |
1da177e4 LT |
389 | #define NS_SCD_TAIL_MASK_VAR 0x00001FF0 |
390 | #define NS_SCD_TAIL_MASK_FIX 0x000003F0 | |
391 | #define NS_SCD_HEAD_MASK_VAR 0x00001FF0 | |
392 | #define NS_SCD_HEAD_MASK_FIX 0x000003F0 | |
393 | #define NS_SCD_XMITFOREVER 0x02000000 | |
394 | ||
395 | /* NOTE: There are other fields in word 2 of the SCD, but as they should | |
098fde11 | 396 | not be needed in the device driver they are not defined here. */ |
1da177e4 | 397 | |
098fde11 | 398 | /* NICStAR local SRAM memory map */ |
1da177e4 LT |
399 | |
400 | #define NS_RCT 0x00000 | |
401 | #define NS_RCT_32_END 0x03FFF | |
402 | #define NS_RCT_128_END 0x0FFFF | |
403 | #define NS_UNUSED_32 0x04000 | |
404 | #define NS_UNUSED_128 0x10000 | |
405 | #define NS_UNUSED_END 0x1BFFF | |
406 | #define NS_TST_FRSCD 0x1C000 | |
407 | #define NS_TST_FRSCD_END 0x1E7DB | |
408 | #define NS_VRSCD2 0x1E7DC | |
409 | #define NS_VRSCD2_END 0x1E7E7 | |
410 | #define NS_VRSCD1 0x1E7E8 | |
411 | #define NS_VRSCD1_END 0x1E7F3 | |
412 | #define NS_VRSCD0 0x1E7F4 | |
413 | #define NS_VRSCD0_END 0x1E7FF | |
414 | #define NS_RXFIFO 0x1E800 | |
415 | #define NS_RXFIFO_END 0x1F7FF | |
416 | #define NS_SMFBQ 0x1F800 | |
417 | #define NS_SMFBQ_END 0x1FBFF | |
418 | #define NS_LGFBQ 0x1FC00 | |
419 | #define NS_LGFBQ_END 0x1FFFF | |
420 | ||
098fde11 | 421 | /* NISCtAR operation registers */ |
1da177e4 LT |
422 | |
423 | /* See Section 3.4 of `IDT77211 NICStAR User Manual' from www.idt.com */ | |
424 | ||
098fde11 C |
425 | enum ns_regs { |
426 | DR0 = 0x00, /* Data Register 0 R/W */ | |
427 | DR1 = 0x04, /* Data Register 1 W */ | |
428 | DR2 = 0x08, /* Data Register 2 W */ | |
429 | DR3 = 0x0C, /* Data Register 3 W */ | |
430 | CMD = 0x10, /* Command W */ | |
431 | CFG = 0x14, /* Configuration R/W */ | |
432 | STAT = 0x18, /* Status R/W */ | |
433 | RSQB = 0x1C, /* Receive Status Queue Base W */ | |
434 | RSQT = 0x20, /* Receive Status Queue Tail R */ | |
435 | RSQH = 0x24, /* Receive Status Queue Head W */ | |
436 | CDC = 0x28, /* Cell Drop Counter R/clear */ | |
437 | VPEC = 0x2C, /* VPI/VCI Lookup Error Count R/clear */ | |
438 | ICC = 0x30, /* Invalid Cell Count R/clear */ | |
439 | RAWCT = 0x34, /* Raw Cell Tail R */ | |
440 | TMR = 0x38, /* Timer R */ | |
441 | TSTB = 0x3C, /* Transmit Schedule Table Base R/W */ | |
442 | TSQB = 0x40, /* Transmit Status Queue Base W */ | |
443 | TSQT = 0x44, /* Transmit Status Queue Tail R */ | |
444 | TSQH = 0x48, /* Transmit Status Queue Head W */ | |
445 | GP = 0x4C, /* General Purpose R/W */ | |
446 | VPM = 0x50 /* VPI/VCI Mask W */ | |
1da177e4 LT |
447 | }; |
448 | ||
098fde11 | 449 | /* NICStAR commands issued to the CMD register */ |
1da177e4 LT |
450 | |
451 | /* Top 4 bits are command opcode, lower 28 are parameters. */ | |
452 | ||
453 | #define NS_CMD_NO_OPERATION 0x00000000 | |
098fde11 | 454 | /* params always 0 */ |
1da177e4 LT |
455 | |
456 | #define NS_CMD_OPENCLOSE_CONNECTION 0x20000000 | |
098fde11 | 457 | /* b19{1=open,0=close} b18-2{SRAM addr} */ |
1da177e4 LT |
458 | |
459 | #define NS_CMD_WRITE_SRAM 0x40000000 | |
098fde11 | 460 | /* b18-2{SRAM addr} b1-0{burst size} */ |
1da177e4 LT |
461 | |
462 | #define NS_CMD_READ_SRAM 0x50000000 | |
098fde11 | 463 | /* b18-2{SRAM addr} */ |
1da177e4 LT |
464 | |
465 | #define NS_CMD_WRITE_FREEBUFQ 0x60000000 | |
098fde11 | 466 | /* b0{large buf indicator} */ |
1da177e4 LT |
467 | |
468 | #define NS_CMD_READ_UTILITY 0x80000000 | |
098fde11 | 469 | /* b8{1=select UTL_CS1} b9{1=select UTL_CS0} b7-0{bus addr} */ |
1da177e4 LT |
470 | |
471 | #define NS_CMD_WRITE_UTILITY 0x90000000 | |
098fde11 | 472 | /* b8{1=select UTL_CS1} b9{1=select UTL_CS0} b7-0{bus addr} */ |
1da177e4 LT |
473 | |
474 | #define NS_CMD_OPEN_CONNECTION (NS_CMD_OPENCLOSE_CONNECTION | 0x00080000) | |
475 | #define NS_CMD_CLOSE_CONNECTION NS_CMD_OPENCLOSE_CONNECTION | |
476 | ||
098fde11 C |
477 | /* NICStAR configuration bits */ |
478 | ||
479 | #define NS_CFG_SWRST 0x80000000 /* Software Reset */ | |
480 | #define NS_CFG_RXPATH 0x20000000 /* Receive Path Enable */ | |
481 | #define NS_CFG_SMBUFSIZE_MASK 0x18000000 /* Small Receive Buffer Size */ | |
482 | #define NS_CFG_LGBUFSIZE_MASK 0x06000000 /* Large Receive Buffer Size */ | |
483 | #define NS_CFG_EFBIE 0x01000000 /* Empty Free Buffer Queue | |
484 | Interrupt Enable */ | |
485 | #define NS_CFG_RSQSIZE_MASK 0x00C00000 /* Receive Status Queue Size */ | |
486 | #define NS_CFG_ICACCEPT 0x00200000 /* Invalid Cell Accept */ | |
487 | #define NS_CFG_IGNOREGFC 0x00100000 /* Ignore General Flow Control */ | |
488 | #define NS_CFG_VPIBITS_MASK 0x000C0000 /* VPI/VCI Bits Size Select */ | |
489 | #define NS_CFG_RCTSIZE_MASK 0x00030000 /* Receive Connection Table Size */ | |
490 | #define NS_CFG_VCERRACCEPT 0x00008000 /* VPI/VCI Error Cell Accept */ | |
491 | #define NS_CFG_RXINT_MASK 0x00007000 /* End of Receive PDU Interrupt | |
492 | Handling */ | |
493 | #define NS_CFG_RAWIE 0x00000800 /* Raw Cell Qu' Interrupt Enable */ | |
494 | #define NS_CFG_RSQAFIE 0x00000400 /* Receive Queue Almost Full | |
495 | Interrupt Enable */ | |
496 | #define NS_CFG_RXRM 0x00000200 /* Receive RM Cells */ | |
497 | #define NS_CFG_TMRROIE 0x00000080 /* Timer Roll Over Interrupt | |
498 | Enable */ | |
499 | #define NS_CFG_TXEN 0x00000020 /* Transmit Operation Enable */ | |
500 | #define NS_CFG_TXIE 0x00000010 /* Transmit Status Interrupt | |
501 | Enable */ | |
502 | #define NS_CFG_TXURIE 0x00000008 /* Transmit Under-run Interrupt | |
503 | Enable */ | |
504 | #define NS_CFG_UMODE 0x00000004 /* Utopia Mode (cell/byte) Select */ | |
505 | #define NS_CFG_TSQFIE 0x00000002 /* Transmit Status Queue Full | |
506 | Interrupt Enable */ | |
507 | #define NS_CFG_PHYIE 0x00000001 /* PHY Interrupt Enable */ | |
1da177e4 LT |
508 | |
509 | #define NS_CFG_SMBUFSIZE_48 0x00000000 | |
510 | #define NS_CFG_SMBUFSIZE_96 0x08000000 | |
511 | #define NS_CFG_SMBUFSIZE_240 0x10000000 | |
512 | #define NS_CFG_SMBUFSIZE_2048 0x18000000 | |
513 | ||
514 | #define NS_CFG_LGBUFSIZE_2048 0x00000000 | |
515 | #define NS_CFG_LGBUFSIZE_4096 0x02000000 | |
516 | #define NS_CFG_LGBUFSIZE_8192 0x04000000 | |
517 | #define NS_CFG_LGBUFSIZE_16384 0x06000000 | |
518 | ||
519 | #define NS_CFG_RSQSIZE_2048 0x00000000 | |
520 | #define NS_CFG_RSQSIZE_4096 0x00400000 | |
521 | #define NS_CFG_RSQSIZE_8192 0x00800000 | |
522 | ||
523 | #define NS_CFG_VPIBITS_0 0x00000000 | |
524 | #define NS_CFG_VPIBITS_1 0x00040000 | |
525 | #define NS_CFG_VPIBITS_2 0x00080000 | |
526 | #define NS_CFG_VPIBITS_8 0x000C0000 | |
527 | ||
528 | #define NS_CFG_RCTSIZE_4096_ENTRIES 0x00000000 | |
529 | #define NS_CFG_RCTSIZE_8192_ENTRIES 0x00010000 | |
530 | #define NS_CFG_RCTSIZE_16384_ENTRIES 0x00020000 | |
531 | ||
532 | #define NS_CFG_RXINT_NOINT 0x00000000 | |
533 | #define NS_CFG_RXINT_NODELAY 0x00001000 | |
534 | #define NS_CFG_RXINT_314US 0x00002000 | |
535 | #define NS_CFG_RXINT_624US 0x00003000 | |
536 | #define NS_CFG_RXINT_899US 0x00004000 | |
537 | ||
098fde11 C |
538 | /* NICStAR STATus bits */ |
539 | ||
540 | #define NS_STAT_SFBQC_MASK 0xFF000000 /* hi 8 bits Small Buffer Queue Count */ | |
541 | #define NS_STAT_LFBQC_MASK 0x00FF0000 /* hi 8 bits Large Buffer Queue Count */ | |
542 | #define NS_STAT_TSIF 0x00008000 /* Transmit Status Queue Indicator */ | |
543 | #define NS_STAT_TXICP 0x00004000 /* Transmit Incomplete PDU */ | |
544 | #define NS_STAT_TSQF 0x00001000 /* Transmit Status Queue Full */ | |
545 | #define NS_STAT_TMROF 0x00000800 /* Timer Overflow */ | |
546 | #define NS_STAT_PHYI 0x00000400 /* PHY Device Interrupt */ | |
547 | #define NS_STAT_CMDBZ 0x00000200 /* Command Busy */ | |
548 | #define NS_STAT_SFBQF 0x00000100 /* Small Buffer Queue Full */ | |
549 | #define NS_STAT_LFBQF 0x00000080 /* Large Buffer Queue Full */ | |
550 | #define NS_STAT_RSQF 0x00000040 /* Receive Status Queue Full */ | |
551 | #define NS_STAT_EOPDU 0x00000020 /* End of PDU */ | |
552 | #define NS_STAT_RAWCF 0x00000010 /* Raw Cell Flag */ | |
553 | #define NS_STAT_SFBQE 0x00000008 /* Small Buffer Queue Empty */ | |
554 | #define NS_STAT_LFBQE 0x00000004 /* Large Buffer Queue Empty */ | |
555 | #define NS_STAT_RSQAF 0x00000002 /* Receive Status Queue Almost Full */ | |
1da177e4 LT |
556 | |
557 | #define ns_stat_sfbqc_get(stat) (((stat) & NS_STAT_SFBQC_MASK) >> 23) | |
558 | #define ns_stat_lfbqc_get(stat) (((stat) & NS_STAT_LFBQC_MASK) >> 15) | |
559 | ||
098fde11 | 560 | /* #defines which depend on other #defines */ |
1da177e4 LT |
561 | |
562 | #define NS_TST0 NS_TST_FRSCD | |
563 | #define NS_TST1 (NS_TST_FRSCD + NS_TST_NUM_ENTRIES + 1) | |
564 | ||
565 | #define NS_FRSCD (NS_TST1 + NS_TST_NUM_ENTRIES + 1) | |
566 | #define NS_FRSCD_SIZE 12 /* 12 dwords */ | |
567 | #define NS_FRSCD_NUM ((NS_TST_FRSCD_END + 1 - NS_FRSCD) / NS_FRSCD_SIZE) | |
568 | ||
569 | #if (NS_SMBUFSIZE == 48) | |
570 | #define NS_CFG_SMBUFSIZE NS_CFG_SMBUFSIZE_48 | |
571 | #elif (NS_SMBUFSIZE == 96) | |
572 | #define NS_CFG_SMBUFSIZE NS_CFG_SMBUFSIZE_96 | |
573 | #elif (NS_SMBUFSIZE == 240) | |
574 | #define NS_CFG_SMBUFSIZE NS_CFG_SMBUFSIZE_240 | |
575 | #elif (NS_SMBUFSIZE == 2048) | |
576 | #define NS_CFG_SMBUFSIZE NS_CFG_SMBUFSIZE_2048 | |
577 | #else | |
578 | #error NS_SMBUFSIZE is incorrect in nicstar.h | |
579 | #endif /* NS_SMBUFSIZE */ | |
580 | ||
581 | #if (NS_LGBUFSIZE == 2048) | |
582 | #define NS_CFG_LGBUFSIZE NS_CFG_LGBUFSIZE_2048 | |
583 | #elif (NS_LGBUFSIZE == 4096) | |
584 | #define NS_CFG_LGBUFSIZE NS_CFG_LGBUFSIZE_4096 | |
585 | #elif (NS_LGBUFSIZE == 8192) | |
586 | #define NS_CFG_LGBUFSIZE NS_CFG_LGBUFSIZE_8192 | |
587 | #elif (NS_LGBUFSIZE == 16384) | |
588 | #define NS_CFG_LGBUFSIZE NS_CFG_LGBUFSIZE_16384 | |
589 | #else | |
590 | #error NS_LGBUFSIZE is incorrect in nicstar.h | |
591 | #endif /* NS_LGBUFSIZE */ | |
592 | ||
593 | #if (NS_RSQSIZE == 2048) | |
594 | #define NS_CFG_RSQSIZE NS_CFG_RSQSIZE_2048 | |
595 | #elif (NS_RSQSIZE == 4096) | |
596 | #define NS_CFG_RSQSIZE NS_CFG_RSQSIZE_4096 | |
597 | #elif (NS_RSQSIZE == 8192) | |
598 | #define NS_CFG_RSQSIZE NS_CFG_RSQSIZE_8192 | |
599 | #else | |
600 | #error NS_RSQSIZE is incorrect in nicstar.h | |
601 | #endif /* NS_RSQSIZE */ | |
602 | ||
603 | #if (NS_VPIBITS == 0) | |
604 | #define NS_CFG_VPIBITS NS_CFG_VPIBITS_0 | |
605 | #elif (NS_VPIBITS == 1) | |
606 | #define NS_CFG_VPIBITS NS_CFG_VPIBITS_1 | |
607 | #elif (NS_VPIBITS == 2) | |
608 | #define NS_CFG_VPIBITS NS_CFG_VPIBITS_2 | |
609 | #elif (NS_VPIBITS == 8) | |
610 | #define NS_CFG_VPIBITS NS_CFG_VPIBITS_8 | |
611 | #else | |
612 | #error NS_VPIBITS is incorrect in nicstar.h | |
613 | #endif /* NS_VPIBITS */ | |
614 | ||
615 | #ifdef RCQ_SUPPORT | |
616 | #define NS_CFG_RAWIE_OPT NS_CFG_RAWIE | |
617 | #else | |
618 | #define NS_CFG_RAWIE_OPT 0x00000000 | |
619 | #endif /* RCQ_SUPPORT */ | |
620 | ||
621 | #ifdef ENABLE_TSQFIE | |
622 | #define NS_CFG_TSQFIE_OPT NS_CFG_TSQFIE | |
623 | #else | |
624 | #define NS_CFG_TSQFIE_OPT 0x00000000 | |
625 | #endif /* ENABLE_TSQFIE */ | |
626 | ||
098fde11 | 627 | /* PCI stuff */ |
1da177e4 LT |
628 | |
629 | #ifndef PCI_VENDOR_ID_IDT | |
630 | #define PCI_VENDOR_ID_IDT 0x111D | |
631 | #endif /* PCI_VENDOR_ID_IDT */ | |
632 | ||
633 | #ifndef PCI_DEVICE_ID_IDT_IDT77201 | |
634 | #define PCI_DEVICE_ID_IDT_IDT77201 0x0001 | |
635 | #endif /* PCI_DEVICE_ID_IDT_IDT77201 */ | |
636 | ||
098fde11 | 637 | /* Device driver structures */ |
1da177e4 | 638 | |
8728b834 | 639 | struct ns_skb_cb { |
098fde11 | 640 | u32 buf_type; /* BUF_SM/BUF_LG/BUF_NONE */ |
8728b834 DM |
641 | }; |
642 | ||
643 | #define NS_SKB_CB(skb) ((struct ns_skb_cb *)((skb)->cb)) | |
644 | ||
098fde11 C |
645 | typedef struct tsq_info { |
646 | void *org; | |
647 | ns_tsi *base; | |
648 | ns_tsi *next; | |
649 | ns_tsi *last; | |
1da177e4 LT |
650 | } tsq_info; |
651 | ||
098fde11 C |
652 | typedef struct scq_info { |
653 | void *org; | |
654 | ns_scqe *base; | |
655 | ns_scqe *last; | |
656 | ns_scqe *next; | |
657 | volatile ns_scqe *tail; /* Not related to the nicstar register */ | |
658 | unsigned num_entries; | |
659 | struct sk_buff **skb; /* Pointer to an array of pointers | |
660 | to the sk_buffs used for tx */ | |
661 | u32 scd; /* SRAM address of the corresponding | |
662 | SCD */ | |
663 | int tbd_count; /* Only meaningful on variable rate */ | |
664 | wait_queue_head_t scqfull_waitq; | |
665 | volatile char full; /* SCQ full indicator */ | |
666 | spinlock_t lock; /* SCQ spinlock */ | |
1da177e4 LT |
667 | } scq_info; |
668 | ||
098fde11 C |
669 | typedef struct rsq_info { |
670 | void *org; | |
671 | ns_rsqe *base; | |
672 | ns_rsqe *next; | |
673 | ns_rsqe *last; | |
1da177e4 LT |
674 | } rsq_info; |
675 | ||
098fde11 C |
676 | typedef struct skb_pool { |
677 | volatile int count; /* number of buffers in the queue */ | |
678 | struct sk_buff_head queue; | |
1da177e4 LT |
679 | } skb_pool; |
680 | ||
681 | /* NOTE: for small and large buffer pools, the count is not used, as the | |
682 | actual value used for buffer management is the one read from the | |
683 | card. */ | |
684 | ||
098fde11 C |
685 | typedef struct vc_map { |
686 | volatile unsigned int tx:1; /* TX vc? */ | |
687 | volatile unsigned int rx:1; /* RX vc? */ | |
688 | struct atm_vcc *tx_vcc, *rx_vcc; | |
689 | struct sk_buff *rx_iov; /* RX iovector skb */ | |
690 | scq_info *scq; /* To keep track of the SCQ */ | |
691 | u32 cbr_scd; /* SRAM address of the corresponding | |
692 | SCD. 0x00000000 for UBR/VBR/ABR */ | |
693 | int tbd_count; | |
1da177e4 LT |
694 | } vc_map; |
695 | ||
098fde11 | 696 | struct ns_skb_data { |
1da177e4 LT |
697 | struct atm_vcc *vcc; |
698 | int iovcnt; | |
699 | }; | |
700 | ||
701 | #define NS_SKB(skb) (((struct ns_skb_data *) (skb)->cb)) | |
702 | ||
098fde11 C |
703 | typedef struct ns_dev { |
704 | int index; /* Card ID to the device driver */ | |
705 | int sram_size; /* In k x 32bit words. 32 or 128 */ | |
706 | void __iomem *membase; /* Card's memory base address */ | |
707 | unsigned long max_pcr; | |
708 | int rct_size; /* Number of entries */ | |
709 | int vpibits; | |
710 | int vcibits; | |
711 | struct pci_dev *pcidev; | |
712 | struct atm_dev *atmdev; | |
713 | tsq_info tsq; | |
714 | rsq_info rsq; | |
715 | scq_info *scq0, *scq1, *scq2; /* VBR SCQs */ | |
716 | skb_pool sbpool; /* Small buffers */ | |
717 | skb_pool lbpool; /* Large buffers */ | |
718 | skb_pool hbpool; /* Pre-allocated huge buffers */ | |
719 | skb_pool iovpool; /* iovector buffers */ | |
720 | volatile int efbie; /* Empty free buf. queue int. enabled */ | |
721 | volatile u32 tst_addr; /* SRAM address of the TST in use */ | |
722 | volatile int tst_free_entries; | |
723 | vc_map vcmap[NS_MAX_RCTSIZE]; | |
724 | vc_map *tste2vc[NS_TST_NUM_ENTRIES]; | |
725 | vc_map *scd2vc[NS_FRSCD_NUM]; | |
726 | buf_nr sbnr; | |
727 | buf_nr lbnr; | |
728 | buf_nr hbnr; | |
729 | buf_nr iovnr; | |
730 | int sbfqc; | |
731 | int lbfqc; | |
732 | u32 sm_handle; | |
733 | u32 sm_addr; | |
734 | u32 lg_handle; | |
735 | u32 lg_addr; | |
736 | struct sk_buff *rcbuf; /* Current raw cell buffer */ | |
737 | u32 rawch; /* Raw cell queue head */ | |
738 | unsigned intcnt; /* Interrupt counter */ | |
739 | spinlock_t int_lock; /* Interrupt lock */ | |
740 | spinlock_t res_lock; /* Card resource lock */ | |
1da177e4 LT |
741 | } ns_dev; |
742 | ||
1da177e4 | 743 | /* NOTE: Each tste2vc entry relates a given TST entry to the corresponding |
098fde11 C |
744 | CBR vc. If the entry is not allocated, it must be NULL. |
745 | ||
746 | There are two TSTs so the driver can modify them on the fly | |
747 | without stopping the transmission. | |
1da177e4 | 748 | |
098fde11 C |
749 | scd2vc allows us to find out unused fixed rate SCDs, because |
750 | they must have a NULL pointer here. */ | |
1da177e4 LT |
751 | |
752 | #endif /* _LINUX_NICSTAR_H_ */ |