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1da177e4 | 1 | /******************************************************************* |
1da177e4 LT |
2 | * |
3 | * Copyright (c) 2000 ATecoM GmbH | |
4 | * | |
5 | * The author may be reached at ecd@atecom.com. | |
6 | * | |
7 | * This program is free software; you can redistribute it and/or modify it | |
8 | * under the terms of the GNU General Public License as published by the | |
9 | * Free Software Foundation; either version 2 of the License, or (at your | |
10 | * option) any later version. | |
11 | * | |
12 | * THIS SOFTWARE IS PROVIDED ``AS IS'' AND ANY EXPRESS OR IMPLIED | |
13 | * WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF | |
14 | * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN | |
15 | * NO EVENT SHALL THE AUTHOR BE LIABLE FOR ANY DIRECT, INDIRECT, | |
16 | * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT | |
17 | * NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF | |
18 | * USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON | |
19 | * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT | |
20 | * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF | |
21 | * THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. | |
22 | * | |
23 | * You should have received a copy of the GNU General Public License along | |
24 | * with this program; if not, write to the Free Software Foundation, Inc., | |
25 | * 675 Mass Ave, Cambridge, MA 02139, USA. | |
26 | * | |
27 | *******************************************************************/ | |
1da177e4 LT |
28 | |
29 | #include <linux/module.h> | |
1da177e4 | 30 | #include <linux/pci.h> |
3c6b3773 | 31 | #include <linux/poison.h> |
1da177e4 LT |
32 | #include <linux/skbuff.h> |
33 | #include <linux/kernel.h> | |
34 | #include <linux/vmalloc.h> | |
35 | #include <linux/netdevice.h> | |
36 | #include <linux/atmdev.h> | |
37 | #include <linux/atm.h> | |
38 | #include <linux/delay.h> | |
39 | #include <linux/init.h> | |
a6b7a407 | 40 | #include <linux/interrupt.h> |
1da177e4 LT |
41 | #include <linux/bitops.h> |
42 | #include <linux/wait.h> | |
e1bd232b | 43 | #include <linux/jiffies.h> |
7e7a2d07 | 44 | #include <linux/mutex.h> |
5a0e3ad6 | 45 | #include <linux/slab.h> |
7e7a2d07 | 46 | |
1da177e4 | 47 | #include <asm/io.h> |
7c0f6ba6 | 48 | #include <linux/uaccess.h> |
60063497 | 49 | #include <linux/atomic.h> |
1da177e4 LT |
50 | #include <asm/byteorder.h> |
51 | ||
52 | #ifdef CONFIG_ATM_IDT77252_USE_SUNI | |
53 | #include "suni.h" | |
54 | #endif /* CONFIG_ATM_IDT77252_USE_SUNI */ | |
55 | ||
56 | ||
57 | #include "idt77252.h" | |
58 | #include "idt77252_tables.h" | |
59 | ||
60 | static unsigned int vpibits = 1; | |
61 | ||
62 | ||
44beac00 | 63 | #define ATM_IDT77252_SEND_IDLE 1 |
1da177e4 LT |
64 | |
65 | ||
66 | /* | |
67 | * Debug HACKs. | |
68 | */ | |
69 | #define DEBUG_MODULE 1 | |
70 | #undef HAVE_EEPROM /* does not work, yet. */ | |
71 | ||
72 | #ifdef CONFIG_ATM_IDT77252_DEBUG | |
73 | static unsigned long debug = DBG_GENERAL; | |
74 | #endif | |
75 | ||
76 | ||
77 | #define SAR_RX_DELAY (SAR_CFG_RXINT_NODELAY) | |
78 | ||
79 | ||
80 | /* | |
81 | * SCQ Handling. | |
82 | */ | |
83 | static struct scq_info *alloc_scq(struct idt77252_dev *, int); | |
84 | static void free_scq(struct idt77252_dev *, struct scq_info *); | |
85 | static int queue_skb(struct idt77252_dev *, struct vc_map *, | |
86 | struct sk_buff *, int oam); | |
87 | static void drain_scq(struct idt77252_dev *, struct vc_map *); | |
88 | static unsigned long get_free_scd(struct idt77252_dev *, struct vc_map *); | |
89 | static void fill_scd(struct idt77252_dev *, struct scq_info *, int); | |
90 | ||
91 | /* | |
92 | * FBQ Handling. | |
93 | */ | |
94 | static int push_rx_skb(struct idt77252_dev *, | |
95 | struct sk_buff *, int queue); | |
96 | static void recycle_rx_skb(struct idt77252_dev *, struct sk_buff *); | |
97 | static void flush_rx_pool(struct idt77252_dev *, struct rx_pool *); | |
98 | static void recycle_rx_pool_skb(struct idt77252_dev *, | |
99 | struct rx_pool *); | |
100 | static void add_rx_skb(struct idt77252_dev *, int queue, | |
101 | unsigned int size, unsigned int count); | |
102 | ||
103 | /* | |
104 | * RSQ Handling. | |
105 | */ | |
106 | static int init_rsq(struct idt77252_dev *); | |
107 | static void deinit_rsq(struct idt77252_dev *); | |
108 | static void idt77252_rx(struct idt77252_dev *); | |
109 | ||
110 | /* | |
111 | * TSQ handling. | |
112 | */ | |
113 | static int init_tsq(struct idt77252_dev *); | |
114 | static void deinit_tsq(struct idt77252_dev *); | |
115 | static void idt77252_tx(struct idt77252_dev *); | |
116 | ||
117 | ||
118 | /* | |
119 | * ATM Interface. | |
120 | */ | |
121 | static void idt77252_dev_close(struct atm_dev *dev); | |
122 | static int idt77252_open(struct atm_vcc *vcc); | |
123 | static void idt77252_close(struct atm_vcc *vcc); | |
124 | static int idt77252_send(struct atm_vcc *vcc, struct sk_buff *skb); | |
125 | static int idt77252_send_oam(struct atm_vcc *vcc, void *cell, | |
126 | int flags); | |
127 | static void idt77252_phy_put(struct atm_dev *dev, unsigned char value, | |
128 | unsigned long addr); | |
129 | static unsigned char idt77252_phy_get(struct atm_dev *dev, unsigned long addr); | |
130 | static int idt77252_change_qos(struct atm_vcc *vcc, struct atm_qos *qos, | |
131 | int flags); | |
132 | static int idt77252_proc_read(struct atm_dev *dev, loff_t * pos, | |
133 | char *page); | |
c4028958 | 134 | static void idt77252_softint(struct work_struct *work); |
1da177e4 LT |
135 | |
136 | ||
46c4b7a5 | 137 | static const struct atmdev_ops idt77252_ops = |
1da177e4 LT |
138 | { |
139 | .dev_close = idt77252_dev_close, | |
140 | .open = idt77252_open, | |
141 | .close = idt77252_close, | |
142 | .send = idt77252_send, | |
143 | .send_oam = idt77252_send_oam, | |
144 | .phy_put = idt77252_phy_put, | |
145 | .phy_get = idt77252_phy_get, | |
146 | .change_qos = idt77252_change_qos, | |
147 | .proc_read = idt77252_proc_read, | |
148 | .owner = THIS_MODULE | |
149 | }; | |
150 | ||
151 | static struct idt77252_dev *idt77252_chain = NULL; | |
152 | static unsigned int idt77252_sram_write_errors = 0; | |
153 | ||
154 | /*****************************************************************************/ | |
155 | /* */ | |
156 | /* I/O and Utility Bus */ | |
157 | /* */ | |
158 | /*****************************************************************************/ | |
159 | ||
160 | static void | |
161 | waitfor_idle(struct idt77252_dev *card) | |
162 | { | |
163 | u32 stat; | |
164 | ||
165 | stat = readl(SAR_REG_STAT); | |
166 | while (stat & SAR_STAT_CMDBZ) | |
167 | stat = readl(SAR_REG_STAT); | |
168 | } | |
169 | ||
170 | static u32 | |
171 | read_sram(struct idt77252_dev *card, unsigned long addr) | |
172 | { | |
173 | unsigned long flags; | |
174 | u32 value; | |
175 | ||
176 | spin_lock_irqsave(&card->cmd_lock, flags); | |
177 | writel(SAR_CMD_READ_SRAM | (addr << 2), SAR_REG_CMD); | |
178 | waitfor_idle(card); | |
179 | value = readl(SAR_REG_DR0); | |
180 | spin_unlock_irqrestore(&card->cmd_lock, flags); | |
181 | return value; | |
182 | } | |
183 | ||
184 | static void | |
185 | write_sram(struct idt77252_dev *card, unsigned long addr, u32 value) | |
186 | { | |
187 | unsigned long flags; | |
188 | ||
189 | if ((idt77252_sram_write_errors == 0) && | |
190 | (((addr > card->tst[0] + card->tst_size - 2) && | |
191 | (addr < card->tst[0] + card->tst_size)) || | |
192 | ((addr > card->tst[1] + card->tst_size - 2) && | |
193 | (addr < card->tst[1] + card->tst_size)))) { | |
194 | printk("%s: ERROR: TST JMP section at %08lx written: %08x\n", | |
195 | card->name, addr, value); | |
196 | } | |
197 | ||
198 | spin_lock_irqsave(&card->cmd_lock, flags); | |
199 | writel(value, SAR_REG_DR0); | |
200 | writel(SAR_CMD_WRITE_SRAM | (addr << 2), SAR_REG_CMD); | |
201 | waitfor_idle(card); | |
202 | spin_unlock_irqrestore(&card->cmd_lock, flags); | |
203 | } | |
204 | ||
205 | static u8 | |
206 | read_utility(void *dev, unsigned long ubus_addr) | |
207 | { | |
208 | struct idt77252_dev *card = dev; | |
209 | unsigned long flags; | |
210 | u8 value; | |
211 | ||
212 | if (!card) { | |
213 | printk("Error: No such device.\n"); | |
214 | return -1; | |
215 | } | |
216 | ||
217 | spin_lock_irqsave(&card->cmd_lock, flags); | |
218 | writel(SAR_CMD_READ_UTILITY + ubus_addr, SAR_REG_CMD); | |
219 | waitfor_idle(card); | |
220 | value = readl(SAR_REG_DR0); | |
221 | spin_unlock_irqrestore(&card->cmd_lock, flags); | |
222 | return value; | |
223 | } | |
224 | ||
225 | static void | |
226 | write_utility(void *dev, unsigned long ubus_addr, u8 value) | |
227 | { | |
228 | struct idt77252_dev *card = dev; | |
229 | unsigned long flags; | |
230 | ||
231 | if (!card) { | |
232 | printk("Error: No such device.\n"); | |
233 | return; | |
234 | } | |
235 | ||
236 | spin_lock_irqsave(&card->cmd_lock, flags); | |
237 | writel((u32) value, SAR_REG_DR0); | |
238 | writel(SAR_CMD_WRITE_UTILITY + ubus_addr, SAR_REG_CMD); | |
239 | waitfor_idle(card); | |
240 | spin_unlock_irqrestore(&card->cmd_lock, flags); | |
241 | } | |
242 | ||
243 | #ifdef HAVE_EEPROM | |
244 | static u32 rdsrtab[] = | |
245 | { | |
246 | SAR_GP_EECS | SAR_GP_EESCLK, | |
247 | 0, | |
248 | SAR_GP_EESCLK, /* 0 */ | |
249 | 0, | |
250 | SAR_GP_EESCLK, /* 0 */ | |
251 | 0, | |
252 | SAR_GP_EESCLK, /* 0 */ | |
253 | 0, | |
254 | SAR_GP_EESCLK, /* 0 */ | |
255 | 0, | |
256 | SAR_GP_EESCLK, /* 0 */ | |
257 | SAR_GP_EEDO, | |
258 | SAR_GP_EESCLK | SAR_GP_EEDO, /* 1 */ | |
259 | 0, | |
260 | SAR_GP_EESCLK, /* 0 */ | |
261 | SAR_GP_EEDO, | |
262 | SAR_GP_EESCLK | SAR_GP_EEDO /* 1 */ | |
263 | }; | |
264 | ||
265 | static u32 wrentab[] = | |
266 | { | |
267 | SAR_GP_EECS | SAR_GP_EESCLK, | |
268 | 0, | |
269 | SAR_GP_EESCLK, /* 0 */ | |
270 | 0, | |
271 | SAR_GP_EESCLK, /* 0 */ | |
272 | 0, | |
273 | SAR_GP_EESCLK, /* 0 */ | |
274 | 0, | |
275 | SAR_GP_EESCLK, /* 0 */ | |
276 | SAR_GP_EEDO, | |
277 | SAR_GP_EESCLK | SAR_GP_EEDO, /* 1 */ | |
278 | SAR_GP_EEDO, | |
279 | SAR_GP_EESCLK | SAR_GP_EEDO, /* 1 */ | |
280 | 0, | |
281 | SAR_GP_EESCLK, /* 0 */ | |
282 | 0, | |
283 | SAR_GP_EESCLK /* 0 */ | |
284 | }; | |
285 | ||
286 | static u32 rdtab[] = | |
287 | { | |
288 | SAR_GP_EECS | SAR_GP_EESCLK, | |
289 | 0, | |
290 | SAR_GP_EESCLK, /* 0 */ | |
291 | 0, | |
292 | SAR_GP_EESCLK, /* 0 */ | |
293 | 0, | |
294 | SAR_GP_EESCLK, /* 0 */ | |
295 | 0, | |
296 | SAR_GP_EESCLK, /* 0 */ | |
297 | 0, | |
298 | SAR_GP_EESCLK, /* 0 */ | |
299 | 0, | |
300 | SAR_GP_EESCLK, /* 0 */ | |
301 | SAR_GP_EEDO, | |
302 | SAR_GP_EESCLK | SAR_GP_EEDO, /* 1 */ | |
303 | SAR_GP_EEDO, | |
304 | SAR_GP_EESCLK | SAR_GP_EEDO /* 1 */ | |
305 | }; | |
306 | ||
307 | static u32 wrtab[] = | |
308 | { | |
309 | SAR_GP_EECS | SAR_GP_EESCLK, | |
310 | 0, | |
311 | SAR_GP_EESCLK, /* 0 */ | |
312 | 0, | |
313 | SAR_GP_EESCLK, /* 0 */ | |
314 | 0, | |
315 | SAR_GP_EESCLK, /* 0 */ | |
316 | 0, | |
317 | SAR_GP_EESCLK, /* 0 */ | |
318 | 0, | |
319 | SAR_GP_EESCLK, /* 0 */ | |
320 | 0, | |
321 | SAR_GP_EESCLK, /* 0 */ | |
322 | SAR_GP_EEDO, | |
323 | SAR_GP_EESCLK | SAR_GP_EEDO, /* 1 */ | |
324 | 0, | |
325 | SAR_GP_EESCLK /* 0 */ | |
326 | }; | |
327 | ||
328 | static u32 clktab[] = | |
329 | { | |
330 | 0, | |
331 | SAR_GP_EESCLK, | |
332 | 0, | |
333 | SAR_GP_EESCLK, | |
334 | 0, | |
335 | SAR_GP_EESCLK, | |
336 | 0, | |
337 | SAR_GP_EESCLK, | |
338 | 0, | |
339 | SAR_GP_EESCLK, | |
340 | 0, | |
341 | SAR_GP_EESCLK, | |
342 | 0, | |
343 | SAR_GP_EESCLK, | |
344 | 0, | |
345 | SAR_GP_EESCLK, | |
346 | 0 | |
347 | }; | |
348 | ||
349 | static u32 | |
350 | idt77252_read_gp(struct idt77252_dev *card) | |
351 | { | |
352 | u32 gp; | |
353 | ||
354 | gp = readl(SAR_REG_GP); | |
355 | #if 0 | |
356 | printk("RD: %s\n", gp & SAR_GP_EEDI ? "1" : "0"); | |
357 | #endif | |
358 | return gp; | |
359 | } | |
360 | ||
361 | static void | |
362 | idt77252_write_gp(struct idt77252_dev *card, u32 value) | |
363 | { | |
364 | unsigned long flags; | |
365 | ||
366 | #if 0 | |
367 | printk("WR: %s %s %s\n", value & SAR_GP_EECS ? " " : "/CS", | |
368 | value & SAR_GP_EESCLK ? "HIGH" : "LOW ", | |
369 | value & SAR_GP_EEDO ? "1" : "0"); | |
370 | #endif | |
371 | ||
372 | spin_lock_irqsave(&card->cmd_lock, flags); | |
373 | waitfor_idle(card); | |
374 | writel(value, SAR_REG_GP); | |
375 | spin_unlock_irqrestore(&card->cmd_lock, flags); | |
376 | } | |
377 | ||
378 | static u8 | |
379 | idt77252_eeprom_read_status(struct idt77252_dev *card) | |
380 | { | |
381 | u8 byte; | |
382 | u32 gp; | |
383 | int i, j; | |
384 | ||
385 | gp = idt77252_read_gp(card) & ~(SAR_GP_EESCLK|SAR_GP_EECS|SAR_GP_EEDO); | |
386 | ||
36fe55d6 | 387 | for (i = 0; i < ARRAY_SIZE(rdsrtab); i++) { |
1da177e4 LT |
388 | idt77252_write_gp(card, gp | rdsrtab[i]); |
389 | udelay(5); | |
390 | } | |
391 | idt77252_write_gp(card, gp | SAR_GP_EECS); | |
392 | udelay(5); | |
393 | ||
394 | byte = 0; | |
395 | for (i = 0, j = 0; i < 8; i++) { | |
396 | byte <<= 1; | |
397 | ||
398 | idt77252_write_gp(card, gp | clktab[j++]); | |
399 | udelay(5); | |
400 | ||
401 | byte |= idt77252_read_gp(card) & SAR_GP_EEDI ? 1 : 0; | |
402 | ||
403 | idt77252_write_gp(card, gp | clktab[j++]); | |
404 | udelay(5); | |
405 | } | |
406 | idt77252_write_gp(card, gp | SAR_GP_EECS); | |
407 | udelay(5); | |
408 | ||
409 | return byte; | |
410 | } | |
411 | ||
412 | static u8 | |
413 | idt77252_eeprom_read_byte(struct idt77252_dev *card, u8 offset) | |
414 | { | |
415 | u8 byte; | |
416 | u32 gp; | |
417 | int i, j; | |
418 | ||
419 | gp = idt77252_read_gp(card) & ~(SAR_GP_EESCLK|SAR_GP_EECS|SAR_GP_EEDO); | |
420 | ||
36fe55d6 | 421 | for (i = 0; i < ARRAY_SIZE(rdtab); i++) { |
1da177e4 LT |
422 | idt77252_write_gp(card, gp | rdtab[i]); |
423 | udelay(5); | |
424 | } | |
425 | idt77252_write_gp(card, gp | SAR_GP_EECS); | |
426 | udelay(5); | |
427 | ||
428 | for (i = 0, j = 0; i < 8; i++) { | |
429 | idt77252_write_gp(card, gp | clktab[j++] | | |
430 | (offset & 1 ? SAR_GP_EEDO : 0)); | |
431 | udelay(5); | |
432 | ||
433 | idt77252_write_gp(card, gp | clktab[j++] | | |
434 | (offset & 1 ? SAR_GP_EEDO : 0)); | |
435 | udelay(5); | |
436 | ||
437 | offset >>= 1; | |
438 | } | |
439 | idt77252_write_gp(card, gp | SAR_GP_EECS); | |
440 | udelay(5); | |
441 | ||
442 | byte = 0; | |
443 | for (i = 0, j = 0; i < 8; i++) { | |
444 | byte <<= 1; | |
445 | ||
446 | idt77252_write_gp(card, gp | clktab[j++]); | |
447 | udelay(5); | |
448 | ||
449 | byte |= idt77252_read_gp(card) & SAR_GP_EEDI ? 1 : 0; | |
450 | ||
451 | idt77252_write_gp(card, gp | clktab[j++]); | |
452 | udelay(5); | |
453 | } | |
454 | idt77252_write_gp(card, gp | SAR_GP_EECS); | |
455 | udelay(5); | |
456 | ||
457 | return byte; | |
458 | } | |
459 | ||
460 | static void | |
461 | idt77252_eeprom_write_byte(struct idt77252_dev *card, u8 offset, u8 data) | |
462 | { | |
463 | u32 gp; | |
464 | int i, j; | |
465 | ||
466 | gp = idt77252_read_gp(card) & ~(SAR_GP_EESCLK|SAR_GP_EECS|SAR_GP_EEDO); | |
467 | ||
36fe55d6 | 468 | for (i = 0; i < ARRAY_SIZE(wrentab); i++) { |
1da177e4 LT |
469 | idt77252_write_gp(card, gp | wrentab[i]); |
470 | udelay(5); | |
471 | } | |
472 | idt77252_write_gp(card, gp | SAR_GP_EECS); | |
473 | udelay(5); | |
474 | ||
36fe55d6 | 475 | for (i = 0; i < ARRAY_SIZE(wrtab); i++) { |
1da177e4 LT |
476 | idt77252_write_gp(card, gp | wrtab[i]); |
477 | udelay(5); | |
478 | } | |
479 | idt77252_write_gp(card, gp | SAR_GP_EECS); | |
480 | udelay(5); | |
481 | ||
482 | for (i = 0, j = 0; i < 8; i++) { | |
483 | idt77252_write_gp(card, gp | clktab[j++] | | |
484 | (offset & 1 ? SAR_GP_EEDO : 0)); | |
485 | udelay(5); | |
486 | ||
487 | idt77252_write_gp(card, gp | clktab[j++] | | |
488 | (offset & 1 ? SAR_GP_EEDO : 0)); | |
489 | udelay(5); | |
490 | ||
491 | offset >>= 1; | |
492 | } | |
493 | idt77252_write_gp(card, gp | SAR_GP_EECS); | |
494 | udelay(5); | |
495 | ||
496 | for (i = 0, j = 0; i < 8; i++) { | |
497 | idt77252_write_gp(card, gp | clktab[j++] | | |
498 | (data & 1 ? SAR_GP_EEDO : 0)); | |
499 | udelay(5); | |
500 | ||
501 | idt77252_write_gp(card, gp | clktab[j++] | | |
502 | (data & 1 ? SAR_GP_EEDO : 0)); | |
503 | udelay(5); | |
504 | ||
505 | data >>= 1; | |
506 | } | |
507 | idt77252_write_gp(card, gp | SAR_GP_EECS); | |
508 | udelay(5); | |
509 | } | |
510 | ||
511 | static void | |
512 | idt77252_eeprom_init(struct idt77252_dev *card) | |
513 | { | |
514 | u32 gp; | |
515 | ||
516 | gp = idt77252_read_gp(card) & ~(SAR_GP_EESCLK|SAR_GP_EECS|SAR_GP_EEDO); | |
517 | ||
518 | idt77252_write_gp(card, gp | SAR_GP_EECS | SAR_GP_EESCLK); | |
519 | udelay(5); | |
520 | idt77252_write_gp(card, gp | SAR_GP_EECS); | |
521 | udelay(5); | |
522 | idt77252_write_gp(card, gp | SAR_GP_EECS | SAR_GP_EESCLK); | |
523 | udelay(5); | |
524 | idt77252_write_gp(card, gp | SAR_GP_EECS); | |
525 | udelay(5); | |
526 | } | |
527 | #endif /* HAVE_EEPROM */ | |
528 | ||
529 | ||
530 | #ifdef CONFIG_ATM_IDT77252_DEBUG | |
531 | static void | |
532 | dump_tct(struct idt77252_dev *card, int index) | |
533 | { | |
534 | unsigned long tct; | |
535 | int i; | |
536 | ||
537 | tct = (unsigned long) (card->tct_base + index * SAR_SRAM_TCT_SIZE); | |
538 | ||
539 | printk("%s: TCT %x:", card->name, index); | |
540 | for (i = 0; i < 8; i++) { | |
541 | printk(" %08x", read_sram(card, tct + i)); | |
542 | } | |
543 | printk("\n"); | |
544 | } | |
545 | ||
546 | static void | |
547 | idt77252_tx_dump(struct idt77252_dev *card) | |
548 | { | |
549 | struct atm_vcc *vcc; | |
550 | struct vc_map *vc; | |
551 | int i; | |
552 | ||
5a346a10 | 553 | printk("%s\n", __func__); |
1da177e4 LT |
554 | for (i = 0; i < card->tct_size; i++) { |
555 | vc = card->vcs[i]; | |
556 | if (!vc) | |
557 | continue; | |
558 | ||
559 | vcc = NULL; | |
560 | if (vc->rx_vcc) | |
561 | vcc = vc->rx_vcc; | |
562 | else if (vc->tx_vcc) | |
563 | vcc = vc->tx_vcc; | |
564 | ||
565 | if (!vcc) | |
566 | continue; | |
567 | ||
568 | printk("%s: Connection %d:\n", card->name, vc->index); | |
569 | dump_tct(card, vc->index); | |
570 | } | |
571 | } | |
572 | #endif | |
573 | ||
574 | ||
575 | /*****************************************************************************/ | |
576 | /* */ | |
577 | /* SCQ Handling */ | |
578 | /* */ | |
579 | /*****************************************************************************/ | |
580 | ||
581 | static int | |
582 | sb_pool_add(struct idt77252_dev *card, struct sk_buff *skb, int queue) | |
583 | { | |
584 | struct sb_pool *pool = &card->sbpool[queue]; | |
585 | int index; | |
586 | ||
587 | index = pool->index; | |
588 | while (pool->skb[index]) { | |
589 | index = (index + 1) & FBQ_MASK; | |
590 | if (index == pool->index) | |
591 | return -ENOBUFS; | |
592 | } | |
593 | ||
594 | pool->skb[index] = skb; | |
595 | IDT77252_PRV_POOL(skb) = POOL_HANDLE(queue, index); | |
596 | ||
597 | pool->index = (index + 1) & FBQ_MASK; | |
598 | return 0; | |
599 | } | |
600 | ||
601 | static void | |
602 | sb_pool_remove(struct idt77252_dev *card, struct sk_buff *skb) | |
603 | { | |
604 | unsigned int queue, index; | |
605 | u32 handle; | |
606 | ||
607 | handle = IDT77252_PRV_POOL(skb); | |
608 | ||
609 | queue = POOL_QUEUE(handle); | |
610 | if (queue > 3) | |
611 | return; | |
612 | ||
613 | index = POOL_INDEX(handle); | |
614 | if (index > FBQ_SIZE - 1) | |
615 | return; | |
616 | ||
617 | card->sbpool[queue].skb[index] = NULL; | |
618 | } | |
619 | ||
620 | static struct sk_buff * | |
621 | sb_pool_skb(struct idt77252_dev *card, u32 handle) | |
622 | { | |
623 | unsigned int queue, index; | |
624 | ||
625 | queue = POOL_QUEUE(handle); | |
626 | if (queue > 3) | |
627 | return NULL; | |
628 | ||
629 | index = POOL_INDEX(handle); | |
630 | if (index > FBQ_SIZE - 1) | |
631 | return NULL; | |
632 | ||
633 | return card->sbpool[queue].skb[index]; | |
634 | } | |
635 | ||
636 | static struct scq_info * | |
637 | alloc_scq(struct idt77252_dev *card, int class) | |
638 | { | |
639 | struct scq_info *scq; | |
640 | ||
0c1cca1d | 641 | scq = kzalloc(sizeof(struct scq_info), GFP_KERNEL); |
1da177e4 LT |
642 | if (!scq) |
643 | return NULL; | |
750afb08 LC |
644 | scq->base = dma_alloc_coherent(&card->pcidev->dev, SCQ_SIZE, |
645 | &scq->paddr, GFP_KERNEL); | |
1da177e4 LT |
646 | if (scq->base == NULL) { |
647 | kfree(scq); | |
648 | return NULL; | |
649 | } | |
1da177e4 LT |
650 | |
651 | scq->next = scq->base; | |
652 | scq->last = scq->base + (SCQ_ENTRIES - 1); | |
653 | atomic_set(&scq->used, 0); | |
654 | ||
655 | spin_lock_init(&scq->lock); | |
656 | spin_lock_init(&scq->skblock); | |
657 | ||
658 | skb_queue_head_init(&scq->transmit); | |
659 | skb_queue_head_init(&scq->pending); | |
660 | ||
661 | TXPRINTK("idt77252: SCQ: base 0x%p, next 0x%p, last 0x%p, paddr %08llx\n", | |
662 | scq->base, scq->next, scq->last, (unsigned long long)scq->paddr); | |
663 | ||
664 | return scq; | |
665 | } | |
666 | ||
667 | static void | |
668 | free_scq(struct idt77252_dev *card, struct scq_info *scq) | |
669 | { | |
670 | struct sk_buff *skb; | |
671 | struct atm_vcc *vcc; | |
672 | ||
ede58ef2 C |
673 | dma_free_coherent(&card->pcidev->dev, SCQ_SIZE, |
674 | scq->base, scq->paddr); | |
1da177e4 LT |
675 | |
676 | while ((skb = skb_dequeue(&scq->transmit))) { | |
ede58ef2 C |
677 | dma_unmap_single(&card->pcidev->dev, IDT77252_PRV_PADDR(skb), |
678 | skb->len, DMA_TO_DEVICE); | |
1da177e4 LT |
679 | |
680 | vcc = ATM_SKB(skb)->vcc; | |
681 | if (vcc->pop) | |
682 | vcc->pop(vcc, skb); | |
683 | else | |
684 | dev_kfree_skb(skb); | |
685 | } | |
686 | ||
687 | while ((skb = skb_dequeue(&scq->pending))) { | |
ede58ef2 C |
688 | dma_unmap_single(&card->pcidev->dev, IDT77252_PRV_PADDR(skb), |
689 | skb->len, DMA_TO_DEVICE); | |
1da177e4 LT |
690 | |
691 | vcc = ATM_SKB(skb)->vcc; | |
692 | if (vcc->pop) | |
693 | vcc->pop(vcc, skb); | |
694 | else | |
695 | dev_kfree_skb(skb); | |
696 | } | |
697 | ||
698 | kfree(scq); | |
699 | } | |
700 | ||
701 | ||
702 | static int | |
703 | push_on_scq(struct idt77252_dev *card, struct vc_map *vc, struct sk_buff *skb) | |
704 | { | |
705 | struct scq_info *scq = vc->scq; | |
706 | unsigned long flags; | |
707 | struct scqe *tbd; | |
708 | int entries; | |
709 | ||
710 | TXPRINTK("%s: SCQ: next 0x%p\n", card->name, scq->next); | |
711 | ||
712 | atomic_inc(&scq->used); | |
713 | entries = atomic_read(&scq->used); | |
714 | if (entries > (SCQ_ENTRIES - 1)) { | |
715 | atomic_dec(&scq->used); | |
716 | goto out; | |
717 | } | |
718 | ||
719 | skb_queue_tail(&scq->transmit, skb); | |
720 | ||
721 | spin_lock_irqsave(&vc->lock, flags); | |
722 | if (vc->estimator) { | |
723 | struct atm_vcc *vcc = vc->tx_vcc; | |
724 | struct sock *sk = sk_atm(vcc); | |
725 | ||
726 | vc->estimator->cells += (skb->len + 47) / 48; | |
14afee4b | 727 | if (refcount_read(&sk->sk_wmem_alloc) > |
1da177e4 LT |
728 | (sk->sk_sndbuf >> 1)) { |
729 | u32 cps = vc->estimator->maxcps; | |
730 | ||
731 | vc->estimator->cps = cps; | |
732 | vc->estimator->avcps = cps << 5; | |
733 | if (vc->lacr < vc->init_er) { | |
734 | vc->lacr = vc->init_er; | |
735 | writel(TCMDQ_LACR | (vc->lacr << 16) | | |
736 | vc->index, SAR_REG_TCMDQ); | |
737 | } | |
738 | } | |
739 | } | |
740 | spin_unlock_irqrestore(&vc->lock, flags); | |
741 | ||
742 | tbd = &IDT77252_PRV_TBD(skb); | |
743 | ||
744 | spin_lock_irqsave(&scq->lock, flags); | |
745 | scq->next->word_1 = cpu_to_le32(tbd->word_1 | | |
746 | SAR_TBD_TSIF | SAR_TBD_GTSI); | |
747 | scq->next->word_2 = cpu_to_le32(tbd->word_2); | |
748 | scq->next->word_3 = cpu_to_le32(tbd->word_3); | |
749 | scq->next->word_4 = cpu_to_le32(tbd->word_4); | |
750 | ||
751 | if (scq->next == scq->last) | |
752 | scq->next = scq->base; | |
753 | else | |
754 | scq->next++; | |
755 | ||
756 | write_sram(card, scq->scd, | |
757 | scq->paddr + | |
758 | (u32)((unsigned long)scq->next - (unsigned long)scq->base)); | |
759 | spin_unlock_irqrestore(&scq->lock, flags); | |
760 | ||
761 | scq->trans_start = jiffies; | |
762 | ||
763 | if (test_and_clear_bit(VCF_IDLE, &vc->flags)) { | |
764 | writel(TCMDQ_START_LACR | (vc->lacr << 16) | vc->index, | |
765 | SAR_REG_TCMDQ); | |
766 | } | |
767 | ||
768 | TXPRINTK("%d entries in SCQ used (push).\n", atomic_read(&scq->used)); | |
769 | ||
770 | XPRINTK("%s: SCQ (after push %2d) head = 0x%x, next = 0x%p.\n", | |
771 | card->name, atomic_read(&scq->used), | |
772 | read_sram(card, scq->scd + 1), scq->next); | |
773 | ||
774 | return 0; | |
775 | ||
776 | out: | |
e1bd232b | 777 | if (time_after(jiffies, scq->trans_start + HZ)) { |
1da177e4 LT |
778 | printk("%s: Error pushing TBD for %d.%d\n", |
779 | card->name, vc->tx_vcc->vpi, vc->tx_vcc->vci); | |
780 | #ifdef CONFIG_ATM_IDT77252_DEBUG | |
781 | idt77252_tx_dump(card); | |
782 | #endif | |
783 | scq->trans_start = jiffies; | |
784 | } | |
785 | ||
786 | return -ENOBUFS; | |
787 | } | |
788 | ||
789 | ||
790 | static void | |
791 | drain_scq(struct idt77252_dev *card, struct vc_map *vc) | |
792 | { | |
793 | struct scq_info *scq = vc->scq; | |
794 | struct sk_buff *skb; | |
795 | struct atm_vcc *vcc; | |
796 | ||
797 | TXPRINTK("%s: SCQ (before drain %2d) next = 0x%p.\n", | |
798 | card->name, atomic_read(&scq->used), scq->next); | |
799 | ||
800 | skb = skb_dequeue(&scq->transmit); | |
801 | if (skb) { | |
802 | TXPRINTK("%s: freeing skb at %p.\n", card->name, skb); | |
803 | ||
ede58ef2 C |
804 | dma_unmap_single(&card->pcidev->dev, IDT77252_PRV_PADDR(skb), |
805 | skb->len, DMA_TO_DEVICE); | |
1da177e4 LT |
806 | |
807 | vcc = ATM_SKB(skb)->vcc; | |
808 | ||
809 | if (vcc->pop) | |
810 | vcc->pop(vcc, skb); | |
811 | else | |
812 | dev_kfree_skb(skb); | |
813 | ||
814 | atomic_inc(&vcc->stats->tx); | |
815 | } | |
816 | ||
817 | atomic_dec(&scq->used); | |
818 | ||
819 | spin_lock(&scq->skblock); | |
820 | while ((skb = skb_dequeue(&scq->pending))) { | |
821 | if (push_on_scq(card, vc, skb)) { | |
822 | skb_queue_head(&vc->scq->pending, skb); | |
823 | break; | |
824 | } | |
825 | } | |
826 | spin_unlock(&scq->skblock); | |
827 | } | |
828 | ||
829 | static int | |
830 | queue_skb(struct idt77252_dev *card, struct vc_map *vc, | |
831 | struct sk_buff *skb, int oam) | |
832 | { | |
833 | struct atm_vcc *vcc; | |
834 | struct scqe *tbd; | |
835 | unsigned long flags; | |
836 | int error; | |
837 | int aal; | |
cbbb64f6 | 838 | u32 word4; |
1da177e4 LT |
839 | |
840 | if (skb->len == 0) { | |
841 | printk("%s: invalid skb->len (%d)\n", card->name, skb->len); | |
842 | return -EINVAL; | |
843 | } | |
844 | ||
845 | TXPRINTK("%s: Sending %d bytes of data.\n", | |
846 | card->name, skb->len); | |
847 | ||
848 | tbd = &IDT77252_PRV_TBD(skb); | |
849 | vcc = ATM_SKB(skb)->vcc; | |
cbbb64f6 JJB |
850 | word4 = (skb->data[0] << 24) | (skb->data[1] << 16) | |
851 | (skb->data[2] << 8) | (skb->data[3] << 0); | |
1da177e4 | 852 | |
ede58ef2 C |
853 | IDT77252_PRV_PADDR(skb) = dma_map_single(&card->pcidev->dev, skb->data, |
854 | skb->len, DMA_TO_DEVICE); | |
1da177e4 LT |
855 | |
856 | error = -EINVAL; | |
857 | ||
858 | if (oam) { | |
859 | if (skb->len != 52) | |
860 | goto errout; | |
861 | ||
862 | tbd->word_1 = SAR_TBD_OAM | ATM_CELL_PAYLOAD | SAR_TBD_EPDU; | |
863 | tbd->word_2 = IDT77252_PRV_PADDR(skb) + 4; | |
864 | tbd->word_3 = 0x00000000; | |
cbbb64f6 | 865 | tbd->word_4 = word4; |
1da177e4 LT |
866 | |
867 | if (test_bit(VCF_RSV, &vc->flags)) | |
868 | vc = card->vcs[0]; | |
869 | ||
870 | goto done; | |
871 | } | |
872 | ||
873 | if (test_bit(VCF_RSV, &vc->flags)) { | |
874 | printk("%s: Trying to transmit on reserved VC\n", card->name); | |
875 | goto errout; | |
876 | } | |
877 | ||
878 | aal = vcc->qos.aal; | |
879 | ||
880 | switch (aal) { | |
881 | case ATM_AAL0: | |
882 | case ATM_AAL34: | |
883 | if (skb->len > 52) | |
884 | goto errout; | |
885 | ||
886 | if (aal == ATM_AAL0) | |
887 | tbd->word_1 = SAR_TBD_EPDU | SAR_TBD_AAL0 | | |
888 | ATM_CELL_PAYLOAD; | |
889 | else | |
890 | tbd->word_1 = SAR_TBD_EPDU | SAR_TBD_AAL34 | | |
891 | ATM_CELL_PAYLOAD; | |
892 | ||
893 | tbd->word_2 = IDT77252_PRV_PADDR(skb) + 4; | |
894 | tbd->word_3 = 0x00000000; | |
cbbb64f6 | 895 | tbd->word_4 = word4; |
1da177e4 LT |
896 | break; |
897 | ||
898 | case ATM_AAL5: | |
899 | tbd->word_1 = SAR_TBD_EPDU | SAR_TBD_AAL5 | skb->len; | |
900 | tbd->word_2 = IDT77252_PRV_PADDR(skb); | |
901 | tbd->word_3 = skb->len; | |
902 | tbd->word_4 = (vcc->vpi << SAR_TBD_VPI_SHIFT) | | |
903 | (vcc->vci << SAR_TBD_VCI_SHIFT); | |
904 | break; | |
905 | ||
906 | case ATM_AAL1: | |
907 | case ATM_AAL2: | |
908 | default: | |
909 | printk("%s: Traffic type not supported.\n", card->name); | |
910 | error = -EPROTONOSUPPORT; | |
911 | goto errout; | |
912 | } | |
913 | ||
914 | done: | |
915 | spin_lock_irqsave(&vc->scq->skblock, flags); | |
916 | skb_queue_tail(&vc->scq->pending, skb); | |
917 | ||
918 | while ((skb = skb_dequeue(&vc->scq->pending))) { | |
919 | if (push_on_scq(card, vc, skb)) { | |
920 | skb_queue_head(&vc->scq->pending, skb); | |
921 | break; | |
922 | } | |
923 | } | |
924 | spin_unlock_irqrestore(&vc->scq->skblock, flags); | |
925 | ||
926 | return 0; | |
927 | ||
928 | errout: | |
ede58ef2 C |
929 | dma_unmap_single(&card->pcidev->dev, IDT77252_PRV_PADDR(skb), |
930 | skb->len, DMA_TO_DEVICE); | |
1da177e4 LT |
931 | return error; |
932 | } | |
933 | ||
934 | static unsigned long | |
935 | get_free_scd(struct idt77252_dev *card, struct vc_map *vc) | |
936 | { | |
937 | int i; | |
938 | ||
939 | for (i = 0; i < card->scd_size; i++) { | |
940 | if (!card->scd2vc[i]) { | |
941 | card->scd2vc[i] = vc; | |
942 | vc->scd_index = i; | |
943 | return card->scd_base + i * SAR_SRAM_SCD_SIZE; | |
944 | } | |
945 | } | |
946 | return 0; | |
947 | } | |
948 | ||
949 | static void | |
950 | fill_scd(struct idt77252_dev *card, struct scq_info *scq, int class) | |
951 | { | |
952 | write_sram(card, scq->scd, scq->paddr); | |
953 | write_sram(card, scq->scd + 1, 0x00000000); | |
954 | write_sram(card, scq->scd + 2, 0xffffffff); | |
955 | write_sram(card, scq->scd + 3, 0x00000000); | |
956 | } | |
957 | ||
958 | static void | |
959 | clear_scd(struct idt77252_dev *card, struct scq_info *scq, int class) | |
960 | { | |
961 | return; | |
962 | } | |
963 | ||
964 | /*****************************************************************************/ | |
965 | /* */ | |
966 | /* RSQ Handling */ | |
967 | /* */ | |
968 | /*****************************************************************************/ | |
969 | ||
970 | static int | |
971 | init_rsq(struct idt77252_dev *card) | |
972 | { | |
973 | struct rsq_entry *rsqe; | |
974 | ||
750afb08 LC |
975 | card->rsq.base = dma_alloc_coherent(&card->pcidev->dev, RSQSIZE, |
976 | &card->rsq.paddr, GFP_KERNEL); | |
1da177e4 LT |
977 | if (card->rsq.base == NULL) { |
978 | printk("%s: can't allocate RSQ.\n", card->name); | |
979 | return -1; | |
980 | } | |
1da177e4 LT |
981 | |
982 | card->rsq.last = card->rsq.base + RSQ_NUM_ENTRIES - 1; | |
983 | card->rsq.next = card->rsq.last; | |
984 | for (rsqe = card->rsq.base; rsqe <= card->rsq.last; rsqe++) | |
985 | rsqe->word_4 = 0; | |
986 | ||
987 | writel((unsigned long) card->rsq.last - (unsigned long) card->rsq.base, | |
988 | SAR_REG_RSQH); | |
989 | writel(card->rsq.paddr, SAR_REG_RSQB); | |
990 | ||
991 | IPRINTK("%s: RSQ base at 0x%lx (0x%x).\n", card->name, | |
992 | (unsigned long) card->rsq.base, | |
993 | readl(SAR_REG_RSQB)); | |
994 | IPRINTK("%s: RSQ head = 0x%x, base = 0x%x, tail = 0x%x.\n", | |
995 | card->name, | |
996 | readl(SAR_REG_RSQH), | |
997 | readl(SAR_REG_RSQB), | |
998 | readl(SAR_REG_RSQT)); | |
999 | ||
1000 | return 0; | |
1001 | } | |
1002 | ||
1003 | static void | |
1004 | deinit_rsq(struct idt77252_dev *card) | |
1005 | { | |
ede58ef2 C |
1006 | dma_free_coherent(&card->pcidev->dev, RSQSIZE, |
1007 | card->rsq.base, card->rsq.paddr); | |
1da177e4 LT |
1008 | } |
1009 | ||
1010 | static void | |
1011 | dequeue_rx(struct idt77252_dev *card, struct rsq_entry *rsqe) | |
1012 | { | |
1013 | struct atm_vcc *vcc; | |
1014 | struct sk_buff *skb; | |
1015 | struct rx_pool *rpp; | |
1016 | struct vc_map *vc; | |
1017 | u32 header, vpi, vci; | |
1018 | u32 stat; | |
1019 | int i; | |
1020 | ||
1021 | stat = le32_to_cpu(rsqe->word_4); | |
1022 | ||
1023 | if (stat & SAR_RSQE_IDLE) { | |
1024 | RXPRINTK("%s: message about inactive connection.\n", | |
1025 | card->name); | |
1026 | return; | |
1027 | } | |
1028 | ||
1029 | skb = sb_pool_skb(card, le32_to_cpu(rsqe->word_2)); | |
1030 | if (skb == NULL) { | |
1031 | printk("%s: NULL skb in %s, rsqe: %08x %08x %08x %08x\n", | |
5a346a10 | 1032 | card->name, __func__, |
1da177e4 LT |
1033 | le32_to_cpu(rsqe->word_1), le32_to_cpu(rsqe->word_2), |
1034 | le32_to_cpu(rsqe->word_3), le32_to_cpu(rsqe->word_4)); | |
1035 | return; | |
1036 | } | |
1037 | ||
1038 | header = le32_to_cpu(rsqe->word_1); | |
1039 | vpi = (header >> 16) & 0x00ff; | |
1040 | vci = (header >> 0) & 0xffff; | |
1041 | ||
1042 | RXPRINTK("%s: SDU for %d.%d received in buffer 0x%p (data 0x%p).\n", | |
1043 | card->name, vpi, vci, skb, skb->data); | |
1044 | ||
1045 | if ((vpi >= (1 << card->vpibits)) || (vci != (vci & card->vcimask))) { | |
1046 | printk("%s: SDU received for out-of-range vc %u.%u\n", | |
1047 | card->name, vpi, vci); | |
1048 | recycle_rx_skb(card, skb); | |
1049 | return; | |
1050 | } | |
1051 | ||
1052 | vc = card->vcs[VPCI2VC(card, vpi, vci)]; | |
1053 | if (!vc || !test_bit(VCF_RX, &vc->flags)) { | |
1054 | printk("%s: SDU received on non RX vc %u.%u\n", | |
1055 | card->name, vpi, vci); | |
1056 | recycle_rx_skb(card, skb); | |
1057 | return; | |
1058 | } | |
1059 | ||
1060 | vcc = vc->rx_vcc; | |
1061 | ||
ede58ef2 C |
1062 | dma_sync_single_for_cpu(&card->pcidev->dev, IDT77252_PRV_PADDR(skb), |
1063 | skb_end_pointer(skb) - skb->data, | |
1064 | DMA_FROM_DEVICE); | |
1da177e4 LT |
1065 | |
1066 | if ((vcc->qos.aal == ATM_AAL0) || | |
1067 | (vcc->qos.aal == ATM_AAL34)) { | |
1068 | struct sk_buff *sb; | |
1069 | unsigned char *cell; | |
1070 | u32 aal0; | |
1071 | ||
1072 | cell = skb->data; | |
1073 | for (i = (stat & SAR_RSQE_CELLCNT); i; i--) { | |
1074 | if ((sb = dev_alloc_skb(64)) == NULL) { | |
1075 | printk("%s: Can't allocate buffers for aal0.\n", | |
1076 | card->name); | |
1077 | atomic_add(i, &vcc->stats->rx_drop); | |
1078 | break; | |
1079 | } | |
1080 | if (!atm_charge(vcc, sb->truesize)) { | |
1081 | RXPRINTK("%s: atm_charge() dropped aal0 packets.\n", | |
1082 | card->name); | |
1083 | atomic_add(i - 1, &vcc->stats->rx_drop); | |
1084 | dev_kfree_skb(sb); | |
1085 | break; | |
1086 | } | |
1087 | aal0 = (vpi << ATM_HDR_VPI_SHIFT) | | |
1088 | (vci << ATM_HDR_VCI_SHIFT); | |
1089 | aal0 |= (stat & SAR_RSQE_EPDU) ? 0x00000002 : 0; | |
1090 | aal0 |= (stat & SAR_RSQE_CLP) ? 0x00000001 : 0; | |
1091 | ||
1092 | *((u32 *) sb->data) = aal0; | |
1093 | skb_put(sb, sizeof(u32)); | |
59ae1d12 | 1094 | skb_put_data(sb, cell, ATM_CELL_PAYLOAD); |
1da177e4 LT |
1095 | |
1096 | ATM_SKB(sb)->vcc = vcc; | |
a61bbcf2 | 1097 | __net_timestamp(sb); |
1da177e4 LT |
1098 | vcc->push(vcc, sb); |
1099 | atomic_inc(&vcc->stats->rx); | |
1100 | ||
1101 | cell += ATM_CELL_PAYLOAD; | |
1102 | } | |
1103 | ||
1104 | recycle_rx_skb(card, skb); | |
1105 | return; | |
1106 | } | |
1107 | if (vcc->qos.aal != ATM_AAL5) { | |
1108 | printk("%s: Unexpected AAL type in dequeue_rx(): %d.\n", | |
1109 | card->name, vcc->qos.aal); | |
1110 | recycle_rx_skb(card, skb); | |
1111 | return; | |
1112 | } | |
1113 | skb->len = (stat & SAR_RSQE_CELLCNT) * ATM_CELL_PAYLOAD; | |
1114 | ||
1115 | rpp = &vc->rcv.rx_pool; | |
1116 | ||
ceade961 | 1117 | __skb_queue_tail(&rpp->queue, skb); |
1da177e4 | 1118 | rpp->len += skb->len; |
1da177e4 LT |
1119 | |
1120 | if (stat & SAR_RSQE_EPDU) { | |
1121 | unsigned char *l1l2; | |
1122 | unsigned int len; | |
1123 | ||
1124 | l1l2 = (unsigned char *) ((unsigned long) skb->data + skb->len - 6); | |
1125 | ||
1126 | len = (l1l2[0] << 8) | l1l2[1]; | |
1127 | len = len ? len : 0x10000; | |
1128 | ||
1129 | RXPRINTK("%s: PDU has %d bytes.\n", card->name, len); | |
1130 | ||
1131 | if ((len + 8 > rpp->len) || (len + (47 + 8) < rpp->len)) { | |
1132 | RXPRINTK("%s: AAL5 PDU size mismatch: %d != %d. " | |
1133 | "(CDC: %08x)\n", | |
1134 | card->name, len, rpp->len, readl(SAR_REG_CDC)); | |
1135 | recycle_rx_pool_skb(card, rpp); | |
1136 | atomic_inc(&vcc->stats->rx_err); | |
1137 | return; | |
1138 | } | |
1139 | if (stat & SAR_RSQE_CRC) { | |
1140 | RXPRINTK("%s: AAL5 CRC error.\n", card->name); | |
1141 | recycle_rx_pool_skb(card, rpp); | |
1142 | atomic_inc(&vcc->stats->rx_err); | |
1143 | return; | |
1144 | } | |
ceade961 | 1145 | if (skb_queue_len(&rpp->queue) > 1) { |
1da177e4 LT |
1146 | struct sk_buff *sb; |
1147 | ||
1148 | skb = dev_alloc_skb(rpp->len); | |
1149 | if (!skb) { | |
1150 | RXPRINTK("%s: Can't alloc RX skb.\n", | |
1151 | card->name); | |
1152 | recycle_rx_pool_skb(card, rpp); | |
1153 | atomic_inc(&vcc->stats->rx_err); | |
1154 | return; | |
1155 | } | |
1156 | if (!atm_charge(vcc, skb->truesize)) { | |
1157 | recycle_rx_pool_skb(card, rpp); | |
1158 | dev_kfree_skb(skb); | |
1159 | return; | |
1160 | } | |
ceade961 | 1161 | skb_queue_walk(&rpp->queue, sb) |
59ae1d12 | 1162 | skb_put_data(skb, sb->data, sb->len); |
1da177e4 LT |
1163 | |
1164 | recycle_rx_pool_skb(card, rpp); | |
1165 | ||
1166 | skb_trim(skb, len); | |
1167 | ATM_SKB(skb)->vcc = vcc; | |
a61bbcf2 | 1168 | __net_timestamp(skb); |
1da177e4 LT |
1169 | |
1170 | vcc->push(vcc, skb); | |
1171 | atomic_inc(&vcc->stats->rx); | |
1172 | ||
1173 | return; | |
1174 | } | |
1175 | ||
1da177e4 LT |
1176 | flush_rx_pool(card, rpp); |
1177 | ||
1178 | if (!atm_charge(vcc, skb->truesize)) { | |
1179 | recycle_rx_skb(card, skb); | |
1180 | return; | |
1181 | } | |
1182 | ||
ede58ef2 | 1183 | dma_unmap_single(&card->pcidev->dev, IDT77252_PRV_PADDR(skb), |
4305b541 | 1184 | skb_end_pointer(skb) - skb->data, |
ede58ef2 | 1185 | DMA_FROM_DEVICE); |
1da177e4 LT |
1186 | sb_pool_remove(card, skb); |
1187 | ||
1188 | skb_trim(skb, len); | |
1189 | ATM_SKB(skb)->vcc = vcc; | |
a61bbcf2 | 1190 | __net_timestamp(skb); |
1da177e4 LT |
1191 | |
1192 | vcc->push(vcc, skb); | |
1193 | atomic_inc(&vcc->stats->rx); | |
1194 | ||
1195 | if (skb->truesize > SAR_FB_SIZE_3) | |
1196 | add_rx_skb(card, 3, SAR_FB_SIZE_3, 1); | |
1197 | else if (skb->truesize > SAR_FB_SIZE_2) | |
1198 | add_rx_skb(card, 2, SAR_FB_SIZE_2, 1); | |
1199 | else if (skb->truesize > SAR_FB_SIZE_1) | |
1200 | add_rx_skb(card, 1, SAR_FB_SIZE_1, 1); | |
1201 | else | |
1202 | add_rx_skb(card, 0, SAR_FB_SIZE_0, 1); | |
1203 | return; | |
1204 | } | |
1205 | } | |
1206 | ||
1207 | static void | |
1208 | idt77252_rx(struct idt77252_dev *card) | |
1209 | { | |
1210 | struct rsq_entry *rsqe; | |
1211 | ||
1212 | if (card->rsq.next == card->rsq.last) | |
1213 | rsqe = card->rsq.base; | |
1214 | else | |
1215 | rsqe = card->rsq.next + 1; | |
1216 | ||
1217 | if (!(le32_to_cpu(rsqe->word_4) & SAR_RSQE_VALID)) { | |
1218 | RXPRINTK("%s: no entry in RSQ.\n", card->name); | |
1219 | return; | |
1220 | } | |
1221 | ||
1222 | do { | |
1223 | dequeue_rx(card, rsqe); | |
1224 | rsqe->word_4 = 0; | |
1225 | card->rsq.next = rsqe; | |
1226 | if (card->rsq.next == card->rsq.last) | |
1227 | rsqe = card->rsq.base; | |
1228 | else | |
1229 | rsqe = card->rsq.next + 1; | |
1230 | } while (le32_to_cpu(rsqe->word_4) & SAR_RSQE_VALID); | |
1231 | ||
1232 | writel((unsigned long) card->rsq.next - (unsigned long) card->rsq.base, | |
1233 | SAR_REG_RSQH); | |
1234 | } | |
1235 | ||
1236 | static void | |
1237 | idt77252_rx_raw(struct idt77252_dev *card) | |
1238 | { | |
1239 | struct sk_buff *queue; | |
1240 | u32 head, tail; | |
1241 | struct atm_vcc *vcc; | |
1242 | struct vc_map *vc; | |
1243 | struct sk_buff *sb; | |
1244 | ||
1245 | if (card->raw_cell_head == NULL) { | |
1246 | u32 handle = le32_to_cpu(*(card->raw_cell_hnd + 1)); | |
1247 | card->raw_cell_head = sb_pool_skb(card, handle); | |
1248 | } | |
1249 | ||
1250 | queue = card->raw_cell_head; | |
1251 | if (!queue) | |
1252 | return; | |
1253 | ||
1254 | head = IDT77252_PRV_PADDR(queue) + (queue->data - queue->head - 16); | |
1255 | tail = readl(SAR_REG_RAWCT); | |
1256 | ||
ede58ef2 C |
1257 | dma_sync_single_for_cpu(&card->pcidev->dev, IDT77252_PRV_PADDR(queue), |
1258 | skb_end_offset(queue) - 16, | |
1259 | DMA_FROM_DEVICE); | |
1da177e4 LT |
1260 | |
1261 | while (head != tail) { | |
edb4dcb7 | 1262 | unsigned int vpi, vci; |
1da177e4 LT |
1263 | u32 header; |
1264 | ||
1265 | header = le32_to_cpu(*(u32 *) &queue->data[0]); | |
1266 | ||
1267 | vpi = (header & ATM_HDR_VPI_MASK) >> ATM_HDR_VPI_SHIFT; | |
1268 | vci = (header & ATM_HDR_VCI_MASK) >> ATM_HDR_VCI_SHIFT; | |
1da177e4 LT |
1269 | |
1270 | #ifdef CONFIG_ATM_IDT77252_DEBUG | |
1271 | if (debug & DBG_RAW_CELL) { | |
1272 | int i; | |
1273 | ||
1274 | printk("%s: raw cell %x.%02x.%04x.%x.%x\n", | |
1275 | card->name, (header >> 28) & 0x000f, | |
1276 | (header >> 20) & 0x00ff, | |
1277 | (header >> 4) & 0xffff, | |
1278 | (header >> 1) & 0x0007, | |
1279 | (header >> 0) & 0x0001); | |
1280 | for (i = 16; i < 64; i++) | |
1281 | printk(" %02x", queue->data[i]); | |
1282 | printk("\n"); | |
1283 | } | |
1284 | #endif | |
1285 | ||
1286 | if (vpi >= (1<<card->vpibits) || vci >= (1<<card->vcibits)) { | |
1287 | RPRINTK("%s: SDU received for out-of-range vc %u.%u\n", | |
1288 | card->name, vpi, vci); | |
1289 | goto drop; | |
1290 | } | |
1291 | ||
1292 | vc = card->vcs[VPCI2VC(card, vpi, vci)]; | |
1293 | if (!vc || !test_bit(VCF_RX, &vc->flags)) { | |
1294 | RPRINTK("%s: SDU received on non RX vc %u.%u\n", | |
1295 | card->name, vpi, vci); | |
1296 | goto drop; | |
1297 | } | |
1298 | ||
1299 | vcc = vc->rx_vcc; | |
1300 | ||
1301 | if (vcc->qos.aal != ATM_AAL0) { | |
1302 | RPRINTK("%s: raw cell for non AAL0 vc %u.%u\n", | |
1303 | card->name, vpi, vci); | |
1304 | atomic_inc(&vcc->stats->rx_drop); | |
1305 | goto drop; | |
1306 | } | |
1307 | ||
1308 | if ((sb = dev_alloc_skb(64)) == NULL) { | |
1309 | printk("%s: Can't allocate buffers for AAL0.\n", | |
1310 | card->name); | |
1311 | atomic_inc(&vcc->stats->rx_err); | |
1312 | goto drop; | |
1313 | } | |
1314 | ||
1315 | if (!atm_charge(vcc, sb->truesize)) { | |
1316 | RXPRINTK("%s: atm_charge() dropped AAL0 packets.\n", | |
1317 | card->name); | |
1318 | dev_kfree_skb(sb); | |
1319 | goto drop; | |
1320 | } | |
1321 | ||
1322 | *((u32 *) sb->data) = header; | |
1323 | skb_put(sb, sizeof(u32)); | |
59ae1d12 | 1324 | skb_put_data(sb, &(queue->data[16]), ATM_CELL_PAYLOAD); |
1da177e4 LT |
1325 | |
1326 | ATM_SKB(sb)->vcc = vcc; | |
a61bbcf2 | 1327 | __net_timestamp(sb); |
1da177e4 LT |
1328 | vcc->push(vcc, sb); |
1329 | atomic_inc(&vcc->stats->rx); | |
1330 | ||
1331 | drop: | |
1332 | skb_pull(queue, 64); | |
1333 | ||
1334 | head = IDT77252_PRV_PADDR(queue) | |
1335 | + (queue->data - queue->head - 16); | |
1336 | ||
1337 | if (queue->len < 128) { | |
1338 | struct sk_buff *next; | |
1339 | u32 handle; | |
1340 | ||
1341 | head = le32_to_cpu(*(u32 *) &queue->data[0]); | |
1342 | handle = le32_to_cpu(*(u32 *) &queue->data[4]); | |
1343 | ||
1344 | next = sb_pool_skb(card, handle); | |
1345 | recycle_rx_skb(card, queue); | |
1346 | ||
1347 | if (next) { | |
1348 | card->raw_cell_head = next; | |
1349 | queue = card->raw_cell_head; | |
ede58ef2 C |
1350 | dma_sync_single_for_cpu(&card->pcidev->dev, |
1351 | IDT77252_PRV_PADDR(queue), | |
1352 | (skb_end_pointer(queue) - | |
1353 | queue->data), | |
1354 | DMA_FROM_DEVICE); | |
1da177e4 LT |
1355 | } else { |
1356 | card->raw_cell_head = NULL; | |
1357 | printk("%s: raw cell queue overrun\n", | |
1358 | card->name); | |
1359 | break; | |
1360 | } | |
1361 | } | |
1362 | } | |
1363 | } | |
1364 | ||
1365 | ||
1366 | /*****************************************************************************/ | |
1367 | /* */ | |
1368 | /* TSQ Handling */ | |
1369 | /* */ | |
1370 | /*****************************************************************************/ | |
1371 | ||
1372 | static int | |
1373 | init_tsq(struct idt77252_dev *card) | |
1374 | { | |
1375 | struct tsq_entry *tsqe; | |
1376 | ||
ede58ef2 C |
1377 | card->tsq.base = dma_alloc_coherent(&card->pcidev->dev, RSQSIZE, |
1378 | &card->tsq.paddr, GFP_KERNEL); | |
1da177e4 LT |
1379 | if (card->tsq.base == NULL) { |
1380 | printk("%s: can't allocate TSQ.\n", card->name); | |
1381 | return -1; | |
1382 | } | |
1da177e4 LT |
1383 | |
1384 | card->tsq.last = card->tsq.base + TSQ_NUM_ENTRIES - 1; | |
1385 | card->tsq.next = card->tsq.last; | |
1386 | for (tsqe = card->tsq.base; tsqe <= card->tsq.last; tsqe++) | |
1387 | tsqe->word_2 = cpu_to_le32(SAR_TSQE_INVALID); | |
1388 | ||
1389 | writel(card->tsq.paddr, SAR_REG_TSQB); | |
1390 | writel((unsigned long) card->tsq.next - (unsigned long) card->tsq.base, | |
1391 | SAR_REG_TSQH); | |
1392 | ||
1393 | return 0; | |
1394 | } | |
1395 | ||
1396 | static void | |
1397 | deinit_tsq(struct idt77252_dev *card) | |
1398 | { | |
ede58ef2 C |
1399 | dma_free_coherent(&card->pcidev->dev, TSQSIZE, |
1400 | card->tsq.base, card->tsq.paddr); | |
1da177e4 LT |
1401 | } |
1402 | ||
1403 | static void | |
1404 | idt77252_tx(struct idt77252_dev *card) | |
1405 | { | |
1406 | struct tsq_entry *tsqe; | |
1407 | unsigned int vpi, vci; | |
1408 | struct vc_map *vc; | |
1409 | u32 conn, stat; | |
1410 | ||
1411 | if (card->tsq.next == card->tsq.last) | |
1412 | tsqe = card->tsq.base; | |
1413 | else | |
1414 | tsqe = card->tsq.next + 1; | |
1415 | ||
1416 | TXPRINTK("idt77252_tx: tsq %p: base %p, next %p, last %p\n", tsqe, | |
1417 | card->tsq.base, card->tsq.next, card->tsq.last); | |
1418 | TXPRINTK("idt77252_tx: tsqb %08x, tsqt %08x, tsqh %08x, \n", | |
1419 | readl(SAR_REG_TSQB), | |
1420 | readl(SAR_REG_TSQT), | |
1421 | readl(SAR_REG_TSQH)); | |
1422 | ||
1423 | stat = le32_to_cpu(tsqe->word_2); | |
1424 | ||
1425 | if (stat & SAR_TSQE_INVALID) | |
1426 | return; | |
1427 | ||
1428 | do { | |
1429 | TXPRINTK("tsqe: 0x%p [0x%08x 0x%08x]\n", tsqe, | |
1430 | le32_to_cpu(tsqe->word_1), | |
1431 | le32_to_cpu(tsqe->word_2)); | |
1432 | ||
1433 | switch (stat & SAR_TSQE_TYPE) { | |
1434 | case SAR_TSQE_TYPE_TIMER: | |
1435 | TXPRINTK("%s: Timer RollOver detected.\n", card->name); | |
1436 | break; | |
1437 | ||
1438 | case SAR_TSQE_TYPE_IDLE: | |
1439 | ||
1440 | conn = le32_to_cpu(tsqe->word_1); | |
1441 | ||
1442 | if (SAR_TSQE_TAG(stat) == 0x10) { | |
1443 | #ifdef NOTDEF | |
1444 | printk("%s: Connection %d halted.\n", | |
1445 | card->name, | |
1446 | le32_to_cpu(tsqe->word_1) & 0x1fff); | |
1447 | #endif | |
1448 | break; | |
1449 | } | |
1450 | ||
1451 | vc = card->vcs[conn & 0x1fff]; | |
1452 | if (!vc) { | |
1453 | printk("%s: could not find VC from conn %d\n", | |
1454 | card->name, conn & 0x1fff); | |
1455 | break; | |
1456 | } | |
1457 | ||
1458 | printk("%s: Connection %d IDLE.\n", | |
1459 | card->name, vc->index); | |
1460 | ||
1461 | set_bit(VCF_IDLE, &vc->flags); | |
1462 | break; | |
1463 | ||
1464 | case SAR_TSQE_TYPE_TSR: | |
1465 | ||
1466 | conn = le32_to_cpu(tsqe->word_1); | |
1467 | ||
1468 | vc = card->vcs[conn & 0x1fff]; | |
1469 | if (!vc) { | |
1470 | printk("%s: no VC at index %d\n", | |
1471 | card->name, | |
1472 | le32_to_cpu(tsqe->word_1) & 0x1fff); | |
1473 | break; | |
1474 | } | |
1475 | ||
1476 | drain_scq(card, vc); | |
1477 | break; | |
1478 | ||
1479 | case SAR_TSQE_TYPE_TBD_COMP: | |
1480 | ||
1481 | conn = le32_to_cpu(tsqe->word_1); | |
1482 | ||
1483 | vpi = (conn >> SAR_TBD_VPI_SHIFT) & 0x00ff; | |
1484 | vci = (conn >> SAR_TBD_VCI_SHIFT) & 0xffff; | |
1485 | ||
1486 | if (vpi >= (1 << card->vpibits) || | |
1487 | vci >= (1 << card->vcibits)) { | |
1488 | printk("%s: TBD complete: " | |
1489 | "out of range VPI.VCI %u.%u\n", | |
1490 | card->name, vpi, vci); | |
1491 | break; | |
1492 | } | |
1493 | ||
1494 | vc = card->vcs[VPCI2VC(card, vpi, vci)]; | |
1495 | if (!vc) { | |
1496 | printk("%s: TBD complete: " | |
1497 | "no VC at VPI.VCI %u.%u\n", | |
1498 | card->name, vpi, vci); | |
1499 | break; | |
1500 | } | |
1501 | ||
1502 | drain_scq(card, vc); | |
1503 | break; | |
1504 | } | |
1505 | ||
1506 | tsqe->word_2 = cpu_to_le32(SAR_TSQE_INVALID); | |
1507 | ||
1508 | card->tsq.next = tsqe; | |
1509 | if (card->tsq.next == card->tsq.last) | |
1510 | tsqe = card->tsq.base; | |
1511 | else | |
1512 | tsqe = card->tsq.next + 1; | |
1513 | ||
1514 | TXPRINTK("tsqe: %p: base %p, next %p, last %p\n", tsqe, | |
1515 | card->tsq.base, card->tsq.next, card->tsq.last); | |
1516 | ||
1517 | stat = le32_to_cpu(tsqe->word_2); | |
1518 | ||
1519 | } while (!(stat & SAR_TSQE_INVALID)); | |
1520 | ||
1521 | writel((unsigned long)card->tsq.next - (unsigned long)card->tsq.base, | |
1522 | SAR_REG_TSQH); | |
1523 | ||
1524 | XPRINTK("idt77252_tx-after writel%d: TSQ head = 0x%x, tail = 0x%x, next = 0x%p.\n", | |
1525 | card->index, readl(SAR_REG_TSQH), | |
1526 | readl(SAR_REG_TSQT), card->tsq.next); | |
1527 | } | |
1528 | ||
1529 | ||
1530 | static void | |
e99e88a9 | 1531 | tst_timer(struct timer_list *t) |
1da177e4 | 1532 | { |
e99e88a9 | 1533 | struct idt77252_dev *card = from_timer(card, t, tst_timer); |
1da177e4 LT |
1534 | unsigned long base, idle, jump; |
1535 | unsigned long flags; | |
1536 | u32 pc; | |
1537 | int e; | |
1538 | ||
1539 | spin_lock_irqsave(&card->tst_lock, flags); | |
1540 | ||
1541 | base = card->tst[card->tst_index]; | |
1542 | idle = card->tst[card->tst_index ^ 1]; | |
1543 | ||
1544 | if (test_bit(TST_SWITCH_WAIT, &card->tst_state)) { | |
1545 | jump = base + card->tst_size - 2; | |
1546 | ||
1547 | pc = readl(SAR_REG_NOW) >> 2; | |
1548 | if ((pc ^ idle) & ~(card->tst_size - 1)) { | |
1549 | mod_timer(&card->tst_timer, jiffies + 1); | |
1550 | goto out; | |
1551 | } | |
1552 | ||
1553 | clear_bit(TST_SWITCH_WAIT, &card->tst_state); | |
1554 | ||
1555 | card->tst_index ^= 1; | |
1556 | write_sram(card, jump, TSTE_OPC_JMP | (base << 2)); | |
1557 | ||
1558 | base = card->tst[card->tst_index]; | |
1559 | idle = card->tst[card->tst_index ^ 1]; | |
1560 | ||
1561 | for (e = 0; e < card->tst_size - 2; e++) { | |
1562 | if (card->soft_tst[e].tste & TSTE_PUSH_IDLE) { | |
1563 | write_sram(card, idle + e, | |
1564 | card->soft_tst[e].tste & TSTE_MASK); | |
1565 | card->soft_tst[e].tste &= ~(TSTE_PUSH_IDLE); | |
1566 | } | |
1567 | } | |
1568 | } | |
1569 | ||
1570 | if (test_and_clear_bit(TST_SWITCH_PENDING, &card->tst_state)) { | |
1571 | ||
1572 | for (e = 0; e < card->tst_size - 2; e++) { | |
1573 | if (card->soft_tst[e].tste & TSTE_PUSH_ACTIVE) { | |
1574 | write_sram(card, idle + e, | |
1575 | card->soft_tst[e].tste & TSTE_MASK); | |
1576 | card->soft_tst[e].tste &= ~(TSTE_PUSH_ACTIVE); | |
1577 | card->soft_tst[e].tste |= TSTE_PUSH_IDLE; | |
1578 | } | |
1579 | } | |
1580 | ||
1581 | jump = base + card->tst_size - 2; | |
1582 | ||
1583 | write_sram(card, jump, TSTE_OPC_NULL); | |
1584 | set_bit(TST_SWITCH_WAIT, &card->tst_state); | |
1585 | ||
1586 | mod_timer(&card->tst_timer, jiffies + 1); | |
1587 | } | |
1588 | ||
1589 | out: | |
1590 | spin_unlock_irqrestore(&card->tst_lock, flags); | |
1591 | } | |
1592 | ||
1593 | static int | |
1594 | __fill_tst(struct idt77252_dev *card, struct vc_map *vc, | |
1595 | int n, unsigned int opc) | |
1596 | { | |
1597 | unsigned long cl, avail; | |
1598 | unsigned long idle; | |
1599 | int e, r; | |
1600 | u32 data; | |
1601 | ||
1602 | avail = card->tst_size - 2; | |
1603 | for (e = 0; e < avail; e++) { | |
1604 | if (card->soft_tst[e].vc == NULL) | |
1605 | break; | |
1606 | } | |
1607 | if (e >= avail) { | |
1608 | printk("%s: No free TST entries found\n", card->name); | |
1609 | return -1; | |
1610 | } | |
1611 | ||
1612 | NPRINTK("%s: conn %d: first TST entry at %d.\n", | |
1613 | card->name, vc ? vc->index : -1, e); | |
1614 | ||
1615 | r = n; | |
1616 | cl = avail; | |
1617 | data = opc & TSTE_OPC_MASK; | |
1618 | if (vc && (opc != TSTE_OPC_NULL)) | |
1619 | data = opc | vc->index; | |
1620 | ||
1621 | idle = card->tst[card->tst_index ^ 1]; | |
1622 | ||
1623 | /* | |
1624 | * Fill Soft TST. | |
1625 | */ | |
1626 | while (r > 0) { | |
1627 | if ((cl >= avail) && (card->soft_tst[e].vc == NULL)) { | |
1628 | if (vc) | |
1629 | card->soft_tst[e].vc = vc; | |
1630 | else | |
1631 | card->soft_tst[e].vc = (void *)-1; | |
1632 | ||
1633 | card->soft_tst[e].tste = data; | |
1634 | if (timer_pending(&card->tst_timer)) | |
1635 | card->soft_tst[e].tste |= TSTE_PUSH_ACTIVE; | |
1636 | else { | |
1637 | write_sram(card, idle + e, data); | |
1638 | card->soft_tst[e].tste |= TSTE_PUSH_IDLE; | |
1639 | } | |
1640 | ||
1641 | cl -= card->tst_size; | |
1642 | r--; | |
1643 | } | |
1644 | ||
1645 | if (++e == avail) | |
1646 | e = 0; | |
1647 | cl += n; | |
1648 | } | |
1649 | ||
1650 | return 0; | |
1651 | } | |
1652 | ||
1653 | static int | |
1654 | fill_tst(struct idt77252_dev *card, struct vc_map *vc, int n, unsigned int opc) | |
1655 | { | |
1656 | unsigned long flags; | |
1657 | int res; | |
1658 | ||
1659 | spin_lock_irqsave(&card->tst_lock, flags); | |
1660 | ||
1661 | res = __fill_tst(card, vc, n, opc); | |
1662 | ||
1663 | set_bit(TST_SWITCH_PENDING, &card->tst_state); | |
1664 | if (!timer_pending(&card->tst_timer)) | |
1665 | mod_timer(&card->tst_timer, jiffies + 1); | |
1666 | ||
1667 | spin_unlock_irqrestore(&card->tst_lock, flags); | |
1668 | return res; | |
1669 | } | |
1670 | ||
1671 | static int | |
1672 | __clear_tst(struct idt77252_dev *card, struct vc_map *vc) | |
1673 | { | |
1674 | unsigned long idle; | |
1675 | int e; | |
1676 | ||
1677 | idle = card->tst[card->tst_index ^ 1]; | |
1678 | ||
1679 | for (e = 0; e < card->tst_size - 2; e++) { | |
1680 | if (card->soft_tst[e].vc == vc) { | |
1681 | card->soft_tst[e].vc = NULL; | |
1682 | ||
1683 | card->soft_tst[e].tste = TSTE_OPC_VAR; | |
1684 | if (timer_pending(&card->tst_timer)) | |
1685 | card->soft_tst[e].tste |= TSTE_PUSH_ACTIVE; | |
1686 | else { | |
1687 | write_sram(card, idle + e, TSTE_OPC_VAR); | |
1688 | card->soft_tst[e].tste |= TSTE_PUSH_IDLE; | |
1689 | } | |
1690 | } | |
1691 | } | |
1692 | ||
1693 | return 0; | |
1694 | } | |
1695 | ||
1696 | static int | |
1697 | clear_tst(struct idt77252_dev *card, struct vc_map *vc) | |
1698 | { | |
1699 | unsigned long flags; | |
1700 | int res; | |
1701 | ||
1702 | spin_lock_irqsave(&card->tst_lock, flags); | |
1703 | ||
1704 | res = __clear_tst(card, vc); | |
1705 | ||
1706 | set_bit(TST_SWITCH_PENDING, &card->tst_state); | |
1707 | if (!timer_pending(&card->tst_timer)) | |
1708 | mod_timer(&card->tst_timer, jiffies + 1); | |
1709 | ||
1710 | spin_unlock_irqrestore(&card->tst_lock, flags); | |
1711 | return res; | |
1712 | } | |
1713 | ||
1714 | static int | |
1715 | change_tst(struct idt77252_dev *card, struct vc_map *vc, | |
1716 | int n, unsigned int opc) | |
1717 | { | |
1718 | unsigned long flags; | |
1719 | int res; | |
1720 | ||
1721 | spin_lock_irqsave(&card->tst_lock, flags); | |
1722 | ||
1723 | __clear_tst(card, vc); | |
1724 | res = __fill_tst(card, vc, n, opc); | |
1725 | ||
1726 | set_bit(TST_SWITCH_PENDING, &card->tst_state); | |
1727 | if (!timer_pending(&card->tst_timer)) | |
1728 | mod_timer(&card->tst_timer, jiffies + 1); | |
1729 | ||
1730 | spin_unlock_irqrestore(&card->tst_lock, flags); | |
1731 | return res; | |
1732 | } | |
1733 | ||
1734 | ||
1735 | static int | |
1736 | set_tct(struct idt77252_dev *card, struct vc_map *vc) | |
1737 | { | |
1738 | unsigned long tct; | |
1739 | ||
1740 | tct = (unsigned long) (card->tct_base + vc->index * SAR_SRAM_TCT_SIZE); | |
1741 | ||
1742 | switch (vc->class) { | |
1743 | case SCHED_CBR: | |
1744 | OPRINTK("%s: writing TCT at 0x%lx, SCD 0x%lx.\n", | |
1745 | card->name, tct, vc->scq->scd); | |
1746 | ||
1747 | write_sram(card, tct + 0, TCT_CBR | vc->scq->scd); | |
1748 | write_sram(card, tct + 1, 0); | |
1749 | write_sram(card, tct + 2, 0); | |
1750 | write_sram(card, tct + 3, 0); | |
1751 | write_sram(card, tct + 4, 0); | |
1752 | write_sram(card, tct + 5, 0); | |
1753 | write_sram(card, tct + 6, 0); | |
1754 | write_sram(card, tct + 7, 0); | |
1755 | break; | |
1756 | ||
1757 | case SCHED_UBR: | |
1758 | OPRINTK("%s: writing TCT at 0x%lx, SCD 0x%lx.\n", | |
1759 | card->name, tct, vc->scq->scd); | |
1760 | ||
1761 | write_sram(card, tct + 0, TCT_UBR | vc->scq->scd); | |
1762 | write_sram(card, tct + 1, 0); | |
1763 | write_sram(card, tct + 2, TCT_TSIF); | |
1764 | write_sram(card, tct + 3, TCT_HALT | TCT_IDLE); | |
1765 | write_sram(card, tct + 4, 0); | |
1766 | write_sram(card, tct + 5, vc->init_er); | |
1767 | write_sram(card, tct + 6, 0); | |
1768 | write_sram(card, tct + 7, TCT_FLAG_UBR); | |
1769 | break; | |
1770 | ||
1771 | case SCHED_VBR: | |
1772 | case SCHED_ABR: | |
1773 | default: | |
1774 | return -ENOSYS; | |
1775 | } | |
1776 | ||
1777 | return 0; | |
1778 | } | |
1779 | ||
1780 | /*****************************************************************************/ | |
1781 | /* */ | |
1782 | /* FBQ Handling */ | |
1783 | /* */ | |
1784 | /*****************************************************************************/ | |
1785 | ||
1da177e4 LT |
1786 | static __inline__ int |
1787 | idt77252_fbq_full(struct idt77252_dev *card, int queue) | |
1788 | { | |
1789 | return (readl(SAR_REG_STAT) >> (16 + (queue << 2))) == 0x0f; | |
1790 | } | |
1791 | ||
1792 | static int | |
1793 | push_rx_skb(struct idt77252_dev *card, struct sk_buff *skb, int queue) | |
1794 | { | |
1795 | unsigned long flags; | |
1796 | u32 handle; | |
1797 | u32 addr; | |
1798 | ||
27a884dc ACM |
1799 | skb->data = skb->head; |
1800 | skb_reset_tail_pointer(skb); | |
1da177e4 LT |
1801 | skb->len = 0; |
1802 | ||
1803 | skb_reserve(skb, 16); | |
1804 | ||
1805 | switch (queue) { | |
1806 | case 0: | |
1807 | skb_put(skb, SAR_FB_SIZE_0); | |
1808 | break; | |
1809 | case 1: | |
1810 | skb_put(skb, SAR_FB_SIZE_1); | |
1811 | break; | |
1812 | case 2: | |
1813 | skb_put(skb, SAR_FB_SIZE_2); | |
1814 | break; | |
1815 | case 3: | |
1816 | skb_put(skb, SAR_FB_SIZE_3); | |
1817 | break; | |
1818 | default: | |
1da177e4 LT |
1819 | return -1; |
1820 | } | |
1821 | ||
1822 | if (idt77252_fbq_full(card, queue)) | |
1823 | return -1; | |
1824 | ||
1825 | memset(&skb->data[(skb->len & ~(0x3f)) - 64], 0, 2 * sizeof(u32)); | |
1826 | ||
1827 | handle = IDT77252_PRV_POOL(skb); | |
1828 | addr = IDT77252_PRV_PADDR(skb); | |
1829 | ||
1830 | spin_lock_irqsave(&card->cmd_lock, flags); | |
1831 | writel(handle, card->fbq[queue]); | |
1832 | writel(addr, card->fbq[queue]); | |
1833 | spin_unlock_irqrestore(&card->cmd_lock, flags); | |
1834 | ||
1835 | return 0; | |
1836 | } | |
1837 | ||
1838 | static void | |
1839 | add_rx_skb(struct idt77252_dev *card, int queue, | |
1840 | unsigned int size, unsigned int count) | |
1841 | { | |
1842 | struct sk_buff *skb; | |
1843 | dma_addr_t paddr; | |
1844 | u32 handle; | |
1845 | ||
1846 | while (count--) { | |
1847 | skb = dev_alloc_skb(size); | |
1848 | if (!skb) | |
1849 | return; | |
1850 | ||
1851 | if (sb_pool_add(card, skb, queue)) { | |
5a346a10 | 1852 | printk("%s: SB POOL full\n", __func__); |
1da177e4 LT |
1853 | goto outfree; |
1854 | } | |
1855 | ||
ede58ef2 | 1856 | paddr = dma_map_single(&card->pcidev->dev, skb->data, |
4305b541 | 1857 | skb_end_pointer(skb) - skb->data, |
ede58ef2 | 1858 | DMA_FROM_DEVICE); |
1da177e4 LT |
1859 | IDT77252_PRV_PADDR(skb) = paddr; |
1860 | ||
1861 | if (push_rx_skb(card, skb, queue)) { | |
5a346a10 | 1862 | printk("%s: FB QUEUE full\n", __func__); |
1da177e4 LT |
1863 | goto outunmap; |
1864 | } | |
1865 | } | |
1866 | ||
1867 | return; | |
1868 | ||
1869 | outunmap: | |
ede58ef2 C |
1870 | dma_unmap_single(&card->pcidev->dev, IDT77252_PRV_PADDR(skb), |
1871 | skb_end_pointer(skb) - skb->data, DMA_FROM_DEVICE); | |
1da177e4 LT |
1872 | |
1873 | handle = IDT77252_PRV_POOL(skb); | |
1874 | card->sbpool[POOL_QUEUE(handle)].skb[POOL_INDEX(handle)] = NULL; | |
1875 | ||
1876 | outfree: | |
1877 | dev_kfree_skb(skb); | |
1878 | } | |
1879 | ||
1880 | ||
1881 | static void | |
1882 | recycle_rx_skb(struct idt77252_dev *card, struct sk_buff *skb) | |
1883 | { | |
1884 | u32 handle = IDT77252_PRV_POOL(skb); | |
1885 | int err; | |
1886 | ||
ede58ef2 C |
1887 | dma_sync_single_for_device(&card->pcidev->dev, IDT77252_PRV_PADDR(skb), |
1888 | skb_end_pointer(skb) - skb->data, | |
1889 | DMA_FROM_DEVICE); | |
1da177e4 LT |
1890 | |
1891 | err = push_rx_skb(card, skb, POOL_QUEUE(handle)); | |
1892 | if (err) { | |
ede58ef2 | 1893 | dma_unmap_single(&card->pcidev->dev, IDT77252_PRV_PADDR(skb), |
4305b541 | 1894 | skb_end_pointer(skb) - skb->data, |
ede58ef2 | 1895 | DMA_FROM_DEVICE); |
1da177e4 LT |
1896 | sb_pool_remove(card, skb); |
1897 | dev_kfree_skb(skb); | |
1898 | } | |
1899 | } | |
1900 | ||
1901 | static void | |
1902 | flush_rx_pool(struct idt77252_dev *card, struct rx_pool *rpp) | |
1903 | { | |
ceade961 | 1904 | skb_queue_head_init(&rpp->queue); |
1da177e4 | 1905 | rpp->len = 0; |
1da177e4 LT |
1906 | } |
1907 | ||
1908 | static void | |
1909 | recycle_rx_pool_skb(struct idt77252_dev *card, struct rx_pool *rpp) | |
1910 | { | |
ceade961 | 1911 | struct sk_buff *skb, *tmp; |
1da177e4 | 1912 | |
ceade961 | 1913 | skb_queue_walk_safe(&rpp->queue, skb, tmp) |
1da177e4 | 1914 | recycle_rx_skb(card, skb); |
ceade961 | 1915 | |
1da177e4 LT |
1916 | flush_rx_pool(card, rpp); |
1917 | } | |
1918 | ||
1919 | /*****************************************************************************/ | |
1920 | /* */ | |
1921 | /* ATM Interface */ | |
1922 | /* */ | |
1923 | /*****************************************************************************/ | |
1924 | ||
1925 | static void | |
1926 | idt77252_phy_put(struct atm_dev *dev, unsigned char value, unsigned long addr) | |
1927 | { | |
1928 | write_utility(dev->dev_data, 0x100 + (addr & 0x1ff), value); | |
1929 | } | |
1930 | ||
1931 | static unsigned char | |
1932 | idt77252_phy_get(struct atm_dev *dev, unsigned long addr) | |
1933 | { | |
1934 | return read_utility(dev->dev_data, 0x100 + (addr & 0x1ff)); | |
1935 | } | |
1936 | ||
1937 | static inline int | |
1938 | idt77252_send_skb(struct atm_vcc *vcc, struct sk_buff *skb, int oam) | |
1939 | { | |
1940 | struct atm_dev *dev = vcc->dev; | |
1941 | struct idt77252_dev *card = dev->dev_data; | |
1942 | struct vc_map *vc = vcc->dev_data; | |
1943 | int err; | |
1944 | ||
1945 | if (vc == NULL) { | |
1946 | printk("%s: NULL connection in send().\n", card->name); | |
1947 | atomic_inc(&vcc->stats->tx_err); | |
1948 | dev_kfree_skb(skb); | |
1949 | return -EINVAL; | |
1950 | } | |
1951 | if (!test_bit(VCF_TX, &vc->flags)) { | |
1952 | printk("%s: Trying to transmit on a non-tx VC.\n", card->name); | |
1953 | atomic_inc(&vcc->stats->tx_err); | |
1954 | dev_kfree_skb(skb); | |
1955 | return -EINVAL; | |
1956 | } | |
1957 | ||
1958 | switch (vcc->qos.aal) { | |
1959 | case ATM_AAL0: | |
1960 | case ATM_AAL1: | |
1961 | case ATM_AAL5: | |
1962 | break; | |
1963 | default: | |
1964 | printk("%s: Unsupported AAL: %d\n", card->name, vcc->qos.aal); | |
1965 | atomic_inc(&vcc->stats->tx_err); | |
1966 | dev_kfree_skb(skb); | |
1967 | return -EINVAL; | |
1968 | } | |
1969 | ||
1970 | if (skb_shinfo(skb)->nr_frags != 0) { | |
1971 | printk("%s: No scatter-gather yet.\n", card->name); | |
1972 | atomic_inc(&vcc->stats->tx_err); | |
1973 | dev_kfree_skb(skb); | |
1974 | return -EINVAL; | |
1975 | } | |
1976 | ATM_SKB(skb)->vcc = vcc; | |
1977 | ||
1978 | err = queue_skb(card, vc, skb, oam); | |
1979 | if (err) { | |
1980 | atomic_inc(&vcc->stats->tx_err); | |
1981 | dev_kfree_skb(skb); | |
1982 | return err; | |
1983 | } | |
1984 | ||
1985 | return 0; | |
1986 | } | |
1987 | ||
f4c4b4a6 | 1988 | static int idt77252_send(struct atm_vcc *vcc, struct sk_buff *skb) |
1da177e4 LT |
1989 | { |
1990 | return idt77252_send_skb(vcc, skb, 0); | |
1991 | } | |
1992 | ||
1993 | static int | |
1994 | idt77252_send_oam(struct atm_vcc *vcc, void *cell, int flags) | |
1995 | { | |
1996 | struct atm_dev *dev = vcc->dev; | |
1997 | struct idt77252_dev *card = dev->dev_data; | |
1998 | struct sk_buff *skb; | |
1999 | ||
2000 | skb = dev_alloc_skb(64); | |
2001 | if (!skb) { | |
2002 | printk("%s: Out of memory in send_oam().\n", card->name); | |
2003 | atomic_inc(&vcc->stats->tx_err); | |
2004 | return -ENOMEM; | |
2005 | } | |
14afee4b | 2006 | refcount_add(skb->truesize, &sk_atm(vcc)->sk_wmem_alloc); |
1da177e4 | 2007 | |
59ae1d12 | 2008 | skb_put_data(skb, cell, 52); |
1da177e4 LT |
2009 | |
2010 | return idt77252_send_skb(vcc, skb, 1); | |
2011 | } | |
2012 | ||
2013 | static __inline__ unsigned int | |
2014 | idt77252_fls(unsigned int x) | |
2015 | { | |
2016 | int r = 1; | |
2017 | ||
2018 | if (x == 0) | |
2019 | return 0; | |
2020 | if (x & 0xffff0000) { | |
2021 | x >>= 16; | |
2022 | r += 16; | |
2023 | } | |
2024 | if (x & 0xff00) { | |
2025 | x >>= 8; | |
2026 | r += 8; | |
2027 | } | |
2028 | if (x & 0xf0) { | |
2029 | x >>= 4; | |
2030 | r += 4; | |
2031 | } | |
2032 | if (x & 0xc) { | |
2033 | x >>= 2; | |
2034 | r += 2; | |
2035 | } | |
2036 | if (x & 0x2) | |
2037 | r += 1; | |
2038 | return r; | |
2039 | } | |
2040 | ||
2041 | static u16 | |
2042 | idt77252_int_to_atmfp(unsigned int rate) | |
2043 | { | |
2044 | u16 m, e; | |
2045 | ||
2046 | if (rate == 0) | |
2047 | return 0; | |
2048 | e = idt77252_fls(rate) - 1; | |
2049 | if (e < 9) | |
2050 | m = (rate - (1 << e)) << (9 - e); | |
2051 | else if (e == 9) | |
2052 | m = (rate - (1 << e)); | |
2053 | else /* e > 9 */ | |
2054 | m = (rate - (1 << e)) >> (e - 9); | |
2055 | return 0x4000 | (e << 9) | m; | |
2056 | } | |
2057 | ||
2058 | static u8 | |
2059 | idt77252_rate_logindex(struct idt77252_dev *card, int pcr) | |
2060 | { | |
2061 | u16 afp; | |
2062 | ||
2063 | afp = idt77252_int_to_atmfp(pcr < 0 ? -pcr : pcr); | |
2064 | if (pcr < 0) | |
2065 | return rate_to_log[(afp >> 5) & 0x1ff]; | |
2066 | return rate_to_log[((afp >> 5) + 1) & 0x1ff]; | |
2067 | } | |
2068 | ||
2069 | static void | |
3d2ceaa6 | 2070 | idt77252_est_timer(struct timer_list *t) |
1da177e4 | 2071 | { |
3d2ceaa6 KC |
2072 | struct rate_estimator *est = from_timer(est, t, timer); |
2073 | struct vc_map *vc = est->vc; | |
1da177e4 | 2074 | struct idt77252_dev *card = vc->card; |
1da177e4 LT |
2075 | unsigned long flags; |
2076 | u32 rate, cps; | |
2077 | u64 ncells; | |
2078 | u8 lacr; | |
2079 | ||
2080 | spin_lock_irqsave(&vc->lock, flags); | |
3d2ceaa6 | 2081 | if (!vc->estimator) |
1da177e4 | 2082 | goto out; |
1da177e4 LT |
2083 | ncells = est->cells; |
2084 | ||
2085 | rate = ((u32)(ncells - est->last_cells)) << (7 - est->interval); | |
2086 | est->last_cells = ncells; | |
2087 | est->avcps += ((long)rate - (long)est->avcps) >> est->ewma_log; | |
2088 | est->cps = (est->avcps + 0x1f) >> 5; | |
2089 | ||
2090 | cps = est->cps; | |
2091 | if (cps < (est->maxcps >> 4)) | |
2092 | cps = est->maxcps >> 4; | |
2093 | ||
2094 | lacr = idt77252_rate_logindex(card, cps); | |
2095 | if (lacr > vc->max_er) | |
2096 | lacr = vc->max_er; | |
2097 | ||
2098 | if (lacr != vc->lacr) { | |
2099 | vc->lacr = lacr; | |
2100 | writel(TCMDQ_LACR|(vc->lacr << 16)|vc->index, SAR_REG_TCMDQ); | |
2101 | } | |
2102 | ||
2103 | est->timer.expires = jiffies + ((HZ / 4) << est->interval); | |
2104 | add_timer(&est->timer); | |
2105 | ||
2106 | out: | |
2107 | spin_unlock_irqrestore(&vc->lock, flags); | |
2108 | } | |
2109 | ||
2110 | static struct rate_estimator * | |
2111 | idt77252_init_est(struct vc_map *vc, int pcr) | |
2112 | { | |
2113 | struct rate_estimator *est; | |
2114 | ||
0c1cca1d | 2115 | est = kzalloc(sizeof(struct rate_estimator), GFP_KERNEL); |
1da177e4 LT |
2116 | if (!est) |
2117 | return NULL; | |
1da177e4 LT |
2118 | est->maxcps = pcr < 0 ? -pcr : pcr; |
2119 | est->cps = est->maxcps; | |
2120 | est->avcps = est->cps << 5; | |
3d2ceaa6 | 2121 | est->vc = vc; |
1da177e4 LT |
2122 | |
2123 | est->interval = 2; /* XXX: make this configurable */ | |
2124 | est->ewma_log = 2; /* XXX: make this configurable */ | |
3d2ceaa6 | 2125 | timer_setup(&est->timer, idt77252_est_timer, 0); |
b973154a | 2126 | mod_timer(&est->timer, jiffies + ((HZ / 4) << est->interval)); |
1da177e4 LT |
2127 | |
2128 | return est; | |
2129 | } | |
2130 | ||
2131 | static int | |
2132 | idt77252_init_cbr(struct idt77252_dev *card, struct vc_map *vc, | |
2133 | struct atm_vcc *vcc, struct atm_qos *qos) | |
2134 | { | |
2135 | int tst_free, tst_used, tst_entries; | |
2136 | unsigned long tmpl, modl; | |
2137 | int tcr, tcra; | |
2138 | ||
2139 | if ((qos->txtp.max_pcr == 0) && | |
2140 | (qos->txtp.pcr == 0) && (qos->txtp.min_pcr == 0)) { | |
2141 | printk("%s: trying to open a CBR VC with cell rate = 0\n", | |
2142 | card->name); | |
2143 | return -EINVAL; | |
2144 | } | |
2145 | ||
2146 | tst_used = 0; | |
2147 | tst_free = card->tst_free; | |
2148 | if (test_bit(VCF_TX, &vc->flags)) | |
2149 | tst_used = vc->ntste; | |
2150 | tst_free += tst_used; | |
2151 | ||
2152 | tcr = atm_pcr_goal(&qos->txtp); | |
2153 | tcra = tcr >= 0 ? tcr : -tcr; | |
2154 | ||
2155 | TXPRINTK("%s: CBR target cell rate = %d\n", card->name, tcra); | |
2156 | ||
2157 | tmpl = (unsigned long) tcra * ((unsigned long) card->tst_size - 2); | |
2158 | modl = tmpl % (unsigned long)card->utopia_pcr; | |
2159 | ||
2160 | tst_entries = (int) (tmpl / card->utopia_pcr); | |
2161 | if (tcr > 0) { | |
2162 | if (modl > 0) | |
2163 | tst_entries++; | |
2164 | } else if (tcr == 0) { | |
2165 | tst_entries = tst_free - SAR_TST_RESERVED; | |
2166 | if (tst_entries <= 0) { | |
2167 | printk("%s: no CBR bandwidth free.\n", card->name); | |
2168 | return -ENOSR; | |
2169 | } | |
2170 | } | |
2171 | ||
2172 | if (tst_entries == 0) { | |
2173 | printk("%s: selected CBR bandwidth < granularity.\n", | |
2174 | card->name); | |
2175 | return -EINVAL; | |
2176 | } | |
2177 | ||
2178 | if (tst_entries > (tst_free - SAR_TST_RESERVED)) { | |
2179 | printk("%s: not enough CBR bandwidth free.\n", card->name); | |
2180 | return -ENOSR; | |
2181 | } | |
2182 | ||
2183 | vc->ntste = tst_entries; | |
2184 | ||
2185 | card->tst_free = tst_free - tst_entries; | |
2186 | if (test_bit(VCF_TX, &vc->flags)) { | |
2187 | if (tst_used == tst_entries) | |
2188 | return 0; | |
2189 | ||
2190 | OPRINTK("%s: modify %d -> %d entries in TST.\n", | |
2191 | card->name, tst_used, tst_entries); | |
2192 | change_tst(card, vc, tst_entries, TSTE_OPC_CBR); | |
2193 | return 0; | |
2194 | } | |
2195 | ||
2196 | OPRINTK("%s: setting %d entries in TST.\n", card->name, tst_entries); | |
2197 | fill_tst(card, vc, tst_entries, TSTE_OPC_CBR); | |
2198 | return 0; | |
2199 | } | |
2200 | ||
2201 | static int | |
2202 | idt77252_init_ubr(struct idt77252_dev *card, struct vc_map *vc, | |
2203 | struct atm_vcc *vcc, struct atm_qos *qos) | |
2204 | { | |
3d2ceaa6 | 2205 | struct rate_estimator *est = NULL; |
1da177e4 LT |
2206 | unsigned long flags; |
2207 | int tcr; | |
2208 | ||
2209 | spin_lock_irqsave(&vc->lock, flags); | |
2210 | if (vc->estimator) { | |
3d2ceaa6 | 2211 | est = vc->estimator; |
1da177e4 LT |
2212 | vc->estimator = NULL; |
2213 | } | |
2214 | spin_unlock_irqrestore(&vc->lock, flags); | |
3d2ceaa6 | 2215 | if (est) { |
292a089d | 2216 | timer_shutdown_sync(&est->timer); |
3d2ceaa6 KC |
2217 | kfree(est); |
2218 | } | |
1da177e4 LT |
2219 | |
2220 | tcr = atm_pcr_goal(&qos->txtp); | |
2221 | if (tcr == 0) | |
2222 | tcr = card->link_pcr; | |
2223 | ||
2224 | vc->estimator = idt77252_init_est(vc, tcr); | |
2225 | ||
2226 | vc->class = SCHED_UBR; | |
2227 | vc->init_er = idt77252_rate_logindex(card, tcr); | |
2228 | vc->lacr = vc->init_er; | |
2229 | if (tcr < 0) | |
2230 | vc->max_er = vc->init_er; | |
2231 | else | |
2232 | vc->max_er = 0xff; | |
2233 | ||
2234 | return 0; | |
2235 | } | |
2236 | ||
2237 | static int | |
2238 | idt77252_init_tx(struct idt77252_dev *card, struct vc_map *vc, | |
2239 | struct atm_vcc *vcc, struct atm_qos *qos) | |
2240 | { | |
2241 | int error; | |
2242 | ||
2243 | if (test_bit(VCF_TX, &vc->flags)) | |
2244 | return -EBUSY; | |
2245 | ||
2246 | switch (qos->txtp.traffic_class) { | |
2247 | case ATM_CBR: | |
2248 | vc->class = SCHED_CBR; | |
2249 | break; | |
2250 | ||
2251 | case ATM_UBR: | |
2252 | vc->class = SCHED_UBR; | |
2253 | break; | |
2254 | ||
2255 | case ATM_VBR: | |
2256 | case ATM_ABR: | |
2257 | default: | |
2258 | return -EPROTONOSUPPORT; | |
2259 | } | |
2260 | ||
2261 | vc->scq = alloc_scq(card, vc->class); | |
2262 | if (!vc->scq) { | |
2263 | printk("%s: can't get SCQ.\n", card->name); | |
2264 | return -ENOMEM; | |
2265 | } | |
2266 | ||
2267 | vc->scq->scd = get_free_scd(card, vc); | |
2268 | if (vc->scq->scd == 0) { | |
2269 | printk("%s: no SCD available.\n", card->name); | |
2270 | free_scq(card, vc->scq); | |
2271 | return -ENOMEM; | |
2272 | } | |
2273 | ||
2274 | fill_scd(card, vc->scq, vc->class); | |
2275 | ||
2276 | if (set_tct(card, vc)) { | |
2277 | printk("%s: class %d not supported.\n", | |
2278 | card->name, qos->txtp.traffic_class); | |
2279 | ||
2280 | card->scd2vc[vc->scd_index] = NULL; | |
2281 | free_scq(card, vc->scq); | |
2282 | return -EPROTONOSUPPORT; | |
2283 | } | |
2284 | ||
2285 | switch (vc->class) { | |
2286 | case SCHED_CBR: | |
2287 | error = idt77252_init_cbr(card, vc, vcc, qos); | |
2288 | if (error) { | |
2289 | card->scd2vc[vc->scd_index] = NULL; | |
2290 | free_scq(card, vc->scq); | |
2291 | return error; | |
2292 | } | |
2293 | ||
2294 | clear_bit(VCF_IDLE, &vc->flags); | |
2295 | writel(TCMDQ_START | vc->index, SAR_REG_TCMDQ); | |
2296 | break; | |
2297 | ||
2298 | case SCHED_UBR: | |
2299 | error = idt77252_init_ubr(card, vc, vcc, qos); | |
2300 | if (error) { | |
2301 | card->scd2vc[vc->scd_index] = NULL; | |
2302 | free_scq(card, vc->scq); | |
2303 | return error; | |
2304 | } | |
2305 | ||
2306 | set_bit(VCF_IDLE, &vc->flags); | |
2307 | break; | |
2308 | } | |
2309 | ||
2310 | vc->tx_vcc = vcc; | |
2311 | set_bit(VCF_TX, &vc->flags); | |
2312 | return 0; | |
2313 | } | |
2314 | ||
2315 | static int | |
2316 | idt77252_init_rx(struct idt77252_dev *card, struct vc_map *vc, | |
2317 | struct atm_vcc *vcc, struct atm_qos *qos) | |
2318 | { | |
2319 | unsigned long flags; | |
2320 | unsigned long addr; | |
2321 | u32 rcte = 0; | |
2322 | ||
2323 | if (test_bit(VCF_RX, &vc->flags)) | |
2324 | return -EBUSY; | |
2325 | ||
2326 | vc->rx_vcc = vcc; | |
2327 | set_bit(VCF_RX, &vc->flags); | |
2328 | ||
2329 | if ((vcc->vci == 3) || (vcc->vci == 4)) | |
2330 | return 0; | |
2331 | ||
2332 | flush_rx_pool(card, &vc->rcv.rx_pool); | |
2333 | ||
2334 | rcte |= SAR_RCTE_CONNECTOPEN; | |
2335 | rcte |= SAR_RCTE_RAWCELLINTEN; | |
2336 | ||
2337 | switch (qos->aal) { | |
2338 | case ATM_AAL0: | |
2339 | rcte |= SAR_RCTE_RCQ; | |
2340 | break; | |
2341 | case ATM_AAL1: | |
2342 | rcte |= SAR_RCTE_OAM; /* Let SAR drop Video */ | |
2343 | break; | |
2344 | case ATM_AAL34: | |
2345 | rcte |= SAR_RCTE_AAL34; | |
2346 | break; | |
2347 | case ATM_AAL5: | |
2348 | rcte |= SAR_RCTE_AAL5; | |
2349 | break; | |
2350 | default: | |
2351 | rcte |= SAR_RCTE_RCQ; | |
2352 | break; | |
2353 | } | |
2354 | ||
2355 | if (qos->aal != ATM_AAL5) | |
2356 | rcte |= SAR_RCTE_FBP_1; | |
2357 | else if (qos->rxtp.max_sdu > SAR_FB_SIZE_2) | |
2358 | rcte |= SAR_RCTE_FBP_3; | |
2359 | else if (qos->rxtp.max_sdu > SAR_FB_SIZE_1) | |
2360 | rcte |= SAR_RCTE_FBP_2; | |
2361 | else if (qos->rxtp.max_sdu > SAR_FB_SIZE_0) | |
2362 | rcte |= SAR_RCTE_FBP_1; | |
2363 | else | |
2364 | rcte |= SAR_RCTE_FBP_01; | |
2365 | ||
2366 | addr = card->rct_base + (vc->index << 2); | |
2367 | ||
2368 | OPRINTK("%s: writing RCT at 0x%lx\n", card->name, addr); | |
2369 | write_sram(card, addr, rcte); | |
2370 | ||
2371 | spin_lock_irqsave(&card->cmd_lock, flags); | |
2372 | writel(SAR_CMD_OPEN_CONNECTION | (addr << 2), SAR_REG_CMD); | |
2373 | waitfor_idle(card); | |
2374 | spin_unlock_irqrestore(&card->cmd_lock, flags); | |
2375 | ||
2376 | return 0; | |
2377 | } | |
2378 | ||
2379 | static int | |
2380 | idt77252_open(struct atm_vcc *vcc) | |
2381 | { | |
2382 | struct atm_dev *dev = vcc->dev; | |
2383 | struct idt77252_dev *card = dev->dev_data; | |
2384 | struct vc_map *vc; | |
2385 | unsigned int index; | |
2386 | unsigned int inuse; | |
2387 | int error; | |
2388 | int vci = vcc->vci; | |
2389 | short vpi = vcc->vpi; | |
2390 | ||
2391 | if (vpi == ATM_VPI_UNSPEC || vci == ATM_VCI_UNSPEC) | |
2392 | return 0; | |
2393 | ||
2394 | if (vpi >= (1 << card->vpibits)) { | |
2395 | printk("%s: unsupported VPI: %d\n", card->name, vpi); | |
2396 | return -EINVAL; | |
2397 | } | |
2398 | ||
2399 | if (vci >= (1 << card->vcibits)) { | |
2400 | printk("%s: unsupported VCI: %d\n", card->name, vci); | |
2401 | return -EINVAL; | |
2402 | } | |
2403 | ||
2404 | set_bit(ATM_VF_ADDR, &vcc->flags); | |
2405 | ||
7e7a2d07 | 2406 | mutex_lock(&card->mutex); |
1da177e4 LT |
2407 | |
2408 | OPRINTK("%s: opening vpi.vci: %d.%d\n", card->name, vpi, vci); | |
2409 | ||
2410 | switch (vcc->qos.aal) { | |
2411 | case ATM_AAL0: | |
2412 | case ATM_AAL1: | |
2413 | case ATM_AAL5: | |
2414 | break; | |
2415 | default: | |
2416 | printk("%s: Unsupported AAL: %d\n", card->name, vcc->qos.aal); | |
7e7a2d07 | 2417 | mutex_unlock(&card->mutex); |
1da177e4 LT |
2418 | return -EPROTONOSUPPORT; |
2419 | } | |
2420 | ||
2421 | index = VPCI2VC(card, vpi, vci); | |
2422 | if (!card->vcs[index]) { | |
0c1cca1d | 2423 | card->vcs[index] = kzalloc(sizeof(struct vc_map), GFP_KERNEL); |
1da177e4 LT |
2424 | if (!card->vcs[index]) { |
2425 | printk("%s: can't alloc vc in open()\n", card->name); | |
7e7a2d07 | 2426 | mutex_unlock(&card->mutex); |
1da177e4 LT |
2427 | return -ENOMEM; |
2428 | } | |
1da177e4 LT |
2429 | card->vcs[index]->card = card; |
2430 | card->vcs[index]->index = index; | |
2431 | ||
2432 | spin_lock_init(&card->vcs[index]->lock); | |
2433 | } | |
2434 | vc = card->vcs[index]; | |
2435 | ||
2436 | vcc->dev_data = vc; | |
2437 | ||
2438 | IPRINTK("%s: idt77252_open: vc = %d (%d.%d) %s/%s (max RX SDU: %u)\n", | |
2439 | card->name, vc->index, vcc->vpi, vcc->vci, | |
2440 | vcc->qos.rxtp.traffic_class != ATM_NONE ? "rx" : "--", | |
2441 | vcc->qos.txtp.traffic_class != ATM_NONE ? "tx" : "--", | |
2442 | vcc->qos.rxtp.max_sdu); | |
2443 | ||
2444 | inuse = 0; | |
2445 | if (vcc->qos.txtp.traffic_class != ATM_NONE && | |
2446 | test_bit(VCF_TX, &vc->flags)) | |
2447 | inuse = 1; | |
2448 | if (vcc->qos.rxtp.traffic_class != ATM_NONE && | |
2449 | test_bit(VCF_RX, &vc->flags)) | |
2450 | inuse += 2; | |
2451 | ||
2452 | if (inuse) { | |
2453 | printk("%s: %s vci already in use.\n", card->name, | |
2454 | inuse == 1 ? "tx" : inuse == 2 ? "rx" : "tx and rx"); | |
7e7a2d07 | 2455 | mutex_unlock(&card->mutex); |
1da177e4 LT |
2456 | return -EADDRINUSE; |
2457 | } | |
2458 | ||
2459 | if (vcc->qos.txtp.traffic_class != ATM_NONE) { | |
2460 | error = idt77252_init_tx(card, vc, vcc, &vcc->qos); | |
2461 | if (error) { | |
7e7a2d07 | 2462 | mutex_unlock(&card->mutex); |
1da177e4 LT |
2463 | return error; |
2464 | } | |
2465 | } | |
2466 | ||
2467 | if (vcc->qos.rxtp.traffic_class != ATM_NONE) { | |
2468 | error = idt77252_init_rx(card, vc, vcc, &vcc->qos); | |
2469 | if (error) { | |
7e7a2d07 | 2470 | mutex_unlock(&card->mutex); |
1da177e4 LT |
2471 | return error; |
2472 | } | |
2473 | } | |
2474 | ||
2475 | set_bit(ATM_VF_READY, &vcc->flags); | |
2476 | ||
7e7a2d07 | 2477 | mutex_unlock(&card->mutex); |
1da177e4 LT |
2478 | return 0; |
2479 | } | |
2480 | ||
2481 | static void | |
2482 | idt77252_close(struct atm_vcc *vcc) | |
2483 | { | |
2484 | struct atm_dev *dev = vcc->dev; | |
2485 | struct idt77252_dev *card = dev->dev_data; | |
2486 | struct vc_map *vc = vcc->dev_data; | |
2487 | unsigned long flags; | |
2488 | unsigned long addr; | |
2489 | unsigned long timeout; | |
2490 | ||
7e7a2d07 | 2491 | mutex_lock(&card->mutex); |
1da177e4 LT |
2492 | |
2493 | IPRINTK("%s: idt77252_close: vc = %d (%d.%d)\n", | |
2494 | card->name, vc->index, vcc->vpi, vcc->vci); | |
2495 | ||
2496 | clear_bit(ATM_VF_READY, &vcc->flags); | |
2497 | ||
2498 | if (vcc->qos.rxtp.traffic_class != ATM_NONE) { | |
2499 | ||
2500 | spin_lock_irqsave(&vc->lock, flags); | |
2501 | clear_bit(VCF_RX, &vc->flags); | |
2502 | vc->rx_vcc = NULL; | |
2503 | spin_unlock_irqrestore(&vc->lock, flags); | |
2504 | ||
2505 | if ((vcc->vci == 3) || (vcc->vci == 4)) | |
2506 | goto done; | |
2507 | ||
2508 | addr = card->rct_base + vc->index * SAR_SRAM_RCT_SIZE; | |
2509 | ||
2510 | spin_lock_irqsave(&card->cmd_lock, flags); | |
2511 | writel(SAR_CMD_CLOSE_CONNECTION | (addr << 2), SAR_REG_CMD); | |
2512 | waitfor_idle(card); | |
2513 | spin_unlock_irqrestore(&card->cmd_lock, flags); | |
2514 | ||
ceade961 | 2515 | if (skb_queue_len(&vc->rcv.rx_pool.queue) != 0) { |
1da177e4 LT |
2516 | DPRINTK("%s: closing a VC with pending rx buffers.\n", |
2517 | card->name); | |
2518 | ||
2519 | recycle_rx_pool_skb(card, &vc->rcv.rx_pool); | |
2520 | } | |
2521 | } | |
2522 | ||
2523 | done: | |
2524 | if (vcc->qos.txtp.traffic_class != ATM_NONE) { | |
2525 | ||
2526 | spin_lock_irqsave(&vc->lock, flags); | |
2527 | clear_bit(VCF_TX, &vc->flags); | |
2528 | clear_bit(VCF_IDLE, &vc->flags); | |
2529 | clear_bit(VCF_RSV, &vc->flags); | |
2530 | vc->tx_vcc = NULL; | |
2531 | ||
2532 | if (vc->estimator) { | |
292a089d | 2533 | timer_shutdown(&vc->estimator->timer); |
1da177e4 LT |
2534 | kfree(vc->estimator); |
2535 | vc->estimator = NULL; | |
2536 | } | |
2537 | spin_unlock_irqrestore(&vc->lock, flags); | |
2538 | ||
2539 | timeout = 5 * 1000; | |
2540 | while (atomic_read(&vc->scq->used) > 0) { | |
2541 | timeout = msleep_interruptible(timeout); | |
7e910357 PST |
2542 | if (!timeout) { |
2543 | pr_warn("%s: SCQ drain timeout: %u used\n", | |
2544 | card->name, atomic_read(&vc->scq->used)); | |
1da177e4 | 2545 | break; |
7e910357 | 2546 | } |
1da177e4 | 2547 | } |
1da177e4 LT |
2548 | |
2549 | writel(TCMDQ_HALT | vc->index, SAR_REG_TCMDQ); | |
2550 | clear_scd(card, vc->scq, vc->class); | |
2551 | ||
2552 | if (vc->class == SCHED_CBR) { | |
2553 | clear_tst(card, vc); | |
2554 | card->tst_free += vc->ntste; | |
2555 | vc->ntste = 0; | |
2556 | } | |
2557 | ||
2558 | card->scd2vc[vc->scd_index] = NULL; | |
2559 | free_scq(card, vc->scq); | |
2560 | } | |
2561 | ||
7e7a2d07 | 2562 | mutex_unlock(&card->mutex); |
1da177e4 LT |
2563 | } |
2564 | ||
2565 | static int | |
2566 | idt77252_change_qos(struct atm_vcc *vcc, struct atm_qos *qos, int flags) | |
2567 | { | |
2568 | struct atm_dev *dev = vcc->dev; | |
2569 | struct idt77252_dev *card = dev->dev_data; | |
2570 | struct vc_map *vc = vcc->dev_data; | |
2571 | int error = 0; | |
2572 | ||
7e7a2d07 | 2573 | mutex_lock(&card->mutex); |
1da177e4 LT |
2574 | |
2575 | if (qos->txtp.traffic_class != ATM_NONE) { | |
2576 | if (!test_bit(VCF_TX, &vc->flags)) { | |
2577 | error = idt77252_init_tx(card, vc, vcc, qos); | |
2578 | if (error) | |
2579 | goto out; | |
2580 | } else { | |
2581 | switch (qos->txtp.traffic_class) { | |
2582 | case ATM_CBR: | |
2583 | error = idt77252_init_cbr(card, vc, vcc, qos); | |
2584 | if (error) | |
2585 | goto out; | |
2586 | break; | |
2587 | ||
2588 | case ATM_UBR: | |
2589 | error = idt77252_init_ubr(card, vc, vcc, qos); | |
2590 | if (error) | |
2591 | goto out; | |
2592 | ||
2593 | if (!test_bit(VCF_IDLE, &vc->flags)) { | |
2594 | writel(TCMDQ_LACR | (vc->lacr << 16) | | |
2595 | vc->index, SAR_REG_TCMDQ); | |
2596 | } | |
2597 | break; | |
2598 | ||
2599 | case ATM_VBR: | |
2600 | case ATM_ABR: | |
2601 | error = -EOPNOTSUPP; | |
2602 | goto out; | |
2603 | } | |
2604 | } | |
2605 | } | |
2606 | ||
2607 | if ((qos->rxtp.traffic_class != ATM_NONE) && | |
2608 | !test_bit(VCF_RX, &vc->flags)) { | |
2609 | error = idt77252_init_rx(card, vc, vcc, qos); | |
2610 | if (error) | |
2611 | goto out; | |
2612 | } | |
2613 | ||
2614 | memcpy(&vcc->qos, qos, sizeof(struct atm_qos)); | |
2615 | ||
2616 | set_bit(ATM_VF_HASQOS, &vcc->flags); | |
2617 | ||
2618 | out: | |
7e7a2d07 | 2619 | mutex_unlock(&card->mutex); |
1da177e4 LT |
2620 | return error; |
2621 | } | |
2622 | ||
2623 | static int | |
2624 | idt77252_proc_read(struct atm_dev *dev, loff_t * pos, char *page) | |
2625 | { | |
2626 | struct idt77252_dev *card = dev->dev_data; | |
2627 | int i, left; | |
2628 | ||
2629 | left = (int) *pos; | |
2630 | if (!left--) | |
2631 | return sprintf(page, "IDT77252 Interrupts:\n"); | |
2632 | if (!left--) | |
2633 | return sprintf(page, "TSIF: %lu\n", card->irqstat[15]); | |
2634 | if (!left--) | |
2635 | return sprintf(page, "TXICP: %lu\n", card->irqstat[14]); | |
2636 | if (!left--) | |
2637 | return sprintf(page, "TSQF: %lu\n", card->irqstat[12]); | |
2638 | if (!left--) | |
2639 | return sprintf(page, "TMROF: %lu\n", card->irqstat[11]); | |
2640 | if (!left--) | |
2641 | return sprintf(page, "PHYI: %lu\n", card->irqstat[10]); | |
2642 | if (!left--) | |
2643 | return sprintf(page, "FBQ3A: %lu\n", card->irqstat[8]); | |
2644 | if (!left--) | |
2645 | return sprintf(page, "FBQ2A: %lu\n", card->irqstat[7]); | |
2646 | if (!left--) | |
2647 | return sprintf(page, "RSQF: %lu\n", card->irqstat[6]); | |
2648 | if (!left--) | |
2649 | return sprintf(page, "EPDU: %lu\n", card->irqstat[5]); | |
2650 | if (!left--) | |
2651 | return sprintf(page, "RAWCF: %lu\n", card->irqstat[4]); | |
2652 | if (!left--) | |
2653 | return sprintf(page, "FBQ1A: %lu\n", card->irqstat[3]); | |
2654 | if (!left--) | |
2655 | return sprintf(page, "FBQ0A: %lu\n", card->irqstat[2]); | |
2656 | if (!left--) | |
2657 | return sprintf(page, "RSQAF: %lu\n", card->irqstat[1]); | |
2658 | if (!left--) | |
2659 | return sprintf(page, "IDT77252 Transmit Connection Table:\n"); | |
2660 | ||
2661 | for (i = 0; i < card->tct_size; i++) { | |
2662 | unsigned long tct; | |
2663 | struct atm_vcc *vcc; | |
2664 | struct vc_map *vc; | |
2665 | char *p; | |
2666 | ||
2667 | vc = card->vcs[i]; | |
2668 | if (!vc) | |
2669 | continue; | |
2670 | ||
2671 | vcc = NULL; | |
2672 | if (vc->tx_vcc) | |
2673 | vcc = vc->tx_vcc; | |
2674 | if (!vcc) | |
2675 | continue; | |
2676 | if (left--) | |
2677 | continue; | |
2678 | ||
2679 | p = page; | |
2680 | p += sprintf(p, " %4u: %u.%u: ", i, vcc->vpi, vcc->vci); | |
2681 | tct = (unsigned long) (card->tct_base + i * SAR_SRAM_TCT_SIZE); | |
2682 | ||
2683 | for (i = 0; i < 8; i++) | |
2684 | p += sprintf(p, " %08x", read_sram(card, tct + i)); | |
2685 | p += sprintf(p, "\n"); | |
2686 | return p - page; | |
2687 | } | |
2688 | return 0; | |
2689 | } | |
2690 | ||
2691 | /*****************************************************************************/ | |
2692 | /* */ | |
2693 | /* Interrupt handler */ | |
2694 | /* */ | |
2695 | /*****************************************************************************/ | |
2696 | ||
2697 | static void | |
2698 | idt77252_collect_stat(struct idt77252_dev *card) | |
2699 | { | |
edb4dcb7 DM |
2700 | (void) readl(SAR_REG_CDC); |
2701 | (void) readl(SAR_REG_VPEC); | |
2702 | (void) readl(SAR_REG_ICC); | |
1da177e4 | 2703 | |
1da177e4 LT |
2704 | } |
2705 | ||
2706 | static irqreturn_t | |
7d12e780 | 2707 | idt77252_interrupt(int irq, void *dev_id) |
1da177e4 LT |
2708 | { |
2709 | struct idt77252_dev *card = dev_id; | |
2710 | u32 stat; | |
2711 | ||
2712 | stat = readl(SAR_REG_STAT) & 0xffff; | |
2713 | if (!stat) /* no interrupt for us */ | |
2714 | return IRQ_NONE; | |
2715 | ||
2716 | if (test_and_set_bit(IDT77252_BIT_INTERRUPT, &card->flags)) { | |
2717 | printk("%s: Re-entering irq_handler()\n", card->name); | |
2718 | goto out; | |
2719 | } | |
2720 | ||
2721 | writel(stat, SAR_REG_STAT); /* reset interrupt */ | |
2722 | ||
2723 | if (stat & SAR_STAT_TSIF) { /* entry written to TSQ */ | |
2724 | INTPRINTK("%s: TSIF\n", card->name); | |
2725 | card->irqstat[15]++; | |
2726 | idt77252_tx(card); | |
2727 | } | |
2728 | if (stat & SAR_STAT_TXICP) { /* Incomplete CS-PDU has */ | |
2729 | INTPRINTK("%s: TXICP\n", card->name); | |
2730 | card->irqstat[14]++; | |
2731 | #ifdef CONFIG_ATM_IDT77252_DEBUG | |
2732 | idt77252_tx_dump(card); | |
2733 | #endif | |
2734 | } | |
2735 | if (stat & SAR_STAT_TSQF) { /* TSQ 7/8 full */ | |
2736 | INTPRINTK("%s: TSQF\n", card->name); | |
2737 | card->irqstat[12]++; | |
2738 | idt77252_tx(card); | |
2739 | } | |
2740 | if (stat & SAR_STAT_TMROF) { /* Timer overflow */ | |
2741 | INTPRINTK("%s: TMROF\n", card->name); | |
2742 | card->irqstat[11]++; | |
2743 | idt77252_collect_stat(card); | |
2744 | } | |
2745 | ||
2746 | if (stat & SAR_STAT_EPDU) { /* Got complete CS-PDU */ | |
2747 | INTPRINTK("%s: EPDU\n", card->name); | |
2748 | card->irqstat[5]++; | |
2749 | idt77252_rx(card); | |
2750 | } | |
2751 | if (stat & SAR_STAT_RSQAF) { /* RSQ is 7/8 full */ | |
2752 | INTPRINTK("%s: RSQAF\n", card->name); | |
2753 | card->irqstat[1]++; | |
2754 | idt77252_rx(card); | |
2755 | } | |
2756 | if (stat & SAR_STAT_RSQF) { /* RSQ is full */ | |
2757 | INTPRINTK("%s: RSQF\n", card->name); | |
2758 | card->irqstat[6]++; | |
2759 | idt77252_rx(card); | |
2760 | } | |
2761 | if (stat & SAR_STAT_RAWCF) { /* Raw cell received */ | |
2762 | INTPRINTK("%s: RAWCF\n", card->name); | |
2763 | card->irqstat[4]++; | |
2764 | idt77252_rx_raw(card); | |
2765 | } | |
2766 | ||
2767 | if (stat & SAR_STAT_PHYI) { /* PHY device interrupt */ | |
2768 | INTPRINTK("%s: PHYI", card->name); | |
2769 | card->irqstat[10]++; | |
2770 | if (card->atmdev->phy && card->atmdev->phy->interrupt) | |
2771 | card->atmdev->phy->interrupt(card->atmdev); | |
2772 | } | |
2773 | ||
2774 | if (stat & (SAR_STAT_FBQ0A | SAR_STAT_FBQ1A | | |
2775 | SAR_STAT_FBQ2A | SAR_STAT_FBQ3A)) { | |
2776 | ||
2777 | writel(readl(SAR_REG_CFG) & ~(SAR_CFG_FBIE), SAR_REG_CFG); | |
2778 | ||
2779 | INTPRINTK("%s: FBQA: %04x\n", card->name, stat); | |
2780 | ||
2781 | if (stat & SAR_STAT_FBQ0A) | |
2782 | card->irqstat[2]++; | |
2783 | if (stat & SAR_STAT_FBQ1A) | |
2784 | card->irqstat[3]++; | |
2785 | if (stat & SAR_STAT_FBQ2A) | |
2786 | card->irqstat[7]++; | |
2787 | if (stat & SAR_STAT_FBQ3A) | |
2788 | card->irqstat[8]++; | |
2789 | ||
2790 | schedule_work(&card->tqueue); | |
2791 | } | |
2792 | ||
2793 | out: | |
2794 | clear_bit(IDT77252_BIT_INTERRUPT, &card->flags); | |
2795 | return IRQ_HANDLED; | |
2796 | } | |
2797 | ||
2798 | static void | |
c4028958 | 2799 | idt77252_softint(struct work_struct *work) |
1da177e4 | 2800 | { |
c4028958 DH |
2801 | struct idt77252_dev *card = |
2802 | container_of(work, struct idt77252_dev, tqueue); | |
1da177e4 LT |
2803 | u32 stat; |
2804 | int done; | |
2805 | ||
2806 | for (done = 1; ; done = 1) { | |
2807 | stat = readl(SAR_REG_STAT) >> 16; | |
2808 | ||
2809 | if ((stat & 0x0f) < SAR_FBQ0_HIGH) { | |
2810 | add_rx_skb(card, 0, SAR_FB_SIZE_0, 32); | |
2811 | done = 0; | |
2812 | } | |
2813 | ||
2814 | stat >>= 4; | |
2815 | if ((stat & 0x0f) < SAR_FBQ1_HIGH) { | |
2816 | add_rx_skb(card, 1, SAR_FB_SIZE_1, 32); | |
2817 | done = 0; | |
2818 | } | |
2819 | ||
2820 | stat >>= 4; | |
2821 | if ((stat & 0x0f) < SAR_FBQ2_HIGH) { | |
2822 | add_rx_skb(card, 2, SAR_FB_SIZE_2, 32); | |
2823 | done = 0; | |
2824 | } | |
2825 | ||
2826 | stat >>= 4; | |
2827 | if ((stat & 0x0f) < SAR_FBQ3_HIGH) { | |
2828 | add_rx_skb(card, 3, SAR_FB_SIZE_3, 32); | |
2829 | done = 0; | |
2830 | } | |
2831 | ||
2832 | if (done) | |
2833 | break; | |
2834 | } | |
2835 | ||
2836 | writel(readl(SAR_REG_CFG) | SAR_CFG_FBIE, SAR_REG_CFG); | |
2837 | } | |
2838 | ||
2839 | ||
2840 | static int | |
2841 | open_card_oam(struct idt77252_dev *card) | |
2842 | { | |
2843 | unsigned long flags; | |
2844 | unsigned long addr; | |
2845 | struct vc_map *vc; | |
2846 | int vpi, vci; | |
2847 | int index; | |
2848 | u32 rcte; | |
2849 | ||
2850 | for (vpi = 0; vpi < (1 << card->vpibits); vpi++) { | |
2851 | for (vci = 3; vci < 5; vci++) { | |
2852 | index = VPCI2VC(card, vpi, vci); | |
2853 | ||
0c1cca1d | 2854 | vc = kzalloc(sizeof(struct vc_map), GFP_KERNEL); |
1da177e4 LT |
2855 | if (!vc) { |
2856 | printk("%s: can't alloc vc\n", card->name); | |
2857 | return -ENOMEM; | |
2858 | } | |
1da177e4 LT |
2859 | vc->index = index; |
2860 | card->vcs[index] = vc; | |
2861 | ||
2862 | flush_rx_pool(card, &vc->rcv.rx_pool); | |
2863 | ||
2864 | rcte = SAR_RCTE_CONNECTOPEN | | |
2865 | SAR_RCTE_RAWCELLINTEN | | |
2866 | SAR_RCTE_RCQ | | |
2867 | SAR_RCTE_FBP_1; | |
2868 | ||
2869 | addr = card->rct_base + (vc->index << 2); | |
2870 | write_sram(card, addr, rcte); | |
2871 | ||
2872 | spin_lock_irqsave(&card->cmd_lock, flags); | |
2873 | writel(SAR_CMD_OPEN_CONNECTION | (addr << 2), | |
2874 | SAR_REG_CMD); | |
2875 | waitfor_idle(card); | |
2876 | spin_unlock_irqrestore(&card->cmd_lock, flags); | |
2877 | } | |
2878 | } | |
2879 | ||
2880 | return 0; | |
2881 | } | |
2882 | ||
2883 | static void | |
2884 | close_card_oam(struct idt77252_dev *card) | |
2885 | { | |
2886 | unsigned long flags; | |
2887 | unsigned long addr; | |
2888 | struct vc_map *vc; | |
2889 | int vpi, vci; | |
2890 | int index; | |
2891 | ||
2892 | for (vpi = 0; vpi < (1 << card->vpibits); vpi++) { | |
2893 | for (vci = 3; vci < 5; vci++) { | |
2894 | index = VPCI2VC(card, vpi, vci); | |
2895 | vc = card->vcs[index]; | |
2896 | ||
2897 | addr = card->rct_base + vc->index * SAR_SRAM_RCT_SIZE; | |
2898 | ||
2899 | spin_lock_irqsave(&card->cmd_lock, flags); | |
2900 | writel(SAR_CMD_CLOSE_CONNECTION | (addr << 2), | |
2901 | SAR_REG_CMD); | |
2902 | waitfor_idle(card); | |
2903 | spin_unlock_irqrestore(&card->cmd_lock, flags); | |
2904 | ||
ceade961 | 2905 | if (skb_queue_len(&vc->rcv.rx_pool.queue) != 0) { |
1da177e4 LT |
2906 | DPRINTK("%s: closing a VC " |
2907 | "with pending rx buffers.\n", | |
2908 | card->name); | |
2909 | ||
2910 | recycle_rx_pool_skb(card, &vc->rcv.rx_pool); | |
2911 | } | |
4fe3c885 | 2912 | kfree(vc); |
1da177e4 LT |
2913 | } |
2914 | } | |
2915 | } | |
2916 | ||
2917 | static int | |
2918 | open_card_ubr0(struct idt77252_dev *card) | |
2919 | { | |
2920 | struct vc_map *vc; | |
2921 | ||
0c1cca1d | 2922 | vc = kzalloc(sizeof(struct vc_map), GFP_KERNEL); |
1da177e4 LT |
2923 | if (!vc) { |
2924 | printk("%s: can't alloc vc\n", card->name); | |
2925 | return -ENOMEM; | |
2926 | } | |
1da177e4 LT |
2927 | card->vcs[0] = vc; |
2928 | vc->class = SCHED_UBR0; | |
2929 | ||
2930 | vc->scq = alloc_scq(card, vc->class); | |
2931 | if (!vc->scq) { | |
2932 | printk("%s: can't get SCQ.\n", card->name); | |
2933 | return -ENOMEM; | |
2934 | } | |
2935 | ||
2936 | card->scd2vc[0] = vc; | |
2937 | vc->scd_index = 0; | |
2938 | vc->scq->scd = card->scd_base; | |
2939 | ||
2940 | fill_scd(card, vc->scq, vc->class); | |
2941 | ||
2942 | write_sram(card, card->tct_base + 0, TCT_UBR | card->scd_base); | |
2943 | write_sram(card, card->tct_base + 1, 0); | |
2944 | write_sram(card, card->tct_base + 2, 0); | |
2945 | write_sram(card, card->tct_base + 3, 0); | |
2946 | write_sram(card, card->tct_base + 4, 0); | |
2947 | write_sram(card, card->tct_base + 5, 0); | |
2948 | write_sram(card, card->tct_base + 6, 0); | |
2949 | write_sram(card, card->tct_base + 7, TCT_FLAG_UBR); | |
2950 | ||
2951 | clear_bit(VCF_IDLE, &vc->flags); | |
2952 | writel(TCMDQ_START | 0, SAR_REG_TCMDQ); | |
2953 | return 0; | |
2954 | } | |
2955 | ||
4fe3c885 LZ |
2956 | static void |
2957 | close_card_ubr0(struct idt77252_dev *card) | |
2958 | { | |
2959 | struct vc_map *vc = card->vcs[0]; | |
2960 | ||
2961 | free_scq(card, vc->scq); | |
2962 | kfree(vc); | |
2963 | } | |
2964 | ||
1da177e4 LT |
2965 | static int |
2966 | idt77252_dev_open(struct idt77252_dev *card) | |
2967 | { | |
2968 | u32 conf; | |
2969 | ||
2970 | if (!test_bit(IDT77252_BIT_INIT, &card->flags)) { | |
2971 | printk("%s: SAR not yet initialized.\n", card->name); | |
2972 | return -1; | |
2973 | } | |
2974 | ||
2975 | conf = SAR_CFG_RXPTH| /* enable receive path */ | |
2976 | SAR_RX_DELAY | /* interrupt on complete PDU */ | |
2977 | SAR_CFG_RAWIE | /* interrupt enable on raw cells */ | |
2978 | SAR_CFG_RQFIE | /* interrupt on RSQ almost full */ | |
2979 | SAR_CFG_TMOIE | /* interrupt on timer overflow */ | |
2980 | SAR_CFG_FBIE | /* interrupt on low free buffers */ | |
2981 | SAR_CFG_TXEN | /* transmit operation enable */ | |
2982 | SAR_CFG_TXINT | /* interrupt on transmit status */ | |
2983 | SAR_CFG_TXUIE | /* interrupt on transmit underrun */ | |
2984 | SAR_CFG_TXSFI | /* interrupt on TSQ almost full */ | |
2985 | SAR_CFG_PHYIE /* enable PHY interrupts */ | |
2986 | ; | |
2987 | ||
2988 | #ifdef CONFIG_ATM_IDT77252_RCV_ALL | |
2989 | /* Test RAW cell receive. */ | |
2990 | conf |= SAR_CFG_VPECA; | |
2991 | #endif | |
2992 | ||
2993 | writel(readl(SAR_REG_CFG) | conf, SAR_REG_CFG); | |
2994 | ||
2995 | if (open_card_oam(card)) { | |
2996 | printk("%s: Error initializing OAM.\n", card->name); | |
2997 | return -1; | |
2998 | } | |
2999 | ||
3000 | if (open_card_ubr0(card)) { | |
3001 | printk("%s: Error initializing UBR0.\n", card->name); | |
3002 | return -1; | |
3003 | } | |
3004 | ||
3005 | IPRINTK("%s: opened IDT77252 ABR SAR.\n", card->name); | |
3006 | return 0; | |
3007 | } | |
3008 | ||
f4c4b4a6 | 3009 | static void idt77252_dev_close(struct atm_dev *dev) |
1da177e4 LT |
3010 | { |
3011 | struct idt77252_dev *card = dev->dev_data; | |
3012 | u32 conf; | |
3013 | ||
4fe3c885 | 3014 | close_card_ubr0(card); |
1da177e4 LT |
3015 | close_card_oam(card); |
3016 | ||
3017 | conf = SAR_CFG_RXPTH | /* enable receive path */ | |
3018 | SAR_RX_DELAY | /* interrupt on complete PDU */ | |
3019 | SAR_CFG_RAWIE | /* interrupt enable on raw cells */ | |
3020 | SAR_CFG_RQFIE | /* interrupt on RSQ almost full */ | |
3021 | SAR_CFG_TMOIE | /* interrupt on timer overflow */ | |
3022 | SAR_CFG_FBIE | /* interrupt on low free buffers */ | |
3023 | SAR_CFG_TXEN | /* transmit operation enable */ | |
3024 | SAR_CFG_TXINT | /* interrupt on transmit status */ | |
3025 | SAR_CFG_TXUIE | /* interrupt on xmit underrun */ | |
3026 | SAR_CFG_TXSFI /* interrupt on TSQ almost full */ | |
3027 | ; | |
3028 | ||
3029 | writel(readl(SAR_REG_CFG) & ~(conf), SAR_REG_CFG); | |
3030 | ||
3031 | DIPRINTK("%s: closed IDT77252 ABR SAR.\n", card->name); | |
3032 | } | |
3033 | ||
3034 | ||
3035 | /*****************************************************************************/ | |
3036 | /* */ | |
3037 | /* Initialisation and Deinitialization of IDT77252 */ | |
3038 | /* */ | |
3039 | /*****************************************************************************/ | |
3040 | ||
3041 | ||
3042 | static void | |
3043 | deinit_card(struct idt77252_dev *card) | |
3044 | { | |
3045 | struct sk_buff *skb; | |
3046 | int i, j; | |
3047 | ||
3048 | if (!test_bit(IDT77252_BIT_INIT, &card->flags)) { | |
3049 | printk("%s: SAR not yet initialized.\n", card->name); | |
3050 | return; | |
3051 | } | |
3052 | DIPRINTK("idt77252: deinitialize card %u\n", card->index); | |
3053 | ||
3054 | writel(0, SAR_REG_CFG); | |
3055 | ||
3056 | if (card->atmdev) | |
3057 | atm_dev_deregister(card->atmdev); | |
3058 | ||
3059 | for (i = 0; i < 4; i++) { | |
3060 | for (j = 0; j < FBQ_SIZE; j++) { | |
3061 | skb = card->sbpool[i].skb[j]; | |
3062 | if (skb) { | |
ede58ef2 | 3063 | dma_unmap_single(&card->pcidev->dev, |
1da177e4 | 3064 | IDT77252_PRV_PADDR(skb), |
4305b541 ACM |
3065 | (skb_end_pointer(skb) - |
3066 | skb->data), | |
ede58ef2 | 3067 | DMA_FROM_DEVICE); |
1da177e4 LT |
3068 | card->sbpool[i].skb[j] = NULL; |
3069 | dev_kfree_skb(skb); | |
3070 | } | |
3071 | } | |
3072 | } | |
3073 | ||
3074 | vfree(card->soft_tst); | |
3075 | ||
3076 | vfree(card->scd2vc); | |
3077 | ||
3078 | vfree(card->vcs); | |
3079 | ||
3080 | if (card->raw_cell_hnd) { | |
ede58ef2 C |
3081 | dma_free_coherent(&card->pcidev->dev, 2 * sizeof(u32), |
3082 | card->raw_cell_hnd, card->raw_cell_paddr); | |
1da177e4 LT |
3083 | } |
3084 | ||
3085 | if (card->rsq.base) { | |
3086 | DIPRINTK("%s: Release RSQ ...\n", card->name); | |
3087 | deinit_rsq(card); | |
3088 | } | |
3089 | ||
3090 | if (card->tsq.base) { | |
3091 | DIPRINTK("%s: Release TSQ ...\n", card->name); | |
3092 | deinit_tsq(card); | |
3093 | } | |
3094 | ||
3095 | DIPRINTK("idt77252: Release IRQ.\n"); | |
3096 | free_irq(card->pcidev->irq, card); | |
3097 | ||
3098 | for (i = 0; i < 4; i++) { | |
3099 | if (card->fbq[i]) | |
3100 | iounmap(card->fbq[i]); | |
3101 | } | |
3102 | ||
3103 | if (card->membase) | |
3104 | iounmap(card->membase); | |
3105 | ||
3106 | clear_bit(IDT77252_BIT_INIT, &card->flags); | |
3107 | DIPRINTK("%s: Card deinitialized.\n", card->name); | |
3108 | } | |
3109 | ||
3110 | ||
6c44512d | 3111 | static void init_sram(struct idt77252_dev *card) |
1da177e4 LT |
3112 | { |
3113 | int i; | |
3114 | ||
3115 | for (i = 0; i < card->sramsize; i += 4) | |
3116 | write_sram(card, (i >> 2), 0); | |
3117 | ||
3118 | /* set SRAM layout for THIS card */ | |
3119 | if (card->sramsize == (512 * 1024)) { | |
3120 | card->tct_base = SAR_SRAM_TCT_128_BASE; | |
3121 | card->tct_size = (SAR_SRAM_TCT_128_TOP - card->tct_base + 1) | |
3122 | / SAR_SRAM_TCT_SIZE; | |
3123 | card->rct_base = SAR_SRAM_RCT_128_BASE; | |
3124 | card->rct_size = (SAR_SRAM_RCT_128_TOP - card->rct_base + 1) | |
3125 | / SAR_SRAM_RCT_SIZE; | |
3126 | card->rt_base = SAR_SRAM_RT_128_BASE; | |
3127 | card->scd_base = SAR_SRAM_SCD_128_BASE; | |
3128 | card->scd_size = (SAR_SRAM_SCD_128_TOP - card->scd_base + 1) | |
3129 | / SAR_SRAM_SCD_SIZE; | |
3130 | card->tst[0] = SAR_SRAM_TST1_128_BASE; | |
3131 | card->tst[1] = SAR_SRAM_TST2_128_BASE; | |
3132 | card->tst_size = SAR_SRAM_TST1_128_TOP - card->tst[0] + 1; | |
3133 | card->abrst_base = SAR_SRAM_ABRSTD_128_BASE; | |
3134 | card->abrst_size = SAR_ABRSTD_SIZE_8K; | |
3135 | card->fifo_base = SAR_SRAM_FIFO_128_BASE; | |
3136 | card->fifo_size = SAR_RXFD_SIZE_32K; | |
3137 | } else { | |
3138 | card->tct_base = SAR_SRAM_TCT_32_BASE; | |
3139 | card->tct_size = (SAR_SRAM_TCT_32_TOP - card->tct_base + 1) | |
3140 | / SAR_SRAM_TCT_SIZE; | |
3141 | card->rct_base = SAR_SRAM_RCT_32_BASE; | |
3142 | card->rct_size = (SAR_SRAM_RCT_32_TOP - card->rct_base + 1) | |
3143 | / SAR_SRAM_RCT_SIZE; | |
3144 | card->rt_base = SAR_SRAM_RT_32_BASE; | |
3145 | card->scd_base = SAR_SRAM_SCD_32_BASE; | |
3146 | card->scd_size = (SAR_SRAM_SCD_32_TOP - card->scd_base + 1) | |
3147 | / SAR_SRAM_SCD_SIZE; | |
3148 | card->tst[0] = SAR_SRAM_TST1_32_BASE; | |
3149 | card->tst[1] = SAR_SRAM_TST2_32_BASE; | |
3150 | card->tst_size = (SAR_SRAM_TST1_32_TOP - card->tst[0] + 1); | |
3151 | card->abrst_base = SAR_SRAM_ABRSTD_32_BASE; | |
3152 | card->abrst_size = SAR_ABRSTD_SIZE_1K; | |
3153 | card->fifo_base = SAR_SRAM_FIFO_32_BASE; | |
3154 | card->fifo_size = SAR_RXFD_SIZE_4K; | |
3155 | } | |
3156 | ||
3157 | /* Initialize TCT */ | |
3158 | for (i = 0; i < card->tct_size; i++) { | |
3159 | write_sram(card, i * SAR_SRAM_TCT_SIZE + 0, 0); | |
3160 | write_sram(card, i * SAR_SRAM_TCT_SIZE + 1, 0); | |
3161 | write_sram(card, i * SAR_SRAM_TCT_SIZE + 2, 0); | |
3162 | write_sram(card, i * SAR_SRAM_TCT_SIZE + 3, 0); | |
3163 | write_sram(card, i * SAR_SRAM_TCT_SIZE + 4, 0); | |
3164 | write_sram(card, i * SAR_SRAM_TCT_SIZE + 5, 0); | |
3165 | write_sram(card, i * SAR_SRAM_TCT_SIZE + 6, 0); | |
3166 | write_sram(card, i * SAR_SRAM_TCT_SIZE + 7, 0); | |
3167 | } | |
3168 | ||
3169 | /* Initialize RCT */ | |
3170 | for (i = 0; i < card->rct_size; i++) { | |
3171 | write_sram(card, card->rct_base + i * SAR_SRAM_RCT_SIZE, | |
3172 | (u32) SAR_RCTE_RAWCELLINTEN); | |
3173 | write_sram(card, card->rct_base + i * SAR_SRAM_RCT_SIZE + 1, | |
3174 | (u32) 0); | |
3175 | write_sram(card, card->rct_base + i * SAR_SRAM_RCT_SIZE + 2, | |
3176 | (u32) 0); | |
3177 | write_sram(card, card->rct_base + i * SAR_SRAM_RCT_SIZE + 3, | |
3178 | (u32) 0xffffffff); | |
3179 | } | |
3180 | ||
3c69f792 CIK |
3181 | writel((SAR_FBQ0_LOW << 28) | (SAR_FB_SIZE_0 / 48), SAR_REG_FBQS0); |
3182 | writel((SAR_FBQ1_LOW << 28) | (SAR_FB_SIZE_1 / 48), SAR_REG_FBQS1); | |
3183 | writel((SAR_FBQ2_LOW << 28) | (SAR_FB_SIZE_2 / 48), SAR_REG_FBQS2); | |
3184 | writel((SAR_FBQ3_LOW << 28) | (SAR_FB_SIZE_3 / 48), SAR_REG_FBQS3); | |
1da177e4 LT |
3185 | |
3186 | /* Initialize rate table */ | |
3187 | for (i = 0; i < 256; i++) { | |
3188 | write_sram(card, card->rt_base + i, log_to_rate[i]); | |
3189 | } | |
3190 | ||
3191 | for (i = 0; i < 128; i++) { | |
3192 | unsigned int tmp; | |
3193 | ||
3194 | tmp = rate_to_log[(i << 2) + 0] << 0; | |
3195 | tmp |= rate_to_log[(i << 2) + 1] << 8; | |
3196 | tmp |= rate_to_log[(i << 2) + 2] << 16; | |
3197 | tmp |= rate_to_log[(i << 2) + 3] << 24; | |
3198 | write_sram(card, card->rt_base + 256 + i, tmp); | |
3199 | } | |
3200 | ||
3201 | #if 0 /* Fill RDF and AIR tables. */ | |
3202 | for (i = 0; i < 128; i++) { | |
3203 | unsigned int tmp; | |
3204 | ||
3205 | tmp = RDF[0][(i << 1) + 0] << 16; | |
3206 | tmp |= RDF[0][(i << 1) + 1] << 0; | |
3207 | write_sram(card, card->rt_base + 512 + i, tmp); | |
3208 | } | |
3209 | ||
3210 | for (i = 0; i < 128; i++) { | |
3211 | unsigned int tmp; | |
3212 | ||
3213 | tmp = AIR[0][(i << 1) + 0] << 16; | |
3214 | tmp |= AIR[0][(i << 1) + 1] << 0; | |
3215 | write_sram(card, card->rt_base + 640 + i, tmp); | |
3216 | } | |
3217 | #endif | |
3218 | ||
3219 | IPRINTK("%s: initialize rate table ...\n", card->name); | |
3220 | writel(card->rt_base << 2, SAR_REG_RTBL); | |
3221 | ||
3222 | /* Initialize TSTs */ | |
3223 | IPRINTK("%s: initialize TST ...\n", card->name); | |
3224 | card->tst_free = card->tst_size - 2; /* last two are jumps */ | |
3225 | ||
3226 | for (i = card->tst[0]; i < card->tst[0] + card->tst_size - 2; i++) | |
3227 | write_sram(card, i, TSTE_OPC_VAR); | |
3228 | write_sram(card, i++, TSTE_OPC_JMP | (card->tst[0] << 2)); | |
3229 | idt77252_sram_write_errors = 1; | |
3230 | write_sram(card, i++, TSTE_OPC_JMP | (card->tst[1] << 2)); | |
3231 | idt77252_sram_write_errors = 0; | |
3232 | for (i = card->tst[1]; i < card->tst[1] + card->tst_size - 2; i++) | |
3233 | write_sram(card, i, TSTE_OPC_VAR); | |
3234 | write_sram(card, i++, TSTE_OPC_JMP | (card->tst[1] << 2)); | |
3235 | idt77252_sram_write_errors = 1; | |
3236 | write_sram(card, i++, TSTE_OPC_JMP | (card->tst[0] << 2)); | |
3237 | idt77252_sram_write_errors = 0; | |
3238 | ||
3239 | card->tst_index = 0; | |
3240 | writel(card->tst[0] << 2, SAR_REG_TSTB); | |
3241 | ||
3242 | /* Initialize ABRSTD and Receive FIFO */ | |
3243 | IPRINTK("%s: initialize ABRSTD ...\n", card->name); | |
3244 | writel(card->abrst_size | (card->abrst_base << 2), | |
3245 | SAR_REG_ABRSTD); | |
3246 | ||
3247 | IPRINTK("%s: initialize receive fifo ...\n", card->name); | |
3248 | writel(card->fifo_size | (card->fifo_base << 2), | |
3249 | SAR_REG_RXFD); | |
3250 | ||
3251 | IPRINTK("%s: SRAM initialization complete.\n", card->name); | |
1da177e4 LT |
3252 | } |
3253 | ||
6c44512d | 3254 | static int init_card(struct atm_dev *dev) |
1da177e4 LT |
3255 | { |
3256 | struct idt77252_dev *card = dev->dev_data; | |
3257 | struct pci_dev *pcidev = card->pcidev; | |
3258 | unsigned long tmpl, modl; | |
3259 | unsigned int linkrate, rsvdcr; | |
3260 | unsigned int tst_entries; | |
3261 | struct net_device *tmp; | |
3262 | char tname[10]; | |
3263 | ||
3264 | u32 size; | |
3265 | u_char pci_byte; | |
3266 | u32 conf; | |
3267 | int i, k; | |
3268 | ||
3269 | if (test_bit(IDT77252_BIT_INIT, &card->flags)) { | |
3270 | printk("Error: SAR already initialized.\n"); | |
3271 | return -1; | |
3272 | } | |
3273 | ||
3274 | /*****************************************************************/ | |
3275 | /* P C I C O N F I G U R A T I O N */ | |
3276 | /*****************************************************************/ | |
3277 | ||
3278 | /* Set PCI Retry-Timeout and TRDY timeout */ | |
3279 | IPRINTK("%s: Checking PCI retries.\n", card->name); | |
3280 | if (pci_read_config_byte(pcidev, 0x40, &pci_byte) != 0) { | |
3281 | printk("%s: can't read PCI retry timeout.\n", card->name); | |
3282 | deinit_card(card); | |
3283 | return -1; | |
3284 | } | |
3285 | if (pci_byte != 0) { | |
3286 | IPRINTK("%s: PCI retry timeout: %d, set to 0.\n", | |
3287 | card->name, pci_byte); | |
3288 | if (pci_write_config_byte(pcidev, 0x40, 0) != 0) { | |
3289 | printk("%s: can't set PCI retry timeout.\n", | |
3290 | card->name); | |
3291 | deinit_card(card); | |
3292 | return -1; | |
3293 | } | |
3294 | } | |
3295 | IPRINTK("%s: Checking PCI TRDY.\n", card->name); | |
3296 | if (pci_read_config_byte(pcidev, 0x41, &pci_byte) != 0) { | |
3297 | printk("%s: can't read PCI TRDY timeout.\n", card->name); | |
3298 | deinit_card(card); | |
3299 | return -1; | |
3300 | } | |
3301 | if (pci_byte != 0) { | |
3302 | IPRINTK("%s: PCI TRDY timeout: %d, set to 0.\n", | |
3303 | card->name, pci_byte); | |
3304 | if (pci_write_config_byte(pcidev, 0x41, 0) != 0) { | |
3305 | printk("%s: can't set PCI TRDY timeout.\n", card->name); | |
3306 | deinit_card(card); | |
3307 | return -1; | |
3308 | } | |
3309 | } | |
3310 | /* Reset Timer register */ | |
3311 | if (readl(SAR_REG_STAT) & SAR_STAT_TMROF) { | |
3312 | printk("%s: resetting timer overflow.\n", card->name); | |
3313 | writel(SAR_STAT_TMROF, SAR_REG_STAT); | |
3314 | } | |
3315 | IPRINTK("%s: Request IRQ ... ", card->name); | |
06df277a | 3316 | if (request_irq(pcidev->irq, idt77252_interrupt, IRQF_SHARED, |
1da177e4 LT |
3317 | card->name, card) != 0) { |
3318 | printk("%s: can't allocate IRQ.\n", card->name); | |
3319 | deinit_card(card); | |
3320 | return -1; | |
3321 | } | |
3322 | IPRINTK("got %d.\n", pcidev->irq); | |
3323 | ||
3324 | /*****************************************************************/ | |
3325 | /* C H E C K A N D I N I T S R A M */ | |
3326 | /*****************************************************************/ | |
3327 | ||
3328 | IPRINTK("%s: Initializing SRAM\n", card->name); | |
3329 | ||
3330 | /* preset size of connecton table, so that init_sram() knows about it */ | |
3331 | conf = SAR_CFG_TX_FIFO_SIZE_9 | /* Use maximum fifo size */ | |
3332 | SAR_CFG_RXSTQ_SIZE_8k | /* Receive Status Queue is 8k */ | |
3333 | SAR_CFG_IDLE_CLP | /* Set CLP on idle cells */ | |
44beac00 | 3334 | #ifndef ATM_IDT77252_SEND_IDLE |
1da177e4 LT |
3335 | SAR_CFG_NO_IDLE | /* Do not send idle cells */ |
3336 | #endif | |
3337 | 0; | |
3338 | ||
3339 | if (card->sramsize == (512 * 1024)) | |
3340 | conf |= SAR_CFG_CNTBL_1k; | |
3341 | else | |
3342 | conf |= SAR_CFG_CNTBL_512; | |
3343 | ||
3344 | switch (vpibits) { | |
3345 | case 0: | |
3346 | conf |= SAR_CFG_VPVCS_0; | |
3347 | break; | |
3348 | default: | |
3349 | case 1: | |
3350 | conf |= SAR_CFG_VPVCS_1; | |
3351 | break; | |
3352 | case 2: | |
3353 | conf |= SAR_CFG_VPVCS_2; | |
3354 | break; | |
3355 | case 8: | |
3356 | conf |= SAR_CFG_VPVCS_8; | |
3357 | break; | |
3358 | } | |
3359 | ||
3360 | writel(readl(SAR_REG_CFG) | conf, SAR_REG_CFG); | |
3361 | ||
1790c228 | 3362 | init_sram(card); |
1da177e4 LT |
3363 | |
3364 | /********************************************************************/ | |
3365 | /* A L L O C R A M A N D S E T V A R I O U S T H I N G S */ | |
3366 | /********************************************************************/ | |
3367 | /* Initialize TSQ */ | |
3368 | if (0 != init_tsq(card)) { | |
3369 | deinit_card(card); | |
3370 | return -1; | |
3371 | } | |
3372 | /* Initialize RSQ */ | |
3373 | if (0 != init_rsq(card)) { | |
3374 | deinit_card(card); | |
3375 | return -1; | |
3376 | } | |
3377 | ||
3378 | card->vpibits = vpibits; | |
3379 | if (card->sramsize == (512 * 1024)) { | |
3380 | card->vcibits = 10 - card->vpibits; | |
3381 | } else { | |
3382 | card->vcibits = 9 - card->vpibits; | |
3383 | } | |
3384 | ||
3385 | card->vcimask = 0; | |
3386 | for (k = 0, i = 1; k < card->vcibits; k++) { | |
3387 | card->vcimask |= i; | |
3388 | i <<= 1; | |
3389 | } | |
3390 | ||
3391 | IPRINTK("%s: Setting VPI/VCI mask to zero.\n", card->name); | |
3392 | writel(0, SAR_REG_VPM); | |
3393 | ||
3394 | /* Little Endian Order */ | |
3395 | writel(0, SAR_REG_GP); | |
3396 | ||
3397 | /* Initialize RAW Cell Handle Register */ | |
750afb08 LC |
3398 | card->raw_cell_hnd = dma_alloc_coherent(&card->pcidev->dev, |
3399 | 2 * sizeof(u32), | |
3400 | &card->raw_cell_paddr, | |
3401 | GFP_KERNEL); | |
1da177e4 LT |
3402 | if (!card->raw_cell_hnd) { |
3403 | printk("%s: memory allocation failure.\n", card->name); | |
3404 | deinit_card(card); | |
3405 | return -1; | |
3406 | } | |
1da177e4 LT |
3407 | writel(card->raw_cell_paddr, SAR_REG_RAWHND); |
3408 | IPRINTK("%s: raw cell handle is at 0x%p.\n", card->name, | |
3409 | card->raw_cell_hnd); | |
3410 | ||
3411 | size = sizeof(struct vc_map *) * card->tct_size; | |
3412 | IPRINTK("%s: allocate %d byte for VC map.\n", card->name, size); | |
3a816054 JP |
3413 | card->vcs = vzalloc(size); |
3414 | if (!card->vcs) { | |
1da177e4 LT |
3415 | printk("%s: memory allocation failure.\n", card->name); |
3416 | deinit_card(card); | |
3417 | return -1; | |
3418 | } | |
1da177e4 LT |
3419 | |
3420 | size = sizeof(struct vc_map *) * card->scd_size; | |
3421 | IPRINTK("%s: allocate %d byte for SCD to VC mapping.\n", | |
3422 | card->name, size); | |
3a816054 JP |
3423 | card->scd2vc = vzalloc(size); |
3424 | if (!card->scd2vc) { | |
1da177e4 LT |
3425 | printk("%s: memory allocation failure.\n", card->name); |
3426 | deinit_card(card); | |
3427 | return -1; | |
3428 | } | |
1da177e4 LT |
3429 | |
3430 | size = sizeof(struct tst_info) * (card->tst_size - 2); | |
3431 | IPRINTK("%s: allocate %d byte for TST to VC mapping.\n", | |
3432 | card->name, size); | |
3a816054 JP |
3433 | card->soft_tst = vmalloc(size); |
3434 | if (!card->soft_tst) { | |
1da177e4 LT |
3435 | printk("%s: memory allocation failure.\n", card->name); |
3436 | deinit_card(card); | |
3437 | return -1; | |
3438 | } | |
3439 | for (i = 0; i < card->tst_size - 2; i++) { | |
3440 | card->soft_tst[i].tste = TSTE_OPC_VAR; | |
3441 | card->soft_tst[i].vc = NULL; | |
3442 | } | |
3443 | ||
3444 | if (dev->phy == NULL) { | |
3445 | printk("%s: No LT device defined.\n", card->name); | |
3446 | deinit_card(card); | |
3447 | return -1; | |
3448 | } | |
3449 | if (dev->phy->ioctl == NULL) { | |
25985edc | 3450 | printk("%s: LT had no IOCTL function defined.\n", card->name); |
1da177e4 LT |
3451 | deinit_card(card); |
3452 | return -1; | |
3453 | } | |
3454 | ||
3455 | #ifdef CONFIG_ATM_IDT77252_USE_SUNI | |
3456 | /* | |
3457 | * this is a jhs hack to get around special functionality in the | |
3458 | * phy driver for the atecom hardware; the functionality doesn't | |
3459 | * exist in the linux atm suni driver | |
3460 | * | |
3461 | * it isn't the right way to do things, but as the guy from NIST | |
3462 | * said, talking about their measurement of the fine structure | |
3463 | * constant, "it's good enough for government work." | |
3464 | */ | |
3465 | linkrate = 149760000; | |
3466 | #endif | |
3467 | ||
3468 | card->link_pcr = (linkrate / 8 / 53); | |
3469 | printk("%s: Linkrate on ATM line : %u bit/s, %u cell/s.\n", | |
3470 | card->name, linkrate, card->link_pcr); | |
3471 | ||
44beac00 | 3472 | #ifdef ATM_IDT77252_SEND_IDLE |
1da177e4 LT |
3473 | card->utopia_pcr = card->link_pcr; |
3474 | #else | |
3475 | card->utopia_pcr = (160000000 / 8 / 54); | |
3476 | #endif | |
3477 | ||
3478 | rsvdcr = 0; | |
3479 | if (card->utopia_pcr > card->link_pcr) | |
3480 | rsvdcr = card->utopia_pcr - card->link_pcr; | |
3481 | ||
3482 | tmpl = (unsigned long) rsvdcr * ((unsigned long) card->tst_size - 2); | |
3483 | modl = tmpl % (unsigned long)card->utopia_pcr; | |
3484 | tst_entries = (int) (tmpl / (unsigned long)card->utopia_pcr); | |
3485 | if (modl) | |
3486 | tst_entries++; | |
3487 | card->tst_free -= tst_entries; | |
3488 | fill_tst(card, NULL, tst_entries, TSTE_OPC_NULL); | |
3489 | ||
3490 | #ifdef HAVE_EEPROM | |
3491 | idt77252_eeprom_init(card); | |
3492 | printk("%s: EEPROM: %02x:", card->name, | |
3493 | idt77252_eeprom_read_status(card)); | |
3494 | ||
3495 | for (i = 0; i < 0x80; i++) { | |
3496 | printk(" %02x", | |
3497 | idt77252_eeprom_read_byte(card, i) | |
3498 | ); | |
3499 | } | |
3500 | printk("\n"); | |
3501 | #endif /* HAVE_EEPROM */ | |
3502 | ||
3503 | /* | |
3504 | * XXX: <hack> | |
3505 | */ | |
3506 | sprintf(tname, "eth%d", card->index); | |
881d966b | 3507 | tmp = dev_get_by_name(&init_net, tname); /* jhs: was "tmp = dev_get(tname);" */ |
1da177e4 LT |
3508 | if (tmp) { |
3509 | memcpy(card->atmdev->esi, tmp->dev_addr, 6); | |
b5de4a22 | 3510 | dev_put(tmp); |
aaa09ee7 | 3511 | printk("%s: ESI %pM\n", card->name, card->atmdev->esi); |
1da177e4 LT |
3512 | } |
3513 | /* | |
3514 | * XXX: </hack> | |
3515 | */ | |
3516 | ||
3517 | /* Set Maximum Deficit Count for now. */ | |
3518 | writel(0xffff, SAR_REG_MDFCT); | |
3519 | ||
3520 | set_bit(IDT77252_BIT_INIT, &card->flags); | |
3521 | ||
3522 | XPRINTK("%s: IDT77252 ABR SAR initialization complete.\n", card->name); | |
3523 | return 0; | |
3524 | } | |
3525 | ||
3526 | ||
3527 | /*****************************************************************************/ | |
3528 | /* */ | |
3529 | /* Probing of IDT77252 ABR SAR */ | |
3530 | /* */ | |
3531 | /*****************************************************************************/ | |
3532 | ||
3533 | ||
6c44512d | 3534 | static int idt77252_preset(struct idt77252_dev *card) |
1da177e4 LT |
3535 | { |
3536 | u16 pci_command; | |
3537 | ||
3538 | /*****************************************************************/ | |
3539 | /* P C I C O N F I G U R A T I O N */ | |
3540 | /*****************************************************************/ | |
3541 | ||
3542 | XPRINTK("%s: Enable PCI master and memory access for SAR.\n", | |
3543 | card->name); | |
3544 | if (pci_read_config_word(card->pcidev, PCI_COMMAND, &pci_command)) { | |
3545 | printk("%s: can't read PCI_COMMAND.\n", card->name); | |
3546 | deinit_card(card); | |
3547 | return -1; | |
3548 | } | |
3549 | if (!(pci_command & PCI_COMMAND_IO)) { | |
d43b2393 | 3550 | printk("%s: PCI_COMMAND: %04x (?)\n", |
1da177e4 LT |
3551 | card->name, pci_command); |
3552 | deinit_card(card); | |
3553 | return (-1); | |
3554 | } | |
3555 | pci_command |= (PCI_COMMAND_MEMORY | PCI_COMMAND_MASTER); | |
3556 | if (pci_write_config_word(card->pcidev, PCI_COMMAND, pci_command)) { | |
3557 | printk("%s: can't write PCI_COMMAND.\n", card->name); | |
3558 | deinit_card(card); | |
3559 | return -1; | |
3560 | } | |
3561 | /*****************************************************************/ | |
3562 | /* G E N E R I C R E S E T */ | |
3563 | /*****************************************************************/ | |
3564 | ||
3565 | /* Software reset */ | |
3566 | writel(SAR_CFG_SWRST, SAR_REG_CFG); | |
3567 | mdelay(1); | |
3568 | writel(0, SAR_REG_CFG); | |
3569 | ||
3570 | IPRINTK("%s: Software resetted.\n", card->name); | |
3571 | return 0; | |
3572 | } | |
3573 | ||
3574 | ||
6c44512d | 3575 | static unsigned long probe_sram(struct idt77252_dev *card) |
1da177e4 LT |
3576 | { |
3577 | u32 data, addr; | |
3578 | ||
3579 | writel(0, SAR_REG_DR0); | |
3580 | writel(SAR_CMD_WRITE_SRAM | (0 << 2), SAR_REG_CMD); | |
3581 | ||
3582 | for (addr = 0x4000; addr < 0x80000; addr += 0x4000) { | |
3c6b3773 | 3583 | writel(ATM_POISON, SAR_REG_DR0); |
1da177e4 LT |
3584 | writel(SAR_CMD_WRITE_SRAM | (addr << 2), SAR_REG_CMD); |
3585 | ||
3586 | writel(SAR_CMD_READ_SRAM | (0 << 2), SAR_REG_CMD); | |
3587 | data = readl(SAR_REG_DR0); | |
3588 | ||
3589 | if (data != 0) | |
3590 | break; | |
3591 | } | |
3592 | ||
3593 | return addr * sizeof(u32); | |
3594 | } | |
3595 | ||
6c44512d GKH |
3596 | static int idt77252_init_one(struct pci_dev *pcidev, |
3597 | const struct pci_device_id *id) | |
1da177e4 LT |
3598 | { |
3599 | static struct idt77252_dev **last = &idt77252_chain; | |
3600 | static int index = 0; | |
3601 | ||
3602 | unsigned long membase, srambase; | |
3603 | struct idt77252_dev *card; | |
3604 | struct atm_dev *dev; | |
1da177e4 LT |
3605 | int i, err; |
3606 | ||
3607 | ||
3608 | if ((err = pci_enable_device(pcidev))) { | |
3609 | printk("idt77252: can't enable PCI device at %s\n", pci_name(pcidev)); | |
3610 | return err; | |
3611 | } | |
3612 | ||
ede58ef2 C |
3613 | if ((err = dma_set_mask_and_coherent(&pcidev->dev, DMA_BIT_MASK(32)))) { |
3614 | printk("idt77252: can't enable DMA for PCI device at %s\n", pci_name(pcidev)); | |
8df66af5 | 3615 | goto err_out_disable_pdev; |
ede58ef2 C |
3616 | } |
3617 | ||
0c1cca1d | 3618 | card = kzalloc(sizeof(struct idt77252_dev), GFP_KERNEL); |
1da177e4 LT |
3619 | if (!card) { |
3620 | printk("idt77252-%d: can't allocate private data\n", index); | |
3621 | err = -ENOMEM; | |
3622 | goto err_out_disable_pdev; | |
3623 | } | |
44c10138 | 3624 | card->revision = pcidev->revision; |
1da177e4 LT |
3625 | card->index = index; |
3626 | card->pcidev = pcidev; | |
3627 | sprintf(card->name, "idt77252-%d", card->index); | |
3628 | ||
c4028958 | 3629 | INIT_WORK(&card->tqueue, idt77252_softint); |
1da177e4 LT |
3630 | |
3631 | membase = pci_resource_start(pcidev, 1); | |
3632 | srambase = pci_resource_start(pcidev, 2); | |
3633 | ||
7e7a2d07 | 3634 | mutex_init(&card->mutex); |
1da177e4 LT |
3635 | spin_lock_init(&card->cmd_lock); |
3636 | spin_lock_init(&card->tst_lock); | |
3637 | ||
e99e88a9 | 3638 | timer_setup(&card->tst_timer, tst_timer, 0); |
1da177e4 LT |
3639 | |
3640 | /* Do the I/O remapping... */ | |
3641 | card->membase = ioremap(membase, 1024); | |
3642 | if (!card->membase) { | |
3643 | printk("%s: can't ioremap() membase\n", card->name); | |
3644 | err = -EIO; | |
3645 | goto err_out_free_card; | |
3646 | } | |
3647 | ||
3648 | if (idt77252_preset(card)) { | |
3649 | printk("%s: preset failed\n", card->name); | |
3650 | err = -EIO; | |
3651 | goto err_out_iounmap; | |
3652 | } | |
3653 | ||
d9ca676b DW |
3654 | dev = atm_dev_register("idt77252", &pcidev->dev, &idt77252_ops, -1, |
3655 | NULL); | |
1da177e4 LT |
3656 | if (!dev) { |
3657 | printk("%s: can't register atm device\n", card->name); | |
3658 | err = -EIO; | |
3659 | goto err_out_iounmap; | |
3660 | } | |
3661 | dev->dev_data = card; | |
3662 | card->atmdev = dev; | |
3663 | ||
3664 | #ifdef CONFIG_ATM_IDT77252_USE_SUNI | |
3665 | suni_init(dev); | |
3666 | if (!dev->phy) { | |
3667 | printk("%s: can't init SUNI\n", card->name); | |
3668 | err = -EIO; | |
3669 | goto err_out_deinit_card; | |
3670 | } | |
3671 | #endif /* CONFIG_ATM_IDT77252_USE_SUNI */ | |
3672 | ||
3673 | card->sramsize = probe_sram(card); | |
3674 | ||
3675 | for (i = 0; i < 4; i++) { | |
3676 | card->fbq[i] = ioremap(srambase | 0x200000 | (i << 18), 4); | |
3677 | if (!card->fbq[i]) { | |
3678 | printk("%s: can't ioremap() FBQ%d\n", card->name, i); | |
3679 | err = -EIO; | |
3680 | goto err_out_deinit_card; | |
3681 | } | |
3682 | } | |
3683 | ||
3684 | printk("%s: ABR SAR (Rev %c): MEM %08lx SRAM %08lx [%u KB]\n", | |
44c10138 AK |
3685 | card->name, ((card->revision > 1) && (card->revision < 25)) ? |
3686 | 'A' + card->revision - 1 : '?', membase, srambase, | |
1da177e4 LT |
3687 | card->sramsize / 1024); |
3688 | ||
3689 | if (init_card(dev)) { | |
3690 | printk("%s: init_card failed\n", card->name); | |
3691 | err = -EIO; | |
3692 | goto err_out_deinit_card; | |
3693 | } | |
3694 | ||
3695 | dev->ci_range.vpi_bits = card->vpibits; | |
3696 | dev->ci_range.vci_bits = card->vcibits; | |
3697 | dev->link_rate = card->link_pcr; | |
3698 | ||
3699 | if (dev->phy->start) | |
3700 | dev->phy->start(dev); | |
3701 | ||
3702 | if (idt77252_dev_open(card)) { | |
3703 | printk("%s: dev_open failed\n", card->name); | |
3704 | err = -EIO; | |
3705 | goto err_out_stop; | |
3706 | } | |
3707 | ||
3708 | *last = card; | |
3709 | last = &card->next; | |
3710 | index++; | |
3711 | ||
3712 | return 0; | |
3713 | ||
3714 | err_out_stop: | |
3715 | if (dev->phy->stop) | |
3716 | dev->phy->stop(dev); | |
3717 | ||
3718 | err_out_deinit_card: | |
3719 | deinit_card(card); | |
3720 | ||
3721 | err_out_iounmap: | |
3722 | iounmap(card->membase); | |
3723 | ||
3724 | err_out_free_card: | |
3725 | kfree(card); | |
3726 | ||
3727 | err_out_disable_pdev: | |
3728 | pci_disable_device(pcidev); | |
3729 | return err; | |
3730 | } | |
3731 | ||
97ae5c2a | 3732 | static const struct pci_device_id idt77252_pci_tbl[] = |
1da177e4 | 3733 | { |
e80d3f08 | 3734 | { PCI_VDEVICE(IDT, PCI_DEVICE_ID_IDT_IDT77252), 0 }, |
1da177e4 LT |
3735 | { 0, } |
3736 | }; | |
3737 | ||
3738 | MODULE_DEVICE_TABLE(pci, idt77252_pci_tbl); | |
3739 | ||
3740 | static struct pci_driver idt77252_driver = { | |
3741 | .name = "idt77252", | |
3742 | .id_table = idt77252_pci_tbl, | |
3743 | .probe = idt77252_init_one, | |
3744 | }; | |
3745 | ||
3746 | static int __init idt77252_init(void) | |
3747 | { | |
3748 | struct sk_buff *skb; | |
3749 | ||
5a346a10 | 3750 | printk("%s: at %p\n", __func__, idt77252_init); |
d0a0bbe7 | 3751 | BUILD_BUG_ON(sizeof(skb->cb) < sizeof(struct idt77252_skb_prv) + sizeof(struct atm_skb_data)); |
1da177e4 LT |
3752 | return pci_register_driver(&idt77252_driver); |
3753 | } | |
3754 | ||
3755 | static void __exit idt77252_exit(void) | |
3756 | { | |
3757 | struct idt77252_dev *card; | |
3758 | struct atm_dev *dev; | |
3759 | ||
3760 | pci_unregister_driver(&idt77252_driver); | |
3761 | ||
3762 | while (idt77252_chain) { | |
3763 | card = idt77252_chain; | |
3764 | dev = card->atmdev; | |
3765 | idt77252_chain = card->next; | |
292a089d | 3766 | timer_shutdown_sync(&card->tst_timer); |
1da177e4 LT |
3767 | |
3768 | if (dev->phy->stop) | |
3769 | dev->phy->stop(dev); | |
3770 | deinit_card(card); | |
3771 | pci_disable_device(card->pcidev); | |
3772 | kfree(card); | |
3773 | } | |
3774 | ||
3775 | DIPRINTK("idt77252: finished cleanup-module().\n"); | |
3776 | } | |
3777 | ||
3778 | module_init(idt77252_init); | |
3779 | module_exit(idt77252_exit); | |
3780 | ||
3781 | MODULE_LICENSE("GPL"); | |
3782 | ||
3783 | module_param(vpibits, uint, 0); | |
3784 | MODULE_PARM_DESC(vpibits, "number of VPI bits supported (0, 1, or 2)"); | |
3785 | #ifdef CONFIG_ATM_IDT77252_DEBUG | |
3786 | module_param(debug, ulong, 0644); | |
3787 | MODULE_PARM_DESC(debug, "debug bitmap, see drivers/atm/idt77252.h"); | |
3788 | #endif | |
3789 | ||
3790 | MODULE_AUTHOR("Eddie C. Dost <ecd@atecom.com>"); | |
3791 | MODULE_DESCRIPTION("IDT77252 ABR SAR Driver"); |