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Linux 5.9-rc2
[linux-block.git] / drivers / atm / firestream.c
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8a618bfc 1// SPDX-License-Identifier: GPL-2.0-or-later
1da177e4
LT		 2
3/* drivers/atm/firestream.c - FireStream 155 (MB86697) and
4 * FireStream 50 (MB86695) device driver
5 */
6
7/* Written & (C) 2000 by R.E.Wolff@BitWizard.nl
8 * Copied snippets from zatm.c by Werner Almesberger, EPFL LRC/ICA
9 * and ambassador.c Copyright (C) 1995-1999 Madge Networks Ltd
10 */
11
12/*
1da177e4
LT		 13*/
14
15
16#include <linux/module.h>
17#include <linux/sched.h>
18#include <linux/kernel.h>
19#include <linux/mm.h>
20#include <linux/pci.h>
b3c681e0 21#include <linux/poison.h>
1da177e4
LT		 22#include <linux/errno.h>
23#include <linux/atm.h>
24#include <linux/atmdev.h>
25#include <linux/sonet.h>
26#include <linux/skbuff.h>
27#include <linux/netdevice.h>
28#include <linux/delay.h>
29#include <linux/ioport.h> /* for request_region */
30#include <linux/uio.h>
31#include <linux/init.h>
a6b7a407 32#include <linux/interrupt.h>
1da177e4
LT		 33#include <linux/capability.h>
34#include <linux/bitops.h>
5a0e3ad6 35#include <linux/slab.h>
1da177e4 36#include <asm/byteorder.h>
1da177e4
LT		 37#include <asm/string.h>
38#include <asm/io.h>
60063497 39#include <linux/atomic.h>
7c0f6ba6 40#include <linux/uaccess.h>
1da177e4
LT		 41#include <linux/wait.h>
42
43#include "firestream.h"
44
45static int loopback = 0;
46static int num=0x5a;
47
48/* According to measurements (but they look suspicious to me!) done in
49 * '97, 37% of the packets are one cell in size. So it pays to have
50 * buffers allocated at that size. A large jump in percentage of
51 * packets occurs at packets around 536 bytes in length. So it also
52 * pays to have those pre-allocated. Unfortunately, we can't fully
53 * take advantage of this as the majority of the packets is likely to
54 * be TCP/IP (As where obviously the measurement comes from) There the
55 * link would be opened with say a 1500 byte MTU, and we can't handle
56 * smaller buffers more efficiently than the larger ones. -- REW
57 */
58
59/* Due to the way Linux memory management works, specifying "576" as
60 * an allocation size here isn't going to help. They are allocated
61 * from 1024-byte regions anyway. With the size of the sk_buffs (quite
62 * large), it doesn't pay to allocate the smallest size (64) -- REW */
63
64/* This is all guesswork. Hard numbers to back this up or disprove this,
65 * are appreciated. -- REW */
66
67/* The last entry should be about 64k. However, the "buffer size" is
68 * passed to the chip in a 16 bit field. I don't know how "65536"
69 * would be interpreted. -- REW */
70
71#define NP FS_NR_FREE_POOLS
72static int rx_buf_sizes[NP] = {128, 256, 512, 1024, 2048, 4096, 16384, 65520};
73/* log2: 7 8 9 10 11 12 14 16 */
74
75#if 0
76static int rx_pool_sizes[NP] = {1024, 1024, 512, 256, 128, 64, 32, 32};
77#else
78/* debug */
79static int rx_pool_sizes[NP] = {128, 128, 128, 64, 64, 64, 32, 32};
80#endif
81/* log2: 10 10 9 8 7 6 5 5 */
82/* sumlog2: 17 18 18 18 18 18 19 21 */
83/* mem allocated: 128k 256k 256k 256k 256k 256k 512k 2M */
84/* tot mem: almost 4M */
85
86/* NP is shorter, so that it fits on a single line. */
87#undef NP
88
89
90/* Small hardware gotcha:
91
92 The FS50 CAM (VP/VC match registers) always take the lowest channel
93 number that matches. This is not a problem.
94
95 However, they also ignore whether the channel is enabled or
96 not. This means that if you allocate channel 0 to 1.2 and then
97 channel 1 to 0.0, then disabeling channel 0 and writing 0 to the
98 match channel for channel 0 will "steal" the traffic from channel
99 1, even if you correctly disable channel 0.
100
101 Workaround:
102
103 - When disabling channels, write an invalid VP/VC value to the
104 match register. (We use 0xffffffff, which in the worst case
105 matches VP/VC = <maxVP>/<maxVC>, but I expect it not to match
106 anything as some "when not in use, program to 0" bits are now
107 programmed to 1...)
108
109 - Don't initialize the match registers to 0, as 0.0 is a valid
110 channel.
111*/
112
113
114/* Optimization hints and tips.
115
116 The FireStream chips are very capable of reducing the amount of
117 "interrupt-traffic" for the CPU. This driver requests an interrupt on EVERY
118 action. You could try to minimize this a bit.
119
120 Besides that, the userspace->kernel copy and the PCI bus are the
121 performance limiting issues for this driver.
122
123 You could queue up a bunch of outgoing packets without telling the
124 FireStream. I'm not sure that's going to win you much though. The
125 Linux layer won't tell us in advance when it's not going to give us
126 any more packets in a while. So this is tricky to implement right without
127 introducing extra delays.
128
129 -- REW
130 */
131
132
133
134
135/* The strings that define what the RX queue entry is all about. */
136/* Fujitsu: Please tell me which ones can have a pointer to a
137 freepool descriptor! */
138static char *res_strings[] = {
139 "RX OK: streaming not EOP",
140 "RX OK: streaming EOP",
141 "RX OK: Single buffer packet",
142 "RX OK: packet mode",
143 "RX OK: F4 OAM (end to end)",
144 "RX OK: F4 OAM (Segment)",
145 "RX OK: F5 OAM (end to end)",
146 "RX OK: F5 OAM (Segment)",
147 "RX OK: RM cell",
148 "RX OK: TRANSP cell",
149 "RX OK: TRANSPC cell",
150 "Unmatched cell",
151 "reserved 12",
152 "reserved 13",
153 "reserved 14",
154 "Unrecognized cell",
155 "reserved 16",
fc4fa6e1 156 "reassembly abort: AAL5 abort",
1da177e4
LT		 157 "packet purged",
158 "packet ageing timeout",
159 "channel ageing timeout",
c5c0f33d
JP		 160 "calculated length error",
161 "programmed length limit error",
1da177e4
LT		 162 "aal5 crc32 error",
163 "oam transp or transpc crc10 error",
164 "reserved 25",
165 "reserved 26",
166 "reserved 27",
167 "reserved 28",
168 "reserved 29",
86f04396 169 "reserved 30", /* FIXME: The strings between 30-40 might be wrong. */
1da177e4
LT		 170 "reassembly abort: no buffers",
171 "receive buffer overflow",
172 "change in GFC",
173 "receive buffer full",
174 "low priority discard - no receive descriptor",
175 "low priority discard - missing end of packet",
86f04396
DC		 176 "reserved 37",
177 "reserved 38",
178 "reserved 39",
9af5573f 179 "reserved 40",
1da177e4
LT		 180 "reserved 41",
181 "reserved 42",
182 "reserved 43",
183 "reserved 44",
184 "reserved 45",
185 "reserved 46",
186 "reserved 47",
187 "reserved 48",
188 "reserved 49",
189 "reserved 50",
190 "reserved 51",
191 "reserved 52",
192 "reserved 53",
193 "reserved 54",
194 "reserved 55",
195 "reserved 56",
196 "reserved 57",
197 "reserved 58",
198 "reserved 59",
199 "reserved 60",
200 "reserved 61",
201 "reserved 62",
202 "reserved 63",
203};
204
205static char *irq_bitname[] = {
206 "LPCO",
207 "DPCO",
208 "RBRQ0_W",
209 "RBRQ1_W",
210 "RBRQ2_W",
211 "RBRQ3_W",
212 "RBRQ0_NF",
213 "RBRQ1_NF",
214 "RBRQ2_NF",
215 "RBRQ3_NF",
216 "BFP_SC",
217 "INIT",
218 "INIT_ERR",
219 "USCEO",
220 "UPEC0",
221 "VPFCO",
222 "CRCCO",
223 "HECO",
224 "TBRQ_W",
225 "TBRQ_NF",
226 "CTPQ_E",
227 "GFC_C0",
228 "PCI_FTL",
229 "CSQ_W",
230 "CSQ_NF",
231 "EXT_INT",
232 "RXDMA_S"
233};
234
235
236#define PHY_EOF -1
237#define PHY_CLEARALL -2
238
239struct reginit_item {
240 int reg, val;
241};
242
243
6c44512d 244static struct reginit_item PHY_NTC_INIT[] = {
1da177e4
LT		 245 { PHY_CLEARALL, 0x40 },
246 { 0x12, 0x0001 },
247 { 0x13, 0x7605 },
248 { 0x1A, 0x0001 },
249 { 0x1B, 0x0005 },
250 { 0x38, 0x0003 },
251 { 0x39, 0x0006 }, /* changed here to make loopback */
252 { 0x01, 0x5262 },
253 { 0x15, 0x0213 },
254 { 0x00, 0x0003 },
255 { PHY_EOF, 0}, /* -1 signals end of list */
256};
257
258
259/* Safetyfeature: If the card interrupts more than this number of times
260 in a jiffy (1/100th of a second) then we just disable the interrupt and
261 print a message. This prevents the system from hanging.
262
263 150000 packets per second is close to the limit a PC is going to have
264 anyway. We therefore have to disable this for production. -- REW */
265#undef IRQ_RATE_LIMIT // 100
266
267/* Interrupts work now. Unlike serial cards, ATM cards don't work all
268 that great without interrupts. -- REW */
269#undef FS_POLL_FREQ // 100
270
271/*
272 This driver can spew a whole lot of debugging output at you. If you
273 need maximum performance, you should disable the DEBUG define. To
274 aid in debugging in the field, I'm leaving the compile-time debug
275 features enabled, and disable them "runtime". That allows me to
276 instruct people with problems to enable debugging without requiring
277 them to recompile... -- REW
278*/
279#define DEBUG
280
281#ifdef DEBUG
282#define fs_dprintk(f, str...) if (fs_debug & f) printk (str)
283#else
284#define fs_dprintk(f, str...) /* nothing */
285#endif
286
287
288static int fs_keystream = 0;
289
290#ifdef DEBUG
291/* I didn't forget to set this to zero before shipping. Hit me with a stick
292 if you get this with the debug default not set to zero again. -- REW */
293static int fs_debug = 0;
294#else
295#define fs_debug 0
296#endif
297
298#ifdef MODULE
299#ifdef DEBUG
300module_param(fs_debug, int, 0644);
301#endif
302module_param(loopback, int, 0);
303module_param(num, int, 0);
304module_param(fs_keystream, int, 0);
305/* XXX Add rx_buf_sizes, and rx_pool_sizes As per request Amar. -- REW */
306#endif
307
308
309#define FS_DEBUG_FLOW 0x00000001
310#define FS_DEBUG_OPEN 0x00000002
311#define FS_DEBUG_QUEUE 0x00000004
312#define FS_DEBUG_IRQ 0x00000008
313#define FS_DEBUG_INIT 0x00000010
314#define FS_DEBUG_SEND 0x00000020
315#define FS_DEBUG_PHY 0x00000040
316#define FS_DEBUG_CLEANUP 0x00000080
317#define FS_DEBUG_QOS 0x00000100
318#define FS_DEBUG_TXQ 0x00000200
319#define FS_DEBUG_ALLOC 0x00000400
320#define FS_DEBUG_TXMEM 0x00000800
321#define FS_DEBUG_QSIZE 0x00001000
322
323
5a346a10
HH		 324#define func_enter() fs_dprintk(FS_DEBUG_FLOW, "fs: enter %s\n", __func__)
325#define func_exit() fs_dprintk(FS_DEBUG_FLOW, "fs: exit %s\n", __func__)
1da177e4
LT		 326
327
328static struct fs_dev *fs_boards = NULL;
329
330#ifdef DEBUG
331
332static void my_hd (void *addr, int len)
333{
334 int j, ch;
335 unsigned char *ptr = addr;
336
337 while (len > 0) {
338 printk ("%p ", ptr);
339 for (j=0;j < ((len < 16)?len:16);j++) {
340 printk ("%02x %s", ptr[j], (j==7)?" ":"");
341 }
342 for ( ;j < 16;j++) {
343 printk (" %s", (j==7)?" ":"");
344 }
345 for (j=0;j < ((len < 16)?len:16);j++) {
346 ch = ptr[j];
347 printk ("%c", (ch < 0x20)?'.':((ch > 0x7f)?'.':ch));
348 }
349 printk ("\n");
350 ptr += 16;
351 len -= 16;
352 }
353}
354#else /* DEBUG */
355static void my_hd (void *addr, int len){}
356#endif /* DEBUG */
357
358/********** free an skb (as per ATM device driver documentation) **********/
359
360/* Hmm. If this is ATM specific, why isn't there an ATM routine for this?
361 * I copied it over from the ambassador driver. -- REW */
362
363static inline void fs_kfree_skb (struct sk_buff * skb)
364{
365 if (ATM_SKB(skb)->vcc->pop)
366 ATM_SKB(skb)->vcc->pop (ATM_SKB(skb)->vcc, skb);
367 else
368 dev_kfree_skb_any (skb);
369}
370
371
372
373
374/* It seems the ATM forum recommends this horribly complicated 16bit
375 * floating point format. Turns out the Ambassador uses the exact same
376 * encoding. I just copied it over. If Mitch agrees, I'll move it over
377 * to the atm_misc file or something like that. (and remove it from
378 * here and the ambassador driver) -- REW
379 */
380
381/* The good thing about this format is that it is monotonic. So,
382 a conversion routine need not be very complicated. To be able to
383 round "nearest" we need to take along a few extra bits. Lets
384 put these after 16 bits, so that we can just return the top 16
385 bits of the 32bit number as the result:
386
387 int mr (unsigned int rate, int r)
388 {
389 int e = 16+9;
390 static int round[4]={0, 0, 0xffff, 0x8000};
391 if (!rate) return 0;
392 while (rate & 0xfc000000) {
393 rate >>= 1;
394 e++;
395 }
396 while (! (rate & 0xfe000000)) {
397 rate <<= 1;
398 e--;
399 }
400
401// Now the mantissa is in positions bit 16-25. Excepf for the "hidden 1" that's in bit 26.
402 rate &= ~0x02000000;
403// Next add in the exponent
404 rate |= e << (16+9);
405// And perform the rounding:
406 return (rate + round[r]) >> 16;
407 }
408
409 14 lines-of-code. Compare that with the 120 that the Ambassador
410 guys needed. (would be 8 lines shorter if I'd try to really reduce
411 the number of lines:
412
413 int mr (unsigned int rate, int r)
414 {
415 int e = 16+9;
416 static int round[4]={0, 0, 0xffff, 0x8000};
417 if (!rate) return 0;
418 for (; rate & 0xfc000000 ;rate >>= 1, e++);
419 for (;!(rate & 0xfe000000);rate <<= 1, e--);
420 return ((rate & ~0x02000000) | (e << (16+9)) + round[r]) >> 16;
421 }
422
423 Exercise for the reader: Remove one more line-of-code, without
424 cheating. (Just joining two lines is cheating). (I know it's
425 possible, don't think you've beat me if you found it... If you
426 manage to lose two lines or more, keep me updated! ;-)
427
428 -- REW */
429
430
431#define ROUND_UP 1
432#define ROUND_DOWN 2
433#define ROUND_NEAREST 3
434/********** make rate (not quite as much fun as Horizon) **********/
435
a0ece285
JL		 436static int make_rate(unsigned int rate, int r,
437 u16 *bits, unsigned int *actual)
1da177e4
LT		 438{
439 unsigned char exp = -1; /* hush gcc */
440 unsigned int man = -1; /* hush gcc */
441
442 fs_dprintk (FS_DEBUG_QOS, "make_rate %u", rate);
443
444 /* rates in cells per second, ITU format (nasty 16-bit floating-point)
445 given 5-bit e and 9-bit m:
446 rate = EITHER (1+m/2^9)*2^e OR 0
447 bits = EITHER 1<<14 | e<<9 | m OR 0
448 (bit 15 is "reserved", bit 14 "non-zero")
449 smallest rate is 0 (special representation)
450 largest rate is (1+511/512)*2^31 = 4290772992 (< 2^32-1)
451 smallest non-zero rate is (1+0/512)*2^0 = 1 (> 0)
452 simple algorithm:
453 find position of top bit, this gives e
454 remove top bit and shift (rounding if feeling clever) by 9-e
455 */
456 /* Ambassador ucode bug: please don't set bit 14! so 0 rate not
457 representable. // This should move into the ambassador driver
458 when properly merged. -- REW */
459
460 if (rate > 0xffc00000U) {
461 /* larger than largest representable rate */
462
463 if (r == ROUND_UP) {
464 return -EINVAL;
465 } else {
466 exp = 31;
467 man = 511;
468 }
469
470 } else if (rate) {
471 /* representable rate */
472
473 exp = 31;
474 man = rate;
475
476 /* invariant: rate = man*2^(exp-31) */
477 while (!(man & (1<<31))) {
478 exp = exp - 1;
479 man = man<<1;
480 }
481
482 /* man has top bit set
483 rate = (2^31+(man-2^31))*2^(exp-31)
484 rate = (1+(man-2^31)/2^31)*2^exp
485 */
486 man = man<<1;
487 man &= 0xffffffffU; /* a nop on 32-bit systems */
488 /* rate = (1+man/2^32)*2^exp
489
490 exp is in the range 0 to 31, man is in the range 0 to 2^32-1
491 time to lose significance... we want m in the range 0 to 2^9-1
492 rounding presents a minor problem... we first decide which way
493 we are rounding (based on given rounding direction and possibly
494 the bits of the mantissa that are to be discarded).
495 */
496
497 switch (r) {
498 case ROUND_DOWN: {
499 /* just truncate */
500 man = man>>(32-9);
501 break;
502 }
503 case ROUND_UP: {
504 /* check all bits that we are discarding */
5f3f24fa 505 if (man & (~0U>>9)) {
1da177e4
LT		 506 man = (man>>(32-9)) + 1;
507 if (man == (1<<9)) {
508 /* no need to check for round up outside of range */
509 man = 0;
510 exp += 1;
511 }
512 } else {
513 man = (man>>(32-9));
514 }
515 break;
516 }
517 case ROUND_NEAREST: {
518 /* check msb that we are discarding */
519 if (man & (1<<(32-9-1))) {
520 man = (man>>(32-9)) + 1;
521 if (man == (1<<9)) {
522 /* no need to check for round up outside of range */
523 man = 0;
524 exp += 1;
525 }
526 } else {
527 man = (man>>(32-9));
528 }
529 break;
530 }
531 }
532
533 } else {
534 /* zero rate - not representable */
535
536 if (r == ROUND_DOWN) {
537 return -EINVAL;
538 } else {
539 exp = 0;
540 man = 0;
541 }
542 }
543
544 fs_dprintk (FS_DEBUG_QOS, "rate: man=%u, exp=%hu", man, exp);
545
546 if (bits)
547 *bits = /* (1<<14) | */ (exp<<9) | man;
548
549 if (actual)
550 *actual = (exp >= 9)
551 ? (1 << exp) + (man << (exp-9))
552 : (1 << exp) + ((man + (1<<(9-exp-1))) >> (9-exp));
553
554 return 0;
555}
556
557
558
559
560/* FireStream access routines */
561/* For DEEP-DOWN debugging these can be rigged to intercept accesses to
562 certain registers or to just log all accesses. */
563
564static inline void write_fs (struct fs_dev *dev, int offset, u32 val)
565{
566 writel (val, dev->base + offset);
567}
568
569
570static inline u32 read_fs (struct fs_dev *dev, int offset)
571{
572 return readl (dev->base + offset);
573}
574
575
576
577static inline struct FS_QENTRY *get_qentry (struct fs_dev *dev, struct queue *q)
578{
579 return bus_to_virt (read_fs (dev, Q_WP(q->offset)) & Q_ADDR_MASK);
580}
581
582
583static void submit_qentry (struct fs_dev *dev, struct queue *q, struct FS_QENTRY *qe)
584{
585 u32 wp;
586 struct FS_QENTRY *cqe;
587
588 /* XXX Sanity check: the write pointer can be checked to be
589 still the same as the value passed as qe... -- REW */
590 /* udelay (5); */
591 while ((wp = read_fs (dev, Q_WP (q->offset))) & Q_FULL) {
592 fs_dprintk (FS_DEBUG_TXQ, "Found queue at %x full. Waiting.\n",
593 q->offset);
594 schedule ();
595 }
596
597 wp &= ~0xf;
598 cqe = bus_to_virt (wp);
599 if (qe != cqe) {
600 fs_dprintk (FS_DEBUG_TXQ, "q mismatch! %p %p\n", qe, cqe);
601 }
602
603 write_fs (dev, Q_WP(q->offset), Q_INCWRAP);
604
605 {
606 static int c;
607 if (!(c++ % 100))
608 {
609 int rp, wp;
610 rp = read_fs (dev, Q_RP(q->offset));
611 wp = read_fs (dev, Q_WP(q->offset));
612 fs_dprintk (FS_DEBUG_TXQ, "q at %d: %x-%x: %x entries.\n",
613 q->offset, rp, wp, wp-rp);
614 }
615 }
616}
617
618#ifdef DEBUG_EXTRA
619static struct FS_QENTRY pq[60];
620static int qp;
621
622static struct FS_BPENTRY dq[60];
623static int qd;
624static void *da[60];
625#endif
626
627static void submit_queue (struct fs_dev *dev, struct queue *q,
628 u32 cmd, u32 p1, u32 p2, u32 p3)
629{
630 struct FS_QENTRY *qe;
631
632 qe = get_qentry (dev, q);
633 qe->cmd = cmd;
634 qe->p0 = p1;
635 qe->p1 = p2;
636 qe->p2 = p3;
637 submit_qentry (dev, q, qe);
638
639#ifdef DEBUG_EXTRA
640 pq[qp].cmd = cmd;
641 pq[qp].p0 = p1;
642 pq[qp].p1 = p2;
643 pq[qp].p2 = p3;
644 qp++;
645 if (qp >= 60) qp = 0;
646#endif
647}
648
649/* Test the "other" way one day... -- REW */
650#if 1
651#define submit_command submit_queue
652#else
653
654static void submit_command (struct fs_dev *dev, struct queue *q,
655 u32 cmd, u32 p1, u32 p2, u32 p3)
656{
657 write_fs (dev, CMDR0, cmd);
658 write_fs (dev, CMDR1, p1);
659 write_fs (dev, CMDR2, p2);
660 write_fs (dev, CMDR3, p3);
661}
662#endif
663
664
665
666static void process_return_queue (struct fs_dev *dev, struct queue *q)
667{
668 long rq;
669 struct FS_QENTRY *qe;
670 void *tc;
671
672 while (!((rq = read_fs (dev, Q_RP(q->offset))) & Q_EMPTY)) {
673 fs_dprintk (FS_DEBUG_QUEUE, "reaping return queue entry at %lx\n", rq);
674 qe = bus_to_virt (rq);
675
676 fs_dprintk (FS_DEBUG_QUEUE, "queue entry: %08x %08x %08x %08x. (%d)\n",
677 qe->cmd, qe->p0, qe->p1, qe->p2, STATUS_CODE (qe));
678
679 switch (STATUS_CODE (qe)) {
680 case 5:
681 tc = bus_to_virt (qe->p0);
682 fs_dprintk (FS_DEBUG_ALLOC, "Free tc: %p\n", tc);
683 kfree (tc);
684 break;
685 }
686
687 write_fs (dev, Q_RP(q->offset), Q_INCWRAP);
688 }
689}
690
691
692static void process_txdone_queue (struct fs_dev *dev, struct queue *q)
693{
694 long rq;
695 long tmp;
696 struct FS_QENTRY *qe;
697 struct sk_buff *skb;
698 struct FS_BPENTRY *td;
699
700 while (!((rq = read_fs (dev, Q_RP(q->offset))) & Q_EMPTY)) {
701 fs_dprintk (FS_DEBUG_QUEUE, "reaping txdone entry at %lx\n", rq);
702 qe = bus_to_virt (rq);
703
704 fs_dprintk (FS_DEBUG_QUEUE, "queue entry: %08x %08x %08x %08x: %d\n",
705 qe->cmd, qe->p0, qe->p1, qe->p2, STATUS_CODE (qe));
706
707 if (STATUS_CODE (qe) != 2)
708 fs_dprintk (FS_DEBUG_TXMEM, "queue entry: %08x %08x %08x %08x: %d\n",
709 qe->cmd, qe->p0, qe->p1, qe->p2, STATUS_CODE (qe));
710
711
712 switch (STATUS_CODE (qe)) {
713 case 0x01: /* This is for AAL0 where we put the chip in streaming mode */
714 /* Fall through */
715 case 0x02:
716 /* Process a real txdone entry. */
717 tmp = qe->p0;
718 if (tmp & 0x0f)
719 printk (KERN_WARNING "td not aligned: %ld\n", tmp);
720 tmp &= ~0x0f;
721 td = bus_to_virt (tmp);
722
723 fs_dprintk (FS_DEBUG_QUEUE, "Pool entry: %08x %08x %08x %08x %p.\n",
724 td->flags, td->next, td->bsa, td->aal_bufsize, td->skb );
725
726 skb = td->skb;
727 if (skb == FS_VCC (ATM_SKB(skb)->vcc)->last_skb) {
1da177e4 728 FS_VCC (ATM_SKB(skb)->vcc)->last_skb = NULL;
c73b1f6a 729 wake_up_interruptible (& FS_VCC (ATM_SKB(skb)->vcc)->close_wait);
1da177e4
LT		 730 }
731 td->dev->ntxpckts--;
732
733 {
734 static int c=0;
735
736 if (!(c++ % 100)) {
737 fs_dprintk (FS_DEBUG_QSIZE, "[%d]", td->dev->ntxpckts);
738 }
739 }
740
741 atomic_inc(&ATM_SKB(skb)->vcc->stats->tx);
742
743 fs_dprintk (FS_DEBUG_TXMEM, "i");
744 fs_dprintk (FS_DEBUG_ALLOC, "Free t-skb: %p\n", skb);
745 fs_kfree_skb (skb);
746
747 fs_dprintk (FS_DEBUG_ALLOC, "Free trans-d: %p\n", td);
b3c681e0 748 memset (td, ATM_POISON_FREE, sizeof(struct FS_BPENTRY));
1da177e4
LT		 749 kfree (td);
750 break;
751 default:
752 /* Here we get the tx purge inhibit command ... */
753 /* Action, I believe, is "don't do anything". -- REW */
754 ;
755 }
756
757 write_fs (dev, Q_RP(q->offset), Q_INCWRAP);
758 }
759}
760
761
762static void process_incoming (struct fs_dev *dev, struct queue *q)
763{
764 long rq;
765 struct FS_QENTRY *qe;
766 struct FS_BPENTRY *pe;
767 struct sk_buff *skb;
768 unsigned int channo;
769 struct atm_vcc *atm_vcc;
770
771 while (!((rq = read_fs (dev, Q_RP(q->offset))) & Q_EMPTY)) {
772 fs_dprintk (FS_DEBUG_QUEUE, "reaping incoming queue entry at %lx\n", rq);
773 qe = bus_to_virt (rq);
774
775 fs_dprintk (FS_DEBUG_QUEUE, "queue entry: %08x %08x %08x %08x. ",
776 qe->cmd, qe->p0, qe->p1, qe->p2);
777
778 fs_dprintk (FS_DEBUG_QUEUE, "-> %x: %s\n",
779 STATUS_CODE (qe),
780 res_strings[STATUS_CODE(qe)]);
781
782 pe = bus_to_virt (qe->p0);
783 fs_dprintk (FS_DEBUG_QUEUE, "Pool entry: %08x %08x %08x %08x %p %p.\n",
784 pe->flags, pe->next, pe->bsa, pe->aal_bufsize,
785 pe->skb, pe->fp);
786
787 channo = qe->cmd & 0xffff;
788
789 if (channo < dev->nchannels)
790 atm_vcc = dev->atm_vccs[channo];
791 else
792 atm_vcc = NULL;
793
794 /* Single buffer packet */
795 switch (STATUS_CODE (qe)) {
796 case 0x1:
797 /* Fall through for streaming mode */
798 case 0x2:/* Packet received OK.... */
799 if (atm_vcc) {
800 skb = pe->skb;
801 pe->fp->n--;
802#if 0
803 fs_dprintk (FS_DEBUG_QUEUE, "Got skb: %p\n", skb);
804 if (FS_DEBUG_QUEUE & fs_debug) my_hd (bus_to_virt (pe->bsa), 0x20);
805#endif
806 skb_put (skb, qe->p1 & 0xffff);
807 ATM_SKB(skb)->vcc = atm_vcc;
808 atomic_inc(&atm_vcc->stats->rx);
a61bbcf2 809 __net_timestamp(skb);
1da177e4
LT		 810 fs_dprintk (FS_DEBUG_ALLOC, "Free rec-skb: %p (pushed)\n", skb);
811 atm_vcc->push (atm_vcc, skb);
812 fs_dprintk (FS_DEBUG_ALLOC, "Free rec-d: %p\n", pe);
813 kfree (pe);
814 } else {
815 printk (KERN_ERR "Got a receive on a non-open channel %d.\n", channo);
816 }
817 break;
818 case 0x17:/* AAL 5 CRC32 error. IFF the length field is nonzero, a buffer
819 has been consumed and needs to be processed. -- REW */
820 if (qe->p1 & 0xffff) {
821 pe = bus_to_virt (qe->p0);
822 pe->fp->n--;
823 fs_dprintk (FS_DEBUG_ALLOC, "Free rec-skb: %p\n", pe->skb);
824 dev_kfree_skb_any (pe->skb);
825 fs_dprintk (FS_DEBUG_ALLOC, "Free rec-d: %p\n", pe);
826 kfree (pe);
827 }
828 if (atm_vcc)
829 atomic_inc(&atm_vcc->stats->rx_drop);
830 break;
831 case 0x1f: /* Reassembly abort: no buffers. */
832 /* Silently increment error counter. */
833 if (atm_vcc)
834 atomic_inc(&atm_vcc->stats->rx_drop);
835 break;
836 default: /* Hmm. Haven't written the code to handle the others yet... -- REW */
837 printk (KERN_WARNING "Don't know what to do with RX status %x: %s.\n",
838 STATUS_CODE(qe), res_strings[STATUS_CODE (qe)]);
839 }
840 write_fs (dev, Q_RP(q->offset), Q_INCWRAP);
841 }
842}
843
844
845
846#define DO_DIRECTION(tp) ((tp)->traffic_class != ATM_NONE)
847
848static int fs_open(struct atm_vcc *atm_vcc)
849{
850 struct fs_dev *dev;
851 struct fs_vcc *vcc;
852 struct fs_transmit_config *tc;
853 struct atm_trafprm * txtp;
854 struct atm_trafprm * rxtp;
855 /* struct fs_receive_config *rc;*/
856 /* struct FS_QENTRY *qe; */
857 int error;
858 int bfp;
859 int to;
860 unsigned short tmc0;
861 short vpi = atm_vcc->vpi;
862 int vci = atm_vcc->vci;
863
864 func_enter ();
865
866 dev = FS_DEV(atm_vcc->dev);
867 fs_dprintk (FS_DEBUG_OPEN, "fs: open on dev: %p, vcc at %p\n",
868 dev, atm_vcc);
869
870 if (vci != ATM_VPI_UNSPEC && vpi != ATM_VCI_UNSPEC)
871 set_bit(ATM_VF_ADDR, &atm_vcc->flags);
872
873 if ((atm_vcc->qos.aal != ATM_AAL5) &&
874 (atm_vcc->qos.aal != ATM_AAL2))
875 return -EINVAL; /* XXX AAL0 */
876
877 fs_dprintk (FS_DEBUG_OPEN, "fs: (itf %d): open %d.%d\n",
878 atm_vcc->dev->number, atm_vcc->vpi, atm_vcc->vci);
879
880 /* XXX handle qos parameters (rate limiting) ? */
881
882 vcc = kmalloc(sizeof(struct fs_vcc), GFP_KERNEL);
5b5e0928 883 fs_dprintk (FS_DEBUG_ALLOC, "Alloc VCC: %p(%zd)\n", vcc, sizeof(struct fs_vcc));
1da177e4
LT		 884 if (!vcc) {
885 clear_bit(ATM_VF_ADDR, &atm_vcc->flags);
886 return -ENOMEM;
887 }
888
889 atm_vcc->dev_data = vcc;
890 vcc->last_skb = NULL;
891
892 init_waitqueue_head (&vcc->close_wait);
893
894 txtp = &atm_vcc->qos.txtp;
895 rxtp = &atm_vcc->qos.rxtp;
896
897 if (!test_bit(ATM_VF_PARTIAL, &atm_vcc->flags)) {
898 if (IS_FS50(dev)) {
899 /* Increment the channel numer: take a free one next time. */
900 for (to=33;to;to--, dev->channo++) {
901 /* We only have 32 channels */
902 if (dev->channo >= 32)
903 dev->channo = 0;
904 /* If we need to do RX, AND the RX is inuse, try the next */
905 if (DO_DIRECTION(rxtp) && dev->atm_vccs[dev->channo])
906 continue;
907 /* If we need to do TX, AND the TX is inuse, try the next */
908 if (DO_DIRECTION(txtp) && test_bit (dev->channo, dev->tx_inuse))
909 continue;
910 /* Ok, both are free! (or not needed) */
911 break;
912 }
913 if (!to) {
914 printk ("No more free channels for FS50..\n");
fa865ba1 915 kfree(vcc);
1da177e4
LT		 916 return -EBUSY;
917 }
918 vcc->channo = dev->channo;
919 dev->channo &= dev->channel_mask;
920
921 } else {
922 vcc->channo = (vpi << FS155_VCI_BITS) | (vci);
923 if (((DO_DIRECTION(rxtp) && dev->atm_vccs[vcc->channo])) ||
924 ( DO_DIRECTION(txtp) && test_bit (vcc->channo, dev->tx_inuse))) {
925 printk ("Channel is in use for FS155.\n");
fa865ba1 926 kfree(vcc);
1da177e4
LT		 927 return -EBUSY;
928 }
929 }
930 fs_dprintk (FS_DEBUG_OPEN, "OK. Allocated channel %x(%d).\n",
931 vcc->channo, vcc->channo);
932 }
933
934 if (DO_DIRECTION (txtp)) {
935 tc = kmalloc (sizeof (struct fs_transmit_config), GFP_KERNEL);
5b5e0928 936 fs_dprintk (FS_DEBUG_ALLOC, "Alloc tc: %p(%zd)\n",
1da177e4
LT		 937 tc, sizeof (struct fs_transmit_config));
938 if (!tc) {
939 fs_dprintk (FS_DEBUG_OPEN, "fs: can't alloc transmit_config.\n");
fa865ba1 940 kfree(vcc);
1da177e4
LT		 941 return -ENOMEM;
942 }
943
944 /* Allocate the "open" entry from the high priority txq. This makes
945 it most likely that the chip will notice it. It also prevents us
946 from having to wait for completion. On the other hand, we may
947 need to wait for completion anyway, to see if it completed
d6e05edc 948 successfully. */
1da177e4
LT		 949
950 switch (atm_vcc->qos.aal) {
951 case ATM_AAL2:
952 case ATM_AAL0:
953 tc->flags = 0
954 | TC_FLAGS_TRANSPARENT_PAYLOAD
955 | TC_FLAGS_PACKET
956 | (1 << 28)
957 | TC_FLAGS_TYPE_UBR /* XXX Change to VBR -- PVDL */
958 | TC_FLAGS_CAL0;
959 break;
960 case ATM_AAL5:
961 tc->flags = 0
962 | TC_FLAGS_AAL5
963 | TC_FLAGS_PACKET /* ??? */
964 | TC_FLAGS_TYPE_CBR
965 | TC_FLAGS_CAL0;
966 break;
967 default:
968 printk ("Unknown aal: %d\n", atm_vcc->qos.aal);
969 tc->flags = 0;
970 }
971 /* Docs are vague about this atm_hdr field. By the way, the FS
972 * chip makes odd errors if lower bits are set.... -- REW */
973 tc->atm_hdr = (vpi << 20) | (vci << 4);
d41a95e0 974 tmc0 = 0;
1da177e4
LT		 975 {
976 int pcr = atm_pcr_goal (txtp);
977
978 fs_dprintk (FS_DEBUG_OPEN, "pcr = %d.\n", pcr);
979
980 /* XXX Hmm. officially we're only allowed to do this if rounding
981 is round_down -- REW */
982 if (IS_FS50(dev)) {
983 if (pcr > 51840000/53/8) pcr = 51840000/53/8;
984 } else {
985 if (pcr > 155520000/53/8) pcr = 155520000/53/8;
986 }
987 if (!pcr) {
988 /* no rate cap */
989 tmc0 = IS_FS50(dev)?0x61BE:0x64c9; /* Just copied over the bits from Fujitsu -- REW */
990 } else {
991 int r;
992 if (pcr < 0) {
993 r = ROUND_DOWN;
994 pcr = -pcr;
995 } else {
996 r = ROUND_UP;
997 }
998 error = make_rate (pcr, r, &tmc0, NULL);
663bab6f
JG		 999 if (error) {
1000 kfree(tc);
1001 return error;
1002 }
1da177e4
LT		 1003 }
1004 fs_dprintk (FS_DEBUG_OPEN, "pcr = %d.\n", pcr);
1005 }
1006
1007 tc->TMC[0] = tmc0 | 0x4000;
1008 tc->TMC[1] = 0; /* Unused */
1009 tc->TMC[2] = 0; /* Unused */
1010 tc->TMC[3] = 0; /* Unused */
1011
1012 tc->spec = 0; /* UTOPIA address, UDF, HEC: Unused -> 0 */
1013 tc->rtag[0] = 0; /* What should I do with routing tags???
1014 -- Not used -- AS -- Thanks -- REW*/
1015 tc->rtag[1] = 0;
1016 tc->rtag[2] = 0;
1017
1018 if (fs_debug & FS_DEBUG_OPEN) {
1019 fs_dprintk (FS_DEBUG_OPEN, "TX config record:\n");
1020 my_hd (tc, sizeof (*tc));
1021 }
1022
1023 /* We now use the "submit_command" function to submit commands to
1024 the firestream. There is a define up near the definition of
1025 that routine that switches this routine between immediate write
8e572bab 1026 to the immediate command registers and queuing the commands in
1da177e4
LT		 1027 the HPTXQ for execution. This last technique might be more
1028 efficient if we know we're going to submit a whole lot of
1029 commands in one go, but this driver is not setup to be able to
1030 use such a construct. So it probably doen't matter much right
1031 now. -- REW */
1032
1033 /* The command is IMMediate and INQueue. The parameters are out-of-line.. */
1034 submit_command (dev, &dev->hp_txq,
1035 QE_CMD_CONFIG_TX | QE_CMD_IMM_INQ | vcc->channo,
1036 virt_to_bus (tc), 0, 0);
1037
1038 submit_command (dev, &dev->hp_txq,
1039 QE_CMD_TX_EN | QE_CMD_IMM_INQ | vcc->channo,
1040 0, 0, 0);
1041 set_bit (vcc->channo, dev->tx_inuse);
1042 }
1043
1044 if (DO_DIRECTION (rxtp)) {
1045 dev->atm_vccs[vcc->channo] = atm_vcc;
1046
1047 for (bfp = 0;bfp < FS_NR_FREE_POOLS; bfp++)
1048 if (atm_vcc->qos.rxtp.max_sdu <= dev->rx_fp[bfp].bufsize) break;
1049 if (bfp >= FS_NR_FREE_POOLS) {
1050 fs_dprintk (FS_DEBUG_OPEN, "No free pool fits sdu: %d.\n",
1051 atm_vcc->qos.rxtp.max_sdu);
1052 /* XXX Cleanup? -- Would just calling fs_close work??? -- REW */
1053
1054 /* XXX clear tx inuse. Close TX part? */
1055 dev->atm_vccs[vcc->channo] = NULL;
1056 kfree (vcc);
1057 return -EINVAL;
1058 }
1059
1060 switch (atm_vcc->qos.aal) {
1061 case ATM_AAL0:
1062 case ATM_AAL2:
1063 submit_command (dev, &dev->hp_txq,
1064 QE_CMD_CONFIG_RX | QE_CMD_IMM_INQ | vcc->channo,
1065 RC_FLAGS_TRANSP |
1066 RC_FLAGS_BFPS_BFP * bfp |
1067 RC_FLAGS_RXBM_PSB, 0, 0);
1068 break;
1069 case ATM_AAL5:
1070 submit_command (dev, &dev->hp_txq,
1071 QE_CMD_CONFIG_RX | QE_CMD_IMM_INQ | vcc->channo,
1072 RC_FLAGS_AAL5 |
1073 RC_FLAGS_BFPS_BFP * bfp |
1074 RC_FLAGS_RXBM_PSB, 0, 0);
1075 break;
d5a721c9 1076 }
1da177e4
LT		 1077 if (IS_FS50 (dev)) {
1078 submit_command (dev, &dev->hp_txq,
1079 QE_CMD_REG_WR | QE_CMD_IMM_INQ,
1080 0x80 + vcc->channo,
1081 (vpi << 16) | vci, 0 ); /* XXX -- Use defines. */
1082 }
1083 submit_command (dev, &dev->hp_txq,
1084 QE_CMD_RX_EN | QE_CMD_IMM_INQ | vcc->channo,
1085 0, 0, 0);
1086 }
1087
1088 /* Indicate we're done! */
1089 set_bit(ATM_VF_READY, &atm_vcc->flags);
1090
1091 func_exit ();
1092 return 0;
1093}
1094
1095
1096static void fs_close(struct atm_vcc *atm_vcc)
1097{
1098 struct fs_dev *dev = FS_DEV (atm_vcc->dev);
1099 struct fs_vcc *vcc = FS_VCC (atm_vcc);
1100 struct atm_trafprm * txtp;
1101 struct atm_trafprm * rxtp;
1102
1103 func_enter ();
1104
1105 clear_bit(ATM_VF_READY, &atm_vcc->flags);
1106
1107 fs_dprintk (FS_DEBUG_QSIZE, "--==**[%d]**==--", dev->ntxpckts);
1108 if (vcc->last_skb) {
1109 fs_dprintk (FS_DEBUG_QUEUE, "Waiting for skb %p to be sent.\n",
1110 vcc->last_skb);
1111 /* We're going to wait for the last packet to get sent on this VC. It would
1112 be impolite not to send them don't you think?
1113 XXX
1114 We don't know which packets didn't get sent. So if we get interrupted in
1115 this sleep_on, we'll lose any reference to these packets. Memory leak!
1116 On the other hand, it's awfully convenient that we can abort a "close" that
1117 is taking too long. Maybe just use non-interruptible sleep on? -- REW */
c73b1f6a 1118 wait_event_interruptible(vcc->close_wait, !vcc->last_skb);
1da177e4
LT		 1119 }
1120
1121 txtp = &atm_vcc->qos.txtp;
1122 rxtp = &atm_vcc->qos.rxtp;
1123
1124
1125 /* See App note XXX (Unpublished as of now) for the reason for the
1126 removal of the "CMD_IMM_INQ" part of the TX_PURGE_INH... -- REW */
1127
1128 if (DO_DIRECTION (txtp)) {
1129 submit_command (dev, &dev->hp_txq,
1130 QE_CMD_TX_PURGE_INH | /*QE_CMD_IMM_INQ|*/ vcc->channo, 0,0,0);
1131 clear_bit (vcc->channo, dev->tx_inuse);
1132 }
1133
1134 if (DO_DIRECTION (rxtp)) {
1135 submit_command (dev, &dev->hp_txq,
1136 QE_CMD_RX_PURGE_INH | QE_CMD_IMM_INQ | vcc->channo, 0,0,0);
1137 dev->atm_vccs [vcc->channo] = NULL;
1138
1139 /* This means that this is configured as a receive channel */
1140 if (IS_FS50 (dev)) {
1141 /* Disable the receive filter. Is 0/0 indeed an invalid receive
1142 channel? -- REW. Yes it is. -- Hang. Ok. I'll use -1
1143 (0xfff...) -- REW */
1144 submit_command (dev, &dev->hp_txq,
1145 QE_CMD_REG_WR | QE_CMD_IMM_INQ,
1146 0x80 + vcc->channo, -1, 0 );
1147 }
1148 }
1149
1150 fs_dprintk (FS_DEBUG_ALLOC, "Free vcc: %p\n", vcc);
1151 kfree (vcc);
1152
1153 func_exit ();
1154}
1155
1156
1157static int fs_send (struct atm_vcc *atm_vcc, struct sk_buff *skb)
1158{
1159 struct fs_dev *dev = FS_DEV (atm_vcc->dev);
1160 struct fs_vcc *vcc = FS_VCC (atm_vcc);
1161 struct FS_BPENTRY *td;
1162
1163 func_enter ();
1164
1165 fs_dprintk (FS_DEBUG_TXMEM, "I");
1166 fs_dprintk (FS_DEBUG_SEND, "Send: atm_vcc %p skb %p vcc %p dev %p\n",
1167 atm_vcc, skb, vcc, dev);
1168
1169 fs_dprintk (FS_DEBUG_ALLOC, "Alloc t-skb: %p (atm_send)\n", skb);
1170
1171 ATM_SKB(skb)->vcc = atm_vcc;
1172
1173 vcc->last_skb = skb;
1174
1175 td = kmalloc (sizeof (struct FS_BPENTRY), GFP_ATOMIC);
5b5e0928 1176 fs_dprintk (FS_DEBUG_ALLOC, "Alloc transd: %p(%zd)\n", td, sizeof (struct FS_BPENTRY));
1da177e4
LT		 1177 if (!td) {
1178 /* Oops out of mem */
1179 return -ENOMEM;
1180 }
1181
1182 fs_dprintk (FS_DEBUG_SEND, "first word in buffer: %x\n",
1183 *(int *) skb->data);
1184
1185 td->flags = TD_EPI | TD_DATA | skb->len;
1186 td->next = 0;
1187 td->bsa = virt_to_bus (skb->data);
1188 td->skb = skb;
1189 td->dev = dev;
1190 dev->ntxpckts++;
1191
1192#ifdef DEBUG_EXTRA
1193 da[qd] = td;
1194 dq[qd].flags = td->flags;
1195 dq[qd].next = td->next;
1196 dq[qd].bsa = td->bsa;
1197 dq[qd].skb = td->skb;
1198 dq[qd].dev = td->dev;
1199 qd++;
1200 if (qd >= 60) qd = 0;
1201#endif
1202
1203 submit_queue (dev, &dev->hp_txq,
1204 QE_TRANSMIT_DE | vcc->channo,
1205 virt_to_bus (td), 0,
1206 virt_to_bus (td));
1207
1208 fs_dprintk (FS_DEBUG_QUEUE, "in send: txq %d txrq %d\n",
1209 read_fs (dev, Q_EA (dev->hp_txq.offset)) -
1210 read_fs (dev, Q_SA (dev->hp_txq.offset)),
1211 read_fs (dev, Q_EA (dev->tx_relq.offset)) -
1212 read_fs (dev, Q_SA (dev->tx_relq.offset)));
1213
1214 func_exit ();
1215 return 0;
1216}
1217
1218
1219/* Some function placeholders for functions we don't yet support. */
1220
1221#if 0
1222static int fs_ioctl(struct atm_dev *dev,unsigned int cmd,void __user *arg)
1223{
1224 func_enter ();
1225 func_exit ();
1226 return -ENOIOCTLCMD;
1227}
1228
1229
1230static int fs_getsockopt(struct atm_vcc *vcc,int level,int optname,
1231 void __user *optval,int optlen)
1232{
1233 func_enter ();
1234 func_exit ();
1235 return 0;
1236}
1237
1238
1239static int fs_setsockopt(struct atm_vcc *vcc,int level,int optname,
b7058842 1240 void __user *optval,unsigned int optlen)
1da177e4
LT		 1241{
1242 func_enter ();
1243 func_exit ();
1244 return 0;
1245}
1246
1247
1248static void fs_phy_put(struct atm_dev *dev,unsigned char value,
1249 unsigned long addr)
1250{
1251 func_enter ();
1252 func_exit ();
1253}
1254
1255
1256static unsigned char fs_phy_get(struct atm_dev *dev,unsigned long addr)
1257{
1258 func_enter ();
1259 func_exit ();
1260 return 0;
1261}
1262
1263
1264static int fs_change_qos(struct atm_vcc *vcc,struct atm_qos *qos,int flags)
1265{
1266 func_enter ();
1267 func_exit ();
1268 return 0;
1269};
1270
1271#endif
1272
1273
1274static const struct atmdev_ops ops = {
1275 .open = fs_open,
1276 .close = fs_close,
1277 .send = fs_send,
1278 .owner = THIS_MODULE,
1279 /* ioctl: fs_ioctl, */
1da177e4
LT		 1280 /* change_qos: fs_change_qos, */
1281
1282 /* For now implement these internally here... */
1283 /* phy_put: fs_phy_put, */
1284 /* phy_get: fs_phy_get, */
1285};
1286
1287
6c44512d 1288static void undocumented_pci_fix(struct pci_dev *pdev)
1da177e4 1289{
b4482a4b 1290 u32 tint;
1da177e4
LT		 1291
1292 /* The Windows driver says: */
1293 /* Switch off FireStream Retry Limit Threshold
1294 */
1295
1296 /* The register at 0x28 is documented as "reserved", no further
1297 comments. */
1298
1299 pci_read_config_dword (pdev, 0x28, &tint);
1300 if (tint != 0x80) {
1301 tint = 0x80;
1302 pci_write_config_dword (pdev, 0x28, tint);
1303 }
1304}
1305
1306
1307
1308/**************************************************************************
1309 * PHY routines *
1310 **************************************************************************/
1311
6c44512d 1312static void write_phy(struct fs_dev *dev, int regnum, int val)
1da177e4
LT		 1313{
1314 submit_command (dev, &dev->hp_txq, QE_CMD_PRP_WR | QE_CMD_IMM_INQ,
1315 regnum, val, 0);
1316}
1317
6c44512d 1318static int init_phy(struct fs_dev *dev, struct reginit_item *reginit)
1da177e4
LT		 1319{
1320 int i;
1321
1322 func_enter ();
1323 while (reginit->reg != PHY_EOF) {
1324 if (reginit->reg == PHY_CLEARALL) {
1325 /* "PHY_CLEARALL means clear all registers. Numregisters is in "val". */
1326 for (i=0;i<reginit->val;i++) {
1327 write_phy (dev, i, 0);
1328 }
1329 } else {
1330 write_phy (dev, reginit->reg, reginit->val);
1331 }
1332 reginit++;
1333 }
1334 func_exit ();
1335 return 0;
1336}
1337
1338static void reset_chip (struct fs_dev *dev)
1339{
1340 int i;
1341
1342 write_fs (dev, SARMODE0, SARMODE0_SRTS0);
1343
1344 /* Undocumented delay */
1345 udelay (128);
1346
1347 /* The "internal registers are documented to all reset to zero, but
1348 comments & code in the Windows driver indicates that the pools are
1349 NOT reset. */
1350 for (i=0;i < FS_NR_FREE_POOLS;i++) {
1351 write_fs (dev, FP_CNF (RXB_FP(i)), 0);
1352 write_fs (dev, FP_SA (RXB_FP(i)), 0);
1353 write_fs (dev, FP_EA (RXB_FP(i)), 0);
1354 write_fs (dev, FP_CNT (RXB_FP(i)), 0);
1355 write_fs (dev, FP_CTU (RXB_FP(i)), 0);
1356 }
1357
1358 /* The same goes for the match channel registers, although those are
1359 NOT documented that way in the Windows driver. -- REW */
1360 /* The Windows driver DOES write 0 to these registers somewhere in
1361 the init sequence. However, a small hardware-feature, will
1362 prevent reception of data on VPI/VCI = 0/0 (Unless the channel
1363 allocated happens to have no disabled channels that have a lower
1364 number. -- REW */
1365
1366 /* Clear the match channel registers. */
1367 if (IS_FS50 (dev)) {
1368 for (i=0;i<FS50_NR_CHANNELS;i++) {
1369 write_fs (dev, 0x200 + i * 4, -1);
1370 }
1371 }
1372}
1373
6c44512d 1374static void *aligned_kmalloc(int size, gfp_t flags, int alignment)
1da177e4
LT		 1375{
1376 void *t;
1377
1378 if (alignment <= 0x10) {
1379 t = kmalloc (size, flags);
1380 if ((unsigned long)t & (alignment-1)) {
1381 printk ("Kmalloc doesn't align things correctly! %p\n", t);
1382 kfree (t);
1383 return aligned_kmalloc (size, flags, alignment * 4);
1384 }
1385 return t;
1386 }
1387 printk (KERN_ERR "Request for > 0x10 alignment not yet implemented (hard!)\n");
1388 return NULL;
1389}
1390
6c44512d
GKH		 1391static int init_q(struct fs_dev *dev, struct queue *txq, int queue,
1392 int nentries, int is_rq)
1da177e4
LT		 1393{
1394 int sz = nentries * sizeof (struct FS_QENTRY);
1395 struct FS_QENTRY *p;
1396
1397 func_enter ();
1398
a8842e97 1399 fs_dprintk (FS_DEBUG_INIT, "Initializing queue at %x: %d entries:\n",
1da177e4
LT		 1400 queue, nentries);
1401
1402 p = aligned_kmalloc (sz, GFP_KERNEL, 0x10);
1403 fs_dprintk (FS_DEBUG_ALLOC, "Alloc queue: %p(%d)\n", p, sz);
1404
1405 if (!p) return 0;
1406
1407 write_fs (dev, Q_SA(queue), virt_to_bus(p));
1408 write_fs (dev, Q_EA(queue), virt_to_bus(p+nentries-1));
1409 write_fs (dev, Q_WP(queue), virt_to_bus(p));
1410 write_fs (dev, Q_RP(queue), virt_to_bus(p));
1411 if (is_rq) {
1412 /* Configuration for the receive queue: 0: interrupt immediately,
1413 no pre-warning to empty queues: We do our best to keep the
1414 queue filled anyway. */
1415 write_fs (dev, Q_CNF(queue), 0 );
1416 }
1417
1418 txq->sa = p;
1419 txq->ea = p;
1420 txq->offset = queue;
1421
1422 func_exit ();
1423 return 1;
1424}
1425
1426
6c44512d
GKH		 1427static int init_fp(struct fs_dev *dev, struct freepool *fp, int queue,
1428 int bufsize, int nr_buffers)
1da177e4
LT		 1429{
1430 func_enter ();
1431
a8842e97 1432 fs_dprintk (FS_DEBUG_INIT, "Initializing free pool at %x:\n", queue);
1da177e4
LT		 1433
1434 write_fs (dev, FP_CNF(queue), (bufsize * RBFP_RBS) | RBFP_RBSVAL | RBFP_CME);
1435 write_fs (dev, FP_SA(queue), 0);
1436 write_fs (dev, FP_EA(queue), 0);
1437 write_fs (dev, FP_CTU(queue), 0);
1438 write_fs (dev, FP_CNT(queue), 0);
1439
1440 fp->offset = queue;
1441 fp->bufsize = bufsize;
1442 fp->nr_buffers = nr_buffers;
1443
1444 func_exit ();
1445 return 1;
1446}
1447
1448
1449static inline int nr_buffers_in_freepool (struct fs_dev *dev, struct freepool *fp)
1450{
1451#if 0
1452 /* This seems to be unreliable.... */
1453 return read_fs (dev, FP_CNT (fp->offset));
1454#else
1455 return fp->n;
1456#endif
1457}
1458
1459
1460/* Check if this gets going again if a pool ever runs out. -- Yes, it
1461 does. I've seen "receive abort: no buffers" and things started
1462 working again after that... -- REW */
1463
c9e42614 1464static void top_off_fp (struct fs_dev *dev, struct freepool *fp,
dd0fc66f 1465 gfp_t gfp_flags)
1da177e4
LT		 1466{
1467 struct FS_BPENTRY *qe, *ne;
1468 struct sk_buff *skb;
1469 int n = 0;
b206a65d 1470 u32 qe_tmp;
1da177e4
LT		 1471
1472 fs_dprintk (FS_DEBUG_QUEUE, "Topping off queue at %x (%d-%d/%d)\n",
1473 fp->offset, read_fs (dev, FP_CNT (fp->offset)), fp->n,
1474 fp->nr_buffers);
1475 while (nr_buffers_in_freepool(dev, fp) < fp->nr_buffers) {
1476
1477 skb = alloc_skb (fp->bufsize, gfp_flags);
1478 fs_dprintk (FS_DEBUG_ALLOC, "Alloc rec-skb: %p(%d)\n", skb, fp->bufsize);
1479 if (!skb) break;
1480 ne = kmalloc (sizeof (struct FS_BPENTRY), gfp_flags);
5b5e0928 1481 fs_dprintk (FS_DEBUG_ALLOC, "Alloc rec-d: %p(%zd)\n", ne, sizeof (struct FS_BPENTRY));
1da177e4
LT		 1482 if (!ne) {
1483 fs_dprintk (FS_DEBUG_ALLOC, "Free rec-skb: %p\n", skb);
1484 dev_kfree_skb_any (skb);
1485 break;
1486 }
1487
1488 fs_dprintk (FS_DEBUG_QUEUE, "Adding skb %p desc %p -> %p(%p) ",
1489 skb, ne, skb->data, skb->head);
1490 n++;
1491 ne->flags = FP_FLAGS_EPI | fp->bufsize;
1492 ne->next = virt_to_bus (NULL);
1493 ne->bsa = virt_to_bus (skb->data);
1494 ne->aal_bufsize = fp->bufsize;
1495 ne->skb = skb;
1496 ne->fp = fp;
1497
b206a65d
JG		 1498 /*
1499 * FIXME: following code encodes and decodes
1500 * machine pointers (could be 64-bit) into a
1501 * 32-bit register.
1502 */
1503
1504 qe_tmp = read_fs (dev, FP_EA(fp->offset));
1505 fs_dprintk (FS_DEBUG_QUEUE, "link at %x\n", qe_tmp);
1506 if (qe_tmp) {
1507 qe = bus_to_virt ((long) qe_tmp);
1da177e4
LT		 1508 qe->next = virt_to_bus(ne);
1509 qe->flags &= ~FP_FLAGS_EPI;
1510 } else
1511 write_fs (dev, FP_SA(fp->offset), virt_to_bus(ne));
1512
1513 write_fs (dev, FP_EA(fp->offset), virt_to_bus (ne));
1514 fp->n++; /* XXX Atomic_inc? */
1515 write_fs (dev, FP_CTU(fp->offset), 1);
1516 }
1517
1518 fs_dprintk (FS_DEBUG_QUEUE, "Added %d entries. \n", n);
1519}
1520
6c44512d 1521static void free_queue(struct fs_dev *dev, struct queue *txq)
1da177e4
LT		 1522{
1523 func_enter ();
1524
1525 write_fs (dev, Q_SA(txq->offset), 0);
1526 write_fs (dev, Q_EA(txq->offset), 0);
1527 write_fs (dev, Q_RP(txq->offset), 0);
1528 write_fs (dev, Q_WP(txq->offset), 0);
1529 /* Configuration ? */
1530
1531 fs_dprintk (FS_DEBUG_ALLOC, "Free queue: %p\n", txq->sa);
1532 kfree (txq->sa);
1533
1534 func_exit ();
1535}
1536
6c44512d 1537static void free_freepool(struct fs_dev *dev, struct freepool *fp)
1da177e4
LT		 1538{
1539 func_enter ();
1540
1541 write_fs (dev, FP_CNF(fp->offset), 0);
1542 write_fs (dev, FP_SA (fp->offset), 0);
1543 write_fs (dev, FP_EA (fp->offset), 0);
1544 write_fs (dev, FP_CNT(fp->offset), 0);
1545 write_fs (dev, FP_CTU(fp->offset), 0);
1546
1547 func_exit ();
1548}
1549
1550
1551
7d12e780 1552static irqreturn_t fs_irq (int irq, void *dev_id)
1da177e4
LT		 1553{
1554 int i;
1555 u32 status;
1556 struct fs_dev *dev = dev_id;
1557
1558 status = read_fs (dev, ISR);
1559 if (!status)
1560 return IRQ_NONE;
1561
1562 func_enter ();
1563
1564#ifdef IRQ_RATE_LIMIT
1565 /* Aaargh! I'm ashamed. This costs more lines-of-code than the actual
1566 interrupt routine!. (Well, used to when I wrote that comment) -- REW */
1567 {
1568 static int lastjif;
1569 static int nintr=0;
1570
1571 if (lastjif == jiffies) {
1572 if (++nintr > IRQ_RATE_LIMIT) {
1573 free_irq (dev->irq, dev_id);
1574 printk (KERN_ERR "fs: Too many interrupts. Turning off interrupt %d.\n",
1575 dev->irq);
1576 }
1577 } else {
1578 lastjif = jiffies;
1579 nintr = 0;
1580 }
1581 }
1582#endif
1583 fs_dprintk (FS_DEBUG_QUEUE, "in intr: txq %d txrq %d\n",
1584 read_fs (dev, Q_EA (dev->hp_txq.offset)) -
1585 read_fs (dev, Q_SA (dev->hp_txq.offset)),
1586 read_fs (dev, Q_EA (dev->tx_relq.offset)) -
1587 read_fs (dev, Q_SA (dev->tx_relq.offset)));
1588
1589 /* print the bits in the ISR register. */
1590 if (fs_debug & FS_DEBUG_IRQ) {
3a4fa0a2 1591 /* The FS_DEBUG things are unnecessary here. But this way it is
1da177e4
LT		 1592 clear for grep that these are debug prints. */
1593 fs_dprintk (FS_DEBUG_IRQ, "IRQ status:");
1594 for (i=0;i<27;i++)
1595 if (status & (1 << i))
1596 fs_dprintk (FS_DEBUG_IRQ, " %s", irq_bitname[i]);
1597 fs_dprintk (FS_DEBUG_IRQ, "\n");
1598 }
1599
1600 if (status & ISR_RBRQ0_W) {
1601 fs_dprintk (FS_DEBUG_IRQ, "Iiiin-coming (0)!!!!\n");
1602 process_incoming (dev, &dev->rx_rq[0]);
1603 /* items mentioned on RBRQ0 are from FP 0 or 1. */
1604 top_off_fp (dev, &dev->rx_fp[0], GFP_ATOMIC);
1605 top_off_fp (dev, &dev->rx_fp[1], GFP_ATOMIC);
1606 }
1607
1608 if (status & ISR_RBRQ1_W) {
1609 fs_dprintk (FS_DEBUG_IRQ, "Iiiin-coming (1)!!!!\n");
1610 process_incoming (dev, &dev->rx_rq[1]);
1611 top_off_fp (dev, &dev->rx_fp[2], GFP_ATOMIC);
1612 top_off_fp (dev, &dev->rx_fp[3], GFP_ATOMIC);
1613 }
1614
1615 if (status & ISR_RBRQ2_W) {
1616 fs_dprintk (FS_DEBUG_IRQ, "Iiiin-coming (2)!!!!\n");
1617 process_incoming (dev, &dev->rx_rq[2]);
1618 top_off_fp (dev, &dev->rx_fp[4], GFP_ATOMIC);
1619 top_off_fp (dev, &dev->rx_fp[5], GFP_ATOMIC);
1620 }
1621
1622 if (status & ISR_RBRQ3_W) {
1623 fs_dprintk (FS_DEBUG_IRQ, "Iiiin-coming (3)!!!!\n");
1624 process_incoming (dev, &dev->rx_rq[3]);
1625 top_off_fp (dev, &dev->rx_fp[6], GFP_ATOMIC);
1626 top_off_fp (dev, &dev->rx_fp[7], GFP_ATOMIC);
1627 }
1628
1629 if (status & ISR_CSQ_W) {
1630 fs_dprintk (FS_DEBUG_IRQ, "Command executed ok!\n");
1631 process_return_queue (dev, &dev->st_q);
1632 }
1633
1634 if (status & ISR_TBRQ_W) {
a7cf2cc3 1635 fs_dprintk (FS_DEBUG_IRQ, "Data transmitted!\n");
1da177e4
LT		 1636 process_txdone_queue (dev, &dev->tx_relq);
1637 }
1638
1639 func_exit ();
1640 return IRQ_HANDLED;
1641}
1642
1643
1644#ifdef FS_POLL_FREQ
e99e88a9 1645static void fs_poll (struct timer_list *t)
1da177e4 1646{
e99e88a9 1647 struct fs_dev *dev = from_timer(dev, t, timer);
1da177e4 1648
0da2f0f1 1649 fs_irq (0, dev);
1da177e4
LT		 1650 dev->timer.expires = jiffies + FS_POLL_FREQ;
1651 add_timer (&dev->timer);
1652}
1653#endif
1654
6c44512d 1655static int fs_init(struct fs_dev *dev)
1da177e4
LT		 1656{
1657 struct pci_dev *pci_dev;
1658 int isr, to;
1659 int i;
1660
1661 func_enter ();
1662 pci_dev = dev->pci_dev;
1663
e29419ff 1664 printk (KERN_INFO "found a FireStream %d card, base %16llx, irq%d.\n",
1da177e4 1665 IS_FS50(dev)?50:155,
e29419ff
GKH		 1666 (unsigned long long)pci_resource_start(pci_dev, 0),
1667 dev->pci_dev->irq);
1da177e4
LT		 1668
1669 if (fs_debug & FS_DEBUG_INIT)
1670 my_hd ((unsigned char *) dev, sizeof (*dev));
1671
1672 undocumented_pci_fix (pci_dev);
1673
1674 dev->hw_base = pci_resource_start(pci_dev, 0);
1675
1676 dev->base = ioremap(dev->hw_base, 0x1000);
1677
1678 reset_chip (dev);
1679
1680 write_fs (dev, SARMODE0, 0
1681 | (0 * SARMODE0_SHADEN) /* We don't use shadow registers. */
1682 | (1 * SARMODE0_INTMODE_READCLEAR)
1683 | (1 * SARMODE0_CWRE)
ca1ada88
RK		 1684 | (IS_FS50(dev) ? SARMODE0_PRPWT_FS50_5:
1685 SARMODE0_PRPWT_FS155_3)
1da177e4 1686 | (1 * SARMODE0_CALSUP_1)
ca1ada88 1687 | (IS_FS50(dev) ? (0
1da177e4
LT		 1688 | SARMODE0_RXVCS_32
1689 | SARMODE0_ABRVCS_32
1690 | SARMODE0_TXVCS_32):
1691 (0
1692 | SARMODE0_RXVCS_1k
1693 | SARMODE0_ABRVCS_1k
ca1ada88 1694 | SARMODE0_TXVCS_1k)));
1da177e4
LT		 1695
1696 /* 10ms * 100 is 1 second. That should be enough, as AN3:9 says it takes
1697 1ms. */
1698 to = 100;
1699 while (--to) {
1700 isr = read_fs (dev, ISR);
1701
1702 /* This bit is documented as "RESERVED" */
1703 if (isr & ISR_INIT_ERR) {
1704 printk (KERN_ERR "Error initializing the FS... \n");
78e4be16 1705 goto unmap;
1da177e4
LT		 1706 }
1707 if (isr & ISR_INIT) {
1708 fs_dprintk (FS_DEBUG_INIT, "Ha! Initialized OK!\n");
1709 break;
1710 }
1711
1712 /* Try again after 10ms. */
1713 msleep(10);
1714 }
1715
1716 if (!to) {
1717 printk (KERN_ERR "timeout initializing the FS... \n");
78e4be16 1718 goto unmap;
1da177e4
LT		 1719 }
1720
1721 /* XXX fix for fs155 */
1722 dev->channel_mask = 0x1f;
1723 dev->channo = 0;
1724
1725 /* AN3: 10 */
1726 write_fs (dev, SARMODE1, 0
1727 | (fs_keystream * SARMODE1_DEFHEC) /* XXX PHY */
1728 | ((loopback == 1) * SARMODE1_TSTLP) /* XXX Loopback mode enable... */
1729 | (1 * SARMODE1_DCRM)
1730 | (1 * SARMODE1_DCOAM)
1731 | (0 * SARMODE1_OAMCRC)
1732 | (0 * SARMODE1_DUMPE)
1733 | (0 * SARMODE1_GPLEN)
1734 | (0 * SARMODE1_GNAM)
1735 | (0 * SARMODE1_GVAS)
1736 | (0 * SARMODE1_GPAS)
1737 | (1 * SARMODE1_GPRI)
1738 | (0 * SARMODE1_PMS)
1739 | (0 * SARMODE1_GFCR)
1740 | (1 * SARMODE1_HECM2)
1741 | (1 * SARMODE1_HECM1)
1742 | (1 * SARMODE1_HECM0)
1743 | (1 << 12) /* That's what hang's driver does. Program to 0 */
1744 | (0 * 0xff) /* XXX FS155 */);
1745
1746
1747 /* Cal prescale etc */
1748
1749 /* AN3: 11 */
1750 write_fs (dev, TMCONF, 0x0000000f);
1751 write_fs (dev, CALPRESCALE, 0x01010101 * num);
1752 write_fs (dev, 0x80, 0x000F00E4);
1753
1754 /* AN3: 12 */
1755 write_fs (dev, CELLOSCONF, 0
1756 | ( 0 * CELLOSCONF_CEN)
1757 | ( CELLOSCONF_SC1)
1758 | (0x80 * CELLOSCONF_COBS)
1759 | (num * CELLOSCONF_COPK) /* Changed from 0xff to 0x5a */
1760 | (num * CELLOSCONF_COST));/* after a hint from Hang.
1761 * performance jumped 50->70... */
1762
1763 /* Magic value by Hang */
1764 write_fs (dev, CELLOSCONF_COST, 0x0B809191);
1765
1766 if (IS_FS50 (dev)) {
1767 write_fs (dev, RAS0, RAS0_DCD_XHLT);
1768 dev->atm_dev->ci_range.vpi_bits = 12;
1769 dev->atm_dev->ci_range.vci_bits = 16;
1770 dev->nchannels = FS50_NR_CHANNELS;
1771 } else {
1772 write_fs (dev, RAS0, RAS0_DCD_XHLT
1773 | (((1 << FS155_VPI_BITS) - 1) * RAS0_VPSEL)
1774 | (((1 << FS155_VCI_BITS) - 1) * RAS0_VCSEL));
25985edc 1775 /* We can chose the split arbitrarily. We might be able to
1da177e4
LT		 1776 support more. Whatever. This should do for now. */
1777 dev->atm_dev->ci_range.vpi_bits = FS155_VPI_BITS;
1778 dev->atm_dev->ci_range.vci_bits = FS155_VCI_BITS;
1779
1780 /* Address bits we can't use should be compared to 0. */
1781 write_fs (dev, RAC, 0);
1782
1783 /* Manual (AN9, page 6) says ASF1=0 means compare Utopia address
1784 * too. I can't find ASF1 anywhere. Anyway, we AND with just the
1785 * other bits, then compare with 0, which is exactly what we
1786 * want. */
1787 write_fs (dev, RAM, (1 << (28 - FS155_VPI_BITS - FS155_VCI_BITS)) - 1);
1788 dev->nchannels = FS155_NR_CHANNELS;
1789 }
0c1cca1d 1790 dev->atm_vccs = kcalloc (dev->nchannels, sizeof (struct atm_vcc *),
1da177e4 1791 GFP_KERNEL);
5b5e0928 1792 fs_dprintk (FS_DEBUG_ALLOC, "Alloc atmvccs: %p(%zd)\n",
1da177e4
LT		 1793 dev->atm_vccs, dev->nchannels * sizeof (struct atm_vcc *));
1794
1795 if (!dev->atm_vccs) {
1796 printk (KERN_WARNING "Couldn't allocate memory for VCC buffers. Woops!\n");
1797 /* XXX Clean up..... */
78e4be16 1798 goto unmap;
1da177e4 1799 }
1da177e4 1800
0c1cca1d 1801 dev->tx_inuse = kzalloc (dev->nchannels / 8 /* bits/byte */ , GFP_KERNEL);
1da177e4
LT		 1802 fs_dprintk (FS_DEBUG_ALLOC, "Alloc tx_inuse: %p(%d)\n",
1803 dev->atm_vccs, dev->nchannels / 8);
1804
1805 if (!dev->tx_inuse) {
1806 printk (KERN_WARNING "Couldn't allocate memory for tx_inuse bits!\n");
1807 /* XXX Clean up..... */
78e4be16 1808 goto unmap;
1da177e4 1809 }
1da177e4
LT		 1810 /* -- RAS1 : FS155 and 50 differ. Default (0) should be OK for both */
1811 /* -- RAS2 : FS50 only: Default is OK. */
1812
1813 /* DMAMODE, default should be OK. -- REW */
1814 write_fs (dev, DMAMR, DMAMR_TX_MODE_FULL);
1815
1816 init_q (dev, &dev->hp_txq, TX_PQ(TXQ_HP), TXQ_NENTRIES, 0);
1817 init_q (dev, &dev->lp_txq, TX_PQ(TXQ_LP), TXQ_NENTRIES, 0);
1818 init_q (dev, &dev->tx_relq, TXB_RQ, TXQ_NENTRIES, 1);
1819 init_q (dev, &dev->st_q, ST_Q, TXQ_NENTRIES, 1);
1820
1821 for (i=0;i < FS_NR_FREE_POOLS;i++) {
1822 init_fp (dev, &dev->rx_fp[i], RXB_FP(i),
1823 rx_buf_sizes[i], rx_pool_sizes[i]);
1824 top_off_fp (dev, &dev->rx_fp[i], GFP_KERNEL);
1825 }
1826
1827
1828 for (i=0;i < FS_NR_RX_QUEUES;i++)
1829 init_q (dev, &dev->rx_rq[i], RXB_RQ(i), RXRQ_NENTRIES, 1);
1830
1831 dev->irq = pci_dev->irq;
dace1453 1832 if (request_irq (dev->irq, fs_irq, IRQF_SHARED, "firestream", dev)) {
1da177e4
LT		 1833 printk (KERN_WARNING "couldn't get irq %d for firestream.\n", pci_dev->irq);
1834 /* XXX undo all previous stuff... */
78e4be16 1835 goto unmap;
1da177e4
LT		 1836 }
1837 fs_dprintk (FS_DEBUG_INIT, "Grabbed irq %d for dev at %p.\n", dev->irq, dev);
1838
1839 /* We want to be notified of most things. Just the statistics count
1840 overflows are not interesting */
1841 write_fs (dev, IMR, 0
1842 | ISR_RBRQ0_W
1843 | ISR_RBRQ1_W
1844 | ISR_RBRQ2_W
1845 | ISR_RBRQ3_W
1846 | ISR_TBRQ_W
1847 | ISR_CSQ_W);
1848
1849 write_fs (dev, SARMODE0, 0
1850 | (0 * SARMODE0_SHADEN) /* We don't use shadow registers. */
1851 | (1 * SARMODE0_GINT)
1852 | (1 * SARMODE0_INTMODE_READCLEAR)
1853 | (0 * SARMODE0_CWRE)
1854 | (IS_FS50(dev)?SARMODE0_PRPWT_FS50_5:
1855 SARMODE0_PRPWT_FS155_3)
1856 | (1 * SARMODE0_CALSUP_1)
1857 | (IS_FS50 (dev)?(0
1858 | SARMODE0_RXVCS_32
1859 | SARMODE0_ABRVCS_32
1860 | SARMODE0_TXVCS_32):
1861 (0
1862 | SARMODE0_RXVCS_1k
1863 | SARMODE0_ABRVCS_1k
1864 | SARMODE0_TXVCS_1k))
1865 | (1 * SARMODE0_RUN));
1866
1867 init_phy (dev, PHY_NTC_INIT);
1868
1869 if (loopback == 2) {
1870 write_phy (dev, 0x39, 0x000e);
1871 }
1872
1873#ifdef FS_POLL_FREQ
e99e88a9 1874 timer_setup(&dev->timer, fs_poll, 0);
1da177e4
LT		 1875 dev->timer.expires = jiffies + FS_POLL_FREQ;
1876 add_timer (&dev->timer);
1877#endif
1878
1879 dev->atm_dev->dev_data = dev;
1880
1881 func_exit ();
1882 return 0;
78e4be16
AL		 1883unmap:
1884 iounmap(dev->base);
1885 return 1;
1da177e4
LT		 1886}
1887
6c44512d
GKH		 1888static int firestream_init_one(struct pci_dev *pci_dev,
1889 const struct pci_device_id *ent)
1da177e4
LT		 1890{
1891 struct atm_dev *atm_dev;
1892 struct fs_dev *fs_dev;
1893
1894 if (pci_enable_device(pci_dev))
1895 goto err_out;
1896
0c1cca1d 1897 fs_dev = kzalloc (sizeof (struct fs_dev), GFP_KERNEL);
5b5e0928 1898 fs_dprintk (FS_DEBUG_ALLOC, "Alloc fs-dev: %p(%zd)\n",
1da177e4
LT		 1899 fs_dev, sizeof (struct fs_dev));
1900 if (!fs_dev)
1901 goto err_out;
d9ca676b 1902 atm_dev = atm_dev_register("fs", &pci_dev->dev, &ops, -1, NULL);
1da177e4
LT		 1903 if (!atm_dev)
1904 goto err_out_free_fs_dev;
1905
1906 fs_dev->pci_dev = pci_dev;
1907 fs_dev->atm_dev = atm_dev;
1908 fs_dev->flags = ent->driver_data;
1909
1910 if (fs_init(fs_dev))
1911 goto err_out_free_atm_dev;
1912
1913 fs_dev->next = fs_boards;
1914 fs_boards = fs_dev;
1915 return 0;
1916
1917 err_out_free_atm_dev:
1918 atm_dev_deregister(atm_dev);
1919 err_out_free_fs_dev:
1920 kfree(fs_dev);
1921 err_out:
1922 return -ENODEV;
1923}
1924
6c44512d 1925static void firestream_remove_one(struct pci_dev *pdev)
1da177e4
LT		 1926{
1927 int i;
1928 struct fs_dev *dev, *nxtdev;
1929 struct fs_vcc *vcc;
1930 struct FS_BPENTRY *fp, *nxt;
1931
1932 func_enter ();
1933
1934#if 0
1935 printk ("hptxq:\n");
1936 for (i=0;i<60;i++) {
1937 printk ("%d: %08x %08x %08x %08x \n",
1938 i, pq[qp].cmd, pq[qp].p0, pq[qp].p1, pq[qp].p2);
1939 qp++;
1940 if (qp >= 60) qp = 0;
1941 }
1942
1943 printk ("descriptors:\n");
1944 for (i=0;i<60;i++) {
1945 printk ("%d: %p: %08x %08x %p %p\n",
1946 i, da[qd], dq[qd].flags, dq[qd].bsa, dq[qd].skb, dq[qd].dev);
1947 qd++;
1948 if (qd >= 60) qd = 0;
1949 }
1950#endif
1951
1952 for (dev = fs_boards;dev != NULL;dev=nxtdev) {
1953 fs_dprintk (FS_DEBUG_CLEANUP, "Releasing resources for dev at %p.\n", dev);
1954
1955 /* XXX Hit all the tx channels too! */
1956
1957 for (i=0;i < dev->nchannels;i++) {
1958 if (dev->atm_vccs[i]) {
1959 vcc = FS_VCC (dev->atm_vccs[i]);
1960 submit_command (dev, &dev->hp_txq,
1961 QE_CMD_TX_PURGE_INH | QE_CMD_IMM_INQ | vcc->channo, 0,0,0);
1962 submit_command (dev, &dev->hp_txq,
1963 QE_CMD_RX_PURGE_INH | QE_CMD_IMM_INQ | vcc->channo, 0,0,0);
1964
1965 }
1966 }
1967
1968 /* XXX Wait a while for the chip to release all buffers. */
1969
1970 for (i=0;i < FS_NR_FREE_POOLS;i++) {
1971 for (fp=bus_to_virt (read_fs (dev, FP_SA(dev->rx_fp[i].offset)));
1972 !(fp->flags & FP_FLAGS_EPI);fp = nxt) {
1973 fs_dprintk (FS_DEBUG_ALLOC, "Free rec-skb: %p\n", fp->skb);
1974 dev_kfree_skb_any (fp->skb);
1975 nxt = bus_to_virt (fp->next);
1976 fs_dprintk (FS_DEBUG_ALLOC, "Free rec-d: %p\n", fp);
1977 kfree (fp);
1978 }
1979 fs_dprintk (FS_DEBUG_ALLOC, "Free rec-skb: %p\n", fp->skb);
1980 dev_kfree_skb_any (fp->skb);
1981 fs_dprintk (FS_DEBUG_ALLOC, "Free rec-d: %p\n", fp);
1982 kfree (fp);
1983 }
1984
1985 /* Hang the chip in "reset", prevent it clobbering memory that is
1986 no longer ours. */
1987 reset_chip (dev);
1988
1989 fs_dprintk (FS_DEBUG_CLEANUP, "Freeing irq%d.\n", dev->irq);
1990 free_irq (dev->irq, dev);
aff12acc 1991 del_timer_sync (&dev->timer);
1da177e4
LT		 1992
1993 atm_dev_deregister(dev->atm_dev);
1994 free_queue (dev, &dev->hp_txq);
1995 free_queue (dev, &dev->lp_txq);
1996 free_queue (dev, &dev->tx_relq);
1997 free_queue (dev, &dev->st_q);
1998
1999 fs_dprintk (FS_DEBUG_ALLOC, "Free atmvccs: %p\n", dev->atm_vccs);
2000 kfree (dev->atm_vccs);
2001
2002 for (i=0;i< FS_NR_FREE_POOLS;i++)
2003 free_freepool (dev, &dev->rx_fp[i]);
2004
2005 for (i=0;i < FS_NR_RX_QUEUES;i++)
2006 free_queue (dev, &dev->rx_rq[i]);
2007
78e4be16 2008 iounmap(dev->base);
1da177e4
LT		 2009 fs_dprintk (FS_DEBUG_ALLOC, "Free fs-dev: %p\n", dev);
2010 nxtdev = dev->next;
2011 kfree (dev);
2012 }
2013
2014 func_exit ();
2015}
2016
0fdfb33b 2017static const struct pci_device_id firestream_pci_tbl[] = {
b16170c1
PH		 2018 { PCI_VDEVICE(FUJITSU_ME, PCI_DEVICE_ID_FUJITSU_FS50), FS_IS50},
2019 { PCI_VDEVICE(FUJITSU_ME, PCI_DEVICE_ID_FUJITSU_FS155), FS_IS155},
1da177e4
LT		 2020 { 0, }
2021};
2022
2023MODULE_DEVICE_TABLE(pci, firestream_pci_tbl);
2024
2025static struct pci_driver firestream_driver = {
2026 .name = "firestream",
2027 .id_table = firestream_pci_tbl,
2028 .probe = firestream_init_one,
6c44512d 2029 .remove = firestream_remove_one,
1da177e4
LT		 2030};
2031
2032static int __init firestream_init_module (void)
2033{
2034 int error;
2035
2036 func_enter ();
2037 error = pci_register_driver(&firestream_driver);
2038 func_exit ();
2039 return error;
2040}
2041
2042static void __exit firestream_cleanup_module(void)
2043{
2044 pci_unregister_driver(&firestream_driver);
2045}
2046
2047module_init(firestream_init_module);
2048module_exit(firestream_cleanup_module);
2049
2050MODULE_LICENSE("GPL");
2051
2052
2053
Linux 6.x block layer and io_uring tree(s)