[linux-2.6-block.git] / drivers / ata / sata_vsc.c

// SPDX-License-Identifier: GPL-2.0-or-later
/*
 *  sata_vsc.c - Vitesse VSC7174 4 port DPA SATA
 *
 *  Maintained by:  Jeremy Higdon @ SGI
 * 		    Please ALWAYS copy linux-ide@vger.kernel.org
 *		    on emails.
 *
 *  Copyright 2004 SGI
 *
 *  Bits from Jeff Garzik, Copyright RedHat, Inc.
 *
 *  libata documentation is available via 'make {ps|pdf}docs',
 *  as Documentation/driver-api/libata.rst
 *
 *  Vitesse hardware documentation presumably available under NDA.
 *  Intel 31244 (same hardware interface) documentation presumably
 *  available from http://developer.intel.com/
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/blkdev.h>
#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/dma-mapping.h>
#include <linux/device.h>
#include <scsi/scsi_host.h>
#include <linux/libata.h>

#define DRV_NAME	"sata_vsc"
#define DRV_VERSION	"2.3"

enum {
	VSC_MMIO_BAR			= 0,

	/* Interrupt register offsets (from chip base address) */
	VSC_SATA_INT_STAT_OFFSET	= 0x00,
	VSC_SATA_INT_MASK_OFFSET	= 0x04,

	/* Taskfile registers offsets */
	VSC_SATA_TF_CMD_OFFSET		= 0x00,
	VSC_SATA_TF_DATA_OFFSET		= 0x00,
	VSC_SATA_TF_ERROR_OFFSET	= 0x04,
	VSC_SATA_TF_FEATURE_OFFSET	= 0x06,
	VSC_SATA_TF_NSECT_OFFSET	= 0x08,
	VSC_SATA_TF_LBAL_OFFSET		= 0x0c,
	VSC_SATA_TF_LBAM_OFFSET		= 0x10,
	VSC_SATA_TF_LBAH_OFFSET		= 0x14,
	VSC_SATA_TF_DEVICE_OFFSET	= 0x18,
	VSC_SATA_TF_STATUS_OFFSET	= 0x1c,
	VSC_SATA_TF_COMMAND_OFFSET	= 0x1d,
	VSC_SATA_TF_ALTSTATUS_OFFSET	= 0x28,
	VSC_SATA_TF_CTL_OFFSET		= 0x29,

	/* DMA base */
	VSC_SATA_UP_DESCRIPTOR_OFFSET	= 0x64,
	VSC_SATA_UP_DATA_BUFFER_OFFSET	= 0x6C,
	VSC_SATA_DMA_CMD_OFFSET		= 0x70,

	/* SCRs base */
	VSC_SATA_SCR_STATUS_OFFSET	= 0x100,
	VSC_SATA_SCR_ERROR_OFFSET	= 0x104,
	VSC_SATA_SCR_CONTROL_OFFSET	= 0x108,

	/* Port stride */
	VSC_SATA_PORT_OFFSET		= 0x200,

	/* Error interrupt status bit offsets */
	VSC_SATA_INT_ERROR_CRC		= 0x40,
	VSC_SATA_INT_ERROR_T		= 0x20,
	VSC_SATA_INT_ERROR_P		= 0x10,
	VSC_SATA_INT_ERROR_R		= 0x8,
	VSC_SATA_INT_ERROR_E		= 0x4,
	VSC_SATA_INT_ERROR_M		= 0x2,
	VSC_SATA_INT_PHY_CHANGE		= 0x1,
	VSC_SATA_INT_ERROR = (VSC_SATA_INT_ERROR_CRC  | VSC_SATA_INT_ERROR_T | \
			      VSC_SATA_INT_ERROR_P    | VSC_SATA_INT_ERROR_R | \
			      VSC_SATA_INT_ERROR_E    | VSC_SATA_INT_ERROR_M | \
			      VSC_SATA_INT_PHY_CHANGE),
};

static int vsc_sata_scr_read(struct ata_link *link,
			     unsigned int sc_reg, u32 *val)
{
	if (sc_reg > SCR_CONTROL)
		return -EINVAL;
	*val = readl(link->ap->ioaddr.scr_addr + (sc_reg * 4));
	return 0;
}


static int vsc_sata_scr_write(struct ata_link *link,
			      unsigned int sc_reg, u32 val)
{
	if (sc_reg > SCR_CONTROL)
		return -EINVAL;
	writel(val, link->ap->ioaddr.scr_addr + (sc_reg * 4));
	return 0;
}


static void vsc_freeze(struct ata_port *ap)
{
	void __iomem *mask_addr;

	mask_addr = ap->host->iomap[VSC_MMIO_BAR] +
		VSC_SATA_INT_MASK_OFFSET + ap->port_no;

	writeb(0, mask_addr);
}


static void vsc_thaw(struct ata_port *ap)
{
	void __iomem *mask_addr;

	mask_addr = ap->host->iomap[VSC_MMIO_BAR] +
		VSC_SATA_INT_MASK_OFFSET + ap->port_no;

	writeb(0xff, mask_addr);
}


static void vsc_intr_mask_update(struct ata_port *ap, u8 ctl)
{
	void __iomem *mask_addr;
	u8 mask;

	mask_addr = ap->host->iomap[VSC_MMIO_BAR] +
		VSC_SATA_INT_MASK_OFFSET + ap->port_no;
	mask = readb(mask_addr);
	if (ctl & ATA_NIEN)
		mask |= 0x80;
	else
		mask &= 0x7F;
	writeb(mask, mask_addr);
}


static void vsc_sata_tf_load(struct ata_port *ap, const struct ata_taskfile *tf)
{
	struct ata_ioports *ioaddr = &ap->ioaddr;
	unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR;

	/*
	 * The only thing the ctl register is used for is SRST.
	 * That is not enabled or disabled via tf_load.
	 * However, if ATA_NIEN is changed, then we need to change
	 * the interrupt register.
	 */
	if ((tf->ctl & ATA_NIEN) != (ap->last_ctl & ATA_NIEN)) {
		ap->last_ctl = tf->ctl;
		vsc_intr_mask_update(ap, tf->ctl & ATA_NIEN);
	}
	if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) {
		writew(tf->feature | (((u16)tf->hob_feature) << 8),
		       ioaddr->feature_addr);
		writew(tf->nsect | (((u16)tf->hob_nsect) << 8),
		       ioaddr->nsect_addr);
		writew(tf->lbal | (((u16)tf->hob_lbal) << 8),
		       ioaddr->lbal_addr);
		writew(tf->lbam | (((u16)tf->hob_lbam) << 8),
		       ioaddr->lbam_addr);
		writew(tf->lbah | (((u16)tf->hob_lbah) << 8),
		       ioaddr->lbah_addr);
	} else if (is_addr) {
		writew(tf->feature, ioaddr->feature_addr);
		writew(tf->nsect, ioaddr->nsect_addr);
		writew(tf->lbal, ioaddr->lbal_addr);
		writew(tf->lbam, ioaddr->lbam_addr);
		writew(tf->lbah, ioaddr->lbah_addr);
	}

	if (tf->flags & ATA_TFLAG_DEVICE)
		writeb(tf->device, ioaddr->device_addr);

	ata_wait_idle(ap);
}


static void vsc_sata_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
{
	struct ata_ioports *ioaddr = &ap->ioaddr;
	u16 nsect, lbal, lbam, lbah, error;

	tf->status = ata_sff_check_status(ap);
	tf->device = readw(ioaddr->device_addr);
	error = readw(ioaddr->error_addr);
	nsect = readw(ioaddr->nsect_addr);
	lbal = readw(ioaddr->lbal_addr);
	lbam = readw(ioaddr->lbam_addr);
	lbah = readw(ioaddr->lbah_addr);

	tf->error = error;
	tf->nsect = nsect;
	tf->lbal = lbal;
	tf->lbam = lbam;
	tf->lbah = lbah;

	if (tf->flags & ATA_TFLAG_LBA48) {
		tf->hob_feature = error >> 8;
		tf->hob_nsect = nsect >> 8;
		tf->hob_lbal = lbal >> 8;
		tf->hob_lbam = lbam >> 8;
		tf->hob_lbah = lbah >> 8;
	}
}

static inline void vsc_error_intr(u8 port_status, struct ata_port *ap)
{
	if (port_status & (VSC_SATA_INT_PHY_CHANGE | VSC_SATA_INT_ERROR_M))
		ata_port_freeze(ap);
	else
		ata_port_abort(ap);
}

static void vsc_port_intr(u8 port_status, struct ata_port *ap)
{
	struct ata_queued_cmd *qc;
	int handled = 0;

	if (unlikely(port_status & VSC_SATA_INT_ERROR)) {
		vsc_error_intr(port_status, ap);
		return;
	}

	qc = ata_qc_from_tag(ap, ap->link.active_tag);
	if (qc && likely(!(qc->tf.flags & ATA_TFLAG_POLLING)))
		handled = ata_bmdma_port_intr(ap, qc);

	/* We received an interrupt during a polled command,
	 * or some other spurious condition.  Interrupt reporting
	 * with this hardware is fairly reliable so it is safe to
	 * simply clear the interrupt
	 */
	if (unlikely(!handled))
		ap->ops->sff_check_status(ap);
}

/*
 * vsc_sata_interrupt
 *
 * Read the interrupt register and process for the devices that have
 * them pending.
 */
static irqreturn_t vsc_sata_interrupt(int irq, void *dev_instance)
{
	struct ata_host *host = dev_instance;
	unsigned int i;
	unsigned int handled = 0;
	u32 status;

	status = readl(host->iomap[VSC_MMIO_BAR] + VSC_SATA_INT_STAT_OFFSET);

	if (unlikely(status == 0xffffffff || status == 0)) {
		if (status)
			dev_err(host->dev,
				": IRQ status == 0xffffffff, PCI fault or device removal?\n");
		goto out;
	}

	spin_lock(&host->lock);

	for (i = 0; i < host->n_ports; i++) {
		u8 port_status = (status >> (8 * i)) & 0xff;
		if (port_status) {
			vsc_port_intr(port_status, host->ports[i]);
			handled++;
		}
	}

	spin_unlock(&host->lock);
out:
	return IRQ_RETVAL(handled);
}


static const struct scsi_host_template vsc_sata_sht = {
	ATA_BMDMA_SHT(DRV_NAME),
};


static struct ata_port_operations vsc_sata_ops = {
	.inherits		= &ata_bmdma_port_ops,
	/* The IRQ handling is not quite standard SFF behaviour so we
	   cannot use the default lost interrupt handler */
	.lost_interrupt		= ATA_OP_NULL,
	.sff_tf_load		= vsc_sata_tf_load,
	.sff_tf_read		= vsc_sata_tf_read,
	.freeze			= vsc_freeze,
	.thaw			= vsc_thaw,
	.scr_read		= vsc_sata_scr_read,
	.scr_write		= vsc_sata_scr_write,
};

static void vsc_sata_setup_port(struct ata_ioports *port, void __iomem *base)
{
	port->cmd_addr		= base + VSC_SATA_TF_CMD_OFFSET;
	port->data_addr		= base + VSC_SATA_TF_DATA_OFFSET;
	port->error_addr	= base + VSC_SATA_TF_ERROR_OFFSET;
	port->feature_addr	= base + VSC_SATA_TF_FEATURE_OFFSET;
	port->nsect_addr	= base + VSC_SATA_TF_NSECT_OFFSET;
	port->lbal_addr		= base + VSC_SATA_TF_LBAL_OFFSET;
	port->lbam_addr		= base + VSC_SATA_TF_LBAM_OFFSET;
	port->lbah_addr		= base + VSC_SATA_TF_LBAH_OFFSET;
	port->device_addr	= base + VSC_SATA_TF_DEVICE_OFFSET;
	port->status_addr	= base + VSC_SATA_TF_STATUS_OFFSET;
	port->command_addr	= base + VSC_SATA_TF_COMMAND_OFFSET;
	port->altstatus_addr	= base + VSC_SATA_TF_ALTSTATUS_OFFSET;
	port->ctl_addr		= base + VSC_SATA_TF_CTL_OFFSET;
	port->bmdma_addr	= base + VSC_SATA_DMA_CMD_OFFSET;
	port->scr_addr		= base + VSC_SATA_SCR_STATUS_OFFSET;
	writel(0, base + VSC_SATA_UP_DESCRIPTOR_OFFSET);
	writel(0, base + VSC_SATA_UP_DATA_BUFFER_OFFSET);
}


static int vsc_sata_init_one(struct pci_dev *pdev,
			     const struct pci_device_id *ent)
{
	static const struct ata_port_info pi = {
		.flags		= ATA_FLAG_SATA,
		.pio_mask	= ATA_PIO4,
		.mwdma_mask	= ATA_MWDMA2,
		.udma_mask	= ATA_UDMA6,
		.port_ops	= &vsc_sata_ops,
	};
	const struct ata_port_info *ppi[] = { &pi, NULL };
	struct ata_host *host;
	void __iomem *mmio_base;
	int i, rc;
	u8 cls;

	ata_print_version_once(&pdev->dev, DRV_VERSION);

	/* allocate host */
	host = ata_host_alloc_pinfo(&pdev->dev, ppi, 4);
	if (!host)
		return -ENOMEM;

	rc = pcim_enable_device(pdev);
	if (rc)
		return rc;

	/* check if we have needed resource mapped */
	if (pci_resource_len(pdev, 0) == 0)
		return -ENODEV;

	/* map IO regions and initialize host accordingly */
	rc = pcim_iomap_regions(pdev, 1 << VSC_MMIO_BAR, DRV_NAME);
	if (rc == -EBUSY)
		pcim_pin_device(pdev);
	if (rc)
		return rc;
	host->iomap = pcim_iomap_table(pdev);

	mmio_base = host->iomap[VSC_MMIO_BAR];

	for (i = 0; i < host->n_ports; i++) {
		struct ata_port *ap = host->ports[i];
		unsigned int offset = (i + 1) * VSC_SATA_PORT_OFFSET;

		vsc_sata_setup_port(&ap->ioaddr, mmio_base + offset);

		ata_port_pbar_desc(ap, VSC_MMIO_BAR, -1, "mmio");
		ata_port_pbar_desc(ap, VSC_MMIO_BAR, offset, "port");
	}

	/*
	 * Use 32 bit DMA mask, because 64 bit address support is poor.
	 */
	rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
	if (rc)
		return rc;

	/*
	 * Due to a bug in the chip, the default cache line size can't be
	 * used (unless the default is non-zero).
	 */
	pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &cls);
	if (cls == 0x00)
		pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x80);

	if (pci_enable_msi(pdev) == 0)
		pci_intx(pdev, 0);

	/*
	 * Config offset 0x98 is "Extended Control and Status Register 0"
	 * Default value is (1 << 28).  All bits except bit 28 are reserved in
	 * DPA mode.  If bit 28 is set, LED 0 reflects all ports' activity.
	 * If bit 28 is clear, each port has its own LED.
	 */
	pci_write_config_dword(pdev, 0x98, 0);

	pci_set_master(pdev);
	return ata_host_activate(host, pdev->irq, vsc_sata_interrupt,
				 IRQF_SHARED, &vsc_sata_sht);
}

static const struct pci_device_id vsc_sata_pci_tbl[] = {
	{ PCI_VENDOR_ID_VITESSE, 0x7174,
	  PCI_ANY_ID, PCI_ANY_ID, 0x10600, 0xFFFFFF, 0 },
	{ PCI_VENDOR_ID_INTEL, 0x3200,
	  PCI_ANY_ID, PCI_ANY_ID, 0x10600, 0xFFFFFF, 0 },

	{ }	/* terminate list */
};

static struct pci_driver vsc_sata_pci_driver = {
	.name			= DRV_NAME,
	.id_table		= vsc_sata_pci_tbl,
	.probe			= vsc_sata_init_one,
	.remove			= ata_pci_remove_one,
};

module_pci_driver(vsc_sata_pci_driver);

MODULE_AUTHOR("Jeremy Higdon");
MODULE_DESCRIPTION("low-level driver for Vitesse VSC7174 SATA controller");
MODULE_LICENSE("GPL");
MODULE_DEVICE_TABLE(pci, vsc_sata_pci_tbl);
MODULE_VERSION(DRV_VERSION);
Commit	Line	Data
c82ee6d3	1	// SPDX-License-Identifier: GPL-2.0-or-later
1da177e4 LT	2	/*
	3	* sata_vsc.c - Vitesse VSC7174 4 port DPA SATA
	4	*
	5	* Maintained by: Jeremy Higdon @ SGI
	6	* Please ALWAYS copy linux-ide@vger.kernel.org
	7	* on emails.
	8	*
	9	* Copyright 2004 SGI
	10	*
	11	* Bits from Jeff Garzik, Copyright RedHat, Inc.
	12	*
af36d7f0	13	* libata documentation is available via 'make {ps\|pdf}docs',
19285f3c	14	* as Documentation/driver-api/libata.rst
af36d7f0 JG	15	*
	16	* Vitesse hardware documentation presumably available under NDA.
	17	* Intel 31244 (same hardware interface) documentation presumably
	18	* available from http://developer.intel.com/
1da177e4 LT	19	*/
	20
	21	#include <linux/kernel.h>
	22	#include <linux/module.h>
	23	#include <linux/pci.h>
1da177e4 LT	24	#include <linux/blkdev.h>
	25	#include <linux/delay.h>
	26	#include <linux/interrupt.h>
7003c05d	27	#include <linux/dma-mapping.h>
a9524a76	28	#include <linux/device.h>
1da177e4 LT	29	#include <scsi/scsi_host.h>
	30	#include <linux/libata.h>
	31
	32	#define DRV_NAME "sata_vsc"
2a3103ce	33	#define DRV_VERSION "2.3"
1da177e4	34
55cca65e	35	enum {
0d5ff566 TH	36	VSC_MMIO_BAR = 0,
0d5ff566 TH	37
55cca65e JG	38	/* Interrupt register offsets (from chip base address) */
	39	VSC_SATA_INT_STAT_OFFSET = 0x00,
	40	VSC_SATA_INT_MASK_OFFSET = 0x04,
1da177e4	41
55cca65e JG	42	/* Taskfile registers offsets */
	43	VSC_SATA_TF_CMD_OFFSET = 0x00,
	44	VSC_SATA_TF_DATA_OFFSET = 0x00,
	45	VSC_SATA_TF_ERROR_OFFSET = 0x04,
	46	VSC_SATA_TF_FEATURE_OFFSET = 0x06,
	47	VSC_SATA_TF_NSECT_OFFSET = 0x08,
	48	VSC_SATA_TF_LBAL_OFFSET = 0x0c,
	49	VSC_SATA_TF_LBAM_OFFSET = 0x10,
	50	VSC_SATA_TF_LBAH_OFFSET = 0x14,
	51	VSC_SATA_TF_DEVICE_OFFSET = 0x18,
	52	VSC_SATA_TF_STATUS_OFFSET = 0x1c,
	53	VSC_SATA_TF_COMMAND_OFFSET = 0x1d,
	54	VSC_SATA_TF_ALTSTATUS_OFFSET = 0x28,
	55	VSC_SATA_TF_CTL_OFFSET = 0x29,
1da177e4	56
55cca65e JG	57	/* DMA base */
	58	VSC_SATA_UP_DESCRIPTOR_OFFSET = 0x64,
	59	VSC_SATA_UP_DATA_BUFFER_OFFSET = 0x6C,
	60	VSC_SATA_DMA_CMD_OFFSET = 0x70,
1da177e4	61
55cca65e JG	62	/* SCRs base */
	63	VSC_SATA_SCR_STATUS_OFFSET = 0x100,
	64	VSC_SATA_SCR_ERROR_OFFSET = 0x104,
	65	VSC_SATA_SCR_CONTROL_OFFSET = 0x108,
1da177e4	66
55cca65e JG	67	/* Port stride */
	68	VSC_SATA_PORT_OFFSET = 0x200,
	69
	70	/* Error interrupt status bit offsets */
	71	VSC_SATA_INT_ERROR_CRC = 0x40,
	72	VSC_SATA_INT_ERROR_T = 0x20,
	73	VSC_SATA_INT_ERROR_P = 0x10,
	74	VSC_SATA_INT_ERROR_R = 0x8,
	75	VSC_SATA_INT_ERROR_E = 0x4,
	76	VSC_SATA_INT_ERROR_M = 0x2,
	77	VSC_SATA_INT_PHY_CHANGE = 0x1,
	78	VSC_SATA_INT_ERROR = (VSC_SATA_INT_ERROR_CRC \| VSC_SATA_INT_ERROR_T \| \
	79	VSC_SATA_INT_ERROR_P \| VSC_SATA_INT_ERROR_R \| \
	80	VSC_SATA_INT_ERROR_E \| VSC_SATA_INT_ERROR_M \| \
	81	VSC_SATA_INT_PHY_CHANGE),
7cbaa86b	82	};
c962990a	83
82ef04fb TH	84	static int vsc_sata_scr_read(struct ata_link *link,
82ef04fb TH	85	unsigned int sc_reg, u32 *val)
1da177e4 LT	86	{
1da177e4 LT	87	if (sc_reg > SCR_CONTROL)
da3dbb17	88	return -EINVAL;
82ef04fb	89	val = readl(link->ap->ioaddr.scr_addr + (sc_reg 4));
da3dbb17	90	return 0;
1da177e4 LT	91	}
	92
	93
82ef04fb TH	94	static int vsc_sata_scr_write(struct ata_link *link,
82ef04fb TH	95	unsigned int sc_reg, u32 val)
1da177e4 LT	96	{
1da177e4 LT	97	if (sc_reg > SCR_CONTROL)
da3dbb17	98	return -EINVAL;
82ef04fb	99	writel(val, link->ap->ioaddr.scr_addr + (sc_reg * 4));
da3dbb17	100	return 0;
1da177e4 LT	101	}
	102
	103
ea34e45a DW	104	static void vsc_freeze(struct ata_port *ap)
	105	{
	106	void __iomem *mask_addr;
	107
	108	mask_addr = ap->host->iomap[VSC_MMIO_BAR] +
	109	VSC_SATA_INT_MASK_OFFSET + ap->port_no;
	110
	111	writeb(0, mask_addr);
	112	}
	113
	114
	115	static void vsc_thaw(struct ata_port *ap)
	116	{
	117	void __iomem *mask_addr;
	118
	119	mask_addr = ap->host->iomap[VSC_MMIO_BAR] +
	120	VSC_SATA_INT_MASK_OFFSET + ap->port_no;
	121
	122	writeb(0xff, mask_addr);
	123	}
	124
	125
1da177e4 LT	126	static void vsc_intr_mask_update(struct ata_port *ap, u8 ctl)
1da177e4 LT	127	{
307e4dc2	128	void __iomem *mask_addr;
1da177e4 LT	129	u8 mask;
1da177e4 LT	130
0d5ff566	131	mask_addr = ap->host->iomap[VSC_MMIO_BAR] +
1da177e4 LT	132	VSC_SATA_INT_MASK_OFFSET + ap->port_no;
	133	mask = readb(mask_addr);
	134	if (ctl & ATA_NIEN)
	135	mask \|= 0x80;
	136	else
	137	mask &= 0x7F;
	138	writeb(mask, mask_addr);
	139	}
	140
	141
057ace5e	142	static void vsc_sata_tf_load(struct ata_port ap, const struct ata_taskfile tf)
1da177e4 LT	143	{
	144	struct ata_ioports *ioaddr = &ap->ioaddr;
	145	unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR;
	146
	147	/*
	148	* The only thing the ctl register is used for is SRST.
	149	* That is not enabled or disabled via tf_load.
5796d1c4 JG	150	* However, if ATA_NIEN is changed, then we need to change
5796d1c4 JG	151	* the interrupt register.
1da177e4 LT	152	*/
	153	if ((tf->ctl & ATA_NIEN) != (ap->last_ctl & ATA_NIEN)) {
	154	ap->last_ctl = tf->ctl;
	155	vsc_intr_mask_update(ap, tf->ctl & ATA_NIEN);
	156	}
	157	if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) {
850a9d8a	158	writew(tf->feature \| (((u16)tf->hob_feature) << 8),
0d5ff566	159	ioaddr->feature_addr);
850a9d8a	160	writew(tf->nsect \| (((u16)tf->hob_nsect) << 8),
0d5ff566	161	ioaddr->nsect_addr);
850a9d8a	162	writew(tf->lbal \| (((u16)tf->hob_lbal) << 8),
0d5ff566	163	ioaddr->lbal_addr);
850a9d8a	164	writew(tf->lbam \| (((u16)tf->hob_lbam) << 8),
0d5ff566	165	ioaddr->lbam_addr);
850a9d8a	166	writew(tf->lbah \| (((u16)tf->hob_lbah) << 8),
0d5ff566	167	ioaddr->lbah_addr);
1da177e4	168	} else if (is_addr) {
0d5ff566 TH	169	writew(tf->feature, ioaddr->feature_addr);
	170	writew(tf->nsect, ioaddr->nsect_addr);
	171	writew(tf->lbal, ioaddr->lbal_addr);
	172	writew(tf->lbam, ioaddr->lbam_addr);
	173	writew(tf->lbah, ioaddr->lbah_addr);
1da177e4 LT	174	}
	175
	176	if (tf->flags & ATA_TFLAG_DEVICE)
0d5ff566	177	writeb(tf->device, ioaddr->device_addr);
1da177e4 LT	178
	179	ata_wait_idle(ap);
	180	}
	181
	182
	183	static void vsc_sata_tf_read(struct ata_port ap, struct ata_taskfile tf)
	184	{
	185	struct ata_ioports *ioaddr = &ap->ioaddr;
efcef265	186	u16 nsect, lbal, lbam, lbah, error;
1da177e4	187
efcef265	188	tf->status = ata_sff_check_status(ap);
0d5ff566	189	tf->device = readw(ioaddr->device_addr);
efcef265	190	error = readw(ioaddr->error_addr);
0d5ff566 TH	191	nsect = readw(ioaddr->nsect_addr);
	192	lbal = readw(ioaddr->lbal_addr);
	193	lbam = readw(ioaddr->lbam_addr);
	194	lbah = readw(ioaddr->lbah_addr);
ac19bff2	195
efcef265	196	tf->error = error;
ac19bff2 JG	197	tf->nsect = nsect;
	198	tf->lbal = lbal;
	199	tf->lbam = lbam;
	200	tf->lbah = lbah;
1da177e4 LT	201
1da177e4 LT	202	if (tf->flags & ATA_TFLAG_LBA48) {
efcef265	203	tf->hob_feature = error >> 8;
1da177e4 LT	204	tf->hob_nsect = nsect >> 8;
	205	tf->hob_lbal = lbal >> 8;
	206	tf->hob_lbam = lbam >> 8;
	207	tf->hob_lbah = lbah >> 8;
5796d1c4	208	}
1da177e4 LT	209	}
1da177e4 LT	210
ea34e45a DW	211	static inline void vsc_error_intr(u8 port_status, struct ata_port *ap)
	212	{
	213	if (port_status & (VSC_SATA_INT_PHY_CHANGE \| VSC_SATA_INT_ERROR_M))
	214	ata_port_freeze(ap);
	215	else
	216	ata_port_abort(ap);
	217	}
	218
	219	static void vsc_port_intr(u8 port_status, struct ata_port *ap)
	220	{
	221	struct ata_queued_cmd *qc;
	222	int handled = 0;
	223
	224	if (unlikely(port_status & VSC_SATA_INT_ERROR)) {
	225	vsc_error_intr(port_status, ap);
	226	return;
	227	}
	228
9af5c9c9	229	qc = ata_qc_from_tag(ap, ap->link.active_tag);
ea34e45a	230	if (qc && likely(!(qc->tf.flags & ATA_TFLAG_POLLING)))
c3b28894	231	handled = ata_bmdma_port_intr(ap, qc);
ea34e45a DW	232
	233	/* We received an interrupt during a polled command,
	234	* or some other spurious condition. Interrupt reporting
	235	* with this hardware is fairly reliable so it is safe to
	236	* simply clear the interrupt
	237	*/
	238	if (unlikely(!handled))
5682ed33	239	ap->ops->sff_check_status(ap);
ea34e45a	240	}
1da177e4 LT	241
	242	/*
	243	* vsc_sata_interrupt
	244	*
5796d1c4 JG	245	* Read the interrupt register and process for the devices that have
5796d1c4 JG	246	* them pending.
1da177e4	247	*/
5796d1c4	248	static irqreturn_t vsc_sata_interrupt(int irq, void *dev_instance)
1da177e4	249	{
cca3974e	250	struct ata_host *host = dev_instance;
1da177e4 LT	251	unsigned int i;
1da177e4 LT	252	unsigned int handled = 0;
ea34e45a	253	u32 status;
1da177e4	254
ea34e45a	255	status = readl(host->iomap[VSC_MMIO_BAR] + VSC_SATA_INT_STAT_OFFSET);
1da177e4	256
ea34e45a DW	257	if (unlikely(status == 0xffffffff \|\| status == 0)) {
ea34e45a DW	258	if (status)
a44fec1f JP	259	dev_err(host->dev,
a44fec1f JP	260	": IRQ status == 0xffffffff, PCI fault or device removal?\n");
ea34e45a DW	261	goto out;
ea34e45a DW	262	}
1da177e4	263
ea34e45a	264	spin_lock(&host->lock);
2ae5b30f	265
ea34e45a DW	266	for (i = 0; i < host->n_ports; i++) {
	267	u8 port_status = (status >> (8 * i)) & 0xff;
	268	if (port_status) {
3e4ec344 TH	269	vsc_port_intr(port_status, host->ports[i]);
3e4ec344 TH	270	handled++;
1da177e4 LT	271	}
	272	}
	273
cca3974e	274	spin_unlock(&host->lock);
ea34e45a	275	out:
1da177e4 LT	276	return IRQ_RETVAL(handled);
	277	}
	278
	279
25df73d9	280	static const struct scsi_host_template vsc_sata_sht = {
68d1d07b	281	ATA_BMDMA_SHT(DRV_NAME),
1da177e4 LT	282	};
	283
	284
029cfd6b TH	285	static struct ata_port_operations vsc_sata_ops = {
029cfd6b TH	286	.inherits = &ata_bmdma_port_ops,
c96f1732 AC	287	/* The IRQ handling is not quite standard SFF behaviour so we
	288	cannot use the default lost interrupt handler */
	289	.lost_interrupt = ATA_OP_NULL,
5682ed33 TH	290	.sff_tf_load = vsc_sata_tf_load,
5682ed33 TH	291	.sff_tf_read = vsc_sata_tf_read,
ea34e45a DW	292	.freeze = vsc_freeze,
ea34e45a DW	293	.thaw = vsc_thaw,
1da177e4 LT	294	.scr_read = vsc_sata_scr_read,
1da177e4 LT	295	.scr_write = vsc_sata_scr_write,
1da177e4 LT	296	};
1da177e4 LT	297
0ec24914	298	static void vsc_sata_setup_port(struct ata_ioports port, void __iomem base)
1da177e4 LT	299	{
	300	port->cmd_addr = base + VSC_SATA_TF_CMD_OFFSET;
	301	port->data_addr = base + VSC_SATA_TF_DATA_OFFSET;
	302	port->error_addr = base + VSC_SATA_TF_ERROR_OFFSET;
	303	port->feature_addr = base + VSC_SATA_TF_FEATURE_OFFSET;
	304	port->nsect_addr = base + VSC_SATA_TF_NSECT_OFFSET;
	305	port->lbal_addr = base + VSC_SATA_TF_LBAL_OFFSET;
	306	port->lbam_addr = base + VSC_SATA_TF_LBAM_OFFSET;
	307	port->lbah_addr = base + VSC_SATA_TF_LBAH_OFFSET;
	308	port->device_addr = base + VSC_SATA_TF_DEVICE_OFFSET;
	309	port->status_addr = base + VSC_SATA_TF_STATUS_OFFSET;
	310	port->command_addr = base + VSC_SATA_TF_COMMAND_OFFSET;
	311	port->altstatus_addr = base + VSC_SATA_TF_ALTSTATUS_OFFSET;
	312	port->ctl_addr = base + VSC_SATA_TF_CTL_OFFSET;
	313	port->bmdma_addr = base + VSC_SATA_DMA_CMD_OFFSET;
	314	port->scr_addr = base + VSC_SATA_SCR_STATUS_OFFSET;
0d5ff566 TH	315	writel(0, base + VSC_SATA_UP_DESCRIPTOR_OFFSET);
0d5ff566 TH	316	writel(0, base + VSC_SATA_UP_DATA_BUFFER_OFFSET);
1da177e4 LT	317	}
	318
	319
0ec24914 GKH	320	static int vsc_sata_init_one(struct pci_dev *pdev,
0ec24914 GKH	321	const struct pci_device_id *ent)
1da177e4	322	{
4447d351	323	static const struct ata_port_info pi = {
9cbe056f	324	.flags = ATA_FLAG_SATA,
14bdef98 EIB	325	.pio_mask = ATA_PIO4,
14bdef98 EIB	326	.mwdma_mask = ATA_MWDMA2,
bf6263a8	327	.udma_mask = ATA_UDMA6,
4447d351 TH	328	.port_ops = &vsc_sata_ops,
	329	};
	330	const struct ata_port_info *ppi[] = { &pi, NULL };
4447d351	331	struct ata_host *host;
307e4dc2	332	void __iomem *mmio_base;
4447d351	333	int i, rc;
7de970e1	334	u8 cls;
1da177e4	335
06296a1e	336	ata_print_version_once(&pdev->dev, DRV_VERSION);
1da177e4	337
4447d351 TH	338	/* allocate host */
	339	host = ata_host_alloc_pinfo(&pdev->dev, ppi, 4);
	340	if (!host)
	341	return -ENOMEM;
	342
24dc5f33	343	rc = pcim_enable_device(pdev);
1da177e4 LT	344	if (rc)
	345	return rc;
	346
4447d351	347	/* check if we have needed resource mapped */
24dc5f33 TH	348	if (pci_resource_len(pdev, 0) == 0)
24dc5f33 TH	349	return -ENODEV;
1da177e4	350
b595076a	351	/* map IO regions and initialize host accordingly */
0d5ff566 TH	352	rc = pcim_iomap_regions(pdev, 1 << VSC_MMIO_BAR, DRV_NAME);
0d5ff566 TH	353	if (rc == -EBUSY)
24dc5f33	354	pcim_pin_device(pdev);
0d5ff566	355	if (rc)
24dc5f33	356	return rc;
4447d351 TH	357	host->iomap = pcim_iomap_table(pdev);
	358
	359	mmio_base = host->iomap[VSC_MMIO_BAR];
	360
cbcdd875 TH	361	for (i = 0; i < host->n_ports; i++) {
	362	struct ata_port *ap = host->ports[i];
	363	unsigned int offset = (i + 1) * VSC_SATA_PORT_OFFSET;
	364
	365	vsc_sata_setup_port(&ap->ioaddr, mmio_base + offset);
	366
	367	ata_port_pbar_desc(ap, VSC_MMIO_BAR, -1, "mmio");
	368	ata_port_pbar_desc(ap, VSC_MMIO_BAR, offset, "port");
	369	}
1da177e4 LT	370
	371	/*
	372	* Use 32 bit DMA mask, because 64 bit address support is poor.
	373	*/
b5e55556	374	rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(32));
1da177e4	375	if (rc)
24dc5f33	376	return rc;
7cbaa86b	377
1da177e4	378	/*
7de970e1 ND	379	* Due to a bug in the chip, the default cache line size can't be
7de970e1 ND	380	* used (unless the default is non-zero).
1da177e4	381	*/
7de970e1 ND	382	pci_read_config_byte(pdev, PCI_CACHE_LINE_SIZE, &cls);
	383	if (cls == 0x00)
	384	pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE, 0x80);
1da177e4	385
24dc5f33	386	if (pci_enable_msi(pdev) == 0)
7cbaa86b	387	pci_intx(pdev, 0);
1da177e4	388
8a60a071	389	/*
1da177e4 LT	390	* Config offset 0x98 is "Extended Control and Status Register 0"
	391	* Default value is (1 << 28). All bits except bit 28 are reserved in
	392	* DPA mode. If bit 28 is set, LED 0 reflects all ports' activity.
	393	* If bit 28 is clear, each port has its own LED.
	394	*/
	395	pci_write_config_dword(pdev, 0x98, 0);
	396
4447d351 TH	397	pci_set_master(pdev);
	398	return ata_host_activate(host, pdev->irq, vsc_sata_interrupt,
	399	IRQF_SHARED, &vsc_sata_sht);
1da177e4 LT	400	}
1da177e4 LT	401
3b7d697d	402	static const struct pci_device_id vsc_sata_pci_tbl[] = {
438bc9c3	403	{ PCI_VENDOR_ID_VITESSE, 0x7174,
74d0a988	404	PCI_ANY_ID, PCI_ANY_ID, 0x10600, 0xFFFFFF, 0 },
438bc9c3	405	{ PCI_VENDOR_ID_INTEL, 0x3200,
74d0a988	406	PCI_ANY_ID, PCI_ANY_ID, 0x10600, 0xFFFFFF, 0 },
2d2744fc	407
438bc9c3	408	{ } /* terminate list */
1da177e4 LT	409	};
1da177e4 LT	410
1da177e4 LT	411	static struct pci_driver vsc_sata_pci_driver = {
	412	.name = DRV_NAME,
	413	.id_table = vsc_sata_pci_tbl,
	414	.probe = vsc_sata_init_one,
	415	.remove = ata_pci_remove_one,
	416	};
	417
2fc75da0	418	module_pci_driver(vsc_sata_pci_driver);
1da177e4	419
1da177e4 LT	420	MODULE_AUTHOR("Jeremy Higdon");
	421	MODULE_DESCRIPTION("low-level driver for Vitesse VSC7174 SATA controller");
	422	MODULE_LICENSE("GPL");
	423	MODULE_DEVICE_TABLE(pci, vsc_sata_pci_tbl);
	424	MODULE_VERSION(DRV_VERSION);