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c82ee6d3 | 1 | // SPDX-License-Identifier: GPL-2.0-or-later |
1da177e4 | 2 | /* |
af36d7f0 JG |
3 | * sata_via.c - VIA Serial ATA controllers |
4 | * | |
8c3d3d4b | 5 | * Maintained by: Tejun Heo <tj@kernel.org> |
af36d7f0 | 6 | * Please ALWAYS copy linux-ide@vger.kernel.org |
5796d1c4 | 7 | * on emails. |
af36d7f0 JG |
8 | * |
9 | * Copyright 2003-2004 Red Hat, Inc. All rights reserved. | |
10 | * Copyright 2003-2004 Jeff Garzik | |
11 | * | |
af36d7f0 | 12 | * libata documentation is available via 'make {ps|pdf}docs', |
9bb9a39c | 13 | * as Documentation/driver-api/libata.rst |
af36d7f0 JG |
14 | * |
15 | * Hardware documentation available under NDA. | |
1da177e4 LT |
16 | */ |
17 | ||
18 | #include <linux/kernel.h> | |
19 | #include <linux/module.h> | |
20 | #include <linux/pci.h> | |
1da177e4 LT |
21 | #include <linux/blkdev.h> |
22 | #include <linux/delay.h> | |
a9524a76 | 23 | #include <linux/device.h> |
a55ab496 BH |
24 | #include <scsi/scsi.h> |
25 | #include <scsi/scsi_cmnd.h> | |
1da177e4 LT |
26 | #include <scsi/scsi_host.h> |
27 | #include <linux/libata.h> | |
1da177e4 LT |
28 | |
29 | #define DRV_NAME "sata_via" | |
a55ab496 | 30 | #define DRV_VERSION "2.6" |
1da177e4 | 31 | |
b9d5b89b TH |
32 | /* |
33 | * vt8251 is different from other sata controllers of VIA. It has two | |
34 | * channels, each channel has both Master and Slave slot. | |
35 | */ | |
1da177e4 LT |
36 | enum board_ids_enum { |
37 | vt6420, | |
38 | vt6421, | |
b9d5b89b | 39 | vt8251, |
1da177e4 LT |
40 | }; |
41 | ||
42 | enum { | |
43 | SATA_CHAN_ENAB = 0x40, /* SATA channel enable */ | |
44 | SATA_INT_GATE = 0x41, /* SATA interrupt gating */ | |
45 | SATA_NATIVE_MODE = 0x42, /* Native mode enable */ | |
57e5568f | 46 | SVIA_MISC_3 = 0x46, /* Miscellaneous Control III */ |
d73f30e1 A |
47 | PATA_UDMA_TIMING = 0xB3, /* PATA timing for DMA/ cable detect */ |
48 | PATA_PIO_TIMING = 0xAB, /* PATA timing register */ | |
a84471fe | 49 | |
1da177e4 LT |
50 | PORT0 = (1 << 1), |
51 | PORT1 = (1 << 0), | |
52 | ALL_PORTS = PORT0 | PORT1, | |
1da177e4 LT |
53 | |
54 | NATIVE_MODE_ALL = (1 << 7) | (1 << 6) | (1 << 5) | (1 << 4), | |
55 | ||
56 | SATA_EXT_PHY = (1 << 6), /* 0==use PATA, 1==ext phy */ | |
57e5568f OZ |
57 | |
58 | SATA_HOTPLUG = (1 << 5), /* enable IRQ on hotplug */ | |
1da177e4 LT |
59 | }; |
60 | ||
44a9b494 OZ |
61 | struct svia_priv { |
62 | bool wd_workaround; | |
63 | }; | |
64 | ||
98633258 OZ |
65 | static int vt6420_hotplug; |
66 | module_param_named(vt6420_hotplug, vt6420_hotplug, int, 0644); | |
67 | MODULE_PARM_DESC(vt6420_hotplug, "Enable hot-plug support for VT6420 (0=Don't support, 1=support)"); | |
68 | ||
5796d1c4 | 69 | static int svia_init_one(struct pci_dev *pdev, const struct pci_device_id *ent); |
44a9b494 OZ |
70 | #ifdef CONFIG_PM_SLEEP |
71 | static int svia_pci_device_resume(struct pci_dev *pdev); | |
72 | #endif | |
82ef04fb TH |
73 | static int svia_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val); |
74 | static int svia_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val); | |
b9d5b89b TH |
75 | static int vt8251_scr_read(struct ata_link *link, unsigned int scr, u32 *val); |
76 | static int vt8251_scr_write(struct ata_link *link, unsigned int scr, u32 val); | |
b78152e9 | 77 | static void svia_tf_load(struct ata_port *ap, const struct ata_taskfile *tf); |
17234246 | 78 | static void svia_noop_freeze(struct ata_port *ap); |
a1efdaba | 79 | static int vt6420_prereset(struct ata_link *link, unsigned long deadline); |
a55ab496 | 80 | static void vt6420_bmdma_start(struct ata_queued_cmd *qc); |
a0fcdc02 | 81 | static int vt6421_pata_cable_detect(struct ata_port *ap); |
d73f30e1 A |
82 | static void vt6421_set_pio_mode(struct ata_port *ap, struct ata_device *adev); |
83 | static void vt6421_set_dma_mode(struct ata_port *ap, struct ata_device *adev); | |
44a9b494 | 84 | static void vt6421_error_handler(struct ata_port *ap); |
1da177e4 | 85 | |
3b7d697d | 86 | static const struct pci_device_id svia_pci_tbl[] = { |
96bc103f | 87 | { PCI_VDEVICE(VIA, 0x5337), vt6420 }, |
b9d5b89b TH |
88 | { PCI_VDEVICE(VIA, 0x0591), vt6420 }, /* 2 sata chnls (Master) */ |
89 | { PCI_VDEVICE(VIA, 0x3149), vt6420 }, /* 2 sata chnls (Master) */ | |
90 | { PCI_VDEVICE(VIA, 0x3249), vt6421 }, /* 2 sata chnls, 1 pata chnl */ | |
52df0ee0 JG |
91 | { PCI_VDEVICE(VIA, 0x5372), vt6420 }, |
92 | { PCI_VDEVICE(VIA, 0x7372), vt6420 }, | |
b9d5b89b | 93 | { PCI_VDEVICE(VIA, 0x5287), vt8251 }, /* 2 sata chnls (Master/Slave) */ |
68139520 | 94 | { PCI_VDEVICE(VIA, 0x9000), vt8251 }, |
1da177e4 LT |
95 | |
96 | { } /* terminate list */ | |
97 | }; | |
98 | ||
99 | static struct pci_driver svia_pci_driver = { | |
100 | .name = DRV_NAME, | |
101 | .id_table = svia_pci_tbl, | |
102 | .probe = svia_init_one, | |
58eb8cd5 | 103 | #ifdef CONFIG_PM_SLEEP |
e1e143cf | 104 | .suspend = ata_pci_device_suspend, |
44a9b494 | 105 | .resume = svia_pci_device_resume, |
e1e143cf | 106 | #endif |
1da177e4 LT |
107 | .remove = ata_pci_remove_one, |
108 | }; | |
109 | ||
25df73d9 | 110 | static const struct scsi_host_template svia_sht = { |
68d1d07b | 111 | ATA_BMDMA_SHT(DRV_NAME), |
1da177e4 LT |
112 | }; |
113 | ||
b78152e9 | 114 | static struct ata_port_operations svia_base_ops = { |
029cfd6b | 115 | .inherits = &ata_bmdma_port_ops, |
b78152e9 TH |
116 | .sff_tf_load = svia_tf_load, |
117 | }; | |
118 | ||
119 | static struct ata_port_operations vt6420_sata_ops = { | |
120 | .inherits = &svia_base_ops, | |
17234246 | 121 | .freeze = svia_noop_freeze, |
a1efdaba | 122 | .prereset = vt6420_prereset, |
a55ab496 | 123 | .bmdma_start = vt6420_bmdma_start, |
ac2164d5 TH |
124 | }; |
125 | ||
029cfd6b | 126 | static struct ata_port_operations vt6421_pata_ops = { |
b78152e9 | 127 | .inherits = &svia_base_ops, |
029cfd6b | 128 | .cable_detect = vt6421_pata_cable_detect, |
d73f30e1 A |
129 | .set_piomode = vt6421_set_pio_mode, |
130 | .set_dmamode = vt6421_set_dma_mode, | |
d73f30e1 A |
131 | }; |
132 | ||
029cfd6b | 133 | static struct ata_port_operations vt6421_sata_ops = { |
b78152e9 | 134 | .inherits = &svia_base_ops, |
1da177e4 LT |
135 | .scr_read = svia_scr_read, |
136 | .scr_write = svia_scr_write, | |
44a9b494 | 137 | .error_handler = vt6421_error_handler, |
1da177e4 LT |
138 | }; |
139 | ||
b9d5b89b TH |
140 | static struct ata_port_operations vt8251_ops = { |
141 | .inherits = &svia_base_ops, | |
142 | .hardreset = sata_std_hardreset, | |
143 | .scr_read = vt8251_scr_read, | |
144 | .scr_write = vt8251_scr_write, | |
145 | }; | |
146 | ||
eca25dca | 147 | static const struct ata_port_info vt6420_port_info = { |
9cbe056f | 148 | .flags = ATA_FLAG_SATA, |
14bdef98 EIB |
149 | .pio_mask = ATA_PIO4, |
150 | .mwdma_mask = ATA_MWDMA2, | |
bf6263a8 | 151 | .udma_mask = ATA_UDMA6, |
ac2164d5 | 152 | .port_ops = &vt6420_sata_ops, |
1da177e4 LT |
153 | }; |
154 | ||
f356b082 | 155 | static const struct ata_port_info vt6421_sport_info = { |
9cbe056f | 156 | .flags = ATA_FLAG_SATA, |
14bdef98 EIB |
157 | .pio_mask = ATA_PIO4, |
158 | .mwdma_mask = ATA_MWDMA2, | |
bf6263a8 | 159 | .udma_mask = ATA_UDMA6, |
eca25dca TH |
160 | .port_ops = &vt6421_sata_ops, |
161 | }; | |
162 | ||
f356b082 | 163 | static const struct ata_port_info vt6421_pport_info = { |
9cbe056f | 164 | .flags = ATA_FLAG_SLAVE_POSS, |
14bdef98 EIB |
165 | .pio_mask = ATA_PIO4, |
166 | /* No MWDMA */ | |
bf6263a8 | 167 | .udma_mask = ATA_UDMA6, |
eca25dca TH |
168 | .port_ops = &vt6421_pata_ops, |
169 | }; | |
170 | ||
f356b082 | 171 | static const struct ata_port_info vt8251_port_info = { |
9cbe056f | 172 | .flags = ATA_FLAG_SATA | ATA_FLAG_SLAVE_POSS, |
14bdef98 EIB |
173 | .pio_mask = ATA_PIO4, |
174 | .mwdma_mask = ATA_MWDMA2, | |
b9d5b89b TH |
175 | .udma_mask = ATA_UDMA6, |
176 | .port_ops = &vt8251_ops, | |
177 | }; | |
178 | ||
1da177e4 LT |
179 | MODULE_AUTHOR("Jeff Garzik"); |
180 | MODULE_DESCRIPTION("SCSI low-level driver for VIA SATA controllers"); | |
181 | MODULE_LICENSE("GPL"); | |
182 | MODULE_DEVICE_TABLE(pci, svia_pci_tbl); | |
183 | MODULE_VERSION(DRV_VERSION); | |
184 | ||
82ef04fb | 185 | static int svia_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val) |
1da177e4 LT |
186 | { |
187 | if (sc_reg > SCR_CONTROL) | |
da3dbb17 | 188 | return -EINVAL; |
82ef04fb | 189 | *val = ioread32(link->ap->ioaddr.scr_addr + (4 * sc_reg)); |
da3dbb17 | 190 | return 0; |
1da177e4 LT |
191 | } |
192 | ||
82ef04fb | 193 | static int svia_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val) |
1da177e4 LT |
194 | { |
195 | if (sc_reg > SCR_CONTROL) | |
da3dbb17 | 196 | return -EINVAL; |
82ef04fb | 197 | iowrite32(val, link->ap->ioaddr.scr_addr + (4 * sc_reg)); |
da3dbb17 | 198 | return 0; |
1da177e4 LT |
199 | } |
200 | ||
b9d5b89b TH |
201 | static int vt8251_scr_read(struct ata_link *link, unsigned int scr, u32 *val) |
202 | { | |
203 | static const u8 ipm_tbl[] = { 1, 2, 6, 0 }; | |
204 | struct pci_dev *pdev = to_pci_dev(link->ap->host->dev); | |
205 | int slot = 2 * link->ap->port_no + link->pmp; | |
206 | u32 v = 0; | |
207 | u8 raw; | |
208 | ||
209 | switch (scr) { | |
210 | case SCR_STATUS: | |
211 | pci_read_config_byte(pdev, 0xA0 + slot, &raw); | |
212 | ||
213 | /* read the DET field, bit0 and 1 of the config byte */ | |
214 | v |= raw & 0x03; | |
215 | ||
216 | /* read the SPD field, bit4 of the configure byte */ | |
217 | if (raw & (1 << 4)) | |
218 | v |= 0x02 << 4; | |
219 | else | |
220 | v |= 0x01 << 4; | |
221 | ||
222 | /* read the IPM field, bit2 and 3 of the config byte */ | |
223 | v |= ipm_tbl[(raw >> 2) & 0x3]; | |
224 | break; | |
225 | ||
226 | case SCR_ERROR: | |
227 | /* devices other than 5287 uses 0xA8 as base */ | |
228 | WARN_ON(pdev->device != 0x5287); | |
229 | pci_read_config_dword(pdev, 0xB0 + slot * 4, &v); | |
230 | break; | |
231 | ||
232 | case SCR_CONTROL: | |
233 | pci_read_config_byte(pdev, 0xA4 + slot, &raw); | |
234 | ||
235 | /* read the DET field, bit0 and bit1 */ | |
236 | v |= ((raw & 0x02) << 1) | (raw & 0x01); | |
237 | ||
238 | /* read the IPM field, bit2 and bit3 */ | |
239 | v |= ((raw >> 2) & 0x03) << 8; | |
240 | break; | |
241 | ||
242 | default: | |
243 | return -EINVAL; | |
244 | } | |
245 | ||
246 | *val = v; | |
247 | return 0; | |
248 | } | |
249 | ||
250 | static int vt8251_scr_write(struct ata_link *link, unsigned int scr, u32 val) | |
251 | { | |
252 | struct pci_dev *pdev = to_pci_dev(link->ap->host->dev); | |
253 | int slot = 2 * link->ap->port_no + link->pmp; | |
254 | u32 v = 0; | |
255 | ||
256 | switch (scr) { | |
257 | case SCR_ERROR: | |
258 | /* devices other than 5287 uses 0xA8 as base */ | |
259 | WARN_ON(pdev->device != 0x5287); | |
260 | pci_write_config_dword(pdev, 0xB0 + slot * 4, val); | |
261 | return 0; | |
262 | ||
263 | case SCR_CONTROL: | |
264 | /* set the DET field */ | |
265 | v |= ((val & 0x4) >> 1) | (val & 0x1); | |
266 | ||
267 | /* set the IPM field */ | |
268 | v |= ((val >> 8) & 0x3) << 2; | |
269 | ||
270 | pci_write_config_byte(pdev, 0xA4 + slot, v); | |
271 | return 0; | |
272 | ||
273 | default: | |
274 | return -EINVAL; | |
275 | } | |
276 | } | |
277 | ||
b78152e9 TH |
278 | /** |
279 | * svia_tf_load - send taskfile registers to host controller | |
280 | * @ap: Port to which output is sent | |
281 | * @tf: ATA taskfile register set | |
282 | * | |
283 | * Outputs ATA taskfile to standard ATA host controller. | |
284 | * | |
285 | * This is to fix the internal bug of via chipsets, which will | |
286 | * reset the device register after changing the IEN bit on ctl | |
287 | * register. | |
288 | */ | |
289 | static void svia_tf_load(struct ata_port *ap, const struct ata_taskfile *tf) | |
290 | { | |
291 | struct ata_taskfile ttf; | |
292 | ||
293 | if (tf->ctl != ap->last_ctl) { | |
294 | ttf = *tf; | |
295 | ttf.flags |= ATA_TFLAG_DEVICE; | |
296 | tf = &ttf; | |
297 | } | |
298 | ata_sff_tf_load(ap, tf); | |
299 | } | |
300 | ||
17234246 TH |
301 | static void svia_noop_freeze(struct ata_port *ap) |
302 | { | |
303 | /* Some VIA controllers choke if ATA_NIEN is manipulated in | |
304 | * certain way. Leave it alone and just clear pending IRQ. | |
305 | */ | |
5682ed33 | 306 | ap->ops->sff_check_status(ap); |
37f65b8b | 307 | ata_bmdma_irq_clear(ap); |
17234246 TH |
308 | } |
309 | ||
ac2164d5 TH |
310 | /** |
311 | * vt6420_prereset - prereset for vt6420 | |
cc0680a5 | 312 | * @link: target ATA link |
d4b2bab4 | 313 | * @deadline: deadline jiffies for the operation |
ac2164d5 TH |
314 | * |
315 | * SCR registers on vt6420 are pieces of shit and may hang the | |
316 | * whole machine completely if accessed with the wrong timing. | |
317 | * To avoid such catastrophe, vt6420 doesn't provide generic SCR | |
318 | * access operations, but uses SStatus and SControl only during | |
319 | * boot probing in controlled way. | |
320 | * | |
321 | * As the old (pre EH update) probing code is proven to work, we | |
322 | * strictly follow the access pattern. | |
323 | * | |
324 | * LOCKING: | |
325 | * Kernel thread context (may sleep) | |
326 | * | |
327 | * RETURNS: | |
328 | * 0 on success, -errno otherwise. | |
329 | */ | |
cc0680a5 | 330 | static int vt6420_prereset(struct ata_link *link, unsigned long deadline) |
ac2164d5 | 331 | { |
cc0680a5 | 332 | struct ata_port *ap = link->ap; |
9af5c9c9 | 333 | struct ata_eh_context *ehc = &ap->link.eh_context; |
ac2164d5 TH |
334 | unsigned long timeout = jiffies + (HZ * 5); |
335 | u32 sstatus, scontrol; | |
336 | int online; | |
337 | ||
338 | /* don't do any SCR stuff if we're not loading */ | |
68ff6e8e | 339 | if (!(ap->pflags & ATA_PFLAG_LOADING)) |
ac2164d5 TH |
340 | goto skip_scr; |
341 | ||
a09060ff | 342 | /* Resume phy. This is the old SATA resume sequence */ |
82ef04fb TH |
343 | svia_scr_write(link, SCR_CONTROL, 0x300); |
344 | svia_scr_read(link, SCR_CONTROL, &scontrol); /* flush */ | |
ac2164d5 TH |
345 | |
346 | /* wait for phy to become ready, if necessary */ | |
347 | do { | |
97750ceb | 348 | ata_msleep(link->ap, 200); |
82ef04fb | 349 | svia_scr_read(link, SCR_STATUS, &sstatus); |
da3dbb17 | 350 | if ((sstatus & 0xf) != 1) |
ac2164d5 TH |
351 | break; |
352 | } while (time_before(jiffies, timeout)); | |
353 | ||
354 | /* open code sata_print_link_status() */ | |
82ef04fb TH |
355 | svia_scr_read(link, SCR_STATUS, &sstatus); |
356 | svia_scr_read(link, SCR_CONTROL, &scontrol); | |
ac2164d5 TH |
357 | |
358 | online = (sstatus & 0xf) == 0x3; | |
359 | ||
a9a79dfe JP |
360 | ata_port_info(ap, |
361 | "SATA link %s 1.5 Gbps (SStatus %X SControl %X)\n", | |
362 | online ? "up" : "down", sstatus, scontrol); | |
ac2164d5 TH |
363 | |
364 | /* SStatus is read one more time */ | |
82ef04fb | 365 | svia_scr_read(link, SCR_STATUS, &sstatus); |
ac2164d5 TH |
366 | |
367 | if (!online) { | |
368 | /* tell EH to bail */ | |
cf480626 | 369 | ehc->i.action &= ~ATA_EH_RESET; |
ac2164d5 TH |
370 | return 0; |
371 | } | |
372 | ||
373 | skip_scr: | |
374 | /* wait for !BSY */ | |
705e76be | 375 | ata_sff_wait_ready(link, deadline); |
ac2164d5 TH |
376 | |
377 | return 0; | |
378 | } | |
379 | ||
a55ab496 BH |
380 | static void vt6420_bmdma_start(struct ata_queued_cmd *qc) |
381 | { | |
382 | struct ata_port *ap = qc->ap; | |
383 | if ((qc->tf.command == ATA_CMD_PACKET) && | |
384 | (qc->scsicmd->sc_data_direction == DMA_TO_DEVICE)) { | |
385 | /* Prevents corruption on some ATAPI burners */ | |
386 | ata_sff_pause(ap); | |
387 | } | |
388 | ata_bmdma_start(qc); | |
389 | } | |
390 | ||
a0fcdc02 | 391 | static int vt6421_pata_cable_detect(struct ata_port *ap) |
d73f30e1 A |
392 | { |
393 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); | |
394 | u8 tmp; | |
395 | ||
396 | pci_read_config_byte(pdev, PATA_UDMA_TIMING, &tmp); | |
397 | if (tmp & 0x10) | |
a0fcdc02 JG |
398 | return ATA_CBL_PATA40; |
399 | return ATA_CBL_PATA80; | |
d73f30e1 A |
400 | } |
401 | ||
402 | static void vt6421_set_pio_mode(struct ata_port *ap, struct ata_device *adev) | |
403 | { | |
404 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); | |
405 | static const u8 pio_bits[] = { 0xA8, 0x65, 0x65, 0x31, 0x20 }; | |
02d1d616 BH |
406 | pci_write_config_byte(pdev, PATA_PIO_TIMING - adev->devno, |
407 | pio_bits[adev->pio_mode - XFER_PIO_0]); | |
d73f30e1 A |
408 | } |
409 | ||
410 | static void vt6421_set_dma_mode(struct ata_port *ap, struct ata_device *adev) | |
411 | { | |
412 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); | |
413 | static const u8 udma_bits[] = { 0xEE, 0xE8, 0xE6, 0xE4, 0xE2, 0xE1, 0xE0, 0xE0 }; | |
02d1d616 BH |
414 | pci_write_config_byte(pdev, PATA_UDMA_TIMING - adev->devno, |
415 | udma_bits[adev->dma_mode - XFER_UDMA_0]); | |
d73f30e1 A |
416 | } |
417 | ||
1da177e4 LT |
418 | static const unsigned int svia_bar_sizes[] = { |
419 | 8, 4, 8, 4, 16, 256 | |
420 | }; | |
421 | ||
422 | static const unsigned int vt6421_bar_sizes[] = { | |
423 | 16, 16, 16, 16, 32, 128 | |
424 | }; | |
425 | ||
5796d1c4 | 426 | static void __iomem *svia_scr_addr(void __iomem *addr, unsigned int port) |
1da177e4 LT |
427 | { |
428 | return addr + (port * 128); | |
429 | } | |
430 | ||
5796d1c4 | 431 | static void __iomem *vt6421_scr_addr(void __iomem *addr, unsigned int port) |
1da177e4 LT |
432 | { |
433 | return addr + (port * 64); | |
434 | } | |
435 | ||
eca25dca | 436 | static void vt6421_init_addrs(struct ata_port *ap) |
1da177e4 | 437 | { |
eca25dca TH |
438 | void __iomem * const * iomap = ap->host->iomap; |
439 | void __iomem *reg_addr = iomap[ap->port_no]; | |
440 | void __iomem *bmdma_addr = iomap[4] + (ap->port_no * 8); | |
441 | struct ata_ioports *ioaddr = &ap->ioaddr; | |
442 | ||
443 | ioaddr->cmd_addr = reg_addr; | |
444 | ioaddr->altstatus_addr = | |
445 | ioaddr->ctl_addr = (void __iomem *) | |
0d5ff566 | 446 | ((unsigned long)(reg_addr + 8) | ATA_PCI_CTL_OFS); |
eca25dca TH |
447 | ioaddr->bmdma_addr = bmdma_addr; |
448 | ioaddr->scr_addr = vt6421_scr_addr(iomap[5], ap->port_no); | |
1da177e4 | 449 | |
9363c382 | 450 | ata_sff_std_ports(ioaddr); |
cbcdd875 TH |
451 | |
452 | ata_port_pbar_desc(ap, ap->port_no, -1, "port"); | |
453 | ata_port_pbar_desc(ap, 4, ap->port_no * 8, "bmdma"); | |
1da177e4 LT |
454 | } |
455 | ||
eca25dca | 456 | static int vt6420_prepare_host(struct pci_dev *pdev, struct ata_host **r_host) |
1da177e4 | 457 | { |
eca25dca TH |
458 | const struct ata_port_info *ppi[] = { &vt6420_port_info, NULL }; |
459 | struct ata_host *host; | |
460 | int rc; | |
f20b16ff | 461 | |
98633258 OZ |
462 | if (vt6420_hotplug) { |
463 | ppi[0]->port_ops->scr_read = svia_scr_read; | |
464 | ppi[0]->port_ops->scr_write = svia_scr_write; | |
465 | } | |
466 | ||
1c5afdf7 | 467 | rc = ata_pci_bmdma_prepare_host(pdev, ppi, &host); |
eca25dca TH |
468 | if (rc) |
469 | return rc; | |
470 | *r_host = host; | |
1da177e4 | 471 | |
eca25dca TH |
472 | rc = pcim_iomap_regions(pdev, 1 << 5, DRV_NAME); |
473 | if (rc) { | |
a44fec1f | 474 | dev_err(&pdev->dev, "failed to iomap PCI BAR 5\n"); |
eca25dca | 475 | return rc; |
e1be5d73 TH |
476 | } |
477 | ||
eca25dca TH |
478 | host->ports[0]->ioaddr.scr_addr = svia_scr_addr(host->iomap[5], 0); |
479 | host->ports[1]->ioaddr.scr_addr = svia_scr_addr(host->iomap[5], 1); | |
1da177e4 | 480 | |
eca25dca | 481 | return 0; |
1da177e4 LT |
482 | } |
483 | ||
eca25dca | 484 | static int vt6421_prepare_host(struct pci_dev *pdev, struct ata_host **r_host) |
1da177e4 | 485 | { |
eca25dca TH |
486 | const struct ata_port_info *ppi[] = |
487 | { &vt6421_sport_info, &vt6421_sport_info, &vt6421_pport_info }; | |
488 | struct ata_host *host; | |
489 | int i, rc; | |
490 | ||
491 | *r_host = host = ata_host_alloc_pinfo(&pdev->dev, ppi, ARRAY_SIZE(ppi)); | |
492 | if (!host) { | |
a44fec1f | 493 | dev_err(&pdev->dev, "failed to allocate host\n"); |
eca25dca TH |
494 | return -ENOMEM; |
495 | } | |
1da177e4 | 496 | |
8fd7d1b1 | 497 | rc = pcim_iomap_regions(pdev, 0x3f, DRV_NAME); |
eca25dca | 498 | if (rc) { |
a44fec1f JP |
499 | dev_err(&pdev->dev, "failed to request/iomap PCI BARs (errno=%d)\n", |
500 | rc); | |
eca25dca TH |
501 | return rc; |
502 | } | |
503 | host->iomap = pcim_iomap_table(pdev); | |
e1be5d73 | 504 | |
eca25dca TH |
505 | for (i = 0; i < host->n_ports; i++) |
506 | vt6421_init_addrs(host->ports[i]); | |
1da177e4 | 507 | |
b5e55556 | 508 | return dma_set_mask_and_coherent(&pdev->dev, ATA_DMA_MASK); |
1da177e4 LT |
509 | } |
510 | ||
b9d5b89b TH |
511 | static int vt8251_prepare_host(struct pci_dev *pdev, struct ata_host **r_host) |
512 | { | |
513 | const struct ata_port_info *ppi[] = { &vt8251_port_info, NULL }; | |
514 | struct ata_host *host; | |
515 | int i, rc; | |
516 | ||
1c5afdf7 | 517 | rc = ata_pci_bmdma_prepare_host(pdev, ppi, &host); |
b9d5b89b TH |
518 | if (rc) |
519 | return rc; | |
520 | *r_host = host; | |
521 | ||
522 | rc = pcim_iomap_regions(pdev, 1 << 5, DRV_NAME); | |
523 | if (rc) { | |
a44fec1f | 524 | dev_err(&pdev->dev, "failed to iomap PCI BAR 5\n"); |
b9d5b89b TH |
525 | return rc; |
526 | } | |
527 | ||
528 | /* 8251 hosts four sata ports as M/S of the two channels */ | |
529 | for (i = 0; i < host->n_ports; i++) | |
530 | ata_slave_link_init(host->ports[i]); | |
531 | ||
532 | return 0; | |
533 | } | |
534 | ||
44a9b494 OZ |
535 | static void svia_wd_fix(struct pci_dev *pdev) |
536 | { | |
537 | u8 tmp8; | |
538 | ||
539 | pci_read_config_byte(pdev, 0x52, &tmp8); | |
540 | pci_write_config_byte(pdev, 0x52, tmp8 | BIT(2)); | |
541 | } | |
542 | ||
98633258 | 543 | static irqreturn_t vt642x_interrupt(int irq, void *dev_instance) |
57e5568f OZ |
544 | { |
545 | struct ata_host *host = dev_instance; | |
546 | irqreturn_t rc = ata_bmdma_interrupt(irq, dev_instance); | |
547 | ||
548 | /* if the IRQ was not handled, it might be a hotplug IRQ */ | |
549 | if (rc != IRQ_HANDLED) { | |
550 | u32 serror; | |
551 | unsigned long flags; | |
552 | ||
553 | spin_lock_irqsave(&host->lock, flags); | |
554 | /* check for hotplug on port 0 */ | |
555 | svia_scr_read(&host->ports[0]->link, SCR_ERROR, &serror); | |
556 | if (serror & SERR_PHYRDY_CHG) { | |
557 | ata_ehi_hotplugged(&host->ports[0]->link.eh_info); | |
558 | ata_port_freeze(host->ports[0]); | |
559 | rc = IRQ_HANDLED; | |
560 | } | |
561 | /* check for hotplug on port 1 */ | |
562 | svia_scr_read(&host->ports[1]->link, SCR_ERROR, &serror); | |
563 | if (serror & SERR_PHYRDY_CHG) { | |
564 | ata_ehi_hotplugged(&host->ports[1]->link.eh_info); | |
565 | ata_port_freeze(host->ports[1]); | |
566 | rc = IRQ_HANDLED; | |
567 | } | |
568 | spin_unlock_irqrestore(&host->lock, flags); | |
569 | } | |
570 | ||
571 | return rc; | |
572 | } | |
573 | ||
44a9b494 OZ |
574 | static void vt6421_error_handler(struct ata_port *ap) |
575 | { | |
576 | struct svia_priv *hpriv = ap->host->private_data; | |
577 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); | |
578 | u32 serror; | |
579 | ||
580 | /* see svia_configure() for description */ | |
581 | if (!hpriv->wd_workaround) { | |
582 | svia_scr_read(&ap->link, SCR_ERROR, &serror); | |
583 | if (serror == 0x1000500) { | |
584 | ata_port_warn(ap, "Incompatible drive: enabling workaround. This slows down transfer rate to ~60 MB/s"); | |
585 | svia_wd_fix(pdev); | |
586 | hpriv->wd_workaround = true; | |
587 | ap->link.eh_context.i.flags |= ATA_EHI_QUIET; | |
588 | } | |
589 | } | |
590 | ||
591 | ata_sff_error_handler(ap); | |
592 | } | |
593 | ||
594 | static void svia_configure(struct pci_dev *pdev, int board_id, | |
595 | struct svia_priv *hpriv) | |
1da177e4 LT |
596 | { |
597 | u8 tmp8; | |
598 | ||
599 | pci_read_config_byte(pdev, PCI_INTERRUPT_LINE, &tmp8); | |
a44fec1f JP |
600 | dev_info(&pdev->dev, "routed to hard irq line %d\n", |
601 | (int) (tmp8 & 0xf0) == 0xf0 ? 0 : tmp8 & 0x0f); | |
1da177e4 LT |
602 | |
603 | /* make sure SATA channels are enabled */ | |
604 | pci_read_config_byte(pdev, SATA_CHAN_ENAB, &tmp8); | |
605 | if ((tmp8 & ALL_PORTS) != ALL_PORTS) { | |
5b933e63 JP |
606 | dev_dbg(&pdev->dev, "enabling SATA channels (0x%x)\n", |
607 | (int)tmp8); | |
1da177e4 LT |
608 | tmp8 |= ALL_PORTS; |
609 | pci_write_config_byte(pdev, SATA_CHAN_ENAB, tmp8); | |
610 | } | |
611 | ||
612 | /* make sure interrupts for each channel sent to us */ | |
613 | pci_read_config_byte(pdev, SATA_INT_GATE, &tmp8); | |
614 | if ((tmp8 & ALL_PORTS) != ALL_PORTS) { | |
5b933e63 JP |
615 | dev_dbg(&pdev->dev, "enabling SATA channel interrupts (0x%x)\n", |
616 | (int) tmp8); | |
1da177e4 LT |
617 | tmp8 |= ALL_PORTS; |
618 | pci_write_config_byte(pdev, SATA_INT_GATE, tmp8); | |
619 | } | |
620 | ||
621 | /* make sure native mode is enabled */ | |
622 | pci_read_config_byte(pdev, SATA_NATIVE_MODE, &tmp8); | |
623 | if ((tmp8 & NATIVE_MODE_ALL) != NATIVE_MODE_ALL) { | |
5b933e63 JP |
624 | dev_dbg(&pdev->dev, |
625 | "enabling SATA channel native mode (0x%x)\n", | |
626 | (int) tmp8); | |
1da177e4 LT |
627 | tmp8 |= NATIVE_MODE_ALL; |
628 | pci_write_config_byte(pdev, SATA_NATIVE_MODE, tmp8); | |
629 | } | |
8b27ff4c | 630 | |
98633258 | 631 | if ((board_id == vt6420 && vt6420_hotplug) || board_id == vt6421) { |
3cf86452 OZ |
632 | /* enable IRQ on hotplug */ |
633 | pci_read_config_byte(pdev, SVIA_MISC_3, &tmp8); | |
634 | if ((tmp8 & SATA_HOTPLUG) != SATA_HOTPLUG) { | |
635 | dev_dbg(&pdev->dev, | |
636 | "enabling SATA hotplug (0x%x)\n", | |
637 | (int) tmp8); | |
638 | tmp8 |= SATA_HOTPLUG; | |
639 | pci_write_config_byte(pdev, SVIA_MISC_3, tmp8); | |
640 | } | |
57e5568f OZ |
641 | } |
642 | ||
8b27ff4c | 643 | /* |
b1353e4f | 644 | * vt6420/1 has problems talking to some drives. The following |
b475a3b8 TH |
645 | * is the fix from Joseph Chan <JosephChan@via.com.tw>. |
646 | * | |
647 | * When host issues HOLD, device may send up to 20DW of data | |
648 | * before acknowledging it with HOLDA and the host should be | |
649 | * able to buffer them in FIFO. Unfortunately, some WD drives | |
25985edc | 650 | * send up to 40DW before acknowledging HOLD and, in the |
b475a3b8 TH |
651 | * default configuration, this ends up overflowing vt6421's |
652 | * FIFO, making the controller abort the transaction with | |
653 | * R_ERR. | |
654 | * | |
655 | * Rx52[2] is the internal 128DW FIFO Flow control watermark | |
656 | * adjusting mechanism enable bit and the default value 0 | |
657 | * means host will issue HOLD to device when the left FIFO | |
658 | * size goes below 32DW. Setting it to 1 makes the watermark | |
659 | * 64DW. | |
8b27ff4c TH |
660 | * |
661 | * https://bugzilla.kernel.org/show_bug.cgi?id=15173 | |
b475a3b8 | 662 | * http://article.gmane.org/gmane.linux.ide/46352 |
b1353e4f | 663 | * http://thread.gmane.org/gmane.linux.kernel/1062139 |
44a9b494 OZ |
664 | * |
665 | * As the fix slows down data transfer, apply it only if the error | |
666 | * actually appears - see vt6421_error_handler() | |
667 | * Apply the fix always on vt6420 as we don't know if SCR_ERROR can be | |
668 | * read safely. | |
8b27ff4c | 669 | */ |
44a9b494 OZ |
670 | if (board_id == vt6420) { |
671 | svia_wd_fix(pdev); | |
672 | hpriv->wd_workaround = true; | |
8b27ff4c | 673 | } |
1da177e4 LT |
674 | } |
675 | ||
5796d1c4 | 676 | static int svia_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) |
1da177e4 | 677 | { |
1da177e4 LT |
678 | unsigned int i; |
679 | int rc; | |
f1c22943 | 680 | struct ata_host *host = NULL; |
1da177e4 | 681 | int board_id = (int) ent->driver_data; |
b4482a4b | 682 | const unsigned *bar_sizes; |
44a9b494 | 683 | struct svia_priv *hpriv; |
1da177e4 | 684 | |
06296a1e | 685 | ata_print_version_once(&pdev->dev, DRV_VERSION); |
1da177e4 | 686 | |
24dc5f33 | 687 | rc = pcim_enable_device(pdev); |
1da177e4 LT |
688 | if (rc) |
689 | return rc; | |
690 | ||
b9d5b89b | 691 | if (board_id == vt6421) |
1da177e4 | 692 | bar_sizes = &vt6421_bar_sizes[0]; |
b9d5b89b TH |
693 | else |
694 | bar_sizes = &svia_bar_sizes[0]; | |
1da177e4 LT |
695 | |
696 | for (i = 0; i < ARRAY_SIZE(svia_bar_sizes); i++) | |
697 | if ((pci_resource_start(pdev, i) == 0) || | |
698 | (pci_resource_len(pdev, i) < bar_sizes[i])) { | |
a44fec1f | 699 | dev_err(&pdev->dev, |
e29419ff GKH |
700 | "invalid PCI BAR %u (sz 0x%llx, val 0x%llx)\n", |
701 | i, | |
5796d1c4 JG |
702 | (unsigned long long)pci_resource_start(pdev, i), |
703 | (unsigned long long)pci_resource_len(pdev, i)); | |
24dc5f33 | 704 | return -ENODEV; |
1da177e4 LT |
705 | } |
706 | ||
b9d5b89b TH |
707 | switch (board_id) { |
708 | case vt6420: | |
eca25dca | 709 | rc = vt6420_prepare_host(pdev, &host); |
b9d5b89b TH |
710 | break; |
711 | case vt6421: | |
eca25dca | 712 | rc = vt6421_prepare_host(pdev, &host); |
b9d5b89b TH |
713 | break; |
714 | case vt8251: | |
715 | rc = vt8251_prepare_host(pdev, &host); | |
716 | break; | |
717 | default: | |
554d491d | 718 | rc = -EINVAL; |
b9d5b89b | 719 | } |
554d491d MS |
720 | if (rc) |
721 | return rc; | |
1da177e4 | 722 | |
44a9b494 OZ |
723 | hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL); |
724 | if (!hpriv) | |
725 | return -ENOMEM; | |
726 | host->private_data = hpriv; | |
727 | ||
728 | svia_configure(pdev, board_id, hpriv); | |
1da177e4 LT |
729 | |
730 | pci_set_master(pdev); | |
98633258 OZ |
731 | if ((board_id == vt6420 && vt6420_hotplug) || board_id == vt6421) |
732 | return ata_host_activate(host, pdev->irq, vt642x_interrupt, | |
57e5568f OZ |
733 | IRQF_SHARED, &svia_sht); |
734 | else | |
735 | return ata_host_activate(host, pdev->irq, ata_bmdma_interrupt, | |
736 | IRQF_SHARED, &svia_sht); | |
1da177e4 LT |
737 | } |
738 | ||
44a9b494 OZ |
739 | #ifdef CONFIG_PM_SLEEP |
740 | static int svia_pci_device_resume(struct pci_dev *pdev) | |
741 | { | |
742 | struct ata_host *host = pci_get_drvdata(pdev); | |
743 | struct svia_priv *hpriv = host->private_data; | |
744 | int rc; | |
745 | ||
746 | rc = ata_pci_device_do_resume(pdev); | |
747 | if (rc) | |
748 | return rc; | |
749 | ||
750 | if (hpriv->wd_workaround) | |
751 | svia_wd_fix(pdev); | |
752 | ata_host_resume(host); | |
753 | ||
754 | return 0; | |
755 | } | |
756 | #endif | |
757 | ||
2fc75da0 | 758 | module_pci_driver(svia_pci_driver); |