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Merge tag 'powerpc-6.7-2' of git://git.kernel.org/pub/scm/linux/kernel/git/powerpc...
[linux-2.6-block.git] / drivers / ata / sata_sx4.c
CommitLineData
c82ee6d3 1// SPDX-License-Identifier: GPL-2.0-or-later
1da177e4
LT		 2/*
3 * sata_sx4.c - Promise SATA
4 *
8c3d3d4b 5 * Maintained by: Tejun Heo <tj@kernel.org>
1da177e4
LT		 6 * Please ALWAYS copy linux-ide@vger.kernel.org
7 * on emails.
8 *
9 * Copyright 2003-2004 Red Hat, Inc.
10 *
af36d7f0 11 * libata documentation is available via 'make {ps|pdf}docs',
19285f3c 12 * as Documentation/driver-api/libata.rst
af36d7f0
JG		 13 *
14 * Hardware documentation available under NDA.
1da177e4
LT		 15 */
16
a09060ff
JG		 17/*
18 Theory of operation
19 -------------------
20
21 The SX4 (PDC20621) chip features a single Host DMA (HDMA) copy
22 engine, DIMM memory, and four ATA engines (one per SATA port).
23 Data is copied to/from DIMM memory by the HDMA engine, before
24 handing off to one (or more) of the ATA engines. The ATA
25 engines operate solely on DIMM memory.
26
27 The SX4 behaves like a PATA chip, with no SATA controls or
28 knowledge whatsoever, leading to the presumption that
29 PATA<->SATA bridges exist on SX4 boards, external to the
30 PDC20621 chip itself.
31
32 The chip is quite capable, supporting an XOR engine and linked
33 hardware commands (permits a string to transactions to be
34 submitted and waited-on as a single unit), and an optional
35 microprocessor.
36
37 The limiting factor is largely software. This Linux driver was
38 written to multiplex the single HDMA engine to copy disk
39 transactions into a fixed DIMM memory space, from where an ATA
40 engine takes over. As a result, each WRITE looks like this:
41
42 submit HDMA packet to hardware
43 hardware copies data from system memory to DIMM
44 hardware raises interrupt
45
46 submit ATA packet to hardware
47 hardware executes ATA WRITE command, w/ data in DIMM
48 hardware raises interrupt
2dcb407e 49
a09060ff
JG		 50 and each READ looks like this:
51
52 submit ATA packet to hardware
53 hardware executes ATA READ command, w/ data in DIMM
54 hardware raises interrupt
2dcb407e 55
a09060ff
JG		 56 submit HDMA packet to hardware
57 hardware copies data from DIMM to system memory
58 hardware raises interrupt
59
60 This is a very slow, lock-step way of doing things that can
61 certainly be improved by motivated kernel hackers.
62
63 */
64
1da177e4
LT		 65#include <linux/kernel.h>
66#include <linux/module.h>
67#include <linux/pci.h>
5a0e3ad6 68#include <linux/slab.h>
1da177e4
LT		 69#include <linux/blkdev.h>
70#include <linux/delay.h>
71#include <linux/interrupt.h>
a9524a76 72#include <linux/device.h>
1da177e4 73#include <scsi/scsi_host.h>
193515d5 74#include <scsi/scsi_cmnd.h>
1da177e4 75#include <linux/libata.h>
1da177e4
LT		 76#include "sata_promise.h"
77
78#define DRV_NAME "sata_sx4"
2a3103ce 79#define DRV_VERSION "0.12"
1da177e4 80
f11c5403
HR		 81static int dimm_test;
82module_param(dimm_test, int, 0644);
83MODULE_PARM_DESC(dimm_test, "Enable DIMM test during startup (1 = enabled)");
1da177e4
LT		 84
85enum {
0d5ff566
TH		 86 PDC_MMIO_BAR = 3,
87 PDC_DIMM_BAR = 4,
88
1da177e4
LT		 89 PDC_PRD_TBL = 0x44, /* Direct command DMA table addr */
90
91 PDC_PKT_SUBMIT = 0x40, /* Command packet pointer addr */
92 PDC_HDMA_PKT_SUBMIT = 0x100, /* Host DMA packet pointer addr */
93 PDC_INT_SEQMASK = 0x40, /* Mask of asserted SEQ INTs */
94 PDC_HDMA_CTLSTAT = 0x12C, /* Host DMA control / status */
95
a09060ff
JG		 96 PDC_CTLSTAT = 0x60, /* IDEn control / status */
97
1da177e4
LT		 98 PDC_20621_SEQCTL = 0x400,
99 PDC_20621_SEQMASK = 0x480,
100 PDC_20621_GENERAL_CTL = 0x484,
101 PDC_20621_PAGE_SIZE = (32 * 1024),
102
103 /* chosen, not constant, values; we design our own DIMM mem map */
104 PDC_20621_DIMM_WINDOW = 0x0C, /* page# for 32K DIMM window */
105 PDC_20621_DIMM_BASE = 0x00200000,
106 PDC_20621_DIMM_DATA = (64 * 1024),
107 PDC_DIMM_DATA_STEP = (256 * 1024),
108 PDC_DIMM_WINDOW_STEP = (8 * 1024),
109 PDC_DIMM_HOST_PRD = (6 * 1024),
110 PDC_DIMM_HOST_PKT = (128 * 0),
111 PDC_DIMM_HPKT_PRD = (128 * 1),
112 PDC_DIMM_ATA_PKT = (128 * 2),
113 PDC_DIMM_APKT_PRD = (128 * 3),
114 PDC_DIMM_HEADER_SZ = PDC_DIMM_APKT_PRD + 128,
115 PDC_PAGE_WINDOW = 0x40,
116 PDC_PAGE_DATA = PDC_PAGE_WINDOW +
117 (PDC_20621_DIMM_DATA / PDC_20621_PAGE_SIZE),
118 PDC_PAGE_SET = PDC_DIMM_DATA_STEP / PDC_20621_PAGE_SIZE,
119
120 PDC_CHIP0_OFS = 0xC0000, /* offset of chip #0 */
121
122 PDC_20621_ERR_MASK = (1<<19) | (1<<20) | (1<<21) | (1<<22) |
123 (1<<23),
124
125 board_20621 = 0, /* FastTrak S150 SX4 */
126
b2d46b61
JG		 127 PDC_MASK_INT = (1 << 10), /* HDMA/ATA mask int */
128 PDC_RESET = (1 << 11), /* HDMA/ATA reset */
a09060ff 129 PDC_DMA_ENABLE = (1 << 7), /* DMA start/stop */
1da177e4
LT		 130
131 PDC_MAX_HDMA = 32,
132 PDC_HDMA_Q_MASK = (PDC_MAX_HDMA - 1),
133
b2d46b61
JG		 134 PDC_DIMM0_SPD_DEV_ADDRESS = 0x50,
135 PDC_DIMM1_SPD_DEV_ADDRESS = 0x51,
136 PDC_I2C_CONTROL = 0x48,
137 PDC_I2C_ADDR_DATA = 0x4C,
138 PDC_DIMM0_CONTROL = 0x80,
139 PDC_DIMM1_CONTROL = 0x84,
140 PDC_SDRAM_CONTROL = 0x88,
141 PDC_I2C_WRITE = 0, /* master -> slave */
142 PDC_I2C_READ = (1 << 6), /* master <- slave */
143 PDC_I2C_START = (1 << 7), /* start I2C proto */
144 PDC_I2C_MASK_INT = (1 << 5), /* mask I2C interrupt */
145 PDC_I2C_COMPLETE = (1 << 16), /* I2C normal compl. */
146 PDC_I2C_NO_ACK = (1 << 20), /* slave no-ack addr */
147 PDC_DIMM_SPD_SUBADDRESS_START = 0x00,
148 PDC_DIMM_SPD_SUBADDRESS_END = 0x7F,
149 PDC_DIMM_SPD_ROW_NUM = 3,
150 PDC_DIMM_SPD_COLUMN_NUM = 4,
151 PDC_DIMM_SPD_MODULE_ROW = 5,
152 PDC_DIMM_SPD_TYPE = 11,
153 PDC_DIMM_SPD_FRESH_RATE = 12,
154 PDC_DIMM_SPD_BANK_NUM = 17,
155 PDC_DIMM_SPD_CAS_LATENCY = 18,
156 PDC_DIMM_SPD_ATTRIBUTE = 21,
157 PDC_DIMM_SPD_ROW_PRE_CHARGE = 27,
158 PDC_DIMM_SPD_ROW_ACTIVE_DELAY = 28,
159 PDC_DIMM_SPD_RAS_CAS_DELAY = 29,
160 PDC_DIMM_SPD_ACTIVE_PRECHARGE = 30,
161 PDC_DIMM_SPD_SYSTEM_FREQ = 126,
162 PDC_CTL_STATUS = 0x08,
163 PDC_DIMM_WINDOW_CTLR = 0x0C,
164 PDC_TIME_CONTROL = 0x3C,
165 PDC_TIME_PERIOD = 0x40,
166 PDC_TIME_COUNTER = 0x44,
167 PDC_GENERAL_CTLR = 0x484,
168 PCI_PLL_INIT = 0x8A531824,
169 PCI_X_TCOUNT = 0xEE1E5CFF,
170
171 /* PDC_TIME_CONTROL bits */
172 PDC_TIMER_BUZZER = (1 << 10),
173 PDC_TIMER_MODE_PERIODIC = 0, /* bits 9:8 == 00 */
174 PDC_TIMER_MODE_ONCE = (1 << 8), /* bits 9:8 == 01 */
175 PDC_TIMER_ENABLE = (1 << 7),
176 PDC_TIMER_MASK_INT = (1 << 5),
177 PDC_TIMER_SEQ_MASK = 0x1f, /* SEQ ID for timer */
178 PDC_TIMER_DEFAULT = PDC_TIMER_MODE_ONCE |
179 PDC_TIMER_ENABLE |
180 PDC_TIMER_MASK_INT,
1da177e4
LT		 181};
182
f35b5e7c 183#define ECC_ERASE_BUF_SZ (128 * 1024)
1da177e4
LT		 184
185struct pdc_port_priv {
186 u8 dimm_buf[(ATA_PRD_SZ * ATA_MAX_PRD) + 512];
187 u8 *pkt;
188 dma_addr_t pkt_dma;
189};
190
191struct pdc_host_priv {
1da177e4
LT		 192 unsigned int doing_hdma;
193 unsigned int hdma_prod;
194 unsigned int hdma_cons;
195 struct {
196 struct ata_queued_cmd *qc;
197 unsigned int seq;
198 unsigned long pkt_ofs;
199 } hdma[32];
200};
201
202
5796d1c4 203static int pdc_sata_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
67651ee5
JG		 204static void pdc_error_handler(struct ata_port *ap);
205static void pdc_freeze(struct ata_port *ap);
206static void pdc_thaw(struct ata_port *ap);
1da177e4 207static int pdc_port_start(struct ata_port *ap);
95364f36 208static enum ata_completion_errors pdc20621_qc_prep(struct ata_queued_cmd *qc);
057ace5e
JG		 209static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf);
210static void pdc_exec_command_mmio(struct ata_port *ap, const struct ata_taskfile *tf);
4447d351
TH		 211static unsigned int pdc20621_dimm_init(struct ata_host *host);
212static int pdc20621_detect_dimm(struct ata_host *host);
213static unsigned int pdc20621_i2c_read(struct ata_host *host,
1da177e4 214 u32 device, u32 subaddr, u32 *pdata);
4447d351
TH		 215static int pdc20621_prog_dimm0(struct ata_host *host);
216static unsigned int pdc20621_prog_dimm_global(struct ata_host *host);
4447d351 217static void pdc20621_get_from_dimm(struct ata_host *host,
1da177e4 218 void *psource, u32 offset, u32 size);
4447d351 219static void pdc20621_put_to_dimm(struct ata_host *host,
1da177e4
LT		 220 void *psource, u32 offset, u32 size);
221static void pdc20621_irq_clear(struct ata_port *ap);
9363c382 222static unsigned int pdc20621_qc_issue(struct ata_queued_cmd *qc);
67651ee5
JG		 223static int pdc_softreset(struct ata_link *link, unsigned int *class,
224 unsigned long deadline);
225static void pdc_post_internal_cmd(struct ata_queued_cmd *qc);
226static int pdc_check_atapi_dma(struct ata_queued_cmd *qc);
1da177e4
LT		 227
228
25df73d9 229static const struct scsi_host_template pdc_sata_sht = {
68d1d07b 230 ATA_BASE_SHT(DRV_NAME),
1da177e4 231 .sg_tablesize = LIBATA_MAX_PRD,
1da177e4 232 .dma_boundary = ATA_DMA_BOUNDARY,
1da177e4
LT		 233};
234
029cfd6b 235static struct ata_port_operations pdc_20621_ops = {
67651ee5
JG		 236 .inherits = &ata_sff_port_ops,
237
238 .check_atapi_dma = pdc_check_atapi_dma,
1da177e4 239 .qc_prep = pdc20621_qc_prep,
9363c382 240 .qc_issue = pdc20621_qc_issue,
67651ee5
JG		 241
242 .freeze = pdc_freeze,
243 .thaw = pdc_thaw,
244 .softreset = pdc_softreset,
245 .error_handler = pdc_error_handler,
246 .lost_interrupt = ATA_OP_NULL,
247 .post_internal_cmd = pdc_post_internal_cmd,
248
1da177e4 249 .port_start = pdc_port_start,
67651ee5
JG		 250
251 .sff_tf_load = pdc_tf_load_mmio,
252 .sff_exec_command = pdc_exec_command_mmio,
253 .sff_irq_clear = pdc20621_irq_clear,
1da177e4
LT		 254};
255
98ac62de 256static const struct ata_port_info pdc_port_info[] = {
1da177e4
LT		 257 /* board_20621 */
258 {
9cbe056f
SS		 259 .flags = ATA_FLAG_SATA | ATA_FLAG_NO_ATAPI |
260 ATA_FLAG_PIO_POLLING,
14bdef98
EIB		 261 .pio_mask = ATA_PIO4,
262 .mwdma_mask = ATA_MWDMA2,
469248ab 263 .udma_mask = ATA_UDMA6,
1da177e4
LT		 264 .port_ops = &pdc_20621_ops,
265 },
266
267};
268
3b7d697d 269static const struct pci_device_id pdc_sata_pci_tbl[] = {
54bb3a94
JG		 270 { PCI_VDEVICE(PROMISE, 0x6622), board_20621 },
271
1da177e4
LT		 272 { } /* terminate list */
273};
274
1da177e4
LT		 275static struct pci_driver pdc_sata_pci_driver = {
276 .name = DRV_NAME,
277 .id_table = pdc_sata_pci_tbl,
278 .probe = pdc_sata_init_one,
279 .remove = ata_pci_remove_one,
280};
281
282
1da177e4
LT		 283static int pdc_port_start(struct ata_port *ap)
284{
cca3974e 285 struct device *dev = ap->host->dev;
1da177e4 286 struct pdc_port_priv *pp;
1da177e4 287
24dc5f33
TH		 288 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
289 if (!pp)
290 return -ENOMEM;
1da177e4 291
24dc5f33
TH		 292 pp->pkt = dmam_alloc_coherent(dev, 128, &pp->pkt_dma, GFP_KERNEL);
293 if (!pp->pkt)
294 return -ENOMEM;
1da177e4
LT		 295
296 ap->private_data = pp;
297
298 return 0;
1da177e4
LT		 299}
300
7c26deab
SS		 301static inline void pdc20621_ata_sg(u8 *buf, unsigned int portno,
302 unsigned int total_len)
1da177e4
LT		 303{
304 u32 addr;
305 unsigned int dw = PDC_DIMM_APKT_PRD >> 2;
4ca4e439 306 __le32 *buf32 = (__le32 *) buf;
1da177e4
LT		 307
308 /* output ATA packet S/G table */
309 addr = PDC_20621_DIMM_BASE + PDC_20621_DIMM_DATA +
310 (PDC_DIMM_DATA_STEP * portno);
bc21c105 311
1da177e4
LT		 312 buf32[dw] = cpu_to_le32(addr);
313 buf32[dw + 1] = cpu_to_le32(total_len | ATA_PRD_EOT);
1da177e4
LT		 314}
315
7c26deab
SS		 316static inline void pdc20621_host_sg(u8 *buf, unsigned int portno,
317 unsigned int total_len)
1da177e4
LT		 318{
319 u32 addr;
320 unsigned int dw = PDC_DIMM_HPKT_PRD >> 2;
4ca4e439 321 __le32 *buf32 = (__le32 *) buf;
1da177e4
LT		 322
323 /* output Host DMA packet S/G table */
324 addr = PDC_20621_DIMM_BASE + PDC_20621_DIMM_DATA +
325 (PDC_DIMM_DATA_STEP * portno);
326
327 buf32[dw] = cpu_to_le32(addr);
328 buf32[dw + 1] = cpu_to_le32(total_len | ATA_PRD_EOT);
1da177e4
LT		 329}
330
331static inline unsigned int pdc20621_ata_pkt(struct ata_taskfile *tf,
332 unsigned int devno, u8 *buf,
333 unsigned int portno)
334{
335 unsigned int i, dw;
4ca4e439 336 __le32 *buf32 = (__le32 *) buf;
1da177e4
LT		 337 u8 dev_reg;
338
339 unsigned int dimm_sg = PDC_20621_DIMM_BASE +
340 (PDC_DIMM_WINDOW_STEP * portno) +
341 PDC_DIMM_APKT_PRD;
1da177e4
LT		 342
343 i = PDC_DIMM_ATA_PKT;
344
345 /*
346 * Set up ATA packet
347 */
348 if ((tf->protocol == ATA_PROT_DMA) && (!(tf->flags & ATA_TFLAG_WRITE)))
349 buf[i++] = PDC_PKT_READ;
350 else if (tf->protocol == ATA_PROT_NODATA)
351 buf[i++] = PDC_PKT_NODATA;
352 else
353 buf[i++] = 0;
354 buf[i++] = 0; /* reserved */
355 buf[i++] = portno + 1; /* seq. id */
356 buf[i++] = 0xff; /* delay seq. id */
357
358 /* dimm dma S/G, and next-pkt */
359 dw = i >> 2;
360 if (tf->protocol == ATA_PROT_NODATA)
361 buf32[dw] = 0;
362 else
363 buf32[dw] = cpu_to_le32(dimm_sg);
364 buf32[dw + 1] = 0;
365 i += 8;
366
367 if (devno == 0)
368 dev_reg = ATA_DEVICE_OBS;
369 else
370 dev_reg = ATA_DEVICE_OBS | ATA_DEV1;
371
372 /* select device */
373 buf[i++] = (1 << 5) | PDC_PKT_CLEAR_BSY | ATA_REG_DEVICE;
374 buf[i++] = dev_reg;
375
376 /* device control register */
377 buf[i++] = (1 << 5) | PDC_REG_DEVCTL;
378 buf[i++] = tf->ctl;
379
380 return i;
381}
382
383static inline void pdc20621_host_pkt(struct ata_taskfile *tf, u8 *buf,
384 unsigned int portno)
385{
386 unsigned int dw;
4ca4e439
AV		 387 u32 tmp;
388 __le32 *buf32 = (__le32 *) buf;
1da177e4
LT		 389
390 unsigned int host_sg = PDC_20621_DIMM_BASE +
391 (PDC_DIMM_WINDOW_STEP * portno) +
392 PDC_DIMM_HOST_PRD;
393 unsigned int dimm_sg = PDC_20621_DIMM_BASE +
394 (PDC_DIMM_WINDOW_STEP * portno) +
395 PDC_DIMM_HPKT_PRD;
1da177e4
LT		 396
397 dw = PDC_DIMM_HOST_PKT >> 2;
398
399 /*
400 * Set up Host DMA packet
401 */
402 if ((tf->protocol == ATA_PROT_DMA) && (!(tf->flags & ATA_TFLAG_WRITE)))
403 tmp = PDC_PKT_READ;
404 else
405 tmp = 0;
406 tmp |= ((portno + 1 + 4) << 16); /* seq. id */
407 tmp |= (0xff << 24); /* delay seq. id */
408 buf32[dw + 0] = cpu_to_le32(tmp);
409 buf32[dw + 1] = cpu_to_le32(host_sg);
410 buf32[dw + 2] = cpu_to_le32(dimm_sg);
411 buf32[dw + 3] = 0;
1da177e4
LT		 412}
413
414static void pdc20621_dma_prep(struct ata_queued_cmd *qc)
415{
cedc9a47 416 struct scatterlist *sg;
1da177e4
LT		 417 struct ata_port *ap = qc->ap;
418 struct pdc_port_priv *pp = ap->private_data;
0d5ff566
TH		 419 void __iomem *mmio = ap->host->iomap[PDC_MMIO_BAR];
420 void __iomem *dimm_mmio = ap->host->iomap[PDC_DIMM_BAR];
1da177e4 421 unsigned int portno = ap->port_no;
ff2aeb1e 422 unsigned int i, si, idx, total_len = 0, sgt_len;
826cd156 423 __le32 *buf = (__le32 *) &pp->dimm_buf[PDC_DIMM_HEADER_SZ];
1da177e4 424
beec7dbc 425 WARN_ON(!(qc->flags & ATA_QCFLAG_DMAMAP));
1da177e4 426
1da177e4
LT		 427 /* hard-code chip #0 */
428 mmio += PDC_CHIP0_OFS;
429
430 /*
431 * Build S/G table
432 */
1da177e4 433 idx = 0;
ff2aeb1e 434 for_each_sg(qc->sg, sg, qc->n_elem, si) {
cedc9a47
JG		 435 buf[idx++] = cpu_to_le32(sg_dma_address(sg));
436 buf[idx++] = cpu_to_le32(sg_dma_len(sg));
437 total_len += sg_dma_len(sg);
1da177e4
LT		 438 }
439 buf[idx - 1] |= cpu_to_le32(ATA_PRD_EOT);
440 sgt_len = idx * 4;
441
442 /*
443 * Build ATA, host DMA packets
444 */
7c26deab 445 pdc20621_host_sg(&pp->dimm_buf[0], portno, total_len);
1da177e4
LT		 446 pdc20621_host_pkt(&qc->tf, &pp->dimm_buf[0], portno);
447
7c26deab 448 pdc20621_ata_sg(&pp->dimm_buf[0], portno, total_len);
1da177e4
LT		 449 i = pdc20621_ata_pkt(&qc->tf, qc->dev->devno, &pp->dimm_buf[0], portno);
450
451 if (qc->tf.flags & ATA_TFLAG_LBA48)
452 i = pdc_prep_lba48(&qc->tf, &pp->dimm_buf[0], i);
453 else
454 i = pdc_prep_lba28(&qc->tf, &pp->dimm_buf[0], i);
455
456 pdc_pkt_footer(&qc->tf, &pp->dimm_buf[0], i);
457
458 /* copy three S/G tables and two packets to DIMM MMIO window */
459 memcpy_toio(dimm_mmio + (portno * PDC_DIMM_WINDOW_STEP),
460 &pp->dimm_buf, PDC_DIMM_HEADER_SZ);
461 memcpy_toio(dimm_mmio + (portno * PDC_DIMM_WINDOW_STEP) +
462 PDC_DIMM_HOST_PRD,
463 &pp->dimm_buf[PDC_DIMM_HEADER_SZ], sgt_len);
464
465 /* force host FIFO dump */
466 writel(0x00000001, mmio + PDC_20621_GENERAL_CTL);
467
468 readl(dimm_mmio); /* MMIO PCI posting flush */
469
bc21c105
HR		 470 ata_port_dbg(ap, "ata pkt buf ofs %u, prd size %u, mmio copied\n",
471 i, sgt_len);
1da177e4
LT		 472}
473
474static void pdc20621_nodata_prep(struct ata_queued_cmd *qc)
475{
476 struct ata_port *ap = qc->ap;
477 struct pdc_port_priv *pp = ap->private_data;
0d5ff566
TH		 478 void __iomem *mmio = ap->host->iomap[PDC_MMIO_BAR];
479 void __iomem *dimm_mmio = ap->host->iomap[PDC_DIMM_BAR];
1da177e4
LT		 480 unsigned int portno = ap->port_no;
481 unsigned int i;
482
1da177e4
LT		 483 /* hard-code chip #0 */
484 mmio += PDC_CHIP0_OFS;
485
486 i = pdc20621_ata_pkt(&qc->tf, qc->dev->devno, &pp->dimm_buf[0], portno);
487
488 if (qc->tf.flags & ATA_TFLAG_LBA48)
489 i = pdc_prep_lba48(&qc->tf, &pp->dimm_buf[0], i);
490 else
491 i = pdc_prep_lba28(&qc->tf, &pp->dimm_buf[0], i);
492
493 pdc_pkt_footer(&qc->tf, &pp->dimm_buf[0], i);
494
495 /* copy three S/G tables and two packets to DIMM MMIO window */
496 memcpy_toio(dimm_mmio + (portno * PDC_DIMM_WINDOW_STEP),
497 &pp->dimm_buf, PDC_DIMM_HEADER_SZ);
498
499 /* force host FIFO dump */
500 writel(0x00000001, mmio + PDC_20621_GENERAL_CTL);
501
502 readl(dimm_mmio); /* MMIO PCI posting flush */
503
bc21c105 504 ata_port_dbg(ap, "ata pkt buf ofs %u, mmio copied\n", i);
1da177e4
LT		 505}
506
95364f36 507static enum ata_completion_errors pdc20621_qc_prep(struct ata_queued_cmd *qc)
1da177e4
LT		 508{
509 switch (qc->tf.protocol) {
510 case ATA_PROT_DMA:
511 pdc20621_dma_prep(qc);
512 break;
513 case ATA_PROT_NODATA:
514 pdc20621_nodata_prep(qc);
515 break;
516 default:
517 break;
518 }
95364f36
JS		 519
520 return AC_ERR_OK;
1da177e4
LT		 521}
522
523static void __pdc20621_push_hdma(struct ata_queued_cmd *qc,
524 unsigned int seq,
525 u32 pkt_ofs)
526{
527 struct ata_port *ap = qc->ap;
cca3974e 528 struct ata_host *host = ap->host;
0d5ff566 529 void __iomem *mmio = host->iomap[PDC_MMIO_BAR];
1da177e4
LT		 530
531 /* hard-code chip #0 */
532 mmio += PDC_CHIP0_OFS;
533
534 writel(0x00000001, mmio + PDC_20621_SEQCTL + (seq * 4));
535 readl(mmio + PDC_20621_SEQCTL + (seq * 4)); /* flush */
536
537 writel(pkt_ofs, mmio + PDC_HDMA_PKT_SUBMIT);
538 readl(mmio + PDC_HDMA_PKT_SUBMIT); /* flush */
539}
540
541static void pdc20621_push_hdma(struct ata_queued_cmd *qc,
542 unsigned int seq,
543 u32 pkt_ofs)
544{
545 struct ata_port *ap = qc->ap;
cca3974e 546 struct pdc_host_priv *pp = ap->host->private_data;
1da177e4
LT		 547 unsigned int idx = pp->hdma_prod & PDC_HDMA_Q_MASK;
548
549 if (!pp->doing_hdma) {
550 __pdc20621_push_hdma(qc, seq, pkt_ofs);
551 pp->doing_hdma = 1;
552 return;
553 }
554
555 pp->hdma[idx].qc = qc;
556 pp->hdma[idx].seq = seq;
557 pp->hdma[idx].pkt_ofs = pkt_ofs;
558 pp->hdma_prod++;
559}
560
561static void pdc20621_pop_hdma(struct ata_queued_cmd *qc)
562{
563 struct ata_port *ap = qc->ap;
cca3974e 564 struct pdc_host_priv *pp = ap->host->private_data;
1da177e4
LT		 565 unsigned int idx = pp->hdma_cons & PDC_HDMA_Q_MASK;
566
567 /* if nothing on queue, we're done */
568 if (pp->hdma_prod == pp->hdma_cons) {
569 pp->doing_hdma = 0;
570 return;
571 }
572
573 __pdc20621_push_hdma(pp->hdma[idx].qc, pp->hdma[idx].seq,
574 pp->hdma[idx].pkt_ofs);
575 pp->hdma_cons++;
576}
577
1da177e4
LT		 578static void pdc20621_dump_hdma(struct ata_queued_cmd *qc)
579{
580 struct ata_port *ap = qc->ap;
581 unsigned int port_no = ap->port_no;
0d5ff566 582 void __iomem *dimm_mmio = ap->host->iomap[PDC_DIMM_BAR];
1da177e4
LT		 583
584 dimm_mmio += (port_no * PDC_DIMM_WINDOW_STEP);
585 dimm_mmio += PDC_DIMM_HOST_PKT;
586
f11c5403
HR		 587 ata_port_dbg(ap, "HDMA 0x%08X 0x%08X 0x%08X 0x%08X\n",
588 readl(dimm_mmio), readl(dimm_mmio + 4),
589 readl(dimm_mmio + 8), readl(dimm_mmio + 12));
1da177e4 590}
1da177e4
LT		 591
592static void pdc20621_packet_start(struct ata_queued_cmd *qc)
593{
594 struct ata_port *ap = qc->ap;
cca3974e 595 struct ata_host *host = ap->host;
1da177e4 596 unsigned int port_no = ap->port_no;
0d5ff566 597 void __iomem *mmio = host->iomap[PDC_MMIO_BAR];
1da177e4
LT		 598 unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE);
599 u8 seq = (u8) (port_no + 1);
600 unsigned int port_ofs;
601
602 /* hard-code chip #0 */
603 mmio += PDC_CHIP0_OFS;
604
1da177e4
LT		 605 wmb(); /* flush PRD, pkt writes */
606
607 port_ofs = PDC_20621_DIMM_BASE + (PDC_DIMM_WINDOW_STEP * port_no);
608
609 /* if writing, we (1) DMA to DIMM, then (2) do ATA command */
610 if (rw && qc->tf.protocol == ATA_PROT_DMA) {
611 seq += 4;
612
613 pdc20621_dump_hdma(qc);
614 pdc20621_push_hdma(qc, seq, port_ofs + PDC_DIMM_HOST_PKT);
bc21c105 615 ata_port_dbg(ap, "queued ofs 0x%x (%u), seq %u\n",
1da177e4
LT		 616 port_ofs + PDC_DIMM_HOST_PKT,
617 port_ofs + PDC_DIMM_HOST_PKT,
618 seq);
619 } else {
620 writel(0x00000001, mmio + PDC_20621_SEQCTL + (seq * 4));
621 readl(mmio + PDC_20621_SEQCTL + (seq * 4)); /* flush */
622
623 writel(port_ofs + PDC_DIMM_ATA_PKT,
0d5ff566
TH		 624 ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT);
625 readl(ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT);
bc21c105 626 ata_port_dbg(ap, "submitted ofs 0x%x (%u), seq %u\n",
1da177e4
LT		 627 port_ofs + PDC_DIMM_ATA_PKT,
628 port_ofs + PDC_DIMM_ATA_PKT,
629 seq);
630 }
631}
632
9363c382 633static unsigned int pdc20621_qc_issue(struct ata_queued_cmd *qc)
1da177e4
LT		 634{
635 switch (qc->tf.protocol) {
1da177e4 636 case ATA_PROT_NODATA:
19799bfc
DM		 637 if (qc->tf.flags & ATA_TFLAG_POLLING)
638 break;
df561f66 639 fallthrough;
19799bfc 640 case ATA_PROT_DMA:
1da177e4
LT		 641 pdc20621_packet_start(qc);
642 return 0;
643
0dc36888 644 case ATAPI_PROT_DMA:
1da177e4
LT		 645 BUG();
646 break;
647
648 default:
649 break;
650 }
651
9363c382 652 return ata_sff_qc_issue(qc);
1da177e4
LT		 653}
654
5796d1c4
JG		 655static inline unsigned int pdc20621_host_intr(struct ata_port *ap,
656 struct ata_queued_cmd *qc,
1da177e4 657 unsigned int doing_hdma,
ea6ba10b 658 void __iomem *mmio)
1da177e4
LT		 659{
660 unsigned int port_no = ap->port_no;
661 unsigned int port_ofs =
662 PDC_20621_DIMM_BASE + (PDC_DIMM_WINDOW_STEP * port_no);
663 u8 status;
664 unsigned int handled = 0;
665
1da177e4
LT		 666 if ((qc->tf.protocol == ATA_PROT_DMA) && /* read */
667 (!(qc->tf.flags & ATA_TFLAG_WRITE))) {
668
669 /* step two - DMA from DIMM to host */
670 if (doing_hdma) {
bc21c105 671 ata_port_dbg(ap, "read hdma, 0x%x 0x%x\n",
1da177e4
LT		 672 readl(mmio + 0x104), readl(mmio + PDC_HDMA_CTLSTAT));
673 /* get drive status; clear intr; complete txn */
a22e2eb0
AL		 674 qc->err_mask |= ac_err_mask(ata_wait_idle(ap));
675 ata_qc_complete(qc);
1da177e4
LT		 676 pdc20621_pop_hdma(qc);
677 }
678
679 /* step one - exec ATA command */
680 else {
681 u8 seq = (u8) (port_no + 1 + 4);
bc21c105 682 ata_port_dbg(ap, "read ata, 0x%x 0x%x\n",
1da177e4
LT		 683 readl(mmio + 0x104), readl(mmio + PDC_HDMA_CTLSTAT));
684
685 /* submit hdma pkt */
686 pdc20621_dump_hdma(qc);
687 pdc20621_push_hdma(qc, seq,
688 port_ofs + PDC_DIMM_HOST_PKT);
689 }
690 handled = 1;
691
692 } else if (qc->tf.protocol == ATA_PROT_DMA) { /* write */
693
694 /* step one - DMA from host to DIMM */
695 if (doing_hdma) {
696 u8 seq = (u8) (port_no + 1);
bc21c105 697 ata_port_dbg(ap, "write hdma, 0x%x 0x%x\n",
1da177e4
LT		 698 readl(mmio + 0x104), readl(mmio + PDC_HDMA_CTLSTAT));
699
700 /* submit ata pkt */
701 writel(0x00000001, mmio + PDC_20621_SEQCTL + (seq * 4));
702 readl(mmio + PDC_20621_SEQCTL + (seq * 4));
703 writel(port_ofs + PDC_DIMM_ATA_PKT,
0d5ff566
TH		 704 ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT);
705 readl(ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT);
1da177e4
LT		 706 }
707
708 /* step two - execute ATA command */
709 else {
bc21c105 710 ata_port_dbg(ap, "write ata, 0x%x 0x%x\n",
1da177e4
LT		 711 readl(mmio + 0x104), readl(mmio + PDC_HDMA_CTLSTAT));
712 /* get drive status; clear intr; complete txn */
a22e2eb0
AL		 713 qc->err_mask |= ac_err_mask(ata_wait_idle(ap));
714 ata_qc_complete(qc);
1da177e4
LT		 715 pdc20621_pop_hdma(qc);
716 }
717 handled = 1;
718
719 /* command completion, but no data xfer */
720 } else if (qc->tf.protocol == ATA_PROT_NODATA) {
721
9363c382 722 status = ata_sff_busy_wait(ap, ATA_BUSY | ATA_DRQ, 1000);
bc21c105 723 ata_port_dbg(ap, "BUS_NODATA (drv_stat 0x%X)\n", status);
a22e2eb0
AL		 724 qc->err_mask |= ac_err_mask(status);
725 ata_qc_complete(qc);
1da177e4
LT		 726 handled = 1;
727
728 } else {
729 ap->stats.idle_irq++;
730 }
731
732 return handled;
733}
734
735static void pdc20621_irq_clear(struct ata_port *ap)
736{
19799bfc 737 ioread8(ap->ioaddr.status_addr);
1da177e4
LT		 738}
739
5796d1c4 740static irqreturn_t pdc20621_interrupt(int irq, void *dev_instance)
1da177e4 741{
cca3974e 742 struct ata_host *host = dev_instance;
1da177e4
LT		 743 struct ata_port *ap;
744 u32 mask = 0;
745 unsigned int i, tmp, port_no;
746 unsigned int handled = 0;
ea6ba10b 747 void __iomem *mmio_base;
1da177e4 748
bc21c105 749 if (!host || !host->iomap[PDC_MMIO_BAR])
1da177e4 750 return IRQ_NONE;
1da177e4 751
0d5ff566 752 mmio_base = host->iomap[PDC_MMIO_BAR];
1da177e4
LT		 753
754 /* reading should also clear interrupts */
755 mmio_base += PDC_CHIP0_OFS;
756 mask = readl(mmio_base + PDC_20621_SEQMASK);
1da177e4 757
bc21c105 758 if (mask == 0xffffffff)
1da177e4 759 return IRQ_NONE;
bc21c105 760
1da177e4 761 mask &= 0xffff; /* only 16 tags possible */
bc21c105 762 if (!mask)
1da177e4 763 return IRQ_NONE;
1da177e4 764
5796d1c4 765 spin_lock(&host->lock);
1da177e4 766
5796d1c4 767 for (i = 1; i < 9; i++) {
1da177e4
LT		 768 port_no = i - 1;
769 if (port_no > 3)
770 port_no -= 4;
cca3974e 771 if (port_no >= host->n_ports)
1da177e4
LT		 772 ap = NULL;
773 else
cca3974e 774 ap = host->ports[port_no];
1da177e4 775 tmp = mask & (1 << i);
bc21c105
HR		 776 if (ap)
777 ata_port_dbg(ap, "seq %u, tmp %x\n", i, tmp);
3e4ec344 778 if (tmp && ap) {
1da177e4
LT		 779 struct ata_queued_cmd *qc;
780
9af5c9c9 781 qc = ata_qc_from_tag(ap, ap->link.active_tag);
e50362ec 782 if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING)))
1da177e4
LT		 783 handled += pdc20621_host_intr(ap, qc, (i > 4),
784 mmio_base);
785 }
786 }
787
5796d1c4 788 spin_unlock(&host->lock);
1da177e4 789
1da177e4
LT		 790 return IRQ_RETVAL(handled);
791}
792
67651ee5 793static void pdc_freeze(struct ata_port *ap)
1da177e4 794{
67651ee5
JG		 795 void __iomem *mmio = ap->ioaddr.cmd_addr;
796 u32 tmp;
1da177e4 797
67651ee5 798 /* FIXME: if all 4 ATA engines are stopped, also stop HDMA engine */
1da177e4 799
67651ee5
JG		 800 tmp = readl(mmio + PDC_CTLSTAT);
801 tmp |= PDC_MASK_INT;
802 tmp &= ~PDC_DMA_ENABLE;
803 writel(tmp, mmio + PDC_CTLSTAT);
804 readl(mmio + PDC_CTLSTAT); /* flush */
805}
b8f6153e 806
67651ee5
JG		 807static void pdc_thaw(struct ata_port *ap)
808{
809 void __iomem *mmio = ap->ioaddr.cmd_addr;
67651ee5 810 u32 tmp;
1da177e4 811
67651ee5 812 /* FIXME: start HDMA engine, if zero ATA engines running */
1da177e4 813
19799bfc
DM		 814 /* clear IRQ */
815 ioread8(ap->ioaddr.status_addr);
1da177e4 816
67651ee5
JG		 817 /* turn IRQ back on */
818 tmp = readl(mmio + PDC_CTLSTAT);
819 tmp &= ~PDC_MASK_INT;
820 writel(tmp, mmio + PDC_CTLSTAT);
821 readl(mmio + PDC_CTLSTAT); /* flush */
822}
1da177e4 823
67651ee5
JG		 824static void pdc_reset_port(struct ata_port *ap)
825{
826 void __iomem *mmio = ap->ioaddr.cmd_addr + PDC_CTLSTAT;
827 unsigned int i;
828 u32 tmp;
829
830 /* FIXME: handle HDMA copy engine */
831
832 for (i = 11; i > 0; i--) {
833 tmp = readl(mmio);
834 if (tmp & PDC_RESET)
835 break;
836
837 udelay(100);
838
839 tmp |= PDC_RESET;
840 writel(tmp, mmio);
1da177e4
LT		 841 }
842
67651ee5
JG		 843 tmp &= ~PDC_RESET;
844 writel(tmp, mmio);
845 readl(mmio); /* flush */
846}
847
848static int pdc_softreset(struct ata_link *link, unsigned int *class,
849 unsigned long deadline)
850{
851 pdc_reset_port(link->ap);
852 return ata_sff_softreset(link, class, deadline);
853}
854
855static void pdc_error_handler(struct ata_port *ap)
856{
4cb7c6f1 857 if (!ata_port_is_frozen(ap))
67651ee5
JG		 858 pdc_reset_port(ap);
859
fe06e5f9 860 ata_sff_error_handler(ap);
67651ee5
JG		 861}
862
863static void pdc_post_internal_cmd(struct ata_queued_cmd *qc)
864{
865 struct ata_port *ap = qc->ap;
866
867 /* make DMA engine forget about the failed command */
87629312 868 if (qc->flags & ATA_QCFLAG_EH)
67651ee5
JG		 869 pdc_reset_port(ap);
870}
871
872static int pdc_check_atapi_dma(struct ata_queued_cmd *qc)
873{
874 u8 *scsicmd = qc->scsicmd->cmnd;
875 int pio = 1; /* atapi dma off by default */
876
877 /* Whitelist commands that may use DMA. */
878 switch (scsicmd[0]) {
879 case WRITE_12:
880 case WRITE_10:
881 case WRITE_6:
882 case READ_12:
883 case READ_10:
884 case READ_6:
885 case 0xad: /* READ_DVD_STRUCTURE */
886 case 0xbe: /* READ_CD */
887 pio = 0;
888 }
889 /* -45150 (FFFF4FA2) to -1 (FFFFFFFF) shall use PIO mode */
890 if (scsicmd[0] == WRITE_10) {
891 unsigned int lba =
892 (scsicmd[2] << 24) |
893 (scsicmd[3] << 16) |
894 (scsicmd[4] << 8) |
895 scsicmd[5];
896 if (lba >= 0xFFFF4FA2)
897 pio = 1;
898 }
899 return pio;
1da177e4
LT		 900}
901
057ace5e 902static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf)
1da177e4 903{
5796d1c4 904 WARN_ON(tf->protocol == ATA_PROT_DMA ||
19799bfc 905 tf->protocol == ATAPI_PROT_DMA);
9363c382 906 ata_sff_tf_load(ap, tf);
1da177e4
LT		 907}
908
909
057ace5e 910static void pdc_exec_command_mmio(struct ata_port *ap, const struct ata_taskfile *tf)
1da177e4 911{
5796d1c4 912 WARN_ON(tf->protocol == ATA_PROT_DMA ||
19799bfc 913 tf->protocol == ATAPI_PROT_DMA);
9363c382 914 ata_sff_exec_command(ap, tf);
1da177e4
LT		 915}
916
917
0d5ff566 918static void pdc_sata_setup_port(struct ata_ioports *port, void __iomem *base)
1da177e4
LT		 919{
920 port->cmd_addr = base;
921 port->data_addr = base;
922 port->feature_addr =
923 port->error_addr = base + 0x4;
924 port->nsect_addr = base + 0x8;
925 port->lbal_addr = base + 0xc;
926 port->lbam_addr = base + 0x10;
927 port->lbah_addr = base + 0x14;
928 port->device_addr = base + 0x18;
929 port->command_addr =
930 port->status_addr = base + 0x1c;
931 port->altstatus_addr =
932 port->ctl_addr = base + 0x38;
933}
934
935
4447d351 936static void pdc20621_get_from_dimm(struct ata_host *host, void *psource,
1da177e4
LT		 937 u32 offset, u32 size)
938{
939 u32 window_size;
940 u16 idx;
941 u8 page_mask;
942 long dist;
4447d351
TH		 943 void __iomem *mmio = host->iomap[PDC_MMIO_BAR];
944 void __iomem *dimm_mmio = host->iomap[PDC_DIMM_BAR];
1da177e4
LT		 945
946 /* hard-code chip #0 */
947 mmio += PDC_CHIP0_OFS;
948
8a60a071 949 page_mask = 0x00;
5796d1c4 950 window_size = 0x2000 * 4; /* 32K byte uchar size */
8a60a071 951 idx = (u16) (offset / window_size);
1da177e4
LT		 952
953 writel(0x01, mmio + PDC_GENERAL_CTLR);
954 readl(mmio + PDC_GENERAL_CTLR);
955 writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR);
956 readl(mmio + PDC_DIMM_WINDOW_CTLR);
957
958 offset -= (idx * window_size);
959 idx++;
8a60a071 960 dist = ((long) (window_size - (offset + size))) >= 0 ? size :
1da177e4 961 (long) (window_size - offset);
d5185d65 962 memcpy_fromio(psource, dimm_mmio + offset / 4, dist);
1da177e4 963
8a60a071 964 psource += dist;
1da177e4
LT		 965 size -= dist;
966 for (; (long) size >= (long) window_size ;) {
967 writel(0x01, mmio + PDC_GENERAL_CTLR);
968 readl(mmio + PDC_GENERAL_CTLR);
969 writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR);
970 readl(mmio + PDC_DIMM_WINDOW_CTLR);
d5185d65 971 memcpy_fromio(psource, dimm_mmio, window_size / 4);
1da177e4
LT		 972 psource += window_size;
973 size -= window_size;
5796d1c4 974 idx++;
1da177e4
LT		 975 }
976
977 if (size) {
978 writel(0x01, mmio + PDC_GENERAL_CTLR);
979 readl(mmio + PDC_GENERAL_CTLR);
980 writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR);
981 readl(mmio + PDC_DIMM_WINDOW_CTLR);
d5185d65 982 memcpy_fromio(psource, dimm_mmio, size / 4);
1da177e4
LT		 983 }
984}
1da177e4
LT		 985
986
4447d351 987static void pdc20621_put_to_dimm(struct ata_host *host, void *psource,
1da177e4
LT		 988 u32 offset, u32 size)
989{
990 u32 window_size;
991 u16 idx;
992 u8 page_mask;
993 long dist;
4447d351
TH		 994 void __iomem *mmio = host->iomap[PDC_MMIO_BAR];
995 void __iomem *dimm_mmio = host->iomap[PDC_DIMM_BAR];
1da177e4 996
8a60a071 997 /* hard-code chip #0 */
1da177e4
LT		 998 mmio += PDC_CHIP0_OFS;
999
8a60a071 1000 page_mask = 0x00;
5796d1c4 1001 window_size = 0x2000 * 4; /* 32K byte uchar size */
1da177e4
LT		 1002 idx = (u16) (offset / window_size);
1003
1004 writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR);
1005 readl(mmio + PDC_DIMM_WINDOW_CTLR);
8a60a071 1006 offset -= (idx * window_size);
1da177e4
LT		 1007 idx++;
1008 dist = ((long)(s32)(window_size - (offset + size))) >= 0 ? size :
1009 (long) (window_size - offset);
a9afd7cd 1010 memcpy_toio(dimm_mmio + offset / 4, psource, dist);
1da177e4
LT		 1011 writel(0x01, mmio + PDC_GENERAL_CTLR);
1012 readl(mmio + PDC_GENERAL_CTLR);
1013
8a60a071 1014 psource += dist;
1da177e4
LT		 1015 size -= dist;
1016 for (; (long) size >= (long) window_size ;) {
1017 writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR);
1018 readl(mmio + PDC_DIMM_WINDOW_CTLR);
a9afd7cd 1019 memcpy_toio(dimm_mmio, psource, window_size / 4);
1da177e4
LT		 1020 writel(0x01, mmio + PDC_GENERAL_CTLR);
1021 readl(mmio + PDC_GENERAL_CTLR);
1022 psource += window_size;
1023 size -= window_size;
5796d1c4 1024 idx++;
1da177e4 1025 }
8a60a071 1026
1da177e4
LT		 1027 if (size) {
1028 writel(((idx) << page_mask), mmio + PDC_DIMM_WINDOW_CTLR);
1029 readl(mmio + PDC_DIMM_WINDOW_CTLR);
a9afd7cd 1030 memcpy_toio(dimm_mmio, psource, size / 4);
1da177e4
LT		 1031 writel(0x01, mmio + PDC_GENERAL_CTLR);
1032 readl(mmio + PDC_GENERAL_CTLR);
1033 }
1034}
1035
1036
4447d351 1037static unsigned int pdc20621_i2c_read(struct ata_host *host, u32 device,
1da177e4
LT		 1038 u32 subaddr, u32 *pdata)
1039{
4447d351 1040 void __iomem *mmio = host->iomap[PDC_MMIO_BAR];
1da177e4 1041 u32 i2creg = 0;
8a60a071 1042 u32 status;
5796d1c4 1043 u32 count = 0;
1da177e4
LT		 1044
1045 /* hard-code chip #0 */
1046 mmio += PDC_CHIP0_OFS;
1047
1048 i2creg |= device << 24;
1049 i2creg |= subaddr << 16;
1050
1051 /* Set the device and subaddress */
b2d46b61
JG		 1052 writel(i2creg, mmio + PDC_I2C_ADDR_DATA);
1053 readl(mmio + PDC_I2C_ADDR_DATA);
1da177e4
LT		 1054
1055 /* Write Control to perform read operation, mask int */
8a60a071 1056 writel(PDC_I2C_READ | PDC_I2C_START | PDC_I2C_MASK_INT,
b2d46b61 1057 mmio + PDC_I2C_CONTROL);
1da177e4
LT		 1058
1059 for (count = 0; count <= 1000; count ++) {
b2d46b61 1060 status = readl(mmio + PDC_I2C_CONTROL);
1da177e4 1061 if (status & PDC_I2C_COMPLETE) {
b2d46b61 1062 status = readl(mmio + PDC_I2C_ADDR_DATA);
1da177e4
LT		 1063 break;
1064 } else if (count == 1000)
1065 return 0;
1066 }
1067
1068 *pdata = (status >> 8) & 0x000000ff;
8a60a071 1069 return 1;
1da177e4
LT		 1070}
1071
1072
4447d351 1073static int pdc20621_detect_dimm(struct ata_host *host)
1da177e4 1074{
5796d1c4 1075 u32 data = 0;
4447d351 1076 if (pdc20621_i2c_read(host, PDC_DIMM0_SPD_DEV_ADDRESS,
1da177e4 1077 PDC_DIMM_SPD_SYSTEM_FREQ, &data)) {
5796d1c4 1078 if (data == 100)
1da177e4 1079 return 100;
5796d1c4 1080 } else
1da177e4 1081 return 0;
8a60a071 1082
4447d351 1083 if (pdc20621_i2c_read(host, PDC_DIMM0_SPD_DEV_ADDRESS, 9, &data)) {
b447916e 1084 if (data <= 0x75)
1da177e4 1085 return 133;
5796d1c4 1086 } else
1da177e4 1087 return 0;
8a60a071 1088
5796d1c4 1089 return 0;
1da177e4
LT		 1090}
1091
1092
4447d351 1093static int pdc20621_prog_dimm0(struct ata_host *host)
1da177e4
LT		 1094{
1095 u32 spd0[50];
1096 u32 data = 0;
5796d1c4
JG		 1097 int size, i;
1098 u8 bdimmsize;
4447d351 1099 void __iomem *mmio = host->iomap[PDC_MMIO_BAR];
1da177e4
LT		 1100 static const struct {
1101 unsigned int reg;
1102 unsigned int ofs;
1103 } pdc_i2c_read_data [] = {
8a60a071 1104 { PDC_DIMM_SPD_TYPE, 11 },
1da177e4 1105 { PDC_DIMM_SPD_FRESH_RATE, 12 },
8a60a071 1106 { PDC_DIMM_SPD_COLUMN_NUM, 4 },
1da177e4
LT		 1107 { PDC_DIMM_SPD_ATTRIBUTE, 21 },
1108 { PDC_DIMM_SPD_ROW_NUM, 3 },
1109 { PDC_DIMM_SPD_BANK_NUM, 17 },
1110 { PDC_DIMM_SPD_MODULE_ROW, 5 },
1111 { PDC_DIMM_SPD_ROW_PRE_CHARGE, 27 },
1112 { PDC_DIMM_SPD_ROW_ACTIVE_DELAY, 28 },
1113 { PDC_DIMM_SPD_RAS_CAS_DELAY, 29 },
1114 { PDC_DIMM_SPD_ACTIVE_PRECHARGE, 30 },
8a60a071 1115 { PDC_DIMM_SPD_CAS_LATENCY, 18 },
1da177e4
LT		 1116 };
1117
1118 /* hard-code chip #0 */
1119 mmio += PDC_CHIP0_OFS;
1120
5796d1c4 1121 for (i = 0; i < ARRAY_SIZE(pdc_i2c_read_data); i++)
4447d351 1122 pdc20621_i2c_read(host, PDC_DIMM0_SPD_DEV_ADDRESS,
8a60a071 1123 pdc_i2c_read_data[i].reg,
1da177e4 1124 &spd0[pdc_i2c_read_data[i].ofs]);
8a60a071 1125
5796d1c4
JG		 1126 data |= (spd0[4] - 8) | ((spd0[21] != 0) << 3) | ((spd0[3]-11) << 4);
1127 data |= ((spd0[17] / 4) << 6) | ((spd0[5] / 2) << 7) |
1da177e4 1128 ((((spd0[27] + 9) / 10) - 1) << 8) ;
5796d1c4 1129 data |= (((((spd0[29] > spd0[28])
8a60a071 1130 ? spd0[29] : spd0[28]) + 9) / 10) - 1) << 10;
5796d1c4 1131 data |= ((spd0[30] - spd0[29] + 9) / 10 - 2) << 12;
8a60a071 1132
5796d1c4 1133 if (spd0[18] & 0x08)
1da177e4 1134 data |= ((0x03) << 14);
5796d1c4 1135 else if (spd0[18] & 0x04)
1da177e4 1136 data |= ((0x02) << 14);
5796d1c4 1137 else if (spd0[18] & 0x01)
1da177e4 1138 data |= ((0x01) << 14);
5796d1c4 1139 else
1da177e4
LT		 1140 data |= (0 << 14);
1141
5796d1c4 1142 /*
1da177e4
LT		 1143 Calculate the size of bDIMMSize (power of 2) and
1144 merge the DIMM size by program start/end address.
1145 */
1146
5796d1c4
JG		 1147 bdimmsize = spd0[4] + (spd0[5] / 2) + spd0[3] + (spd0[17] / 2) + 3;
1148 size = (1 << bdimmsize) >> 20; /* size = xxx(MB) */
1149 data |= (((size / 16) - 1) << 16);
1150 data |= (0 << 23);
1da177e4 1151 data |= 8;
5796d1c4 1152 writel(data, mmio + PDC_DIMM0_CONTROL);
b2d46b61 1153 readl(mmio + PDC_DIMM0_CONTROL);
5796d1c4 1154 return size;
1da177e4
LT		 1155}
1156
1157
4447d351 1158static unsigned int pdc20621_prog_dimm_global(struct ata_host *host)
1da177e4
LT		 1159{
1160 u32 data, spd0;
0d5ff566 1161 int error, i;
4447d351 1162 void __iomem *mmio = host->iomap[PDC_MMIO_BAR];
1da177e4
LT		 1163
1164 /* hard-code chip #0 */
5796d1c4 1165 mmio += PDC_CHIP0_OFS;
1da177e4 1166
5796d1c4 1167 /*
1da177e4
LT		 1168 Set To Default : DIMM Module Global Control Register (0x022259F1)
1169 DIMM Arbitration Disable (bit 20)
1170 DIMM Data/Control Output Driving Selection (bit12 - bit15)
1171 Refresh Enable (bit 17)
1172 */
1173
8a60a071 1174 data = 0x022259F1;
b2d46b61
JG		 1175 writel(data, mmio + PDC_SDRAM_CONTROL);
1176 readl(mmio + PDC_SDRAM_CONTROL);
1da177e4
LT		 1177
1178 /* Turn on for ECC */
bb44e154
TB		 1179 if (!pdc20621_i2c_read(host, PDC_DIMM0_SPD_DEV_ADDRESS,
1180 PDC_DIMM_SPD_TYPE, &spd0)) {
16d6623f
HR		 1181 dev_err(host->dev,
1182 "Failed in i2c read: device=%#x, subaddr=%#x\n",
1183 PDC_DIMM0_SPD_DEV_ADDRESS, PDC_DIMM_SPD_TYPE);
bb44e154
TB		 1184 return 1;
1185 }
1da177e4
LT		 1186 if (spd0 == 0x02) {
1187 data |= (0x01 << 16);
b2d46b61
JG		 1188 writel(data, mmio + PDC_SDRAM_CONTROL);
1189 readl(mmio + PDC_SDRAM_CONTROL);
16d6623f 1190 dev_err(host->dev, "Local DIMM ECC Enabled\n");
5796d1c4 1191 }
1da177e4 1192
5796d1c4
JG		 1193 /* DIMM Initialization Select/Enable (bit 18/19) */
1194 data &= (~(1<<18));
1195 data |= (1<<19);
1196 writel(data, mmio + PDC_SDRAM_CONTROL);
1da177e4 1197
5796d1c4
JG		 1198 error = 1;
1199 for (i = 1; i <= 10; i++) { /* polling ~5 secs */
b2d46b61 1200 data = readl(mmio + PDC_SDRAM_CONTROL);
1da177e4 1201 if (!(data & (1<<19))) {
5796d1c4
JG		 1202 error = 0;
1203 break;
1da177e4
LT		 1204 }
1205 msleep(i*100);
5796d1c4
JG		 1206 }
1207 return error;
1da177e4 1208}
8a60a071 1209
1da177e4 1210
4447d351 1211static unsigned int pdc20621_dimm_init(struct ata_host *host)
1da177e4 1212{
8a60a071 1213 int speed, size, length;
5796d1c4 1214 u32 addr, spd0, pci_status;
5796d1c4
JG		 1215 u32 time_period = 0;
1216 u32 tcount = 0;
1217 u32 ticks = 0;
1218 u32 clock = 0;
1219 u32 fparam = 0;
4447d351 1220 void __iomem *mmio = host->iomap[PDC_MMIO_BAR];
1da177e4
LT		 1221
1222 /* hard-code chip #0 */
5796d1c4 1223 mmio += PDC_CHIP0_OFS;
1da177e4
LT		 1224
1225 /* Initialize PLL based upon PCI Bus Frequency */
1226
1227 /* Initialize Time Period Register */
1228 writel(0xffffffff, mmio + PDC_TIME_PERIOD);
1229 time_period = readl(mmio + PDC_TIME_PERIOD);
bc21c105 1230 dev_dbg(host->dev, "Time Period Register (0x40): 0x%x\n", time_period);
1da177e4
LT		 1231
1232 /* Enable timer */
b2d46b61 1233 writel(PDC_TIMER_DEFAULT, mmio + PDC_TIME_CONTROL);
1da177e4
LT		 1234 readl(mmio + PDC_TIME_CONTROL);
1235
1236 /* Wait 3 seconds */
1237 msleep(3000);
1238
8a60a071 1239 /*
1da177e4
LT		 1240 When timer is enabled, counter is decreased every internal
1241 clock cycle.
1242 */
1243
1244 tcount = readl(mmio + PDC_TIME_COUNTER);
bc21c105 1245 dev_dbg(host->dev, "Time Counter Register (0x44): 0x%x\n", tcount);
1da177e4 1246
8a60a071 1247 /*
1da177e4
LT		 1248 If SX4 is on PCI-X bus, after 3 seconds, the timer counter
1249 register should be >= (0xffffffff - 3x10^8).
1250 */
b447916e 1251 if (tcount >= PCI_X_TCOUNT) {
1da177e4 1252 ticks = (time_period - tcount);
bc21c105 1253 dev_dbg(host->dev, "Num counters 0x%x (%d)\n", ticks, ticks);
8a60a071 1254
1da177e4 1255 clock = (ticks / 300000);
bc21c105
HR		 1256 dev_dbg(host->dev, "10 * Internal clk = 0x%x (%d)\n",
1257 clock, clock);
8a60a071 1258
1da177e4 1259 clock = (clock * 33);
bc21c105
HR		 1260 dev_dbg(host->dev, "10 * Internal clk * 33 = 0x%x (%d)\n",
1261 clock, clock);
1da177e4
LT		 1262
1263 /* PLL F Param (bit 22:16) */
1264 fparam = (1400000 / clock) - 2;
bc21c105 1265 dev_dbg(host->dev, "PLL F Param: 0x%x (%d)\n", fparam, fparam);
8a60a071 1266
1da177e4
LT		 1267 /* OD param = 0x2 (bit 31:30), R param = 0x5 (bit 29:25) */
1268 pci_status = (0x8a001824 | (fparam << 16));
1269 } else
1270 pci_status = PCI_PLL_INIT;
1271
1272 /* Initialize PLL. */
bc21c105 1273 dev_dbg(host->dev, "pci_status: 0x%x\n", pci_status);
1da177e4
LT		 1274 writel(pci_status, mmio + PDC_CTL_STATUS);
1275 readl(mmio + PDC_CTL_STATUS);
1276
8a60a071 1277 /*
1da177e4
LT		 1278 Read SPD of DIMM by I2C interface,
1279 and program the DIMM Module Controller.
1280 */
4447d351 1281 if (!(speed = pdc20621_detect_dimm(host))) {
16d6623f 1282 dev_err(host->dev, "Detect Local DIMM Fail\n");
1da177e4 1283 return 1; /* DIMM error */
5796d1c4 1284 }
bc21c105 1285 dev_dbg(host->dev, "Local DIMM Speed = %d\n", speed);
1da177e4 1286
5796d1c4 1287 /* Programming DIMM0 Module Control Register (index_CID0:80h) */
4447d351 1288 size = pdc20621_prog_dimm0(host);
bc21c105 1289 dev_dbg(host->dev, "Local DIMM Size = %dMB\n", size);
1da177e4 1290
5796d1c4 1291 /* Programming DIMM Module Global Control Register (index_CID0:88h) */
4447d351 1292 if (pdc20621_prog_dimm_global(host)) {
bc21c105
HR		 1293 dev_err(host->dev,
1294 "Programming DIMM Module Global Control Register Fail\n");
1da177e4 1295 return 1;
5796d1c4 1296 }
1da177e4 1297
f11c5403 1298 if (dimm_test) {
5796d1c4
JG		 1299 u8 test_parttern1[40] =
1300 {0x55,0xAA,'P','r','o','m','i','s','e',' ',
1301 'N','o','t',' ','Y','e','t',' ',
1302 'D','e','f','i','n','e','d',' ',
1303 '1','.','1','0',
1304 '9','8','0','3','1','6','1','2',0,0};
1da177e4
LT		 1305 u8 test_parttern2[40] = {0};
1306
5796d1c4
JG		 1307 pdc20621_put_to_dimm(host, test_parttern2, 0x10040, 40);
1308 pdc20621_put_to_dimm(host, test_parttern2, 0x40, 40);
1da177e4 1309
5796d1c4
JG		 1310 pdc20621_put_to_dimm(host, test_parttern1, 0x10040, 40);
1311 pdc20621_get_from_dimm(host, test_parttern2, 0x40, 40);
f11c5403 1312 dev_info(host->dev, "DIMM test pattern 1: %x, %x, %s\n", test_parttern2[0],
1da177e4 1313 test_parttern2[1], &(test_parttern2[2]));
5796d1c4 1314 pdc20621_get_from_dimm(host, test_parttern2, 0x10040,
1da177e4 1315 40);
f11c5403
HR		 1316 dev_info(host->dev, "DIMM test pattern 2: %x, %x, %s\n",
1317 test_parttern2[0],
1318 test_parttern2[1], &(test_parttern2[2]));
1da177e4 1319
5796d1c4
JG		 1320 pdc20621_put_to_dimm(host, test_parttern1, 0x40, 40);
1321 pdc20621_get_from_dimm(host, test_parttern2, 0x40, 40);
f11c5403
HR		 1322 dev_info(host->dev, "DIMM test pattern 3: %x, %x, %s\n",
1323 test_parttern2[0],
1324 test_parttern2[1], &(test_parttern2[2]));
1da177e4 1325 }
1da177e4
LT		 1326
1327 /* ECC initiliazation. */
1328
bb44e154
TB		 1329 if (!pdc20621_i2c_read(host, PDC_DIMM0_SPD_DEV_ADDRESS,
1330 PDC_DIMM_SPD_TYPE, &spd0)) {
bc21c105
HR		 1331 dev_err(host->dev,
1332 "Failed in i2c read: device=%#x, subaddr=%#x\n",
bb44e154
TB		 1333 PDC_DIMM0_SPD_DEV_ADDRESS, PDC_DIMM_SPD_TYPE);
1334 return 1;
1335 }
1da177e4 1336 if (spd0 == 0x02) {
f35b5e7c 1337 void *buf;
bc21c105 1338 dev_dbg(host->dev, "Start ECC initialization\n");
1da177e4
LT		 1339 addr = 0;
1340 length = size * 1024 * 1024;
f35b5e7c 1341 buf = kzalloc(ECC_ERASE_BUF_SZ, GFP_KERNEL);
427cc61a
IY		 1342 if (!buf)
1343 return 1;
1da177e4 1344 while (addr < length) {
f35b5e7c
AB		 1345 pdc20621_put_to_dimm(host, buf, addr,
1346 ECC_ERASE_BUF_SZ);
1347 addr += ECC_ERASE_BUF_SZ;
1da177e4 1348 }
f35b5e7c 1349 kfree(buf);
bc21c105 1350 dev_dbg(host->dev, "Finish ECC initialization\n");
1da177e4
LT		 1351 }
1352 return 0;
1353}
1354
1355
4447d351 1356static void pdc_20621_init(struct ata_host *host)
1da177e4
LT		 1357{
1358 u32 tmp;
4447d351 1359 void __iomem *mmio = host->iomap[PDC_MMIO_BAR];
1da177e4
LT		 1360
1361 /* hard-code chip #0 */
1362 mmio += PDC_CHIP0_OFS;
1363
1364 /*
1365 * Select page 0x40 for our 32k DIMM window
1366 */
1367 tmp = readl(mmio + PDC_20621_DIMM_WINDOW) & 0xffff0000;
1368 tmp |= PDC_PAGE_WINDOW; /* page 40h; arbitrarily selected */
1369 writel(tmp, mmio + PDC_20621_DIMM_WINDOW);
1370
1371 /*
1372 * Reset Host DMA
1373 */
1374 tmp = readl(mmio + PDC_HDMA_CTLSTAT);
1375 tmp |= PDC_RESET;
1376 writel(tmp, mmio + PDC_HDMA_CTLSTAT);
1377 readl(mmio + PDC_HDMA_CTLSTAT); /* flush */
1378
1379 udelay(10);
1380
1381 tmp = readl(mmio + PDC_HDMA_CTLSTAT);
1382 tmp &= ~PDC_RESET;
1383 writel(tmp, mmio + PDC_HDMA_CTLSTAT);
1384 readl(mmio + PDC_HDMA_CTLSTAT); /* flush */
1385}
1386
5796d1c4
JG		 1387static int pdc_sata_init_one(struct pci_dev *pdev,
1388 const struct pci_device_id *ent)
1da177e4 1389{
4447d351
TH		 1390 const struct ata_port_info *ppi[] =
1391 { &pdc_port_info[ent->driver_data], NULL };
1392 struct ata_host *host;
24dc5f33 1393 struct pdc_host_priv *hpriv;
cbcdd875 1394 int i, rc;
1da177e4 1395
06296a1e 1396 ata_print_version_once(&pdev->dev, DRV_VERSION);
1da177e4 1397
4447d351
TH		 1398 /* allocate host */
1399 host = ata_host_alloc_pinfo(&pdev->dev, ppi, 4);
1400 hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL);
1401 if (!host || !hpriv)
1402 return -ENOMEM;
1403
1404 host->private_data = hpriv;
1405
1406 /* acquire resources and fill host */
24dc5f33 1407 rc = pcim_enable_device(pdev);
1da177e4
LT		 1408 if (rc)
1409 return rc;
1410
0d5ff566
TH		 1411 rc = pcim_iomap_regions(pdev, (1 << PDC_MMIO_BAR) | (1 << PDC_DIMM_BAR),
1412 DRV_NAME);
1413 if (rc == -EBUSY)
24dc5f33 1414 pcim_pin_device(pdev);
0d5ff566 1415 if (rc)
24dc5f33 1416 return rc;
4447d351
TH		 1417 host->iomap = pcim_iomap_table(pdev);
1418
cbcdd875
TH		 1419 for (i = 0; i < 4; i++) {
1420 struct ata_port *ap = host->ports[i];
1421 void __iomem *base = host->iomap[PDC_MMIO_BAR] + PDC_CHIP0_OFS;
1422 unsigned int offset = 0x200 + i * 0x80;
1423
1424 pdc_sata_setup_port(&ap->ioaddr, base + offset);
1425
1426 ata_port_pbar_desc(ap, PDC_MMIO_BAR, -1, "mmio");
1427 ata_port_pbar_desc(ap, PDC_DIMM_BAR, -1, "dimm");
1428 ata_port_pbar_desc(ap, PDC_MMIO_BAR, offset, "port");
1429 }
1da177e4 1430
4447d351 1431 /* configure and activate */
b5e55556 1432 rc = dma_set_mask_and_coherent(&pdev->dev, ATA_DMA_MASK);
1da177e4 1433 if (rc)
24dc5f33 1434 return rc;
1da177e4 1435
4447d351 1436 if (pdc20621_dimm_init(host))
24dc5f33 1437 return -ENOMEM;
4447d351 1438 pdc_20621_init(host);
1da177e4
LT		 1439
1440 pci_set_master(pdev);
4447d351
TH		 1441 return ata_host_activate(host, pdev->irq, pdc20621_interrupt,
1442 IRQF_SHARED, &pdc_sata_sht);
1da177e4
LT		 1443}
1444
2fc75da0 1445module_pci_driver(pdc_sata_pci_driver);
1da177e4
LT		 1446
1447MODULE_AUTHOR("Jeff Garzik");
1448MODULE_DESCRIPTION("Promise SATA low-level driver");
1449MODULE_LICENSE("GPL");
1450MODULE_DEVICE_TABLE(pci, pdc_sata_pci_tbl);
1451MODULE_VERSION(DRV_VERSION);
Linux 6.x block layer and io_uring tree(s)