[linux-2.6-block.git] / drivers / ata / sata_svw.c

// SPDX-License-Identifier: GPL-2.0-or-later
/*
 *  sata_svw.c - ServerWorks / Apple K2 SATA
 *
 *  Maintained by: Benjamin Herrenschmidt <benh@kernel.crashing.org> and
 *		   Jeff Garzik <jgarzik@pobox.com>
 *  		    Please ALWAYS copy linux-ide@vger.kernel.org
 *		    on emails.
 *
 *  Copyright 2003 Benjamin Herrenschmidt <benh@kernel.crashing.org>
 *
 *  Bits from Jeff Garzik, Copyright RedHat, Inc.
 *
 *  This driver probably works with non-Apple versions of the
 *  Broadcom chipset...
 *
 *  libata documentation is available via 'make {ps|pdf}docs',
 *  as Documentation/driver-api/libata.rst
 *
 *  Hardware documentation available under NDA.
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/blkdev.h>
#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/device.h>
#include <scsi/scsi_host.h>
#include <scsi/scsi_cmnd.h>
#include <scsi/scsi.h>
#include <linux/libata.h>
#include <linux/of.h>
#include <linux/of_address.h>

#define DRV_NAME	"sata_svw"
#define DRV_VERSION	"2.3"

enum {
	/* ap->flags bits */
	K2_FLAG_SATA_8_PORTS		= (1 << 24),
	K2_FLAG_NO_ATAPI_DMA		= (1 << 25),
	K2_FLAG_BAR_POS_3			= (1 << 26),

	/* Taskfile registers offsets */
	K2_SATA_TF_CMD_OFFSET		= 0x00,
	K2_SATA_TF_DATA_OFFSET		= 0x00,
	K2_SATA_TF_ERROR_OFFSET		= 0x04,
	K2_SATA_TF_NSECT_OFFSET		= 0x08,
	K2_SATA_TF_LBAL_OFFSET		= 0x0c,
	K2_SATA_TF_LBAM_OFFSET		= 0x10,
	K2_SATA_TF_LBAH_OFFSET		= 0x14,
	K2_SATA_TF_DEVICE_OFFSET	= 0x18,
	K2_SATA_TF_CMDSTAT_OFFSET      	= 0x1c,
	K2_SATA_TF_CTL_OFFSET		= 0x20,

	/* DMA base */
	K2_SATA_DMA_CMD_OFFSET		= 0x30,

	/* SCRs base */
	K2_SATA_SCR_STATUS_OFFSET	= 0x40,
	K2_SATA_SCR_ERROR_OFFSET	= 0x44,
	K2_SATA_SCR_CONTROL_OFFSET	= 0x48,

	/* Others */
	K2_SATA_SICR1_OFFSET		= 0x80,
	K2_SATA_SICR2_OFFSET		= 0x84,
	K2_SATA_SIM_OFFSET		= 0x88,

	/* Port stride */
	K2_SATA_PORT_OFFSET		= 0x100,

	chip_svw4			= 0,
	chip_svw8			= 1,
	chip_svw42			= 2,	/* bar 3 */
	chip_svw43			= 3,	/* bar 5 */
};

static u8 k2_stat_check_status(struct ata_port *ap);


static int k2_sata_check_atapi_dma(struct ata_queued_cmd *qc)
{
	u8 cmnd = qc->scsicmd->cmnd[0];

	if (qc->ap->flags & K2_FLAG_NO_ATAPI_DMA)
		return -1;	/* ATAPI DMA not supported */
	else {
		switch (cmnd) {
		case READ_10:
		case READ_12:
		case READ_16:
		case WRITE_10:
		case WRITE_12:
		case WRITE_16:
			return 0;

		default:
			return -1;
		}

	}
}

static int k2_sata_scr_read(struct ata_link *link,
			    unsigned int sc_reg, u32 *val)
{
	if (sc_reg > SCR_CONTROL)
		return -EINVAL;
	*val = readl(link->ap->ioaddr.scr_addr + (sc_reg * 4));
	return 0;
}


static int k2_sata_scr_write(struct ata_link *link,
			     unsigned int sc_reg, u32 val)
{
	if (sc_reg > SCR_CONTROL)
		return -EINVAL;
	writel(val, link->ap->ioaddr.scr_addr + (sc_reg * 4));
	return 0;
}

static int k2_sata_softreset(struct ata_link *link,
			     unsigned int *class, unsigned long deadline)
{
	u8 dmactl;
	void __iomem *mmio = link->ap->ioaddr.bmdma_addr;

	dmactl = readb(mmio + ATA_DMA_CMD);

	/* Clear the start bit */
	if (dmactl & ATA_DMA_START) {
		dmactl &= ~ATA_DMA_START;
		writeb(dmactl, mmio + ATA_DMA_CMD);
	}

	return ata_sff_softreset(link, class, deadline);
}

static int k2_sata_hardreset(struct ata_link *link,
			     unsigned int *class, unsigned long deadline)
{
	u8 dmactl;
	void __iomem *mmio = link->ap->ioaddr.bmdma_addr;

	dmactl = readb(mmio + ATA_DMA_CMD);

	/* Clear the start bit */
	if (dmactl & ATA_DMA_START) {
		dmactl &= ~ATA_DMA_START;
		writeb(dmactl, mmio + ATA_DMA_CMD);
	}

	return sata_sff_hardreset(link, class, deadline);
}

static void k2_sata_tf_load(struct ata_port *ap, const struct ata_taskfile *tf)
{
	struct ata_ioports *ioaddr = &ap->ioaddr;
	unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR;

	if (tf->ctl != ap->last_ctl) {
		writeb(tf->ctl, ioaddr->ctl_addr);
		ap->last_ctl = tf->ctl;
		ata_wait_idle(ap);
	}
	if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) {
		writew(tf->feature | (((u16)tf->hob_feature) << 8),
		       ioaddr->feature_addr);
		writew(tf->nsect | (((u16)tf->hob_nsect) << 8),
		       ioaddr->nsect_addr);
		writew(tf->lbal | (((u16)tf->hob_lbal) << 8),
		       ioaddr->lbal_addr);
		writew(tf->lbam | (((u16)tf->hob_lbam) << 8),
		       ioaddr->lbam_addr);
		writew(tf->lbah | (((u16)tf->hob_lbah) << 8),
		       ioaddr->lbah_addr);
	} else if (is_addr) {
		writew(tf->feature, ioaddr->feature_addr);
		writew(tf->nsect, ioaddr->nsect_addr);
		writew(tf->lbal, ioaddr->lbal_addr);
		writew(tf->lbam, ioaddr->lbam_addr);
		writew(tf->lbah, ioaddr->lbah_addr);
	}

	if (tf->flags & ATA_TFLAG_DEVICE)
		writeb(tf->device, ioaddr->device_addr);

	ata_wait_idle(ap);
}


static void k2_sata_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
{
	struct ata_ioports *ioaddr = &ap->ioaddr;
	u16 nsect, lbal, lbam, lbah, error;

	tf->status = k2_stat_check_status(ap);
	tf->device = readw(ioaddr->device_addr);
	error = readw(ioaddr->error_addr);
	nsect = readw(ioaddr->nsect_addr);
	lbal = readw(ioaddr->lbal_addr);
	lbam = readw(ioaddr->lbam_addr);
	lbah = readw(ioaddr->lbah_addr);

	tf->error = error;
	tf->nsect = nsect;
	tf->lbal = lbal;
	tf->lbam = lbam;
	tf->lbah = lbah;

	if (tf->flags & ATA_TFLAG_LBA48) {
		tf->hob_feature = error >> 8;
		tf->hob_nsect = nsect >> 8;
		tf->hob_lbal = lbal >> 8;
		tf->hob_lbam = lbam >> 8;
		tf->hob_lbah = lbah >> 8;
	}
}

/**
 *	k2_bmdma_setup_mmio - Set up PCI IDE BMDMA transaction (MMIO)
 *	@qc: Info associated with this ATA transaction.
 *
 *	LOCKING:
 *	spin_lock_irqsave(host lock)
 */

static void k2_bmdma_setup_mmio(struct ata_queued_cmd *qc)
{
	struct ata_port *ap = qc->ap;
	unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE);
	u8 dmactl;
	void __iomem *mmio = ap->ioaddr.bmdma_addr;

	/* load PRD table addr. */
	mb();	/* make sure PRD table writes are visible to controller */
	writel(ap->bmdma_prd_dma, mmio + ATA_DMA_TABLE_OFS);

	/* specify data direction, triple-check start bit is clear */
	dmactl = readb(mmio + ATA_DMA_CMD);
	dmactl &= ~(ATA_DMA_WR | ATA_DMA_START);
	if (!rw)
		dmactl |= ATA_DMA_WR;
	writeb(dmactl, mmio + ATA_DMA_CMD);

	/* issue r/w command if this is not a ATA DMA command*/
	if (qc->tf.protocol != ATA_PROT_DMA)
		ap->ops->sff_exec_command(ap, &qc->tf);
}

/**
 *	k2_bmdma_start_mmio - Start a PCI IDE BMDMA transaction (MMIO)
 *	@qc: Info associated with this ATA transaction.
 *
 *	LOCKING:
 *	spin_lock_irqsave(host lock)
 */

static void k2_bmdma_start_mmio(struct ata_queued_cmd *qc)
{
	struct ata_port *ap = qc->ap;
	void __iomem *mmio = ap->ioaddr.bmdma_addr;
	u8 dmactl;

	/* start host DMA transaction */
	dmactl = readb(mmio + ATA_DMA_CMD);
	writeb(dmactl | ATA_DMA_START, mmio + ATA_DMA_CMD);
	/* This works around possible data corruption.

	   On certain SATA controllers that can be seen when the r/w
	   command is given to the controller before the host DMA is
	   started.

	   On a Read command, the controller would initiate the
	   command to the drive even before it sees the DMA
	   start. When there are very fast drives connected to the
	   controller, or when the data request hits in the drive
	   cache, there is the possibility that the drive returns a
	   part or all of the requested data to the controller before
	   the DMA start is issued.  In this case, the controller
	   would become confused as to what to do with the data.  In
	   the worst case when all the data is returned back to the
	   controller, the controller could hang. In other cases it
	   could return partial data returning in data
	   corruption. This problem has been seen in PPC systems and
	   can also appear on an system with very fast disks, where
	   the SATA controller is sitting behind a number of bridges,
	   and hence there is significant latency between the r/w
	   command and the start command. */
	/* issue r/w command if the access is to ATA */
	if (qc->tf.protocol == ATA_PROT_DMA)
		ap->ops->sff_exec_command(ap, &qc->tf);
}


static u8 k2_stat_check_status(struct ata_port *ap)
{
	return readl(ap->ioaddr.status_addr);
}

static int k2_sata_show_info(struct seq_file *m, struct Scsi_Host *shost)
{
	struct ata_port *ap;
	struct device_node *np;
	int index;

	/* Find  the ata_port */
	ap = ata_shost_to_port(shost);
	if (ap == NULL)
		return 0;

	/* Find the OF node for the PCI device proper */
	np = pci_device_to_OF_node(to_pci_dev(ap->host->dev));
	if (np == NULL)
		return 0;

	/* Match it to a port node */
	index = (ap == ap->host->ports[0]) ? 0 : 1;
	for (np = np->child; np != NULL; np = np->sibling) {
		u64 reg;

		if (of_property_read_reg(np, 0, &reg, NULL))
			continue;
		if (index == reg) {
			seq_printf(m, "devspec: %pOF\n", np);
			break;
		}
	}
	return 0;
}

static const struct scsi_host_template k2_sata_sht = {
	ATA_BMDMA_SHT(DRV_NAME),
	.show_info		= k2_sata_show_info,
};


static struct ata_port_operations k2_sata_ops = {
	.inherits		= &ata_bmdma_port_ops,
	.softreset              = k2_sata_softreset,
	.hardreset              = k2_sata_hardreset,
	.sff_tf_load		= k2_sata_tf_load,
	.sff_tf_read		= k2_sata_tf_read,
	.sff_check_status	= k2_stat_check_status,
	.check_atapi_dma	= k2_sata_check_atapi_dma,
	.bmdma_setup		= k2_bmdma_setup_mmio,
	.bmdma_start		= k2_bmdma_start_mmio,
	.scr_read		= k2_sata_scr_read,
	.scr_write		= k2_sata_scr_write,
};

static const struct ata_port_info k2_port_info[] = {
	/* chip_svw4 */
	{
		.flags		= ATA_FLAG_SATA | K2_FLAG_NO_ATAPI_DMA,
		.pio_mask	= ATA_PIO4,
		.mwdma_mask	= ATA_MWDMA2,
		.udma_mask	= ATA_UDMA6,
		.port_ops	= &k2_sata_ops,
	},
	/* chip_svw8 */
	{
		.flags		= ATA_FLAG_SATA | K2_FLAG_NO_ATAPI_DMA |
				  K2_FLAG_SATA_8_PORTS,
		.pio_mask	= ATA_PIO4,
		.mwdma_mask	= ATA_MWDMA2,
		.udma_mask	= ATA_UDMA6,
		.port_ops	= &k2_sata_ops,
	},
	/* chip_svw42 */
	{
		.flags		= ATA_FLAG_SATA | K2_FLAG_BAR_POS_3,
		.pio_mask	= ATA_PIO4,
		.mwdma_mask	= ATA_MWDMA2,
		.udma_mask	= ATA_UDMA6,
		.port_ops	= &k2_sata_ops,
	},
	/* chip_svw43 */
	{
		.flags		= ATA_FLAG_SATA,
		.pio_mask	= ATA_PIO4,
		.mwdma_mask	= ATA_MWDMA2,
		.udma_mask	= ATA_UDMA6,
		.port_ops	= &k2_sata_ops,
	},
};

static void k2_sata_setup_port(struct ata_ioports *port, void __iomem *base)
{
	port->cmd_addr		= base + K2_SATA_TF_CMD_OFFSET;
	port->data_addr		= base + K2_SATA_TF_DATA_OFFSET;
	port->feature_addr	=
	port->error_addr	= base + K2_SATA_TF_ERROR_OFFSET;
	port->nsect_addr	= base + K2_SATA_TF_NSECT_OFFSET;
	port->lbal_addr		= base + K2_SATA_TF_LBAL_OFFSET;
	port->lbam_addr		= base + K2_SATA_TF_LBAM_OFFSET;
	port->lbah_addr		= base + K2_SATA_TF_LBAH_OFFSET;
	port->device_addr	= base + K2_SATA_TF_DEVICE_OFFSET;
	port->command_addr	=
	port->status_addr	= base + K2_SATA_TF_CMDSTAT_OFFSET;
	port->altstatus_addr	=
	port->ctl_addr		= base + K2_SATA_TF_CTL_OFFSET;
	port->bmdma_addr	= base + K2_SATA_DMA_CMD_OFFSET;
	port->scr_addr		= base + K2_SATA_SCR_STATUS_OFFSET;
}


static int k2_sata_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
{
	const struct ata_port_info *ppi[] =
		{ &k2_port_info[ent->driver_data], NULL };
	struct ata_host *host;
	void __iomem *mmio_base;
	int n_ports, i, rc, bar_pos;

	ata_print_version_once(&pdev->dev, DRV_VERSION);

	/* allocate host */
	n_ports = 4;
	if (ppi[0]->flags & K2_FLAG_SATA_8_PORTS)
		n_ports = 8;

	host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
	if (!host)
		return -ENOMEM;

	bar_pos = 5;
	if (ppi[0]->flags & K2_FLAG_BAR_POS_3)
		bar_pos = 3;
	/*
	 * If this driver happens to only be useful on Apple's K2, then
	 * we should check that here as it has a normal Serverworks ID
	 */
	rc = pcim_enable_device(pdev);
	if (rc)
		return rc;

	/*
	 * Check if we have resources mapped at all (second function may
	 * have been disabled by firmware)
	 */
	if (pci_resource_len(pdev, bar_pos) == 0) {
		/* In IDE mode we need to pin the device to ensure that
			pcim_release does not clear the busmaster bit in config
			space, clearing causes busmaster DMA to fail on
			ports 3 & 4 */
		pcim_pin_device(pdev);
		return -ENODEV;
	}

	/* Request and iomap PCI regions */
	rc = pcim_iomap_regions(pdev, 1 << bar_pos, DRV_NAME);
	if (rc == -EBUSY)
		pcim_pin_device(pdev);
	if (rc)
		return rc;
	host->iomap = pcim_iomap_table(pdev);
	mmio_base = host->iomap[bar_pos];

	/* different controllers have different number of ports - currently 4 or 8 */
	/* All ports are on the same function. Multi-function device is no
	 * longer available. This should not be seen in any system. */
	for (i = 0; i < host->n_ports; i++) {
		struct ata_port *ap = host->ports[i];
		unsigned int offset = i * K2_SATA_PORT_OFFSET;

		k2_sata_setup_port(&ap->ioaddr, mmio_base + offset);

		ata_port_pbar_desc(ap, 5, -1, "mmio");
		ata_port_pbar_desc(ap, 5, offset, "port");
	}

	rc = dma_set_mask_and_coherent(&pdev->dev, ATA_DMA_MASK);
	if (rc)
		return rc;

	/* Clear a magic bit in SCR1 according to Darwin, those help
	 * some funky seagate drives (though so far, those were already
	 * set by the firmware on the machines I had access to)
	 */
	writel(readl(mmio_base + K2_SATA_SICR1_OFFSET) & ~0x00040000,
	       mmio_base + K2_SATA_SICR1_OFFSET);

	/* Clear SATA error & interrupts we don't use */
	writel(0xffffffff, mmio_base + K2_SATA_SCR_ERROR_OFFSET);
	writel(0x0, mmio_base + K2_SATA_SIM_OFFSET);

	pci_set_master(pdev);
	return ata_host_activate(host, pdev->irq, ata_bmdma_interrupt,
				 IRQF_SHARED, &k2_sata_sht);
}

/* 0x240 is device ID for Apple K2 device
 * 0x241 is device ID for Serverworks Frodo4
 * 0x242 is device ID for Serverworks Frodo8
 * 0x24a is device ID for BCM5785 (aka HT1000) HT southbridge integrated SATA
 * controller
 * */
static const struct pci_device_id k2_sata_pci_tbl[] = {
	{ PCI_VDEVICE(SERVERWORKS, 0x0240), chip_svw4 },
	{ PCI_VDEVICE(SERVERWORKS, 0x0241), chip_svw8 },
	{ PCI_VDEVICE(SERVERWORKS, 0x0242), chip_svw4 },
	{ PCI_VDEVICE(SERVERWORKS, 0x024a), chip_svw4 },
	{ PCI_VDEVICE(SERVERWORKS, 0x024b), chip_svw4 },
	{ PCI_VDEVICE(SERVERWORKS, 0x0410), chip_svw42 },
	{ PCI_VDEVICE(SERVERWORKS, 0x0411), chip_svw43 },

	{ }
};

static struct pci_driver k2_sata_pci_driver = {
	.name			= DRV_NAME,
	.id_table		= k2_sata_pci_tbl,
	.probe			= k2_sata_init_one,
	.remove			= ata_pci_remove_one,
};

module_pci_driver(k2_sata_pci_driver);

MODULE_AUTHOR("Benjamin Herrenschmidt");
MODULE_DESCRIPTION("low-level driver for K2 SATA controller");
MODULE_LICENSE("GPL");
MODULE_DEVICE_TABLE(pci, k2_sata_pci_tbl);
MODULE_VERSION(DRV_VERSION);
Commit	Line	Data
c82ee6d3	1	// SPDX-License-Identifier: GPL-2.0-or-later
1da177e4 LT	2	/*
	3	* sata_svw.c - ServerWorks / Apple K2 SATA
	4	*
	5	* Maintained by: Benjamin Herrenschmidt <benh@kernel.crashing.org> and
	6	* Jeff Garzik <jgarzik@pobox.com>
	7	* Please ALWAYS copy linux-ide@vger.kernel.org
	8	* on emails.
	9	*
	10	* Copyright 2003 Benjamin Herrenschmidt <benh@kernel.crashing.org>
	11	*
	12	* Bits from Jeff Garzik, Copyright RedHat, Inc.
	13	*
	14	* This driver probably works with non-Apple versions of the
	15	* Broadcom chipset...
	16	*
af36d7f0	17	* libata documentation is available via 'make {ps\|pdf}docs',
19285f3c	18	* as Documentation/driver-api/libata.rst
af36d7f0 JG	19	*
af36d7f0 JG	20	* Hardware documentation available under NDA.
1da177e4 LT	21	*/
1da177e4 LT	22
1da177e4 LT	23	#include <linux/kernel.h>
	24	#include <linux/module.h>
	25	#include <linux/pci.h>
1da177e4 LT	26	#include <linux/blkdev.h>
	27	#include <linux/delay.h>
	28	#include <linux/interrupt.h>
a9524a76	29	#include <linux/device.h>
1da177e4	30	#include <scsi/scsi_host.h>
931506d3 AS	31	#include <scsi/scsi_cmnd.h>
931506d3 AS	32	#include <scsi/scsi.h>
1da177e4	33	#include <linux/libata.h>
d610f503	34	#include <linux/of.h>
d0b24616	35	#include <linux/of_address.h>
1da177e4 LT	36
1da177e4 LT	37	#define DRV_NAME "sata_svw"
2a3103ce	38	#define DRV_VERSION "2.3"
1da177e4	39
55cca65e	40	enum {
4447d351 TH	41	/* ap->flags bits */
	42	K2_FLAG_SATA_8_PORTS = (1 << 24),
	43	K2_FLAG_NO_ATAPI_DMA = (1 << 25),
931506d3	44	K2_FLAG_BAR_POS_3 = (1 << 26),
c10340ac	45
55cca65e JG	46	/* Taskfile registers offsets */
	47	K2_SATA_TF_CMD_OFFSET = 0x00,
	48	K2_SATA_TF_DATA_OFFSET = 0x00,
	49	K2_SATA_TF_ERROR_OFFSET = 0x04,
	50	K2_SATA_TF_NSECT_OFFSET = 0x08,
	51	K2_SATA_TF_LBAL_OFFSET = 0x0c,
	52	K2_SATA_TF_LBAM_OFFSET = 0x10,
	53	K2_SATA_TF_LBAH_OFFSET = 0x14,
	54	K2_SATA_TF_DEVICE_OFFSET = 0x18,
	55	K2_SATA_TF_CMDSTAT_OFFSET = 0x1c,
	56	K2_SATA_TF_CTL_OFFSET = 0x20,
1da177e4	57
55cca65e JG	58	/* DMA base */
55cca65e JG	59	K2_SATA_DMA_CMD_OFFSET = 0x30,
1da177e4	60
55cca65e JG	61	/* SCRs base */
	62	K2_SATA_SCR_STATUS_OFFSET = 0x40,
	63	K2_SATA_SCR_ERROR_OFFSET = 0x44,
	64	K2_SATA_SCR_CONTROL_OFFSET = 0x48,
1da177e4	65
55cca65e JG	66	/* Others */
	67	K2_SATA_SICR1_OFFSET = 0x80,
	68	K2_SATA_SICR2_OFFSET = 0x84,
	69	K2_SATA_SIM_OFFSET = 0x88,
1da177e4	70
55cca65e JG	71	/* Port stride */
55cca65e JG	72	K2_SATA_PORT_OFFSET = 0x100,
c10340ac	73
931506d3 AS	74	chip_svw4 = 0,
	75	chip_svw8 = 1,
	76	chip_svw42 = 2, /* bar 3 */
	77	chip_svw43 = 3, /* bar 5 */
c10340ac JG	78	};
c10340ac JG	79
ac19bff2 JG	80	static u8 k2_stat_check_status(struct ata_port *ap);
ac19bff2 JG	81
1da177e4	82
c10340ac JG	83	static int k2_sata_check_atapi_dma(struct ata_queued_cmd *qc)
c10340ac JG	84	{
931506d3 AS	85	u8 cmnd = qc->scsicmd->cmnd[0];
931506d3 AS	86
c10340ac JG	87	if (qc->ap->flags & K2_FLAG_NO_ATAPI_DMA)
c10340ac JG	88	return -1; /* ATAPI DMA not supported */
931506d3 AS	89	else {
	90	switch (cmnd) {
	91	case READ_10:
	92	case READ_12:
	93	case READ_16:
	94	case WRITE_10:
	95	case WRITE_12:
	96	case WRITE_16:
	97	return 0;
	98
	99	default:
	100	return -1;
	101	}
c10340ac	102
931506d3	103	}
c10340ac JG	104	}
c10340ac JG	105
82ef04fb TH	106	static int k2_sata_scr_read(struct ata_link *link,
82ef04fb TH	107	unsigned int sc_reg, u32 *val)
1da177e4 LT	108	{
1da177e4 LT	109	if (sc_reg > SCR_CONTROL)
da3dbb17	110	return -EINVAL;
82ef04fb	111	val = readl(link->ap->ioaddr.scr_addr + (sc_reg 4));
da3dbb17	112	return 0;
1da177e4 LT	113	}
	114
	115
82ef04fb TH	116	static int k2_sata_scr_write(struct ata_link *link,
82ef04fb TH	117	unsigned int sc_reg, u32 val)
1da177e4 LT	118	{
1da177e4 LT	119	if (sc_reg > SCR_CONTROL)
da3dbb17	120	return -EINVAL;
82ef04fb	121	writel(val, link->ap->ioaddr.scr_addr + (sc_reg * 4));
da3dbb17	122	return 0;
1da177e4 LT	123	}
1da177e4 LT	124
b03e66a6 DM	125	static int k2_sata_softreset(struct ata_link *link,
	126	unsigned int *class, unsigned long deadline)
	127	{
	128	u8 dmactl;
	129	void __iomem *mmio = link->ap->ioaddr.bmdma_addr;
	130
	131	dmactl = readb(mmio + ATA_DMA_CMD);
	132
	133	/* Clear the start bit */
	134	if (dmactl & ATA_DMA_START) {
	135	dmactl &= ~ATA_DMA_START;
	136	writeb(dmactl, mmio + ATA_DMA_CMD);
	137	}
	138
	139	return ata_sff_softreset(link, class, deadline);
	140	}
	141
	142	static int k2_sata_hardreset(struct ata_link *link,
	143	unsigned int *class, unsigned long deadline)
	144	{
	145	u8 dmactl;
	146	void __iomem *mmio = link->ap->ioaddr.bmdma_addr;
	147
	148	dmactl = readb(mmio + ATA_DMA_CMD);
	149
	150	/* Clear the start bit */
	151	if (dmactl & ATA_DMA_START) {
	152	dmactl &= ~ATA_DMA_START;
	153	writeb(dmactl, mmio + ATA_DMA_CMD);
	154	}
	155
	156	return sata_sff_hardreset(link, class, deadline);
	157	}
1da177e4	158
057ace5e	159	static void k2_sata_tf_load(struct ata_port ap, const struct ata_taskfile tf)
1da177e4 LT	160	{
	161	struct ata_ioports *ioaddr = &ap->ioaddr;
	162	unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR;
	163
	164	if (tf->ctl != ap->last_ctl) {
0d5ff566	165	writeb(tf->ctl, ioaddr->ctl_addr);
1da177e4 LT	166	ap->last_ctl = tf->ctl;
	167	ata_wait_idle(ap);
	168	}
	169	if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) {
850a9d8a	170	writew(tf->feature \| (((u16)tf->hob_feature) << 8),
0d5ff566	171	ioaddr->feature_addr);
850a9d8a	172	writew(tf->nsect \| (((u16)tf->hob_nsect) << 8),
0d5ff566	173	ioaddr->nsect_addr);
850a9d8a	174	writew(tf->lbal \| (((u16)tf->hob_lbal) << 8),
0d5ff566	175	ioaddr->lbal_addr);
850a9d8a	176	writew(tf->lbam \| (((u16)tf->hob_lbam) << 8),
0d5ff566	177	ioaddr->lbam_addr);
850a9d8a	178	writew(tf->lbah \| (((u16)tf->hob_lbah) << 8),
0d5ff566	179	ioaddr->lbah_addr);
1da177e4	180	} else if (is_addr) {
0d5ff566 TH	181	writew(tf->feature, ioaddr->feature_addr);
	182	writew(tf->nsect, ioaddr->nsect_addr);
	183	writew(tf->lbal, ioaddr->lbal_addr);
	184	writew(tf->lbam, ioaddr->lbam_addr);
	185	writew(tf->lbah, ioaddr->lbah_addr);
1da177e4 LT	186	}
	187
	188	if (tf->flags & ATA_TFLAG_DEVICE)
0d5ff566	189	writeb(tf->device, ioaddr->device_addr);
1da177e4 LT	190
	191	ata_wait_idle(ap);
	192	}
	193
	194
	195	static void k2_sata_tf_read(struct ata_port ap, struct ata_taskfile tf)
	196	{
	197	struct ata_ioports *ioaddr = &ap->ioaddr;
efcef265	198	u16 nsect, lbal, lbam, lbah, error;
1da177e4	199
efcef265	200	tf->status = k2_stat_check_status(ap);
0d5ff566	201	tf->device = readw(ioaddr->device_addr);
efcef265	202	error = readw(ioaddr->error_addr);
0d5ff566 TH	203	nsect = readw(ioaddr->nsect_addr);
	204	lbal = readw(ioaddr->lbal_addr);
	205	lbam = readw(ioaddr->lbam_addr);
	206	lbah = readw(ioaddr->lbah_addr);
ac19bff2	207
efcef265	208	tf->error = error;
ac19bff2 JG	209	tf->nsect = nsect;
	210	tf->lbal = lbal;
	211	tf->lbam = lbam;
	212	tf->lbah = lbah;
1da177e4 LT	213
1da177e4 LT	214	if (tf->flags & ATA_TFLAG_LBA48) {
efcef265	215	tf->hob_feature = error >> 8;
1da177e4 LT	216	tf->hob_nsect = nsect >> 8;
	217	tf->hob_lbal = lbal >> 8;
	218	tf->hob_lbam = lbam >> 8;
	219	tf->hob_lbah = lbah >> 8;
5796d1c4	220	}
1da177e4 LT	221	}
	222
	223	/**
	224	* k2_bmdma_setup_mmio - Set up PCI IDE BMDMA transaction (MMIO)
	225	* @qc: Info associated with this ATA transaction.
	226	*
	227	* LOCKING:
cca3974e	228	* spin_lock_irqsave(host lock)
1da177e4 LT	229	*/
1da177e4 LT	230
5796d1c4	231	static void k2_bmdma_setup_mmio(struct ata_queued_cmd *qc)
1da177e4 LT	232	{
	233	struct ata_port *ap = qc->ap;
	234	unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE);
	235	u8 dmactl;
59f99880 JG	236	void __iomem *mmio = ap->ioaddr.bmdma_addr;
59f99880 JG	237
1da177e4 LT	238	/* load PRD table addr. */
1da177e4 LT	239	mb(); /* make sure PRD table writes are visible to controller */
f60d7011	240	writel(ap->bmdma_prd_dma, mmio + ATA_DMA_TABLE_OFS);
1da177e4 LT	241
	242	/* specify data direction, triple-check start bit is clear */
	243	dmactl = readb(mmio + ATA_DMA_CMD);
	244	dmactl &= ~(ATA_DMA_WR \| ATA_DMA_START);
	245	if (!rw)
	246	dmactl \|= ATA_DMA_WR;
	247	writeb(dmactl, mmio + ATA_DMA_CMD);
	248
	249	/* issue r/w command if this is not a ATA DMA command*/
	250	if (qc->tf.protocol != ATA_PROT_DMA)
5682ed33	251	ap->ops->sff_exec_command(ap, &qc->tf);
1da177e4 LT	252	}
	253
	254	/**
	255	* k2_bmdma_start_mmio - Start a PCI IDE BMDMA transaction (MMIO)
	256	* @qc: Info associated with this ATA transaction.
	257	*
	258	* LOCKING:
cca3974e	259	* spin_lock_irqsave(host lock)
1da177e4 LT	260	*/
1da177e4 LT	261
5796d1c4	262	static void k2_bmdma_start_mmio(struct ata_queued_cmd *qc)
1da177e4 LT	263	{
1da177e4 LT	264	struct ata_port *ap = qc->ap;
59f99880	265	void __iomem *mmio = ap->ioaddr.bmdma_addr;
1da177e4 LT	266	u8 dmactl;
	267
	268	/* start host DMA transaction */
	269	dmactl = readb(mmio + ATA_DMA_CMD);
	270	writeb(dmactl \| ATA_DMA_START, mmio + ATA_DMA_CMD);
ec6add99 PM	271	/* This works around possible data corruption.
	272
	273	On certain SATA controllers that can be seen when the r/w
	274	command is given to the controller before the host DMA is
	275	started.
	276
	277	On a Read command, the controller would initiate the
	278	command to the drive even before it sees the DMA
	279	start. When there are very fast drives connected to the
	280	controller, or when the data request hits in the drive
	281	cache, there is the possibility that the drive returns a
	282	part or all of the requested data to the controller before
	283	the DMA start is issued. In this case, the controller
	284	would become confused as to what to do with the data. In
	285	the worst case when all the data is returned back to the
	286	controller, the controller could hang. In other cases it
	287	could return partial data returning in data
	288	corruption. This problem has been seen in PPC systems and
	289	can also appear on an system with very fast disks, where
	290	the SATA controller is sitting behind a number of bridges,
	291	and hence there is significant latency between the r/w
	292	command and the start command. */
	293	/* issue r/w command if the access is to ATA */
1da177e4	294	if (qc->tf.protocol == ATA_PROT_DMA)
5682ed33	295	ap->ops->sff_exec_command(ap, &qc->tf);
1da177e4 LT	296	}
1da177e4 LT	297
8a60a071	298
1da177e4 LT	299	static u8 k2_stat_check_status(struct ata_port *ap)
1da177e4 LT	300	{
5796d1c4	301	return readl(ap->ioaddr.status_addr);
1da177e4 LT	302	}
1da177e4 LT	303
3f025677	304	static int k2_sata_show_info(struct seq_file m, struct Scsi_Host shost)
1da177e4 LT	305	{
	306	struct ata_port *ap;
	307	struct device_node *np;
3f025677	308	int index;
1da177e4 LT	309
1da177e4 LT	310	/* Find the ata_port */
35bb94b1	311	ap = ata_shost_to_port(shost);
1da177e4 LT	312	if (ap == NULL)
	313	return 0;
	314
	315	/* Find the OF node for the PCI device proper */
cca3974e	316	np = pci_device_to_OF_node(to_pci_dev(ap->host->dev));
1da177e4 LT	317	if (np == NULL)
	318	return 0;
	319
	320	/* Match it to a port node */
cca3974e	321	index = (ap == ap->host->ports[0]) ? 0 : 1;
1da177e4	322	for (np = np->child; np != NULL; np = np->sibling) {
d0b24616 RH	323	u64 reg;
	324
	325	if (of_property_read_reg(np, 0, &reg, NULL))
1da177e4	326	continue;
d0b24616	327	if (index == reg) {
cf8984bf	328	seq_printf(m, "devspec: %pOF\n", np);
1da177e4	329	break;
3f025677	330	}
1da177e4	331	}
3f025677	332	return 0;
1da177e4	333	}
1da177e4	334
25df73d9	335	static const struct scsi_host_template k2_sata_sht = {
68d1d07b	336	ATA_BMDMA_SHT(DRV_NAME),
3f025677	337	.show_info = k2_sata_show_info,
1da177e4 LT	338	};
	339
	340
029cfd6b TH	341	static struct ata_port_operations k2_sata_ops = {
029cfd6b TH	342	.inherits = &ata_bmdma_port_ops,
b03e66a6 DM	343	.softreset = k2_sata_softreset,
b03e66a6 DM	344	.hardreset = k2_sata_hardreset,
5682ed33 TH	345	.sff_tf_load = k2_sata_tf_load,
	346	.sff_tf_read = k2_sata_tf_read,
	347	.sff_check_status = k2_stat_check_status,
c10340ac	348	.check_atapi_dma = k2_sata_check_atapi_dma,
1da177e4 LT	349	.bmdma_setup = k2_bmdma_setup_mmio,
1da177e4 LT	350	.bmdma_start = k2_bmdma_start_mmio,
1da177e4 LT	351	.scr_read = k2_sata_scr_read,
1da177e4 LT	352	.scr_write = k2_sata_scr_write,
1da177e4 LT	353	};
1da177e4 LT	354
4447d351	355	static const struct ata_port_info k2_port_info[] = {
931506d3	356	/* chip_svw4 */
4447d351	357	{
9cbe056f	358	.flags = ATA_FLAG_SATA \| K2_FLAG_NO_ATAPI_DMA,
14bdef98 EIB	359	.pio_mask = ATA_PIO4,
14bdef98 EIB	360	.mwdma_mask = ATA_MWDMA2,
bf6263a8	361	.udma_mask = ATA_UDMA6,
4447d351 TH	362	.port_ops = &k2_sata_ops,
4447d351 TH	363	},
931506d3	364	/* chip_svw8 */
4447d351	365	{
9cbe056f SS	366	.flags = ATA_FLAG_SATA \| K2_FLAG_NO_ATAPI_DMA \|
9cbe056f SS	367	K2_FLAG_SATA_8_PORTS,
14bdef98 EIB	368	.pio_mask = ATA_PIO4,
14bdef98 EIB	369	.mwdma_mask = ATA_MWDMA2,
bf6263a8	370	.udma_mask = ATA_UDMA6,
4447d351 TH	371	.port_ops = &k2_sata_ops,
4447d351 TH	372	},
931506d3 AS	373	/* chip_svw42 */
931506d3 AS	374	{
9cbe056f	375	.flags = ATA_FLAG_SATA \| K2_FLAG_BAR_POS_3,
14bdef98 EIB	376	.pio_mask = ATA_PIO4,
14bdef98 EIB	377	.mwdma_mask = ATA_MWDMA2,
931506d3 AS	378	.udma_mask = ATA_UDMA6,
	379	.port_ops = &k2_sata_ops,
	380	},
	381	/* chip_svw43 */
	382	{
9cbe056f	383	.flags = ATA_FLAG_SATA,
14bdef98 EIB	384	.pio_mask = ATA_PIO4,
14bdef98 EIB	385	.mwdma_mask = ATA_MWDMA2,
931506d3 AS	386	.udma_mask = ATA_UDMA6,
	387	.port_ops = &k2_sata_ops,
	388	},
4447d351 TH	389	};
4447d351 TH	390
0d5ff566	391	static void k2_sata_setup_port(struct ata_ioports port, void __iomem base)
1da177e4 LT	392	{
	393	port->cmd_addr = base + K2_SATA_TF_CMD_OFFSET;
	394	port->data_addr = base + K2_SATA_TF_DATA_OFFSET;
	395	port->feature_addr =
	396	port->error_addr = base + K2_SATA_TF_ERROR_OFFSET;
	397	port->nsect_addr = base + K2_SATA_TF_NSECT_OFFSET;
	398	port->lbal_addr = base + K2_SATA_TF_LBAL_OFFSET;
	399	port->lbam_addr = base + K2_SATA_TF_LBAM_OFFSET;
	400	port->lbah_addr = base + K2_SATA_TF_LBAH_OFFSET;
	401	port->device_addr = base + K2_SATA_TF_DEVICE_OFFSET;
	402	port->command_addr =
	403	port->status_addr = base + K2_SATA_TF_CMDSTAT_OFFSET;
	404	port->altstatus_addr =
	405	port->ctl_addr = base + K2_SATA_TF_CTL_OFFSET;
	406	port->bmdma_addr = base + K2_SATA_DMA_CMD_OFFSET;
	407	port->scr_addr = base + K2_SATA_SCR_STATUS_OFFSET;
	408	}
	409
	410
5796d1c4	411	static int k2_sata_init_one(struct pci_dev pdev, const struct pci_device_id ent)
1da177e4	412	{
4447d351 TH	413	const struct ata_port_info *ppi[] =
	414	{ &k2_port_info[ent->driver_data], NULL };
	415	struct ata_host *host;
ea6ba10b	416	void __iomem *mmio_base;
931506d3	417	int n_ports, i, rc, bar_pos;
1da177e4	418
06296a1e	419	ata_print_version_once(&pdev->dev, DRV_VERSION);
1da177e4	420
4447d351 TH	421	/* allocate host */
	422	n_ports = 4;
	423	if (ppi[0]->flags & K2_FLAG_SATA_8_PORTS)
	424	n_ports = 8;
	425
	426	host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
	427	if (!host)
	428	return -ENOMEM;
	429
931506d3 AS	430	bar_pos = 5;
	431	if (ppi[0]->flags & K2_FLAG_BAR_POS_3)
	432	bar_pos = 3;
1da177e4 LT	433	/*
	434	* If this driver happens to only be useful on Apple's K2, then
	435	* we should check that here as it has a normal Serverworks ID
	436	*/
24dc5f33	437	rc = pcim_enable_device(pdev);
1da177e4 LT	438	if (rc)
1da177e4 LT	439	return rc;
4447d351	440
1da177e4 LT	441	/*
	442	* Check if we have resources mapped at all (second function may
	443	* have been disabled by firmware)
	444	*/
931506d3 AS	445	if (pci_resource_len(pdev, bar_pos) == 0) {
	446	/* In IDE mode we need to pin the device to ensure that
	447	pcim_release does not clear the busmaster bit in config
	448	space, clearing causes busmaster DMA to fail on
	449	ports 3 & 4 */
	450	pcim_pin_device(pdev);
1da177e4	451	return -ENODEV;
931506d3	452	}
1da177e4	453
0d5ff566	454	/* Request and iomap PCI regions */
931506d3	455	rc = pcim_iomap_regions(pdev, 1 << bar_pos, DRV_NAME);
0d5ff566	456	if (rc == -EBUSY)
24dc5f33	457	pcim_pin_device(pdev);
0d5ff566	458	if (rc)
24dc5f33	459	return rc;
4447d351	460	host->iomap = pcim_iomap_table(pdev);
931506d3	461	mmio_base = host->iomap[bar_pos];
4447d351 TH	462
	463	/* different controllers have different number of ports - currently 4 or 8 */
	464	/* All ports are on the same function. Multi-function device is no
	465	* longer available. This should not be seen in any system. */
cbcdd875 TH	466	for (i = 0; i < host->n_ports; i++) {
	467	struct ata_port *ap = host->ports[i];
	468	unsigned int offset = i * K2_SATA_PORT_OFFSET;
	469
	470	k2_sata_setup_port(&ap->ioaddr, mmio_base + offset);
	471
	472	ata_port_pbar_desc(ap, 5, -1, "mmio");
	473	ata_port_pbar_desc(ap, 5, offset, "port");
	474	}
1da177e4	475
b5e55556	476	rc = dma_set_mask_and_coherent(&pdev->dev, ATA_DMA_MASK);
1da177e4	477	if (rc)
24dc5f33	478	return rc;
1da177e4	479
0d5ff566 TH	480	/* Clear a magic bit in SCR1 according to Darwin, those help
	481	* some funky seagate drives (though so far, those were already
	482	* set by the firmware on the machines I had access to)
	483	*/
	484	writel(readl(mmio_base + K2_SATA_SICR1_OFFSET) & ~0x00040000,
	485	mmio_base + K2_SATA_SICR1_OFFSET);
	486
	487	/* Clear SATA error & interrupts we don't use */
	488	writel(0xffffffff, mmio_base + K2_SATA_SCR_ERROR_OFFSET);
	489	writel(0x0, mmio_base + K2_SATA_SIM_OFFSET);
1da177e4 LT	490
1da177e4 LT	491	pci_set_master(pdev);
c3b28894	492	return ata_host_activate(host, pdev->irq, ata_bmdma_interrupt,
9363c382	493	IRQF_SHARED, &k2_sata_sht);
1da177e4 LT	494	}
1da177e4 LT	495
60bf09a3 NS	496	/* 0x240 is device ID for Apple K2 device
	497	* 0x241 is device ID for Serverworks Frodo4
	498	* 0x242 is device ID for Serverworks Frodo8
	499	* 0x24a is device ID for BCM5785 (aka HT1000) HT southbridge integrated SATA
	500	* controller
	501	* */
3b7d697d	502	static const struct pci_device_id k2_sata_pci_tbl[] = {
931506d3	503	{ PCI_VDEVICE(SERVERWORKS, 0x0240), chip_svw4 },
aeb74914 JG	504	{ PCI_VDEVICE(SERVERWORKS, 0x0241), chip_svw8 },
aeb74914 JG	505	{ PCI_VDEVICE(SERVERWORKS, 0x0242), chip_svw4 },
931506d3 AS	506	{ PCI_VDEVICE(SERVERWORKS, 0x024a), chip_svw4 },
	507	{ PCI_VDEVICE(SERVERWORKS, 0x024b), chip_svw4 },
	508	{ PCI_VDEVICE(SERVERWORKS, 0x0410), chip_svw42 },
	509	{ PCI_VDEVICE(SERVERWORKS, 0x0411), chip_svw43 },
2d2744fc	510
1da177e4 LT	511	{ }
	512	};
	513
1da177e4 LT	514	static struct pci_driver k2_sata_pci_driver = {
	515	.name = DRV_NAME,
	516	.id_table = k2_sata_pci_tbl,
	517	.probe = k2_sata_init_one,
	518	.remove = ata_pci_remove_one,
	519	};
	520
2fc75da0	521	module_pci_driver(k2_sata_pci_driver);
1da177e4	522
1da177e4 LT	523	MODULE_AUTHOR("Benjamin Herrenschmidt");
	524	MODULE_DESCRIPTION("low-level driver for K2 SATA controller");
	525	MODULE_LICENSE("GPL");
	526	MODULE_DEVICE_TABLE(pci, k2_sata_pci_tbl);
	527	MODULE_VERSION(DRV_VERSION);