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1da177e4 LT |
1 | /* |
2 | * sata_sis.c - Silicon Integrated Systems SATA | |
3 | * | |
4 | * Maintained by: Uwe Koziolek | |
5 | * Please ALWAYS copy linux-ide@vger.kernel.org | |
6 | * on emails. | |
7 | * | |
8 | * Copyright 2004 Uwe Koziolek | |
9 | * | |
af36d7f0 JG |
10 | * |
11 | * This program is free software; you can redistribute it and/or modify | |
12 | * it under the terms of the GNU General Public License as published by | |
13 | * the Free Software Foundation; either version 2, or (at your option) | |
14 | * any later version. | |
15 | * | |
16 | * This program is distributed in the hope that it will be useful, | |
17 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
18 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
19 | * GNU General Public License for more details. | |
20 | * | |
21 | * You should have received a copy of the GNU General Public License | |
22 | * along with this program; see the file COPYING. If not, write to | |
23 | * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. | |
24 | * | |
25 | * | |
26 | * libata documentation is available via 'make {ps|pdf}docs', | |
27 | * as Documentation/DocBook/libata.* | |
28 | * | |
29 | * Hardware documentation available under NDA. | |
1da177e4 LT |
30 | * |
31 | */ | |
32 | ||
1da177e4 LT |
33 | #include <linux/kernel.h> |
34 | #include <linux/module.h> | |
35 | #include <linux/pci.h> | |
36 | #include <linux/init.h> | |
37 | #include <linux/blkdev.h> | |
38 | #include <linux/delay.h> | |
39 | #include <linux/interrupt.h> | |
a9524a76 | 40 | #include <linux/device.h> |
1da177e4 LT |
41 | #include <scsi/scsi_host.h> |
42 | #include <linux/libata.h> | |
77a527ea | 43 | #include "libata.h" |
1da177e4 LT |
44 | |
45 | #define DRV_NAME "sata_sis" | |
3f3e7313 | 46 | #define DRV_VERSION "0.7" |
1da177e4 LT |
47 | |
48 | enum { | |
49 | sis_180 = 0, | |
50 | SIS_SCR_PCI_BAR = 5, | |
51 | ||
52 | /* PCI configuration registers */ | |
53 | SIS_GENCTL = 0x54, /* IDE General Control register */ | |
54 | SIS_SCR_BASE = 0xc0, /* sata0 phy SCR registers */ | |
f2c853bc AP |
55 | SIS180_SATA1_OFS = 0x10, /* offset from sata0->sata1 phy regs */ |
56 | SIS182_SATA1_OFS = 0x20, /* offset from sata0->sata1 phy regs */ | |
57 | SIS_PMR = 0x90, /* port mapping register */ | |
8add7885 | 58 | SIS_PMR_COMBINED = 0x30, |
1da177e4 LT |
59 | |
60 | /* random bits */ | |
61 | SIS_FLAG_CFGSCR = (1 << 30), /* host flag: SCRs via PCI cfg */ | |
62 | ||
63 | GENCTL_IOMAPPED_SCR = (1 << 26), /* if set, SCRs are in IO space */ | |
64 | }; | |
65 | ||
66 | static int sis_init_one (struct pci_dev *pdev, const struct pci_device_id *ent); | |
67 | static u32 sis_scr_read (struct ata_port *ap, unsigned int sc_reg); | |
68 | static void sis_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val); | |
69 | ||
3b7d697d | 70 | static const struct pci_device_id sis_pci_tbl[] = { |
3f3e7313 UK |
71 | { PCI_VDEVICE(SI, 0x0180), sis_180 }, /* SiS 964/180 */ |
72 | { PCI_VDEVICE(SI, 0x0181), sis_180 }, /* SiS 964/180 */ | |
73 | { PCI_VDEVICE(SI, 0x0182), sis_180 }, /* SiS 965/965L */ | |
74 | { PCI_VDEVICE(SI, 0x0183), sis_180 }, /* SiS 965/965L */ | |
75 | { PCI_VDEVICE(SI, 0x1182), sis_180 }, /* SiS 966/966L */ | |
76 | { PCI_VDEVICE(SI, 0x1183), sis_180 }, /* SiS 966/966L */ | |
2d2744fc | 77 | |
1da177e4 LT |
78 | { } /* terminate list */ |
79 | }; | |
80 | ||
1da177e4 LT |
81 | static struct pci_driver sis_pci_driver = { |
82 | .name = DRV_NAME, | |
83 | .id_table = sis_pci_tbl, | |
84 | .probe = sis_init_one, | |
85 | .remove = ata_pci_remove_one, | |
86 | }; | |
87 | ||
193515d5 | 88 | static struct scsi_host_template sis_sht = { |
1da177e4 LT |
89 | .module = THIS_MODULE, |
90 | .name = DRV_NAME, | |
91 | .ioctl = ata_scsi_ioctl, | |
92 | .queuecommand = ata_scsi_queuecmd, | |
1da177e4 LT |
93 | .can_queue = ATA_DEF_QUEUE, |
94 | .this_id = ATA_SHT_THIS_ID, | |
95 | .sg_tablesize = ATA_MAX_PRD, | |
1da177e4 LT |
96 | .cmd_per_lun = ATA_SHT_CMD_PER_LUN, |
97 | .emulated = ATA_SHT_EMULATED, | |
98 | .use_clustering = ATA_SHT_USE_CLUSTERING, | |
99 | .proc_name = DRV_NAME, | |
100 | .dma_boundary = ATA_DMA_BOUNDARY, | |
101 | .slave_configure = ata_scsi_slave_config, | |
ccf68c34 | 102 | .slave_destroy = ata_scsi_slave_destroy, |
1da177e4 | 103 | .bios_param = ata_std_bios_param, |
1da177e4 LT |
104 | }; |
105 | ||
057ace5e | 106 | static const struct ata_port_operations sis_ops = { |
1da177e4 LT |
107 | .port_disable = ata_port_disable, |
108 | .tf_load = ata_tf_load, | |
109 | .tf_read = ata_tf_read, | |
110 | .check_status = ata_check_status, | |
111 | .exec_command = ata_exec_command, | |
112 | .dev_select = ata_std_dev_select, | |
1da177e4 LT |
113 | .bmdma_setup = ata_bmdma_setup, |
114 | .bmdma_start = ata_bmdma_start, | |
115 | .bmdma_stop = ata_bmdma_stop, | |
116 | .bmdma_status = ata_bmdma_status, | |
117 | .qc_prep = ata_qc_prep, | |
118 | .qc_issue = ata_qc_issue_prot, | |
a6b2c5d4 | 119 | .data_xfer = ata_pio_data_xfer, |
d7a80dad TH |
120 | .freeze = ata_bmdma_freeze, |
121 | .thaw = ata_bmdma_thaw, | |
122 | .error_handler = ata_bmdma_error_handler, | |
123 | .post_internal_cmd = ata_bmdma_post_internal_cmd, | |
1da177e4 LT |
124 | .irq_handler = ata_interrupt, |
125 | .irq_clear = ata_bmdma_irq_clear, | |
126 | .scr_read = sis_scr_read, | |
127 | .scr_write = sis_scr_write, | |
128 | .port_start = ata_port_start, | |
1da177e4 LT |
129 | }; |
130 | ||
131 | static struct ata_port_info sis_port_info = { | |
132 | .sht = &sis_sht, | |
cca3974e | 133 | .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY, |
1da177e4 LT |
134 | .pio_mask = 0x1f, |
135 | .mwdma_mask = 0x7, | |
136 | .udma_mask = 0x7f, | |
137 | .port_ops = &sis_ops, | |
138 | }; | |
139 | ||
1da177e4 LT |
140 | MODULE_AUTHOR("Uwe Koziolek"); |
141 | MODULE_DESCRIPTION("low-level driver for Silicon Integratad Systems SATA controller"); | |
142 | MODULE_LICENSE("GPL"); | |
143 | MODULE_DEVICE_TABLE(pci, sis_pci_tbl); | |
144 | MODULE_VERSION(DRV_VERSION); | |
145 | ||
9b14dec5 | 146 | static unsigned int get_scr_cfg_addr(struct ata_port *ap, unsigned int sc_reg) |
1da177e4 | 147 | { |
9b14dec5 | 148 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); |
1da177e4 | 149 | unsigned int addr = SIS_SCR_BASE + (4 * sc_reg); |
9b14dec5 | 150 | u8 pmr; |
1da177e4 | 151 | |
9b14dec5 | 152 | if (ap->port_no) { |
3f3e7313 UK |
153 | switch (pdev->device) { |
154 | case 0x0180: | |
155 | case 0x0181: | |
9b14dec5 A |
156 | pci_read_config_byte(pdev, SIS_PMR, &pmr); |
157 | if ((pmr & SIS_PMR_COMBINED) == 0) | |
158 | addr += SIS180_SATA1_OFS; | |
3f3e7313 UK |
159 | break; |
160 | ||
161 | case 0x0182: | |
162 | case 0x0183: | |
163 | case 0x1182: | |
164 | case 0x1183: | |
165 | addr += SIS182_SATA1_OFS; | |
166 | break; | |
167 | } | |
8add7885 | 168 | } |
1da177e4 LT |
169 | return addr; |
170 | } | |
171 | ||
172 | static u32 sis_scr_cfg_read (struct ata_port *ap, unsigned int sc_reg) | |
173 | { | |
cca3974e | 174 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); |
9b14dec5 | 175 | unsigned int cfg_addr = get_scr_cfg_addr(ap, sc_reg); |
668e4bc7 | 176 | u32 val, val2 = 0; |
f2c853bc | 177 | u8 pmr; |
1da177e4 LT |
178 | |
179 | if (sc_reg == SCR_ERROR) /* doesn't exist in PCI cfg space */ | |
180 | return 0xffffffff; | |
f2c853bc AP |
181 | |
182 | pci_read_config_byte(pdev, SIS_PMR, &pmr); | |
8add7885 | 183 | |
1da177e4 | 184 | pci_read_config_dword(pdev, cfg_addr, &val); |
f2c853bc | 185 | |
3f3e7313 UK |
186 | if ((pdev->device == 0x0182) || (pdev->device == 0x0183) || (pdev->device == 0x1182) || |
187 | (pdev->device == 0x1183) || (pmr & SIS_PMR_COMBINED)) | |
f2c853bc AP |
188 | pci_read_config_dword(pdev, cfg_addr+0x10, &val2); |
189 | ||
4adccf6f | 190 | return (val|val2) & 0xfffffffb; /* avoid problems with powerdowned ports */ |
1da177e4 LT |
191 | } |
192 | ||
9b14dec5 | 193 | static void sis_scr_cfg_write (struct ata_port *ap, unsigned int sc_reg, u32 val) |
1da177e4 | 194 | { |
cca3974e | 195 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); |
9b14dec5 | 196 | unsigned int cfg_addr = get_scr_cfg_addr(ap, sc_reg); |
f2c853bc | 197 | u8 pmr; |
1da177e4 | 198 | |
9b14dec5 | 199 | if (sc_reg == SCR_ERROR) /* doesn't exist in PCI cfg space */ |
1da177e4 | 200 | return; |
f2c853bc AP |
201 | |
202 | pci_read_config_byte(pdev, SIS_PMR, &pmr); | |
8add7885 | 203 | |
1da177e4 | 204 | pci_write_config_dword(pdev, cfg_addr, val); |
f2c853bc | 205 | |
3f3e7313 UK |
206 | if ((pdev->device == 0x0182) || (pdev->device == 0x0183) || (pdev->device == 0x1182) || |
207 | (pdev->device == 0x1183) || (pmr & SIS_PMR_COMBINED)) | |
f2c853bc | 208 | pci_write_config_dword(pdev, cfg_addr+0x10, val); |
1da177e4 LT |
209 | } |
210 | ||
211 | static u32 sis_scr_read (struct ata_port *ap, unsigned int sc_reg) | |
212 | { | |
cca3974e | 213 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); |
8add7885 | 214 | u32 val, val2 = 0; |
f2c853bc AP |
215 | u8 pmr; |
216 | ||
1da177e4 LT |
217 | if (sc_reg > SCR_CONTROL) |
218 | return 0xffffffffU; | |
219 | ||
220 | if (ap->flags & SIS_FLAG_CFGSCR) | |
221 | return sis_scr_cfg_read(ap, sc_reg); | |
f2c853bc AP |
222 | |
223 | pci_read_config_byte(pdev, SIS_PMR, &pmr); | |
224 | ||
225 | val = inl(ap->ioaddr.scr_addr + (sc_reg * 4)); | |
226 | ||
3f3e7313 UK |
227 | if ((pdev->device == 0x0182) || (pdev->device == 0x0183) || (pdev->device == 0x1182) || |
228 | (pdev->device == 0x1183) || (pmr & SIS_PMR_COMBINED)) | |
8add7885 | 229 | val2 = inl(ap->ioaddr.scr_addr + (sc_reg * 4) + 0x10); |
f2c853bc | 230 | |
4adccf6f | 231 | return (val | val2) & 0xfffffffb; |
1da177e4 LT |
232 | } |
233 | ||
234 | static void sis_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val) | |
235 | { | |
cca3974e | 236 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); |
f2c853bc AP |
237 | u8 pmr; |
238 | ||
1da177e4 LT |
239 | if (sc_reg > SCR_CONTROL) |
240 | return; | |
241 | ||
f2c853bc | 242 | pci_read_config_byte(pdev, SIS_PMR, &pmr); |
8add7885 | 243 | |
1da177e4 LT |
244 | if (ap->flags & SIS_FLAG_CFGSCR) |
245 | sis_scr_cfg_write(ap, sc_reg, val); | |
f2c853bc | 246 | else { |
1da177e4 | 247 | outl(val, ap->ioaddr.scr_addr + (sc_reg * 4)); |
3f3e7313 UK |
248 | if ((pdev->device == 0x0182) || (pdev->device == 0x0183) || (pdev->device == 0x1182) || |
249 | (pdev->device == 0x1183) || (pmr & SIS_PMR_COMBINED)) | |
f2c853bc AP |
250 | outl(val, ap->ioaddr.scr_addr + (sc_reg * 4)+0x10); |
251 | } | |
1da177e4 LT |
252 | } |
253 | ||
1da177e4 LT |
254 | static int sis_init_one (struct pci_dev *pdev, const struct pci_device_id *ent) |
255 | { | |
a9524a76 | 256 | static int printed_version; |
1da177e4 LT |
257 | struct ata_probe_ent *probe_ent = NULL; |
258 | int rc; | |
4adccf6f | 259 | u32 genctl, val; |
cf0e812f | 260 | struct ata_port_info pi = sis_port_info, *ppi[2] = { &pi, &pi }; |
f2c853bc | 261 | u8 pmr; |
3f3e7313 | 262 | u8 port2_start = 0x20; |
1da177e4 | 263 | |
a9524a76 JG |
264 | if (!printed_version++) |
265 | dev_printk(KERN_INFO, &pdev->dev, "version " DRV_VERSION "\n"); | |
266 | ||
24dc5f33 | 267 | rc = pcim_enable_device(pdev); |
1da177e4 LT |
268 | if (rc) |
269 | return rc; | |
270 | ||
271 | rc = pci_request_regions(pdev, DRV_NAME); | |
272 | if (rc) { | |
24dc5f33 TH |
273 | pcim_pin_device(pdev); |
274 | return rc; | |
1da177e4 LT |
275 | } |
276 | ||
277 | rc = pci_set_dma_mask(pdev, ATA_DMA_MASK); | |
278 | if (rc) | |
24dc5f33 | 279 | return rc; |
1da177e4 LT |
280 | rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK); |
281 | if (rc) | |
24dc5f33 | 282 | return rc; |
1da177e4 | 283 | |
1da177e4 LT |
284 | /* check and see if the SCRs are in IO space or PCI cfg space */ |
285 | pci_read_config_dword(pdev, SIS_GENCTL, &genctl); | |
286 | if ((genctl & GENCTL_IOMAPPED_SCR) == 0) | |
cf0e812f | 287 | pi.flags |= SIS_FLAG_CFGSCR; |
8a60a071 | 288 | |
1da177e4 LT |
289 | /* if hardware thinks SCRs are in IO space, but there are |
290 | * no IO resources assigned, change to PCI cfg space. | |
291 | */ | |
cf0e812f | 292 | if ((!(pi.flags & SIS_FLAG_CFGSCR)) && |
1da177e4 LT |
293 | ((pci_resource_start(pdev, SIS_SCR_PCI_BAR) == 0) || |
294 | (pci_resource_len(pdev, SIS_SCR_PCI_BAR) < 128))) { | |
295 | genctl &= ~GENCTL_IOMAPPED_SCR; | |
296 | pci_write_config_dword(pdev, SIS_GENCTL, genctl); | |
cf0e812f | 297 | pi.flags |= SIS_FLAG_CFGSCR; |
1da177e4 LT |
298 | } |
299 | ||
f2c853bc | 300 | pci_read_config_byte(pdev, SIS_PMR, &pmr); |
3f3e7313 UK |
301 | switch (ent->device) { |
302 | case 0x0180: | |
303 | case 0x0181: | |
9b14dec5 A |
304 | |
305 | /* The PATA-handling is provided by pata_sis */ | |
306 | switch (pmr & 0x30) { | |
307 | case 0x10: | |
308 | ppi[1] = &sis_info133; | |
309 | break; | |
310 | ||
311 | case 0x30: | |
312 | ppi[0] = &sis_info133; | |
313 | break; | |
314 | } | |
f2c853bc | 315 | if ((pmr & SIS_PMR_COMBINED) == 0) { |
a9524a76 | 316 | dev_printk(KERN_INFO, &pdev->dev, |
4adccf6f | 317 | "Detected SiS 180/181/964 chipset in SATA mode\n"); |
39eb936c | 318 | port2_start = 64; |
3f3e7313 | 319 | } else { |
a9524a76 JG |
320 | dev_printk(KERN_INFO, &pdev->dev, |
321 | "Detected SiS 180/181 chipset in combined mode\n"); | |
f2c853bc | 322 | port2_start=0; |
4adccf6f | 323 | pi.flags |= ATA_FLAG_SLAVE_POSS; |
f2c853bc | 324 | } |
3f3e7313 | 325 | break; |
f20b16ff | 326 | |
3f3e7313 UK |
327 | case 0x0182: |
328 | case 0x0183: | |
4adccf6f UK |
329 | pci_read_config_dword ( pdev, 0x6C, &val); |
330 | if (val & (1L << 31)) { | |
331 | dev_printk(KERN_INFO, &pdev->dev, "Detected SiS 182/965 chipset\n"); | |
332 | pi.flags |= ATA_FLAG_SLAVE_POSS; | |
3f3e7313 | 333 | } else { |
4adccf6f | 334 | dev_printk(KERN_INFO, &pdev->dev, "Detected SiS 182/965L chipset\n"); |
3f3e7313 UK |
335 | } |
336 | break; | |
337 | ||
338 | case 0x1182: | |
339 | case 0x1183: | |
340 | pci_read_config_dword(pdev, 0x64, &val); | |
341 | if (val & 0x10000000) { | |
342 | dev_printk(KERN_INFO, &pdev->dev, "Detected SiS 1182/1183/966L SATA controller\n"); | |
343 | } else { | |
344 | dev_printk(KERN_INFO, &pdev->dev, "Detected SiS 1182/1183/966 SATA controller\n"); | |
345 | pi.flags |= ATA_FLAG_SLAVE_POSS; | |
346 | } | |
347 | break; | |
f2c853bc AP |
348 | } |
349 | ||
cf0e812f | 350 | probe_ent = ata_pci_init_native_mode(pdev, ppi, ATA_PORT_PRIMARY | ATA_PORT_SECONDARY); |
24dc5f33 TH |
351 | if (!probe_ent) |
352 | return -ENOMEM; | |
cf0e812f | 353 | |
cca3974e | 354 | if (!(probe_ent->port_flags & SIS_FLAG_CFGSCR)) { |
1da177e4 LT |
355 | probe_ent->port[0].scr_addr = |
356 | pci_resource_start(pdev, SIS_SCR_PCI_BAR); | |
357 | probe_ent->port[1].scr_addr = | |
f2c853bc | 358 | pci_resource_start(pdev, SIS_SCR_PCI_BAR) + port2_start; |
1da177e4 LT |
359 | } |
360 | ||
361 | pci_set_master(pdev); | |
a04ce0ff | 362 | pci_intx(pdev, 1); |
1da177e4 | 363 | |
24dc5f33 TH |
364 | if (!ata_device_add(probe_ent)) |
365 | return -EIO; | |
1da177e4 | 366 | |
24dc5f33 | 367 | devm_kfree(&pdev->dev, probe_ent); |
1da177e4 LT |
368 | return 0; |
369 | ||
1da177e4 LT |
370 | } |
371 | ||
372 | static int __init sis_init(void) | |
373 | { | |
b7887196 | 374 | return pci_register_driver(&sis_pci_driver); |
1da177e4 LT |
375 | } |
376 | ||
377 | static void __exit sis_exit(void) | |
378 | { | |
379 | pci_unregister_driver(&sis_pci_driver); | |
380 | } | |
381 | ||
382 | module_init(sis_init); | |
383 | module_exit(sis_exit); |