[linux-2.6-block.git] / drivers / ata / sata_sis.c

// SPDX-License-Identifier: GPL-2.0-or-later
/*
 *  sata_sis.c - Silicon Integrated Systems SATA
 *
 *  Maintained by:  Uwe Koziolek
 *  		    Please ALWAYS copy linux-ide@vger.kernel.org
 *		    on emails.
 *
 *  Copyright 2004 Uwe Koziolek
 *
 *  libata documentation is available via 'make {ps|pdf}docs',
 *  as Documentation/driver-api/libata.rst
 *
 *  Hardware documentation available under NDA.
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/blkdev.h>
#include <linux/delay.h>
#include <linux/interrupt.h>
#include <linux/device.h>
#include <scsi/scsi_host.h>
#include <linux/libata.h>
#include "sis.h"

#define DRV_NAME	"sata_sis"
#define DRV_VERSION	"1.0"

enum {
	sis_180			= 0,
	SIS_SCR_PCI_BAR		= 5,

	/* PCI configuration registers */
	SIS_GENCTL		= 0x54, /* IDE General Control register */
	SIS_SCR_BASE		= 0xc0, /* sata0 phy SCR registers */
	SIS180_SATA1_OFS	= 0x10, /* offset from sata0->sata1 phy regs */
	SIS182_SATA1_OFS	= 0x20, /* offset from sata0->sata1 phy regs */
	SIS_PMR			= 0x90, /* port mapping register */
	SIS_PMR_COMBINED	= 0x30,

	/* random bits */
	SIS_FLAG_CFGSCR		= (1 << 30), /* host flag: SCRs via PCI cfg */

	GENCTL_IOMAPPED_SCR	= (1 << 26), /* if set, SCRs are in IO space */
};

static int sis_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
static int sis_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val);
static int sis_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val);

static const struct pci_device_id sis_pci_tbl[] = {
	{ PCI_VDEVICE(SI, 0x0180), sis_180 },	/* SiS 964/180 */
	{ PCI_VDEVICE(SI, 0x0181), sis_180 },	/* SiS 964/180 */
	{ PCI_VDEVICE(SI, 0x0182), sis_180 },	/* SiS 965/965L */
	{ PCI_VDEVICE(SI, 0x0183), sis_180 },	/* SiS 965/965L */
	{ PCI_VDEVICE(SI, 0x1182), sis_180 },	/* SiS 966/680 */
	{ PCI_VDEVICE(SI, 0x1183), sis_180 },	/* SiS 966/966L/968/680 */

	{ }	/* terminate list */
};

static struct pci_driver sis_pci_driver = {
	.name			= DRV_NAME,
	.id_table		= sis_pci_tbl,
	.probe			= sis_init_one,
	.remove			= ata_pci_remove_one,
#ifdef CONFIG_PM_SLEEP
	.suspend		= ata_pci_device_suspend,
	.resume			= ata_pci_device_resume,
#endif
};

static struct scsi_host_template sis_sht = {
	ATA_BMDMA_SHT(DRV_NAME),
};

static struct ata_port_operations sis_ops = {
	.inherits		= &ata_bmdma_port_ops,
	.scr_read		= sis_scr_read,
	.scr_write		= sis_scr_write,
};

static const struct ata_port_info sis_port_info = {
	.flags		= ATA_FLAG_SATA,
	.pio_mask	= ATA_PIO4,
	.mwdma_mask	= ATA_MWDMA2,
	.udma_mask	= ATA_UDMA6,
	.port_ops	= &sis_ops,
};

MODULE_AUTHOR("Uwe Koziolek");
MODULE_DESCRIPTION("low-level driver for Silicon Integrated Systems SATA controller");
MODULE_LICENSE("GPL");
MODULE_DEVICE_TABLE(pci, sis_pci_tbl);
MODULE_VERSION(DRV_VERSION);

static unsigned int get_scr_cfg_addr(struct ata_link *link, unsigned int sc_reg)
{
	struct ata_port *ap = link->ap;
	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	unsigned int addr = SIS_SCR_BASE + (4 * sc_reg);
	u8 pmr;

	if (ap->port_no)  {
		switch (pdev->device) {
		case 0x0180:
		case 0x0181:
			pci_read_config_byte(pdev, SIS_PMR, &pmr);
			if ((pmr & SIS_PMR_COMBINED) == 0)
				addr += SIS180_SATA1_OFS;
			break;

		case 0x0182:
		case 0x0183:
		case 0x1182:
			addr += SIS182_SATA1_OFS;
			break;
		}
	}
	if (link->pmp)
		addr += 0x10;

	return addr;
}

static u32 sis_scr_cfg_read(struct ata_link *link,
			    unsigned int sc_reg, u32 *val)
{
	struct pci_dev *pdev = to_pci_dev(link->ap->host->dev);
	unsigned int cfg_addr = get_scr_cfg_addr(link, sc_reg);

	if (sc_reg == SCR_ERROR) /* doesn't exist in PCI cfg space */
		return -EINVAL;

	pci_read_config_dword(pdev, cfg_addr, val);
	return 0;
}

static int sis_scr_cfg_write(struct ata_link *link,
			     unsigned int sc_reg, u32 val)
{
	struct pci_dev *pdev = to_pci_dev(link->ap->host->dev);
	unsigned int cfg_addr = get_scr_cfg_addr(link, sc_reg);

	pci_write_config_dword(pdev, cfg_addr, val);
	return 0;
}

static int sis_scr_read(struct ata_link *link, unsigned int sc_reg, u32 *val)
{
	struct ata_port *ap = link->ap;
	void __iomem *base = ap->ioaddr.scr_addr + link->pmp * 0x10;

	if (sc_reg > SCR_CONTROL)
		return -EINVAL;

	if (ap->flags & SIS_FLAG_CFGSCR)
		return sis_scr_cfg_read(link, sc_reg, val);

	*val = ioread32(base + sc_reg * 4);
	return 0;
}

static int sis_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val)
{
	struct ata_port *ap = link->ap;
	void __iomem *base = ap->ioaddr.scr_addr + link->pmp * 0x10;

	if (sc_reg > SCR_CONTROL)
		return -EINVAL;

	if (ap->flags & SIS_FLAG_CFGSCR)
		return sis_scr_cfg_write(link, sc_reg, val);

	iowrite32(val, base + (sc_reg * 4));
	return 0;
}

static int sis_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
{
	struct ata_port_info pi = sis_port_info;
	const struct ata_port_info *ppi[] = { &pi, &pi };
	struct ata_host *host;
	u32 genctl, val;
	u8 pmr;
	u8 port2_start = 0x20;
	int i, rc;

	ata_print_version_once(&pdev->dev, DRV_VERSION);

	rc = pcim_enable_device(pdev);
	if (rc)
		return rc;

	/* check and see if the SCRs are in IO space or PCI cfg space */
	pci_read_config_dword(pdev, SIS_GENCTL, &genctl);
	if ((genctl & GENCTL_IOMAPPED_SCR) == 0)
		pi.flags |= SIS_FLAG_CFGSCR;

	/* if hardware thinks SCRs are in IO space, but there are
	 * no IO resources assigned, change to PCI cfg space.
	 */
	if ((!(pi.flags & SIS_FLAG_CFGSCR)) &&
	    ((pci_resource_start(pdev, SIS_SCR_PCI_BAR) == 0) ||
	     (pci_resource_len(pdev, SIS_SCR_PCI_BAR) < 128))) {
		genctl &= ~GENCTL_IOMAPPED_SCR;
		pci_write_config_dword(pdev, SIS_GENCTL, genctl);
		pi.flags |= SIS_FLAG_CFGSCR;
	}

	pci_read_config_byte(pdev, SIS_PMR, &pmr);
	switch (ent->device) {
	case 0x0180:
	case 0x0181:

		/* The PATA-handling is provided by pata_sis */
		switch (pmr & 0x30) {
		case 0x10:
			ppi[1] = &sis_info133_for_sata;
			break;

		case 0x30:
			ppi[0] = &sis_info133_for_sata;
			break;
		}
		if ((pmr & SIS_PMR_COMBINED) == 0) {
			dev_info(&pdev->dev,
				 "Detected SiS 180/181/964 chipset in SATA mode\n");
			port2_start = 64;
		} else {
			dev_info(&pdev->dev,
				 "Detected SiS 180/181 chipset in combined mode\n");
			port2_start = 0;
			pi.flags |= ATA_FLAG_SLAVE_POSS;
		}
		break;

	case 0x0182:
	case 0x0183:
		pci_read_config_dword(pdev, 0x6C, &val);
		if (val & (1L << 31)) {
			dev_info(&pdev->dev, "Detected SiS 182/965 chipset\n");
			pi.flags |= ATA_FLAG_SLAVE_POSS;
		} else {
			dev_info(&pdev->dev, "Detected SiS 182/965L chipset\n");
		}
		break;

	case 0x1182:
		dev_info(&pdev->dev,
			 "Detected SiS 1182/966/680 SATA controller\n");
		pi.flags |= ATA_FLAG_SLAVE_POSS;
		break;

	case 0x1183:
		dev_info(&pdev->dev,
			 "Detected SiS 1183/966/966L/968/680 controller in PATA mode\n");
		ppi[0] = &sis_info133_for_sata;
		ppi[1] = &sis_info133_for_sata;
		break;
	}

	rc = ata_pci_bmdma_prepare_host(pdev, ppi, &host);
	if (rc)
		return rc;

	for (i = 0; i < 2; i++) {
		struct ata_port *ap = host->ports[i];

		if (ap->flags & ATA_FLAG_SATA &&
		    ap->flags & ATA_FLAG_SLAVE_POSS) {
			rc = ata_slave_link_init(ap);
			if (rc)
				return rc;
		}
	}

	if (!(pi.flags & SIS_FLAG_CFGSCR)) {
		void __iomem *mmio;

		rc = pcim_iomap_regions(pdev, 1 << SIS_SCR_PCI_BAR, DRV_NAME);
		if (rc)
			return rc;
		mmio = host->iomap[SIS_SCR_PCI_BAR];

		host->ports[0]->ioaddr.scr_addr = mmio;
		host->ports[1]->ioaddr.scr_addr = mmio + port2_start;
	}

	pci_set_master(pdev);
	pci_intx(pdev, 1);
	return ata_host_activate(host, pdev->irq, ata_bmdma_interrupt,
				 IRQF_SHARED, &sis_sht);
}

module_pci_driver(sis_pci_driver);
Commit	Line	Data
c82ee6d3	1	// SPDX-License-Identifier: GPL-2.0-or-later
1da177e4 LT	2	/*
	3	* sata_sis.c - Silicon Integrated Systems SATA
	4	*
	5	* Maintained by: Uwe Koziolek
	6	* Please ALWAYS copy linux-ide@vger.kernel.org
	7	* on emails.
	8	*
	9	* Copyright 2004 Uwe Koziolek
	10	*
af36d7f0	11	* libata documentation is available via 'make {ps\|pdf}docs',
19285f3c	12	* as Documentation/driver-api/libata.rst
af36d7f0 JG	13	*
af36d7f0 JG	14	* Hardware documentation available under NDA.
1da177e4 LT	15	*/
1da177e4 LT	16
1da177e4 LT	17	#include <linux/kernel.h>
	18	#include <linux/module.h>
	19	#include <linux/pci.h>
1da177e4 LT	20	#include <linux/blkdev.h>
	21	#include <linux/delay.h>
	22	#include <linux/interrupt.h>
a9524a76	23	#include <linux/device.h>
1da177e4 LT	24	#include <scsi/scsi_host.h>
1da177e4 LT	25	#include <linux/libata.h>
4bb64fb9	26	#include "sis.h"
1da177e4 LT	27
1da177e4 LT	28	#define DRV_NAME "sata_sis"
2a3103ce	29	#define DRV_VERSION "1.0"
1da177e4 LT	30
	31	enum {
	32	sis_180 = 0,
	33	SIS_SCR_PCI_BAR = 5,
	34
	35	/* PCI configuration registers */
	36	SIS_GENCTL = 0x54, /* IDE General Control register */
	37	SIS_SCR_BASE = 0xc0, /* sata0 phy SCR registers */
f2c853bc AP	38	SIS180_SATA1_OFS = 0x10, /* offset from sata0->sata1 phy regs */
	39	SIS182_SATA1_OFS = 0x20, /* offset from sata0->sata1 phy regs */
	40	SIS_PMR = 0x90, /* port mapping register */
8add7885	41	SIS_PMR_COMBINED = 0x30,
1da177e4 LT	42
	43	/* random bits */
	44	SIS_FLAG_CFGSCR = (1 << 30), /* host flag: SCRs via PCI cfg */
	45
	46	GENCTL_IOMAPPED_SCR = (1 << 26), /* if set, SCRs are in IO space */
	47	};
	48
5796d1c4	49	static int sis_init_one(struct pci_dev pdev, const struct pci_device_id ent);
82ef04fb TH	50	static int sis_scr_read(struct ata_link link, unsigned int sc_reg, u32 val);
82ef04fb TH	51	static int sis_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val);
1da177e4	52
3b7d697d	53	static const struct pci_device_id sis_pci_tbl[] = {
5796d1c4 JG	54	{ PCI_VDEVICE(SI, 0x0180), sis_180 }, /* SiS 964/180 */
	55	{ PCI_VDEVICE(SI, 0x0181), sis_180 }, /* SiS 964/180 */
	56	{ PCI_VDEVICE(SI, 0x0182), sis_180 }, /* SiS 965/965L */
	57	{ PCI_VDEVICE(SI, 0x0183), sis_180 }, /* SiS 965/965L */
	58	{ PCI_VDEVICE(SI, 0x1182), sis_180 }, /* SiS 966/680 */
	59	{ PCI_VDEVICE(SI, 0x1183), sis_180 }, /* SiS 966/966L/968/680 */
2d2744fc	60
1da177e4 LT	61	{ } /* terminate list */
	62	};
	63
1da177e4 LT	64	static struct pci_driver sis_pci_driver = {
	65	.name = DRV_NAME,
	66	.id_table = sis_pci_tbl,
	67	.probe = sis_init_one,
	68	.remove = ata_pci_remove_one,
58eb8cd5	69	#ifdef CONFIG_PM_SLEEP
55c82a6c A	70	.suspend = ata_pci_device_suspend,
	71	.resume = ata_pci_device_resume,
	72	#endif
1da177e4 LT	73	};
1da177e4 LT	74
193515d5	75	static struct scsi_host_template sis_sht = {
68d1d07b	76	ATA_BMDMA_SHT(DRV_NAME),
1da177e4 LT	77	};
1da177e4 LT	78
029cfd6b TH	79	static struct ata_port_operations sis_ops = {
029cfd6b TH	80	.inherits = &ata_bmdma_port_ops,
1da177e4 LT	81	.scr_read = sis_scr_read,
1da177e4 LT	82	.scr_write = sis_scr_write,
1da177e4 LT	83	};
1da177e4 LT	84
1626aeb8	85	static const struct ata_port_info sis_port_info = {
9cbe056f	86	.flags = ATA_FLAG_SATA,
14bdef98 EIB	87	.pio_mask = ATA_PIO4,
14bdef98 EIB	88	.mwdma_mask = ATA_MWDMA2,
bf6263a8	89	.udma_mask = ATA_UDMA6,
1da177e4 LT	90	.port_ops = &sis_ops,
	91	};
	92
1da177e4	93	MODULE_AUTHOR("Uwe Koziolek");
142924cf	94	MODULE_DESCRIPTION("low-level driver for Silicon Integrated Systems SATA controller");
1da177e4 LT	95	MODULE_LICENSE("GPL");
	96	MODULE_DEVICE_TABLE(pci, sis_pci_tbl);
	97	MODULE_VERSION(DRV_VERSION);
	98
72fee382	99	static unsigned int get_scr_cfg_addr(struct ata_link *link, unsigned int sc_reg)
1da177e4	100	{
72fee382	101	struct ata_port *ap = link->ap;
9b14dec5	102	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
1da177e4	103	unsigned int addr = SIS_SCR_BASE + (4 * sc_reg);
9b14dec5	104	u8 pmr;
1da177e4	105
9b14dec5	106	if (ap->port_no) {
3f3e7313	107	switch (pdev->device) {
5796d1c4 JG	108	case 0x0180:
	109	case 0x0181:
	110	pci_read_config_byte(pdev, SIS_PMR, &pmr);
	111	if ((pmr & SIS_PMR_COMBINED) == 0)
	112	addr += SIS180_SATA1_OFS;
	113	break;
	114
	115	case 0x0182:
	116	case 0x0183:
	117	case 0x1182:
	118	addr += SIS182_SATA1_OFS;
	119	break;
3f3e7313	120	}
8add7885	121	}
72fee382 TH	122	if (link->pmp)
	123	addr += 0x10;
	124
1da177e4 LT	125	return addr;
	126	}
	127
82ef04fb TH	128	static u32 sis_scr_cfg_read(struct ata_link *link,
82ef04fb TH	129	unsigned int sc_reg, u32 *val)
1da177e4	130	{
82ef04fb	131	struct pci_dev *pdev = to_pci_dev(link->ap->host->dev);
72fee382	132	unsigned int cfg_addr = get_scr_cfg_addr(link, sc_reg);
1da177e4 LT	133
1da177e4 LT	134	if (sc_reg == SCR_ERROR) /* doesn't exist in PCI cfg space */
8e5443a0	135	return -EINVAL;
f2c853bc	136
aaa092a1	137	pci_read_config_dword(pdev, cfg_addr, val);
aaa092a1	138	return 0;
1da177e4 LT	139	}
1da177e4 LT	140
82ef04fb TH	141	static int sis_scr_cfg_write(struct ata_link *link,
82ef04fb TH	142	unsigned int sc_reg, u32 val)
1da177e4	143	{
82ef04fb	144	struct pci_dev *pdev = to_pci_dev(link->ap->host->dev);
72fee382	145	unsigned int cfg_addr = get_scr_cfg_addr(link, sc_reg);
8add7885	146
1da177e4	147	pci_write_config_dword(pdev, cfg_addr, val);
8e5443a0	148	return 0;
1da177e4 LT	149	}
1da177e4 LT	150
82ef04fb	151	static int sis_scr_read(struct ata_link link, unsigned int sc_reg, u32 val)
1da177e4	152	{
82ef04fb	153	struct ata_port *ap = link->ap;
72fee382	154	void __iomem base = ap->ioaddr.scr_addr + link->pmp 0x10;
f2c853bc	155
1da177e4	156	if (sc_reg > SCR_CONTROL)
da3dbb17	157	return -EINVAL;
1da177e4 LT	158
1da177e4 LT	159	if (ap->flags & SIS_FLAG_CFGSCR)
82ef04fb	160	return sis_scr_cfg_read(link, sc_reg, val);
f2c853bc	161
72fee382	162	val = ioread32(base + sc_reg 4);
da3dbb17	163	return 0;
1da177e4 LT	164	}
1da177e4 LT	165
82ef04fb	166	static int sis_scr_write(struct ata_link *link, unsigned int sc_reg, u32 val)
1da177e4	167	{
82ef04fb	168	struct ata_port *ap = link->ap;
72fee382	169	void __iomem base = ap->ioaddr.scr_addr + link->pmp 0x10;
f2c853bc	170
1da177e4	171	if (sc_reg > SCR_CONTROL)
da3dbb17	172	return -EINVAL;
1da177e4 LT	173
1da177e4 LT	174	if (ap->flags & SIS_FLAG_CFGSCR)
82ef04fb	175	return sis_scr_cfg_write(link, sc_reg, val);
72fee382 TH	176
	177	iowrite32(val, base + (sc_reg * 4));
	178	return 0;
1da177e4 LT	179	}
1da177e4 LT	180
5796d1c4	181	static int sis_init_one(struct pci_dev pdev, const struct pci_device_id ent)
1da177e4	182	{
9a829ccf	183	struct ata_port_info pi = sis_port_info;
ddfc87a0	184	const struct ata_port_info *ppi[] = { &pi, &pi };
9a829ccf	185	struct ata_host *host;
4adccf6f	186	u32 genctl, val;
f2c853bc	187	u8 pmr;
3f3e7313	188	u8 port2_start = 0x20;
72fee382	189	int i, rc;
1da177e4	190
06296a1e	191	ata_print_version_once(&pdev->dev, DRV_VERSION);
a9524a76	192
24dc5f33	193	rc = pcim_enable_device(pdev);
1da177e4 LT	194	if (rc)
	195	return rc;
	196
1da177e4 LT	197	/* check and see if the SCRs are in IO space or PCI cfg space */
	198	pci_read_config_dword(pdev, SIS_GENCTL, &genctl);
	199	if ((genctl & GENCTL_IOMAPPED_SCR) == 0)
cf0e812f	200	pi.flags \|= SIS_FLAG_CFGSCR;
8a60a071	201
1da177e4 LT	202	/* if hardware thinks SCRs are in IO space, but there are
	203	* no IO resources assigned, change to PCI cfg space.
	204	*/
cf0e812f	205	if ((!(pi.flags & SIS_FLAG_CFGSCR)) &&
1da177e4 LT	206	((pci_resource_start(pdev, SIS_SCR_PCI_BAR) == 0) \|\|
	207	(pci_resource_len(pdev, SIS_SCR_PCI_BAR) < 128))) {
	208	genctl &= ~GENCTL_IOMAPPED_SCR;
	209	pci_write_config_dword(pdev, SIS_GENCTL, genctl);
cf0e812f	210	pi.flags \|= SIS_FLAG_CFGSCR;
1da177e4 LT	211	}
1da177e4 LT	212
f2c853bc	213	pci_read_config_byte(pdev, SIS_PMR, &pmr);
3f3e7313 UK	214	switch (ent->device) {
	215	case 0x0180:
	216	case 0x0181:
9b14dec5 A	217
	218	/* The PATA-handling is provided by pata_sis */
	219	switch (pmr & 0x30) {
	220	case 0x10:
a3cabb27	221	ppi[1] = &sis_info133_for_sata;
9b14dec5	222	break;
a84471fe	223
9b14dec5	224	case 0x30:
a3cabb27	225	ppi[0] = &sis_info133_for_sata;
9b14dec5 A	226	break;
9b14dec5 A	227	}
f2c853bc	228	if ((pmr & SIS_PMR_COMBINED) == 0) {
a44fec1f JP	229	dev_info(&pdev->dev,
a44fec1f JP	230	"Detected SiS 180/181/964 chipset in SATA mode\n");
39eb936c	231	port2_start = 64;
3f3e7313	232	} else {
a44fec1f JP	233	dev_info(&pdev->dev,
a44fec1f JP	234	"Detected SiS 180/181 chipset in combined mode\n");
5796d1c4	235	port2_start = 0;
4adccf6f	236	pi.flags \|= ATA_FLAG_SLAVE_POSS;
f2c853bc	237	}
3f3e7313	238	break;
f20b16ff	239
3f3e7313 UK	240	case 0x0182:
3f3e7313 UK	241	case 0x0183:
5796d1c4	242	pci_read_config_dword(pdev, 0x6C, &val);
4adccf6f	243	if (val & (1L << 31)) {
a44fec1f	244	dev_info(&pdev->dev, "Detected SiS 182/965 chipset\n");
4adccf6f	245	pi.flags \|= ATA_FLAG_SLAVE_POSS;
3f3e7313	246	} else {
a44fec1f	247	dev_info(&pdev->dev, "Detected SiS 182/965L chipset\n");
3f3e7313 UK	248	}
	249	break;
	250
	251	case 0x1182:
a44fec1f JP	252	dev_info(&pdev->dev,
a44fec1f JP	253	"Detected SiS 1182/966/680 SATA controller\n");
a3cabb27 UK	254	pi.flags \|= ATA_FLAG_SLAVE_POSS;
	255	break;
	256
3f3e7313	257	case 0x1183:
a44fec1f JP	258	dev_info(&pdev->dev,
a44fec1f JP	259	"Detected SiS 1183/966/966L/968/680 controller in PATA mode\n");
a3cabb27 UK	260	ppi[0] = &sis_info133_for_sata;
a3cabb27 UK	261	ppi[1] = &sis_info133_for_sata;
3f3e7313	262	break;
f2c853bc AP	263	}
f2c853bc AP	264
1c5afdf7	265	rc = ata_pci_bmdma_prepare_host(pdev, ppi, &host);
9a829ccf TH	266	if (rc)
9a829ccf TH	267	return rc;
cf0e812f	268
72fee382 TH	269	for (i = 0; i < 2; i++) {
	270	struct ata_port *ap = host->ports[i];
	271
	272	if (ap->flags & ATA_FLAG_SATA &&
	273	ap->flags & ATA_FLAG_SLAVE_POSS) {
	274	rc = ata_slave_link_init(ap);
	275	if (rc)
	276	return rc;
	277	}
	278	}
	279
9a829ccf	280	if (!(pi.flags & SIS_FLAG_CFGSCR)) {
edceec3d	281	void __iomem *mmio;
0d5ff566	282
9a829ccf TH	283	rc = pcim_iomap_regions(pdev, 1 << SIS_SCR_PCI_BAR, DRV_NAME);
	284	if (rc)
	285	return rc;
	286	mmio = host->iomap[SIS_SCR_PCI_BAR];
0d5ff566	287
9a829ccf TH	288	host->ports[0]->ioaddr.scr_addr = mmio;
9a829ccf TH	289	host->ports[1]->ioaddr.scr_addr = mmio + port2_start;
1da177e4 LT	290	}
	291
	292	pci_set_master(pdev);
a04ce0ff	293	pci_intx(pdev, 1);
c3b28894	294	return ata_host_activate(host, pdev->irq, ata_bmdma_interrupt,
9363c382	295	IRQF_SHARED, &sis_sht);
1da177e4 LT	296	}
1da177e4 LT	297
2fc75da0	298	module_pci_driver(sis_pci_driver);