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edb33667 TH |
1 | /* |
2 | * sata_sil24.c - Driver for Silicon Image 3124/3132 SATA-2 controllers | |
3 | * | |
4 | * Copyright 2005 Tejun Heo | |
5 | * | |
6 | * Based on preview driver from Silicon Image. | |
7 | * | |
edb33667 TH |
8 | * This program is free software; you can redistribute it and/or modify it |
9 | * under the terms of the GNU General Public License as published by the | |
10 | * Free Software Foundation; either version 2, or (at your option) any | |
11 | * later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, but | |
14 | * WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the GNU | |
16 | * General Public License for more details. | |
17 | * | |
18 | */ | |
19 | ||
20 | #include <linux/kernel.h> | |
21 | #include <linux/module.h> | |
22 | #include <linux/pci.h> | |
23 | #include <linux/blkdev.h> | |
24 | #include <linux/delay.h> | |
25 | #include <linux/interrupt.h> | |
26 | #include <linux/dma-mapping.h> | |
a9524a76 | 27 | #include <linux/device.h> |
edb33667 | 28 | #include <scsi/scsi_host.h> |
193515d5 | 29 | #include <scsi/scsi_cmnd.h> |
edb33667 | 30 | #include <linux/libata.h> |
edb33667 TH |
31 | |
32 | #define DRV_NAME "sata_sil24" | |
3454dc69 | 33 | #define DRV_VERSION "1.1" |
edb33667 | 34 | |
edb33667 TH |
35 | /* |
36 | * Port request block (PRB) 32 bytes | |
37 | */ | |
38 | struct sil24_prb { | |
b4772574 AD |
39 | __le16 ctrl; |
40 | __le16 prot; | |
41 | __le32 rx_cnt; | |
edb33667 TH |
42 | u8 fis[6 * 4]; |
43 | }; | |
44 | ||
45 | /* | |
46 | * Scatter gather entry (SGE) 16 bytes | |
47 | */ | |
48 | struct sil24_sge { | |
b4772574 AD |
49 | __le64 addr; |
50 | __le32 cnt; | |
51 | __le32 flags; | |
edb33667 TH |
52 | }; |
53 | ||
54 | /* | |
55 | * Port multiplier | |
56 | */ | |
57 | struct sil24_port_multiplier { | |
b4772574 AD |
58 | __le32 diag; |
59 | __le32 sactive; | |
edb33667 TH |
60 | }; |
61 | ||
62 | enum { | |
0d5ff566 TH |
63 | SIL24_HOST_BAR = 0, |
64 | SIL24_PORT_BAR = 2, | |
65 | ||
93e2618e TH |
66 | /* sil24 fetches in chunks of 64bytes. The first block |
67 | * contains the PRB and two SGEs. From the second block, it's | |
68 | * consisted of four SGEs and called SGT. Calculate the | |
69 | * number of SGTs that fit into one page. | |
70 | */ | |
71 | SIL24_PRB_SZ = sizeof(struct sil24_prb) | |
72 | + 2 * sizeof(struct sil24_sge), | |
73 | SIL24_MAX_SGT = (PAGE_SIZE - SIL24_PRB_SZ) | |
74 | / (4 * sizeof(struct sil24_sge)), | |
75 | ||
76 | /* This will give us one unused SGEs for ATA. This extra SGE | |
77 | * will be used to store CDB for ATAPI devices. | |
78 | */ | |
79 | SIL24_MAX_SGE = 4 * SIL24_MAX_SGT + 1, | |
80 | ||
edb33667 TH |
81 | /* |
82 | * Global controller registers (128 bytes @ BAR0) | |
83 | */ | |
84 | /* 32 bit regs */ | |
85 | HOST_SLOT_STAT = 0x00, /* 32 bit slot stat * 4 */ | |
86 | HOST_CTRL = 0x40, | |
87 | HOST_IRQ_STAT = 0x44, | |
88 | HOST_PHY_CFG = 0x48, | |
89 | HOST_BIST_CTRL = 0x50, | |
90 | HOST_BIST_PTRN = 0x54, | |
91 | HOST_BIST_STAT = 0x58, | |
92 | HOST_MEM_BIST_STAT = 0x5c, | |
93 | HOST_FLASH_CMD = 0x70, | |
94 | /* 8 bit regs */ | |
95 | HOST_FLASH_DATA = 0x74, | |
96 | HOST_TRANSITION_DETECT = 0x75, | |
97 | HOST_GPIO_CTRL = 0x76, | |
98 | HOST_I2C_ADDR = 0x78, /* 32 bit */ | |
99 | HOST_I2C_DATA = 0x7c, | |
100 | HOST_I2C_XFER_CNT = 0x7e, | |
101 | HOST_I2C_CTRL = 0x7f, | |
102 | ||
103 | /* HOST_SLOT_STAT bits */ | |
104 | HOST_SSTAT_ATTN = (1 << 31), | |
105 | ||
7dafc3fd TH |
106 | /* HOST_CTRL bits */ |
107 | HOST_CTRL_M66EN = (1 << 16), /* M66EN PCI bus signal */ | |
108 | HOST_CTRL_TRDY = (1 << 17), /* latched PCI TRDY */ | |
109 | HOST_CTRL_STOP = (1 << 18), /* latched PCI STOP */ | |
110 | HOST_CTRL_DEVSEL = (1 << 19), /* latched PCI DEVSEL */ | |
111 | HOST_CTRL_REQ64 = (1 << 20), /* latched PCI REQ64 */ | |
d2298dca | 112 | HOST_CTRL_GLOBAL_RST = (1 << 31), /* global reset */ |
7dafc3fd | 113 | |
edb33667 TH |
114 | /* |
115 | * Port registers | |
116 | * (8192 bytes @ +0x0000, +0x2000, +0x4000 and +0x6000 @ BAR2) | |
117 | */ | |
118 | PORT_REGS_SIZE = 0x2000, | |
135da345 | 119 | |
28c8f3b4 | 120 | PORT_LRAM = 0x0000, /* 31 LRAM slots and PMP regs */ |
135da345 | 121 | PORT_LRAM_SLOT_SZ = 0x0080, /* 32 bytes PRB + 2 SGE, ACT... */ |
edb33667 | 122 | |
28c8f3b4 | 123 | PORT_PMP = 0x0f80, /* 8 bytes PMP * 16 (128 bytes) */ |
c0c55908 TH |
124 | PORT_PMP_STATUS = 0x0000, /* port device status offset */ |
125 | PORT_PMP_QACTIVE = 0x0004, /* port device QActive offset */ | |
126 | PORT_PMP_SIZE = 0x0008, /* 8 bytes per PMP */ | |
127 | ||
edb33667 | 128 | /* 32 bit regs */ |
83bbecc9 TH |
129 | PORT_CTRL_STAT = 0x1000, /* write: ctrl-set, read: stat */ |
130 | PORT_CTRL_CLR = 0x1004, /* write: ctrl-clear */ | |
131 | PORT_IRQ_STAT = 0x1008, /* high: status, low: interrupt */ | |
132 | PORT_IRQ_ENABLE_SET = 0x1010, /* write: enable-set */ | |
133 | PORT_IRQ_ENABLE_CLR = 0x1014, /* write: enable-clear */ | |
edb33667 | 134 | PORT_ACTIVATE_UPPER_ADDR= 0x101c, |
83bbecc9 TH |
135 | PORT_EXEC_FIFO = 0x1020, /* command execution fifo */ |
136 | PORT_CMD_ERR = 0x1024, /* command error number */ | |
edb33667 TH |
137 | PORT_FIS_CFG = 0x1028, |
138 | PORT_FIFO_THRES = 0x102c, | |
139 | /* 16 bit regs */ | |
140 | PORT_DECODE_ERR_CNT = 0x1040, | |
141 | PORT_DECODE_ERR_THRESH = 0x1042, | |
142 | PORT_CRC_ERR_CNT = 0x1044, | |
143 | PORT_CRC_ERR_THRESH = 0x1046, | |
144 | PORT_HSHK_ERR_CNT = 0x1048, | |
145 | PORT_HSHK_ERR_THRESH = 0x104a, | |
146 | /* 32 bit regs */ | |
147 | PORT_PHY_CFG = 0x1050, | |
148 | PORT_SLOT_STAT = 0x1800, | |
149 | PORT_CMD_ACTIVATE = 0x1c00, /* 64 bit cmd activate * 31 (248 bytes) */ | |
c0c55908 | 150 | PORT_CONTEXT = 0x1e04, |
edb33667 TH |
151 | PORT_EXEC_DIAG = 0x1e00, /* 32bit exec diag * 16 (64 bytes, 0-10 used on 3124) */ |
152 | PORT_PSD_DIAG = 0x1e40, /* 32bit psd diag * 16 (64 bytes, 0-8 used on 3124) */ | |
153 | PORT_SCONTROL = 0x1f00, | |
154 | PORT_SSTATUS = 0x1f04, | |
155 | PORT_SERROR = 0x1f08, | |
156 | PORT_SACTIVE = 0x1f0c, | |
157 | ||
158 | /* PORT_CTRL_STAT bits */ | |
159 | PORT_CS_PORT_RST = (1 << 0), /* port reset */ | |
160 | PORT_CS_DEV_RST = (1 << 1), /* device reset */ | |
161 | PORT_CS_INIT = (1 << 2), /* port initialize */ | |
162 | PORT_CS_IRQ_WOC = (1 << 3), /* interrupt write one to clear */ | |
d10cb35a | 163 | PORT_CS_CDB16 = (1 << 5), /* 0=12b cdb, 1=16b cdb */ |
28c8f3b4 | 164 | PORT_CS_PMP_RESUME = (1 << 6), /* PMP resume */ |
e382eb1d | 165 | PORT_CS_32BIT_ACTV = (1 << 10), /* 32-bit activation */ |
28c8f3b4 | 166 | PORT_CS_PMP_EN = (1 << 13), /* port multiplier enable */ |
e382eb1d | 167 | PORT_CS_RDY = (1 << 31), /* port ready to accept commands */ |
edb33667 TH |
168 | |
169 | /* PORT_IRQ_STAT/ENABLE_SET/CLR */ | |
170 | /* bits[11:0] are masked */ | |
171 | PORT_IRQ_COMPLETE = (1 << 0), /* command(s) completed */ | |
172 | PORT_IRQ_ERROR = (1 << 1), /* command execution error */ | |
173 | PORT_IRQ_PORTRDY_CHG = (1 << 2), /* port ready change */ | |
174 | PORT_IRQ_PWR_CHG = (1 << 3), /* power management change */ | |
175 | PORT_IRQ_PHYRDY_CHG = (1 << 4), /* PHY ready change */ | |
176 | PORT_IRQ_COMWAKE = (1 << 5), /* COMWAKE received */ | |
7dafc3fd TH |
177 | PORT_IRQ_UNK_FIS = (1 << 6), /* unknown FIS received */ |
178 | PORT_IRQ_DEV_XCHG = (1 << 7), /* device exchanged */ | |
179 | PORT_IRQ_8B10B = (1 << 8), /* 8b/10b decode error threshold */ | |
180 | PORT_IRQ_CRC = (1 << 9), /* CRC error threshold */ | |
181 | PORT_IRQ_HANDSHAKE = (1 << 10), /* handshake error threshold */ | |
3b9f1d0f | 182 | PORT_IRQ_SDB_NOTIFY = (1 << 11), /* SDB notify received */ |
edb33667 | 183 | |
88ce7550 | 184 | DEF_PORT_IRQ = PORT_IRQ_COMPLETE | PORT_IRQ_ERROR | |
0542925b | 185 | PORT_IRQ_PHYRDY_CHG | PORT_IRQ_DEV_XCHG | |
854c73a2 | 186 | PORT_IRQ_UNK_FIS | PORT_IRQ_SDB_NOTIFY, |
88ce7550 | 187 | |
edb33667 TH |
188 | /* bits[27:16] are unmasked (raw) */ |
189 | PORT_IRQ_RAW_SHIFT = 16, | |
190 | PORT_IRQ_MASKED_MASK = 0x7ff, | |
191 | PORT_IRQ_RAW_MASK = (0x7ff << PORT_IRQ_RAW_SHIFT), | |
192 | ||
193 | /* ENABLE_SET/CLR specific, intr steering - 2 bit field */ | |
194 | PORT_IRQ_STEER_SHIFT = 30, | |
195 | PORT_IRQ_STEER_MASK = (3 << PORT_IRQ_STEER_SHIFT), | |
196 | ||
197 | /* PORT_CMD_ERR constants */ | |
198 | PORT_CERR_DEV = 1, /* Error bit in D2H Register FIS */ | |
199 | PORT_CERR_SDB = 2, /* Error bit in SDB FIS */ | |
200 | PORT_CERR_DATA = 3, /* Error in data FIS not detected by dev */ | |
201 | PORT_CERR_SEND = 4, /* Initial cmd FIS transmission failure */ | |
202 | PORT_CERR_INCONSISTENT = 5, /* Protocol mismatch */ | |
203 | PORT_CERR_DIRECTION = 6, /* Data direction mismatch */ | |
204 | PORT_CERR_UNDERRUN = 7, /* Ran out of SGEs while writing */ | |
205 | PORT_CERR_OVERRUN = 8, /* Ran out of SGEs while reading */ | |
206 | PORT_CERR_PKT_PROT = 11, /* DIR invalid in 1st PIO setup of ATAPI */ | |
207 | PORT_CERR_SGT_BOUNDARY = 16, /* PLD ecode 00 - SGT not on qword boundary */ | |
208 | PORT_CERR_SGT_TGTABRT = 17, /* PLD ecode 01 - target abort */ | |
209 | PORT_CERR_SGT_MSTABRT = 18, /* PLD ecode 10 - master abort */ | |
210 | PORT_CERR_SGT_PCIPERR = 19, /* PLD ecode 11 - PCI parity err while fetching SGT */ | |
211 | PORT_CERR_CMD_BOUNDARY = 24, /* ctrl[15:13] 001 - PRB not on qword boundary */ | |
212 | PORT_CERR_CMD_TGTABRT = 25, /* ctrl[15:13] 010 - target abort */ | |
213 | PORT_CERR_CMD_MSTABRT = 26, /* ctrl[15:13] 100 - master abort */ | |
214 | PORT_CERR_CMD_PCIPERR = 27, /* ctrl[15:13] 110 - PCI parity err while fetching PRB */ | |
215 | PORT_CERR_XFR_UNDEF = 32, /* PSD ecode 00 - undefined */ | |
216 | PORT_CERR_XFR_TGTABRT = 33, /* PSD ecode 01 - target abort */ | |
64008802 | 217 | PORT_CERR_XFR_MSTABRT = 34, /* PSD ecode 10 - master abort */ |
edb33667 | 218 | PORT_CERR_XFR_PCIPERR = 35, /* PSD ecode 11 - PCI prity err during transfer */ |
83bbecc9 | 219 | PORT_CERR_SENDSERVICE = 36, /* FIS received while sending service */ |
edb33667 | 220 | |
d10cb35a TH |
221 | /* bits of PRB control field */ |
222 | PRB_CTRL_PROTOCOL = (1 << 0), /* override def. ATA protocol */ | |
223 | PRB_CTRL_PACKET_READ = (1 << 4), /* PACKET cmd read */ | |
224 | PRB_CTRL_PACKET_WRITE = (1 << 5), /* PACKET cmd write */ | |
225 | PRB_CTRL_NIEN = (1 << 6), /* Mask completion irq */ | |
226 | PRB_CTRL_SRST = (1 << 7), /* Soft reset request (ign BSY?) */ | |
227 | ||
228 | /* PRB protocol field */ | |
229 | PRB_PROT_PACKET = (1 << 0), | |
230 | PRB_PROT_TCQ = (1 << 1), | |
231 | PRB_PROT_NCQ = (1 << 2), | |
232 | PRB_PROT_READ = (1 << 3), | |
233 | PRB_PROT_WRITE = (1 << 4), | |
234 | PRB_PROT_TRANSPARENT = (1 << 5), | |
235 | ||
edb33667 TH |
236 | /* |
237 | * Other constants | |
238 | */ | |
239 | SGE_TRM = (1 << 31), /* Last SGE in chain */ | |
d10cb35a TH |
240 | SGE_LNK = (1 << 30), /* linked list |
241 | Points to SGT, not SGE */ | |
242 | SGE_DRD = (1 << 29), /* discard data read (/dev/null) | |
243 | data address ignored */ | |
edb33667 | 244 | |
aee10a03 TH |
245 | SIL24_MAX_CMDS = 31, |
246 | ||
edb33667 TH |
247 | /* board id */ |
248 | BID_SIL3124 = 0, | |
249 | BID_SIL3132 = 1, | |
042c21fd | 250 | BID_SIL3131 = 2, |
edb33667 | 251 | |
9466d85b TH |
252 | /* host flags */ |
253 | SIL24_COMMON_FLAGS = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY | | |
aee10a03 | 254 | ATA_FLAG_MMIO | ATA_FLAG_PIO_DMA | |
854c73a2 | 255 | ATA_FLAG_NCQ | ATA_FLAG_ACPI_SATA | |
3454dc69 | 256 | ATA_FLAG_AN | ATA_FLAG_PMP, |
37024e8e | 257 | SIL24_FLAG_PCIX_IRQ_WOC = (1 << 24), /* IRQ loss errata on PCI-X */ |
9466d85b | 258 | |
edb33667 TH |
259 | IRQ_STAT_4PORTS = 0xf, |
260 | }; | |
261 | ||
69ad185f | 262 | struct sil24_ata_block { |
edb33667 | 263 | struct sil24_prb prb; |
93e2618e | 264 | struct sil24_sge sge[SIL24_MAX_SGE]; |
edb33667 TH |
265 | }; |
266 | ||
69ad185f TH |
267 | struct sil24_atapi_block { |
268 | struct sil24_prb prb; | |
269 | u8 cdb[16]; | |
93e2618e | 270 | struct sil24_sge sge[SIL24_MAX_SGE]; |
69ad185f TH |
271 | }; |
272 | ||
273 | union sil24_cmd_block { | |
274 | struct sil24_ata_block ata; | |
275 | struct sil24_atapi_block atapi; | |
276 | }; | |
277 | ||
88ce7550 TH |
278 | static struct sil24_cerr_info { |
279 | unsigned int err_mask, action; | |
280 | const char *desc; | |
281 | } sil24_cerr_db[] = { | |
f90f0828 | 282 | [0] = { AC_ERR_DEV, 0, |
88ce7550 | 283 | "device error" }, |
f90f0828 | 284 | [PORT_CERR_DEV] = { AC_ERR_DEV, 0, |
88ce7550 | 285 | "device error via D2H FIS" }, |
f90f0828 | 286 | [PORT_CERR_SDB] = { AC_ERR_DEV, 0, |
88ce7550 | 287 | "device error via SDB FIS" }, |
cf480626 | 288 | [PORT_CERR_DATA] = { AC_ERR_ATA_BUS, ATA_EH_RESET, |
88ce7550 | 289 | "error in data FIS" }, |
cf480626 | 290 | [PORT_CERR_SEND] = { AC_ERR_ATA_BUS, ATA_EH_RESET, |
88ce7550 | 291 | "failed to transmit command FIS" }, |
cf480626 | 292 | [PORT_CERR_INCONSISTENT] = { AC_ERR_HSM, ATA_EH_RESET, |
88ce7550 | 293 | "protocol mismatch" }, |
cf480626 | 294 | [PORT_CERR_DIRECTION] = { AC_ERR_HSM, ATA_EH_RESET, |
88ce7550 | 295 | "data directon mismatch" }, |
cf480626 | 296 | [PORT_CERR_UNDERRUN] = { AC_ERR_HSM, ATA_EH_RESET, |
88ce7550 | 297 | "ran out of SGEs while writing" }, |
cf480626 | 298 | [PORT_CERR_OVERRUN] = { AC_ERR_HSM, ATA_EH_RESET, |
88ce7550 | 299 | "ran out of SGEs while reading" }, |
cf480626 | 300 | [PORT_CERR_PKT_PROT] = { AC_ERR_HSM, ATA_EH_RESET, |
88ce7550 | 301 | "invalid data directon for ATAPI CDB" }, |
cf480626 | 302 | [PORT_CERR_SGT_BOUNDARY] = { AC_ERR_SYSTEM, ATA_EH_RESET, |
7293fa8f | 303 | "SGT not on qword boundary" }, |
cf480626 | 304 | [PORT_CERR_SGT_TGTABRT] = { AC_ERR_HOST_BUS, ATA_EH_RESET, |
88ce7550 | 305 | "PCI target abort while fetching SGT" }, |
cf480626 | 306 | [PORT_CERR_SGT_MSTABRT] = { AC_ERR_HOST_BUS, ATA_EH_RESET, |
88ce7550 | 307 | "PCI master abort while fetching SGT" }, |
cf480626 | 308 | [PORT_CERR_SGT_PCIPERR] = { AC_ERR_HOST_BUS, ATA_EH_RESET, |
88ce7550 | 309 | "PCI parity error while fetching SGT" }, |
cf480626 | 310 | [PORT_CERR_CMD_BOUNDARY] = { AC_ERR_SYSTEM, ATA_EH_RESET, |
88ce7550 | 311 | "PRB not on qword boundary" }, |
cf480626 | 312 | [PORT_CERR_CMD_TGTABRT] = { AC_ERR_HOST_BUS, ATA_EH_RESET, |
88ce7550 | 313 | "PCI target abort while fetching PRB" }, |
cf480626 | 314 | [PORT_CERR_CMD_MSTABRT] = { AC_ERR_HOST_BUS, ATA_EH_RESET, |
88ce7550 | 315 | "PCI master abort while fetching PRB" }, |
cf480626 | 316 | [PORT_CERR_CMD_PCIPERR] = { AC_ERR_HOST_BUS, ATA_EH_RESET, |
88ce7550 | 317 | "PCI parity error while fetching PRB" }, |
cf480626 | 318 | [PORT_CERR_XFR_UNDEF] = { AC_ERR_HOST_BUS, ATA_EH_RESET, |
88ce7550 | 319 | "undefined error while transferring data" }, |
cf480626 | 320 | [PORT_CERR_XFR_TGTABRT] = { AC_ERR_HOST_BUS, ATA_EH_RESET, |
88ce7550 | 321 | "PCI target abort while transferring data" }, |
cf480626 | 322 | [PORT_CERR_XFR_MSTABRT] = { AC_ERR_HOST_BUS, ATA_EH_RESET, |
88ce7550 | 323 | "PCI master abort while transferring data" }, |
cf480626 | 324 | [PORT_CERR_XFR_PCIPERR] = { AC_ERR_HOST_BUS, ATA_EH_RESET, |
88ce7550 | 325 | "PCI parity error while transferring data" }, |
cf480626 | 326 | [PORT_CERR_SENDSERVICE] = { AC_ERR_HSM, ATA_EH_RESET, |
88ce7550 TH |
327 | "FIS received while sending service FIS" }, |
328 | }; | |
329 | ||
edb33667 TH |
330 | /* |
331 | * ap->private_data | |
332 | * | |
333 | * The preview driver always returned 0 for status. We emulate it | |
334 | * here from the previous interrupt. | |
335 | */ | |
336 | struct sil24_port_priv { | |
69ad185f | 337 | union sil24_cmd_block *cmd_block; /* 32 cmd blocks */ |
edb33667 | 338 | dma_addr_t cmd_block_dma; /* DMA base addr for them */ |
23818034 | 339 | int do_port_rst; |
edb33667 TH |
340 | }; |
341 | ||
cd0d3bbc | 342 | static void sil24_dev_config(struct ata_device *dev); |
82ef04fb TH |
343 | static int sil24_scr_read(struct ata_link *link, unsigned sc_reg, u32 *val); |
344 | static int sil24_scr_write(struct ata_link *link, unsigned sc_reg, u32 val); | |
3454dc69 | 345 | static int sil24_qc_defer(struct ata_queued_cmd *qc); |
edb33667 | 346 | static void sil24_qc_prep(struct ata_queued_cmd *qc); |
9a3d9eb0 | 347 | static unsigned int sil24_qc_issue(struct ata_queued_cmd *qc); |
79f97dad | 348 | static bool sil24_qc_fill_rtf(struct ata_queued_cmd *qc); |
3454dc69 TH |
349 | static void sil24_pmp_attach(struct ata_port *ap); |
350 | static void sil24_pmp_detach(struct ata_port *ap); | |
88ce7550 TH |
351 | static void sil24_freeze(struct ata_port *ap); |
352 | static void sil24_thaw(struct ata_port *ap); | |
a1efdaba TH |
353 | static int sil24_softreset(struct ata_link *link, unsigned int *class, |
354 | unsigned long deadline); | |
355 | static int sil24_hardreset(struct ata_link *link, unsigned int *class, | |
356 | unsigned long deadline); | |
a1efdaba TH |
357 | static int sil24_pmp_hardreset(struct ata_link *link, unsigned int *class, |
358 | unsigned long deadline); | |
88ce7550 TH |
359 | static void sil24_error_handler(struct ata_port *ap); |
360 | static void sil24_post_internal_cmd(struct ata_queued_cmd *qc); | |
edb33667 | 361 | static int sil24_port_start(struct ata_port *ap); |
edb33667 | 362 | static int sil24_init_one(struct pci_dev *pdev, const struct pci_device_id *ent); |
281d426c | 363 | #ifdef CONFIG_PM |
d2298dca | 364 | static int sil24_pci_device_resume(struct pci_dev *pdev); |
3454dc69 | 365 | static int sil24_port_resume(struct ata_port *ap); |
281d426c | 366 | #endif |
edb33667 | 367 | |
3b7d697d | 368 | static const struct pci_device_id sil24_pci_tbl[] = { |
54bb3a94 JG |
369 | { PCI_VDEVICE(CMD, 0x3124), BID_SIL3124 }, |
370 | { PCI_VDEVICE(INTEL, 0x3124), BID_SIL3124 }, | |
371 | { PCI_VDEVICE(CMD, 0x3132), BID_SIL3132 }, | |
722d67b6 | 372 | { PCI_VDEVICE(CMD, 0x0242), BID_SIL3132 }, |
464b3286 | 373 | { PCI_VDEVICE(CMD, 0x0244), BID_SIL3132 }, |
54bb3a94 JG |
374 | { PCI_VDEVICE(CMD, 0x3131), BID_SIL3131 }, |
375 | { PCI_VDEVICE(CMD, 0x3531), BID_SIL3131 }, | |
376 | ||
1fcce839 | 377 | { } /* terminate list */ |
edb33667 TH |
378 | }; |
379 | ||
380 | static struct pci_driver sil24_pci_driver = { | |
381 | .name = DRV_NAME, | |
382 | .id_table = sil24_pci_tbl, | |
383 | .probe = sil24_init_one, | |
24dc5f33 | 384 | .remove = ata_pci_remove_one, |
281d426c | 385 | #ifdef CONFIG_PM |
d2298dca TH |
386 | .suspend = ata_pci_device_suspend, |
387 | .resume = sil24_pci_device_resume, | |
281d426c | 388 | #endif |
edb33667 TH |
389 | }; |
390 | ||
193515d5 | 391 | static struct scsi_host_template sil24_sht = { |
68d1d07b | 392 | ATA_NCQ_SHT(DRV_NAME), |
aee10a03 | 393 | .can_queue = SIL24_MAX_CMDS, |
93e2618e | 394 | .sg_tablesize = SIL24_MAX_SGE, |
edb33667 | 395 | .dma_boundary = ATA_DMA_BOUNDARY, |
edb33667 TH |
396 | }; |
397 | ||
029cfd6b TH |
398 | static struct ata_port_operations sil24_ops = { |
399 | .inherits = &sata_pmp_port_ops, | |
69ad185f | 400 | |
3454dc69 | 401 | .qc_defer = sil24_qc_defer, |
edb33667 TH |
402 | .qc_prep = sil24_qc_prep, |
403 | .qc_issue = sil24_qc_issue, | |
79f97dad | 404 | .qc_fill_rtf = sil24_qc_fill_rtf, |
edb33667 | 405 | |
029cfd6b TH |
406 | .freeze = sil24_freeze, |
407 | .thaw = sil24_thaw, | |
a1efdaba TH |
408 | .softreset = sil24_softreset, |
409 | .hardreset = sil24_hardreset, | |
071f44b1 | 410 | .pmp_softreset = sil24_softreset, |
a1efdaba | 411 | .pmp_hardreset = sil24_pmp_hardreset, |
029cfd6b TH |
412 | .error_handler = sil24_error_handler, |
413 | .post_internal_cmd = sil24_post_internal_cmd, | |
414 | .dev_config = sil24_dev_config, | |
edb33667 TH |
415 | |
416 | .scr_read = sil24_scr_read, | |
417 | .scr_write = sil24_scr_write, | |
3454dc69 TH |
418 | .pmp_attach = sil24_pmp_attach, |
419 | .pmp_detach = sil24_pmp_detach, | |
3454dc69 | 420 | |
edb33667 | 421 | .port_start = sil24_port_start, |
3454dc69 TH |
422 | #ifdef CONFIG_PM |
423 | .port_resume = sil24_port_resume, | |
424 | #endif | |
edb33667 TH |
425 | }; |
426 | ||
042c21fd | 427 | /* |
cca3974e | 428 | * Use bits 30-31 of port_flags to encode available port numbers. |
042c21fd TH |
429 | * Current maxium is 4. |
430 | */ | |
431 | #define SIL24_NPORTS2FLAG(nports) ((((unsigned)(nports) - 1) & 0x3) << 30) | |
432 | #define SIL24_FLAG2NPORTS(flag) ((((flag) >> 30) & 0x3) + 1) | |
433 | ||
4447d351 | 434 | static const struct ata_port_info sil24_port_info[] = { |
edb33667 TH |
435 | /* sil_3124 */ |
436 | { | |
cca3974e | 437 | .flags = SIL24_COMMON_FLAGS | SIL24_NPORTS2FLAG(4) | |
37024e8e | 438 | SIL24_FLAG_PCIX_IRQ_WOC, |
edb33667 TH |
439 | .pio_mask = 0x1f, /* pio0-4 */ |
440 | .mwdma_mask = 0x07, /* mwdma0-2 */ | |
bf6263a8 | 441 | .udma_mask = ATA_UDMA5, /* udma0-5 */ |
edb33667 TH |
442 | .port_ops = &sil24_ops, |
443 | }, | |
2e9edbf8 | 444 | /* sil_3132 */ |
edb33667 | 445 | { |
cca3974e | 446 | .flags = SIL24_COMMON_FLAGS | SIL24_NPORTS2FLAG(2), |
042c21fd TH |
447 | .pio_mask = 0x1f, /* pio0-4 */ |
448 | .mwdma_mask = 0x07, /* mwdma0-2 */ | |
bf6263a8 | 449 | .udma_mask = ATA_UDMA5, /* udma0-5 */ |
042c21fd TH |
450 | .port_ops = &sil24_ops, |
451 | }, | |
452 | /* sil_3131/sil_3531 */ | |
453 | { | |
cca3974e | 454 | .flags = SIL24_COMMON_FLAGS | SIL24_NPORTS2FLAG(1), |
edb33667 TH |
455 | .pio_mask = 0x1f, /* pio0-4 */ |
456 | .mwdma_mask = 0x07, /* mwdma0-2 */ | |
bf6263a8 | 457 | .udma_mask = ATA_UDMA5, /* udma0-5 */ |
edb33667 TH |
458 | .port_ops = &sil24_ops, |
459 | }, | |
460 | }; | |
461 | ||
aee10a03 TH |
462 | static int sil24_tag(int tag) |
463 | { | |
464 | if (unlikely(ata_tag_internal(tag))) | |
465 | return 0; | |
466 | return tag; | |
467 | } | |
468 | ||
350756f6 TH |
469 | static unsigned long sil24_port_offset(struct ata_port *ap) |
470 | { | |
471 | return ap->port_no * PORT_REGS_SIZE; | |
472 | } | |
473 | ||
474 | static void __iomem *sil24_port_base(struct ata_port *ap) | |
475 | { | |
476 | return ap->host->iomap[SIL24_PORT_BAR] + sil24_port_offset(ap); | |
477 | } | |
478 | ||
cd0d3bbc | 479 | static void sil24_dev_config(struct ata_device *dev) |
69ad185f | 480 | { |
350756f6 | 481 | void __iomem *port = sil24_port_base(dev->link->ap); |
69ad185f | 482 | |
6e7846e9 | 483 | if (dev->cdb_len == 16) |
69ad185f TH |
484 | writel(PORT_CS_CDB16, port + PORT_CTRL_STAT); |
485 | else | |
486 | writel(PORT_CS_CDB16, port + PORT_CTRL_CLR); | |
487 | } | |
488 | ||
e59f0dad | 489 | static void sil24_read_tf(struct ata_port *ap, int tag, struct ata_taskfile *tf) |
6a575fa9 | 490 | { |
350756f6 | 491 | void __iomem *port = sil24_port_base(ap); |
e59f0dad | 492 | struct sil24_prb __iomem *prb; |
4b4a5eae | 493 | u8 fis[6 * 4]; |
6a575fa9 | 494 | |
e59f0dad TH |
495 | prb = port + PORT_LRAM + sil24_tag(tag) * PORT_LRAM_SLOT_SZ; |
496 | memcpy_fromio(fis, prb->fis, sizeof(fis)); | |
497 | ata_tf_from_fis(fis, tf); | |
6a575fa9 TH |
498 | } |
499 | ||
edb33667 TH |
500 | static int sil24_scr_map[] = { |
501 | [SCR_CONTROL] = 0, | |
502 | [SCR_STATUS] = 1, | |
503 | [SCR_ERROR] = 2, | |
504 | [SCR_ACTIVE] = 3, | |
505 | }; | |
506 | ||
82ef04fb | 507 | static int sil24_scr_read(struct ata_link *link, unsigned sc_reg, u32 *val) |
edb33667 | 508 | { |
82ef04fb | 509 | void __iomem *scr_addr = sil24_port_base(link->ap) + PORT_SCONTROL; |
da3dbb17 | 510 | |
edb33667 | 511 | if (sc_reg < ARRAY_SIZE(sil24_scr_map)) { |
4b4a5eae | 512 | void __iomem *addr; |
edb33667 | 513 | addr = scr_addr + sil24_scr_map[sc_reg] * 4; |
da3dbb17 TH |
514 | *val = readl(scr_addr + sil24_scr_map[sc_reg] * 4); |
515 | return 0; | |
edb33667 | 516 | } |
da3dbb17 | 517 | return -EINVAL; |
edb33667 TH |
518 | } |
519 | ||
82ef04fb | 520 | static int sil24_scr_write(struct ata_link *link, unsigned sc_reg, u32 val) |
edb33667 | 521 | { |
82ef04fb | 522 | void __iomem *scr_addr = sil24_port_base(link->ap) + PORT_SCONTROL; |
da3dbb17 | 523 | |
edb33667 | 524 | if (sc_reg < ARRAY_SIZE(sil24_scr_map)) { |
4b4a5eae | 525 | void __iomem *addr; |
edb33667 TH |
526 | addr = scr_addr + sil24_scr_map[sc_reg] * 4; |
527 | writel(val, scr_addr + sil24_scr_map[sc_reg] * 4); | |
da3dbb17 | 528 | return 0; |
edb33667 | 529 | } |
da3dbb17 | 530 | return -EINVAL; |
edb33667 TH |
531 | } |
532 | ||
23818034 TH |
533 | static void sil24_config_port(struct ata_port *ap) |
534 | { | |
350756f6 | 535 | void __iomem *port = sil24_port_base(ap); |
23818034 TH |
536 | |
537 | /* configure IRQ WoC */ | |
538 | if (ap->flags & SIL24_FLAG_PCIX_IRQ_WOC) | |
539 | writel(PORT_CS_IRQ_WOC, port + PORT_CTRL_STAT); | |
540 | else | |
541 | writel(PORT_CS_IRQ_WOC, port + PORT_CTRL_CLR); | |
542 | ||
543 | /* zero error counters. */ | |
544 | writel(0x8000, port + PORT_DECODE_ERR_THRESH); | |
545 | writel(0x8000, port + PORT_CRC_ERR_THRESH); | |
546 | writel(0x8000, port + PORT_HSHK_ERR_THRESH); | |
547 | writel(0x0000, port + PORT_DECODE_ERR_CNT); | |
548 | writel(0x0000, port + PORT_CRC_ERR_CNT); | |
549 | writel(0x0000, port + PORT_HSHK_ERR_CNT); | |
550 | ||
551 | /* always use 64bit activation */ | |
552 | writel(PORT_CS_32BIT_ACTV, port + PORT_CTRL_CLR); | |
553 | ||
554 | /* clear port multiplier enable and resume bits */ | |
555 | writel(PORT_CS_PMP_EN | PORT_CS_PMP_RESUME, port + PORT_CTRL_CLR); | |
556 | } | |
557 | ||
3454dc69 TH |
558 | static void sil24_config_pmp(struct ata_port *ap, int attached) |
559 | { | |
350756f6 | 560 | void __iomem *port = sil24_port_base(ap); |
3454dc69 TH |
561 | |
562 | if (attached) | |
563 | writel(PORT_CS_PMP_EN, port + PORT_CTRL_STAT); | |
564 | else | |
565 | writel(PORT_CS_PMP_EN, port + PORT_CTRL_CLR); | |
566 | } | |
567 | ||
568 | static void sil24_clear_pmp(struct ata_port *ap) | |
569 | { | |
350756f6 | 570 | void __iomem *port = sil24_port_base(ap); |
3454dc69 TH |
571 | int i; |
572 | ||
573 | writel(PORT_CS_PMP_RESUME, port + PORT_CTRL_CLR); | |
574 | ||
575 | for (i = 0; i < SATA_PMP_MAX_PORTS; i++) { | |
576 | void __iomem *pmp_base = port + PORT_PMP + i * PORT_PMP_SIZE; | |
577 | ||
578 | writel(0, pmp_base + PORT_PMP_STATUS); | |
579 | writel(0, pmp_base + PORT_PMP_QACTIVE); | |
580 | } | |
581 | } | |
582 | ||
b5bc421c TH |
583 | static int sil24_init_port(struct ata_port *ap) |
584 | { | |
350756f6 | 585 | void __iomem *port = sil24_port_base(ap); |
23818034 | 586 | struct sil24_port_priv *pp = ap->private_data; |
b5bc421c TH |
587 | u32 tmp; |
588 | ||
3454dc69 | 589 | /* clear PMP error status */ |
071f44b1 | 590 | if (sata_pmp_attached(ap)) |
3454dc69 TH |
591 | sil24_clear_pmp(ap); |
592 | ||
b5bc421c TH |
593 | writel(PORT_CS_INIT, port + PORT_CTRL_STAT); |
594 | ata_wait_register(port + PORT_CTRL_STAT, | |
595 | PORT_CS_INIT, PORT_CS_INIT, 10, 100); | |
596 | tmp = ata_wait_register(port + PORT_CTRL_STAT, | |
597 | PORT_CS_RDY, 0, 10, 100); | |
598 | ||
23818034 TH |
599 | if ((tmp & (PORT_CS_INIT | PORT_CS_RDY)) != PORT_CS_RDY) { |
600 | pp->do_port_rst = 1; | |
cf480626 | 601 | ap->link.eh_context.i.action |= ATA_EH_RESET; |
b5bc421c | 602 | return -EIO; |
23818034 TH |
603 | } |
604 | ||
b5bc421c TH |
605 | return 0; |
606 | } | |
607 | ||
37b99cba TH |
608 | static int sil24_exec_polled_cmd(struct ata_port *ap, int pmp, |
609 | const struct ata_taskfile *tf, | |
610 | int is_cmd, u32 ctrl, | |
611 | unsigned long timeout_msec) | |
edb33667 | 612 | { |
350756f6 | 613 | void __iomem *port = sil24_port_base(ap); |
ca45160d | 614 | struct sil24_port_priv *pp = ap->private_data; |
69ad185f | 615 | struct sil24_prb *prb = &pp->cmd_block[0].ata.prb; |
ca45160d | 616 | dma_addr_t paddr = pp->cmd_block_dma; |
37b99cba TH |
617 | u32 irq_enabled, irq_mask, irq_stat; |
618 | int rc; | |
619 | ||
620 | prb->ctrl = cpu_to_le16(ctrl); | |
621 | ata_tf_to_fis(tf, pmp, is_cmd, prb->fis); | |
622 | ||
623 | /* temporarily plug completion and error interrupts */ | |
624 | irq_enabled = readl(port + PORT_IRQ_ENABLE_SET); | |
625 | writel(PORT_IRQ_COMPLETE | PORT_IRQ_ERROR, port + PORT_IRQ_ENABLE_CLR); | |
626 | ||
627 | writel((u32)paddr, port + PORT_CMD_ACTIVATE); | |
628 | writel((u64)paddr >> 32, port + PORT_CMD_ACTIVATE + 4); | |
629 | ||
630 | irq_mask = (PORT_IRQ_COMPLETE | PORT_IRQ_ERROR) << PORT_IRQ_RAW_SHIFT; | |
631 | irq_stat = ata_wait_register(port + PORT_IRQ_STAT, irq_mask, 0x0, | |
632 | 10, timeout_msec); | |
633 | ||
634 | writel(irq_mask, port + PORT_IRQ_STAT); /* clear IRQs */ | |
635 | irq_stat >>= PORT_IRQ_RAW_SHIFT; | |
636 | ||
637 | if (irq_stat & PORT_IRQ_COMPLETE) | |
638 | rc = 0; | |
639 | else { | |
640 | /* force port into known state */ | |
641 | sil24_init_port(ap); | |
642 | ||
643 | if (irq_stat & PORT_IRQ_ERROR) | |
644 | rc = -EIO; | |
645 | else | |
646 | rc = -EBUSY; | |
647 | } | |
648 | ||
649 | /* restore IRQ enabled */ | |
650 | writel(irq_enabled, port + PORT_IRQ_ENABLE_SET); | |
651 | ||
652 | return rc; | |
653 | } | |
654 | ||
071f44b1 TH |
655 | static int sil24_softreset(struct ata_link *link, unsigned int *class, |
656 | unsigned long deadline) | |
37b99cba | 657 | { |
cc0680a5 | 658 | struct ata_port *ap = link->ap; |
071f44b1 | 659 | int pmp = sata_srst_pmp(link); |
37b99cba | 660 | unsigned long timeout_msec = 0; |
e59f0dad | 661 | struct ata_taskfile tf; |
643be977 | 662 | const char *reason; |
37b99cba | 663 | int rc; |
ca45160d | 664 | |
07b73470 TH |
665 | DPRINTK("ENTER\n"); |
666 | ||
2555d6c2 TH |
667 | /* put the port into known state */ |
668 | if (sil24_init_port(ap)) { | |
5796d1c4 | 669 | reason = "port not ready"; |
2555d6c2 TH |
670 | goto err; |
671 | } | |
672 | ||
0eaa6058 | 673 | /* do SRST */ |
37b99cba TH |
674 | if (time_after(deadline, jiffies)) |
675 | timeout_msec = jiffies_to_msecs(deadline - jiffies); | |
ca45160d | 676 | |
cc0680a5 | 677 | ata_tf_init(link->device, &tf); /* doesn't really matter */ |
975530e8 TH |
678 | rc = sil24_exec_polled_cmd(ap, pmp, &tf, 0, PRB_CTRL_SRST, |
679 | timeout_msec); | |
37b99cba TH |
680 | if (rc == -EBUSY) { |
681 | reason = "timeout"; | |
682 | goto err; | |
683 | } else if (rc) { | |
684 | reason = "SRST command error"; | |
643be977 | 685 | goto err; |
07b73470 | 686 | } |
10d996ad | 687 | |
e59f0dad TH |
688 | sil24_read_tf(ap, 0, &tf); |
689 | *class = ata_dev_classify(&tf); | |
10d996ad | 690 | |
07b73470 | 691 | DPRINTK("EXIT, class=%u\n", *class); |
ca45160d | 692 | return 0; |
643be977 TH |
693 | |
694 | err: | |
cc0680a5 | 695 | ata_link_printk(link, KERN_ERR, "softreset failed (%s)\n", reason); |
643be977 | 696 | return -EIO; |
ca45160d TH |
697 | } |
698 | ||
cc0680a5 | 699 | static int sil24_hardreset(struct ata_link *link, unsigned int *class, |
d4b2bab4 | 700 | unsigned long deadline) |
489ff4c7 | 701 | { |
cc0680a5 | 702 | struct ata_port *ap = link->ap; |
350756f6 | 703 | void __iomem *port = sil24_port_base(ap); |
23818034 TH |
704 | struct sil24_port_priv *pp = ap->private_data; |
705 | int did_port_rst = 0; | |
ecc2e2b9 | 706 | const char *reason; |
e8e008e7 | 707 | int tout_msec, rc; |
ecc2e2b9 TH |
708 | u32 tmp; |
709 | ||
23818034 TH |
710 | retry: |
711 | /* Sometimes, DEV_RST is not enough to recover the controller. | |
712 | * This happens often after PM DMA CS errata. | |
713 | */ | |
714 | if (pp->do_port_rst) { | |
715 | ata_port_printk(ap, KERN_WARNING, "controller in dubious " | |
716 | "state, performing PORT_RST\n"); | |
717 | ||
718 | writel(PORT_CS_PORT_RST, port + PORT_CTRL_STAT); | |
719 | msleep(10); | |
720 | writel(PORT_CS_PORT_RST, port + PORT_CTRL_CLR); | |
721 | ata_wait_register(port + PORT_CTRL_STAT, PORT_CS_RDY, 0, | |
722 | 10, 5000); | |
723 | ||
724 | /* restore port configuration */ | |
725 | sil24_config_port(ap); | |
726 | sil24_config_pmp(ap, ap->nr_pmp_links); | |
727 | ||
728 | pp->do_port_rst = 0; | |
729 | did_port_rst = 1; | |
730 | } | |
731 | ||
ecc2e2b9 | 732 | /* sil24 does the right thing(tm) without any protection */ |
cc0680a5 | 733 | sata_set_spd(link); |
ecc2e2b9 TH |
734 | |
735 | tout_msec = 100; | |
cc0680a5 | 736 | if (ata_link_online(link)) |
ecc2e2b9 TH |
737 | tout_msec = 5000; |
738 | ||
739 | writel(PORT_CS_DEV_RST, port + PORT_CTRL_STAT); | |
740 | tmp = ata_wait_register(port + PORT_CTRL_STAT, | |
5796d1c4 JG |
741 | PORT_CS_DEV_RST, PORT_CS_DEV_RST, 10, |
742 | tout_msec); | |
ecc2e2b9 | 743 | |
e8e008e7 TH |
744 | /* SStatus oscillates between zero and valid status after |
745 | * DEV_RST, debounce it. | |
ecc2e2b9 | 746 | */ |
cc0680a5 | 747 | rc = sata_link_debounce(link, sata_deb_timing_long, deadline); |
e8e008e7 TH |
748 | if (rc) { |
749 | reason = "PHY debouncing failed"; | |
750 | goto err; | |
751 | } | |
ecc2e2b9 TH |
752 | |
753 | if (tmp & PORT_CS_DEV_RST) { | |
cc0680a5 | 754 | if (ata_link_offline(link)) |
ecc2e2b9 TH |
755 | return 0; |
756 | reason = "link not ready"; | |
757 | goto err; | |
758 | } | |
759 | ||
e8e008e7 TH |
760 | /* Sil24 doesn't store signature FIS after hardreset, so we |
761 | * can't wait for BSY to clear. Some devices take a long time | |
762 | * to get ready and those devices will choke if we don't wait | |
763 | * for BSY clearance here. Tell libata to perform follow-up | |
764 | * softreset. | |
ecc2e2b9 | 765 | */ |
e8e008e7 | 766 | return -EAGAIN; |
ecc2e2b9 TH |
767 | |
768 | err: | |
23818034 TH |
769 | if (!did_port_rst) { |
770 | pp->do_port_rst = 1; | |
771 | goto retry; | |
772 | } | |
773 | ||
cc0680a5 | 774 | ata_link_printk(link, KERN_ERR, "hardreset failed (%s)\n", reason); |
ecc2e2b9 | 775 | return -EIO; |
489ff4c7 TH |
776 | } |
777 | ||
edb33667 | 778 | static inline void sil24_fill_sg(struct ata_queued_cmd *qc, |
69ad185f | 779 | struct sil24_sge *sge) |
edb33667 | 780 | { |
972c26bd | 781 | struct scatterlist *sg; |
3be6cbd7 | 782 | struct sil24_sge *last_sge = NULL; |
ff2aeb1e | 783 | unsigned int si; |
edb33667 | 784 | |
ff2aeb1e | 785 | for_each_sg(qc->sg, sg, qc->n_elem, si) { |
edb33667 TH |
786 | sge->addr = cpu_to_le64(sg_dma_address(sg)); |
787 | sge->cnt = cpu_to_le32(sg_dma_len(sg)); | |
3be6cbd7 JG |
788 | sge->flags = 0; |
789 | ||
790 | last_sge = sge; | |
972c26bd | 791 | sge++; |
edb33667 | 792 | } |
3be6cbd7 | 793 | |
ff2aeb1e | 794 | last_sge->flags = cpu_to_le32(SGE_TRM); |
edb33667 TH |
795 | } |
796 | ||
3454dc69 TH |
797 | static int sil24_qc_defer(struct ata_queued_cmd *qc) |
798 | { | |
799 | struct ata_link *link = qc->dev->link; | |
800 | struct ata_port *ap = link->ap; | |
801 | u8 prot = qc->tf.protocol; | |
13cc546b GG |
802 | |
803 | /* | |
804 | * There is a bug in the chip: | |
805 | * Port LRAM Causes the PRB/SGT Data to be Corrupted | |
806 | * If the host issues a read request for LRAM and SActive registers | |
807 | * while active commands are available in the port, PRB/SGT data in | |
808 | * the LRAM can become corrupted. This issue applies only when | |
809 | * reading from, but not writing to, the LRAM. | |
810 | * | |
811 | * Therefore, reading LRAM when there is no particular error [and | |
812 | * other commands may be outstanding] is prohibited. | |
813 | * | |
814 | * To avoid this bug there are two situations where a command must run | |
815 | * exclusive of any other commands on the port: | |
816 | * | |
817 | * - ATAPI commands which check the sense data | |
818 | * - Passthrough ATA commands which always have ATA_QCFLAG_RESULT_TF | |
819 | * set. | |
820 | * | |
821 | */ | |
405e66b3 | 822 | int is_excl = (ata_is_atapi(prot) || |
13cc546b GG |
823 | (qc->flags & ATA_QCFLAG_RESULT_TF)); |
824 | ||
3454dc69 TH |
825 | if (unlikely(ap->excl_link)) { |
826 | if (link == ap->excl_link) { | |
827 | if (ap->nr_active_links) | |
828 | return ATA_DEFER_PORT; | |
829 | qc->flags |= ATA_QCFLAG_CLEAR_EXCL; | |
830 | } else | |
831 | return ATA_DEFER_PORT; | |
13cc546b | 832 | } else if (unlikely(is_excl)) { |
3454dc69 TH |
833 | ap->excl_link = link; |
834 | if (ap->nr_active_links) | |
835 | return ATA_DEFER_PORT; | |
836 | qc->flags |= ATA_QCFLAG_CLEAR_EXCL; | |
837 | } | |
838 | ||
839 | return ata_std_qc_defer(qc); | |
840 | } | |
841 | ||
edb33667 TH |
842 | static void sil24_qc_prep(struct ata_queued_cmd *qc) |
843 | { | |
844 | struct ata_port *ap = qc->ap; | |
845 | struct sil24_port_priv *pp = ap->private_data; | |
aee10a03 | 846 | union sil24_cmd_block *cb; |
69ad185f TH |
847 | struct sil24_prb *prb; |
848 | struct sil24_sge *sge; | |
bad28a37 | 849 | u16 ctrl = 0; |
edb33667 | 850 | |
aee10a03 TH |
851 | cb = &pp->cmd_block[sil24_tag(qc->tag)]; |
852 | ||
405e66b3 | 853 | if (!ata_is_atapi(qc->tf.protocol)) { |
69ad185f TH |
854 | prb = &cb->ata.prb; |
855 | sge = cb->ata.sge; | |
405e66b3 | 856 | } else { |
69ad185f TH |
857 | prb = &cb->atapi.prb; |
858 | sge = cb->atapi.sge; | |
859 | memset(cb->atapi.cdb, 0, 32); | |
6e7846e9 | 860 | memcpy(cb->atapi.cdb, qc->cdb, qc->dev->cdb_len); |
69ad185f | 861 | |
405e66b3 | 862 | if (ata_is_data(qc->tf.protocol)) { |
69ad185f | 863 | if (qc->tf.flags & ATA_TFLAG_WRITE) |
bad28a37 | 864 | ctrl = PRB_CTRL_PACKET_WRITE; |
69ad185f | 865 | else |
bad28a37 TH |
866 | ctrl = PRB_CTRL_PACKET_READ; |
867 | } | |
edb33667 TH |
868 | } |
869 | ||
bad28a37 | 870 | prb->ctrl = cpu_to_le16(ctrl); |
3454dc69 | 871 | ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, prb->fis); |
edb33667 TH |
872 | |
873 | if (qc->flags & ATA_QCFLAG_DMAMAP) | |
69ad185f | 874 | sil24_fill_sg(qc, sge); |
edb33667 TH |
875 | } |
876 | ||
9a3d9eb0 | 877 | static unsigned int sil24_qc_issue(struct ata_queued_cmd *qc) |
edb33667 TH |
878 | { |
879 | struct ata_port *ap = qc->ap; | |
880 | struct sil24_port_priv *pp = ap->private_data; | |
350756f6 | 881 | void __iomem *port = sil24_port_base(ap); |
aee10a03 TH |
882 | unsigned int tag = sil24_tag(qc->tag); |
883 | dma_addr_t paddr; | |
884 | void __iomem *activate; | |
edb33667 | 885 | |
aee10a03 TH |
886 | paddr = pp->cmd_block_dma + tag * sizeof(*pp->cmd_block); |
887 | activate = port + PORT_CMD_ACTIVATE + tag * 8; | |
888 | ||
889 | writel((u32)paddr, activate); | |
890 | writel((u64)paddr >> 32, activate + 4); | |
26ec634c | 891 | |
edb33667 TH |
892 | return 0; |
893 | } | |
894 | ||
79f97dad TH |
895 | static bool sil24_qc_fill_rtf(struct ata_queued_cmd *qc) |
896 | { | |
897 | sil24_read_tf(qc->ap, qc->tag, &qc->result_tf); | |
898 | return true; | |
899 | } | |
900 | ||
3454dc69 TH |
901 | static void sil24_pmp_attach(struct ata_port *ap) |
902 | { | |
906c1ff4 TH |
903 | u32 *gscr = ap->link.device->gscr; |
904 | ||
3454dc69 TH |
905 | sil24_config_pmp(ap, 1); |
906 | sil24_init_port(ap); | |
906c1ff4 TH |
907 | |
908 | if (sata_pmp_gscr_vendor(gscr) == 0x11ab && | |
909 | sata_pmp_gscr_devid(gscr) == 0x4140) { | |
910 | ata_port_printk(ap, KERN_INFO, | |
911 | "disabling NCQ support due to sil24-mv4140 quirk\n"); | |
912 | ap->flags &= ~ATA_FLAG_NCQ; | |
913 | } | |
3454dc69 TH |
914 | } |
915 | ||
916 | static void sil24_pmp_detach(struct ata_port *ap) | |
917 | { | |
918 | sil24_init_port(ap); | |
919 | sil24_config_pmp(ap, 0); | |
906c1ff4 TH |
920 | |
921 | ap->flags |= ATA_FLAG_NCQ; | |
3454dc69 TH |
922 | } |
923 | ||
3454dc69 TH |
924 | static int sil24_pmp_hardreset(struct ata_link *link, unsigned int *class, |
925 | unsigned long deadline) | |
926 | { | |
927 | int rc; | |
928 | ||
929 | rc = sil24_init_port(link->ap); | |
930 | if (rc) { | |
931 | ata_link_printk(link, KERN_ERR, | |
932 | "hardreset failed (port not ready)\n"); | |
933 | return rc; | |
934 | } | |
935 | ||
5958e302 | 936 | return sata_std_hardreset(link, class, deadline); |
3454dc69 TH |
937 | } |
938 | ||
88ce7550 | 939 | static void sil24_freeze(struct ata_port *ap) |
7d1ce682 | 940 | { |
350756f6 | 941 | void __iomem *port = sil24_port_base(ap); |
7d1ce682 | 942 | |
88ce7550 TH |
943 | /* Port-wide IRQ mask in HOST_CTRL doesn't really work, clear |
944 | * PORT_IRQ_ENABLE instead. | |
945 | */ | |
946 | writel(0xffff, port + PORT_IRQ_ENABLE_CLR); | |
7d1ce682 TH |
947 | } |
948 | ||
88ce7550 | 949 | static void sil24_thaw(struct ata_port *ap) |
edb33667 | 950 | { |
350756f6 | 951 | void __iomem *port = sil24_port_base(ap); |
edb33667 TH |
952 | u32 tmp; |
953 | ||
88ce7550 TH |
954 | /* clear IRQ */ |
955 | tmp = readl(port + PORT_IRQ_STAT); | |
956 | writel(tmp, port + PORT_IRQ_STAT); | |
edb33667 | 957 | |
88ce7550 TH |
958 | /* turn IRQ back on */ |
959 | writel(DEF_PORT_IRQ, port + PORT_IRQ_ENABLE_SET); | |
edb33667 TH |
960 | } |
961 | ||
88ce7550 | 962 | static void sil24_error_intr(struct ata_port *ap) |
8746618d | 963 | { |
350756f6 | 964 | void __iomem *port = sil24_port_base(ap); |
e59f0dad | 965 | struct sil24_port_priv *pp = ap->private_data; |
3454dc69 TH |
966 | struct ata_queued_cmd *qc = NULL; |
967 | struct ata_link *link; | |
968 | struct ata_eh_info *ehi; | |
969 | int abort = 0, freeze = 0; | |
88ce7550 | 970 | u32 irq_stat; |
8746618d | 971 | |
88ce7550 | 972 | /* on error, we need to clear IRQ explicitly */ |
8746618d | 973 | irq_stat = readl(port + PORT_IRQ_STAT); |
88ce7550 | 974 | writel(irq_stat, port + PORT_IRQ_STAT); |
ad6e90f6 | 975 | |
88ce7550 | 976 | /* first, analyze and record host port events */ |
3454dc69 TH |
977 | link = &ap->link; |
978 | ehi = &link->eh_info; | |
88ce7550 | 979 | ata_ehi_clear_desc(ehi); |
ad6e90f6 | 980 | |
88ce7550 | 981 | ata_ehi_push_desc(ehi, "irq_stat 0x%08x", irq_stat); |
8746618d | 982 | |
854c73a2 | 983 | if (irq_stat & PORT_IRQ_SDB_NOTIFY) { |
854c73a2 | 984 | ata_ehi_push_desc(ehi, "SDB notify"); |
7d77b247 | 985 | sata_async_notification(ap); |
854c73a2 TH |
986 | } |
987 | ||
0542925b TH |
988 | if (irq_stat & (PORT_IRQ_PHYRDY_CHG | PORT_IRQ_DEV_XCHG)) { |
989 | ata_ehi_hotplugged(ehi); | |
b64bbc39 TH |
990 | ata_ehi_push_desc(ehi, "%s", |
991 | irq_stat & PORT_IRQ_PHYRDY_CHG ? | |
992 | "PHY RDY changed" : "device exchanged"); | |
88ce7550 | 993 | freeze = 1; |
6a575fa9 TH |
994 | } |
995 | ||
88ce7550 TH |
996 | if (irq_stat & PORT_IRQ_UNK_FIS) { |
997 | ehi->err_mask |= AC_ERR_HSM; | |
cf480626 | 998 | ehi->action |= ATA_EH_RESET; |
b64bbc39 | 999 | ata_ehi_push_desc(ehi, "unknown FIS"); |
88ce7550 TH |
1000 | freeze = 1; |
1001 | } | |
1002 | ||
1003 | /* deal with command error */ | |
1004 | if (irq_stat & PORT_IRQ_ERROR) { | |
1005 | struct sil24_cerr_info *ci = NULL; | |
1006 | unsigned int err_mask = 0, action = 0; | |
3454dc69 TH |
1007 | u32 context, cerr; |
1008 | int pmp; | |
1009 | ||
1010 | abort = 1; | |
1011 | ||
1012 | /* DMA Context Switch Failure in Port Multiplier Mode | |
1013 | * errata. If we have active commands to 3 or more | |
1014 | * devices, any error condition on active devices can | |
1015 | * corrupt DMA context switching. | |
1016 | */ | |
1017 | if (ap->nr_active_links >= 3) { | |
1018 | ehi->err_mask |= AC_ERR_OTHER; | |
cf480626 | 1019 | ehi->action |= ATA_EH_RESET; |
3454dc69 | 1020 | ata_ehi_push_desc(ehi, "PMP DMA CS errata"); |
23818034 | 1021 | pp->do_port_rst = 1; |
3454dc69 TH |
1022 | freeze = 1; |
1023 | } | |
1024 | ||
1025 | /* find out the offending link and qc */ | |
071f44b1 | 1026 | if (sata_pmp_attached(ap)) { |
3454dc69 TH |
1027 | context = readl(port + PORT_CONTEXT); |
1028 | pmp = (context >> 5) & 0xf; | |
1029 | ||
1030 | if (pmp < ap->nr_pmp_links) { | |
1031 | link = &ap->pmp_link[pmp]; | |
1032 | ehi = &link->eh_info; | |
1033 | qc = ata_qc_from_tag(ap, link->active_tag); | |
1034 | ||
1035 | ata_ehi_clear_desc(ehi); | |
1036 | ata_ehi_push_desc(ehi, "irq_stat 0x%08x", | |
1037 | irq_stat); | |
1038 | } else { | |
1039 | err_mask |= AC_ERR_HSM; | |
cf480626 | 1040 | action |= ATA_EH_RESET; |
3454dc69 TH |
1041 | freeze = 1; |
1042 | } | |
1043 | } else | |
1044 | qc = ata_qc_from_tag(ap, link->active_tag); | |
88ce7550 TH |
1045 | |
1046 | /* analyze CMD_ERR */ | |
1047 | cerr = readl(port + PORT_CMD_ERR); | |
1048 | if (cerr < ARRAY_SIZE(sil24_cerr_db)) | |
1049 | ci = &sil24_cerr_db[cerr]; | |
1050 | ||
1051 | if (ci && ci->desc) { | |
1052 | err_mask |= ci->err_mask; | |
1053 | action |= ci->action; | |
cf480626 | 1054 | if (action & ATA_EH_RESET) |
c2e14f11 | 1055 | freeze = 1; |
b64bbc39 | 1056 | ata_ehi_push_desc(ehi, "%s", ci->desc); |
88ce7550 TH |
1057 | } else { |
1058 | err_mask |= AC_ERR_OTHER; | |
cf480626 | 1059 | action |= ATA_EH_RESET; |
c2e14f11 | 1060 | freeze = 1; |
b64bbc39 | 1061 | ata_ehi_push_desc(ehi, "unknown command error %d", |
88ce7550 TH |
1062 | cerr); |
1063 | } | |
1064 | ||
1065 | /* record error info */ | |
520d06f9 | 1066 | if (qc) |
88ce7550 | 1067 | qc->err_mask |= err_mask; |
520d06f9 | 1068 | else |
88ce7550 TH |
1069 | ehi->err_mask |= err_mask; |
1070 | ||
1071 | ehi->action |= action; | |
3454dc69 TH |
1072 | |
1073 | /* if PMP, resume */ | |
071f44b1 | 1074 | if (sata_pmp_attached(ap)) |
3454dc69 | 1075 | writel(PORT_CS_PMP_RESUME, port + PORT_CTRL_STAT); |
a22e2eb0 | 1076 | } |
88ce7550 TH |
1077 | |
1078 | /* freeze or abort */ | |
1079 | if (freeze) | |
1080 | ata_port_freeze(ap); | |
3454dc69 TH |
1081 | else if (abort) { |
1082 | if (qc) | |
1083 | ata_link_abort(qc->dev->link); | |
1084 | else | |
1085 | ata_port_abort(ap); | |
1086 | } | |
8746618d TH |
1087 | } |
1088 | ||
edb33667 TH |
1089 | static inline void sil24_host_intr(struct ata_port *ap) |
1090 | { | |
350756f6 | 1091 | void __iomem *port = sil24_port_base(ap); |
aee10a03 TH |
1092 | u32 slot_stat, qc_active; |
1093 | int rc; | |
edb33667 | 1094 | |
228f47b9 TH |
1095 | /* If PCIX_IRQ_WOC, there's an inherent race window between |
1096 | * clearing IRQ pending status and reading PORT_SLOT_STAT | |
1097 | * which may cause spurious interrupts afterwards. This is | |
1098 | * unavoidable and much better than losing interrupts which | |
1099 | * happens if IRQ pending is cleared after reading | |
1100 | * PORT_SLOT_STAT. | |
1101 | */ | |
1102 | if (ap->flags & SIL24_FLAG_PCIX_IRQ_WOC) | |
1103 | writel(PORT_IRQ_COMPLETE, port + PORT_IRQ_STAT); | |
1104 | ||
edb33667 | 1105 | slot_stat = readl(port + PORT_SLOT_STAT); |
37024e8e | 1106 | |
88ce7550 TH |
1107 | if (unlikely(slot_stat & HOST_SSTAT_ATTN)) { |
1108 | sil24_error_intr(ap); | |
1109 | return; | |
1110 | } | |
1111 | ||
aee10a03 | 1112 | qc_active = slot_stat & ~HOST_SSTAT_ATTN; |
79f97dad | 1113 | rc = ata_qc_complete_multiple(ap, qc_active); |
aee10a03 TH |
1114 | if (rc > 0) |
1115 | return; | |
1116 | if (rc < 0) { | |
9af5c9c9 | 1117 | struct ata_eh_info *ehi = &ap->link.eh_info; |
aee10a03 | 1118 | ehi->err_mask |= AC_ERR_HSM; |
cf480626 | 1119 | ehi->action |= ATA_EH_RESET; |
aee10a03 | 1120 | ata_port_freeze(ap); |
88ce7550 TH |
1121 | return; |
1122 | } | |
1123 | ||
228f47b9 TH |
1124 | /* spurious interrupts are expected if PCIX_IRQ_WOC */ |
1125 | if (!(ap->flags & SIL24_FLAG_PCIX_IRQ_WOC) && ata_ratelimit()) | |
88ce7550 | 1126 | ata_port_printk(ap, KERN_INFO, "spurious interrupt " |
aee10a03 | 1127 | "(slot_stat 0x%x active_tag %d sactive 0x%x)\n", |
9af5c9c9 | 1128 | slot_stat, ap->link.active_tag, ap->link.sactive); |
edb33667 TH |
1129 | } |
1130 | ||
7d12e780 | 1131 | static irqreturn_t sil24_interrupt(int irq, void *dev_instance) |
edb33667 | 1132 | { |
cca3974e | 1133 | struct ata_host *host = dev_instance; |
0d5ff566 | 1134 | void __iomem *host_base = host->iomap[SIL24_HOST_BAR]; |
edb33667 TH |
1135 | unsigned handled = 0; |
1136 | u32 status; | |
1137 | int i; | |
1138 | ||
0d5ff566 | 1139 | status = readl(host_base + HOST_IRQ_STAT); |
edb33667 | 1140 | |
06460aea TH |
1141 | if (status == 0xffffffff) { |
1142 | printk(KERN_ERR DRV_NAME ": IRQ status == 0xffffffff, " | |
1143 | "PCI fault or device removal?\n"); | |
1144 | goto out; | |
1145 | } | |
1146 | ||
edb33667 TH |
1147 | if (!(status & IRQ_STAT_4PORTS)) |
1148 | goto out; | |
1149 | ||
cca3974e | 1150 | spin_lock(&host->lock); |
edb33667 | 1151 | |
cca3974e | 1152 | for (i = 0; i < host->n_ports; i++) |
edb33667 | 1153 | if (status & (1 << i)) { |
cca3974e | 1154 | struct ata_port *ap = host->ports[i]; |
198e0fed | 1155 | if (ap && !(ap->flags & ATA_FLAG_DISABLED)) { |
825cd6dd | 1156 | sil24_host_intr(ap); |
3cc4571c TH |
1157 | handled++; |
1158 | } else | |
1159 | printk(KERN_ERR DRV_NAME | |
1160 | ": interrupt from disabled port %d\n", i); | |
edb33667 TH |
1161 | } |
1162 | ||
cca3974e | 1163 | spin_unlock(&host->lock); |
edb33667 TH |
1164 | out: |
1165 | return IRQ_RETVAL(handled); | |
1166 | } | |
1167 | ||
88ce7550 TH |
1168 | static void sil24_error_handler(struct ata_port *ap) |
1169 | { | |
23818034 TH |
1170 | struct sil24_port_priv *pp = ap->private_data; |
1171 | ||
3454dc69 | 1172 | if (sil24_init_port(ap)) |
88ce7550 | 1173 | ata_eh_freeze_port(ap); |
88ce7550 | 1174 | |
a1efdaba | 1175 | sata_pmp_error_handler(ap); |
23818034 TH |
1176 | |
1177 | pp->do_port_rst = 0; | |
88ce7550 TH |
1178 | } |
1179 | ||
1180 | static void sil24_post_internal_cmd(struct ata_queued_cmd *qc) | |
1181 | { | |
1182 | struct ata_port *ap = qc->ap; | |
1183 | ||
88ce7550 | 1184 | /* make DMA engine forget about the failed command */ |
3454dc69 TH |
1185 | if ((qc->flags & ATA_QCFLAG_FAILED) && sil24_init_port(ap)) |
1186 | ata_eh_freeze_port(ap); | |
88ce7550 TH |
1187 | } |
1188 | ||
edb33667 TH |
1189 | static int sil24_port_start(struct ata_port *ap) |
1190 | { | |
cca3974e | 1191 | struct device *dev = ap->host->dev; |
edb33667 | 1192 | struct sil24_port_priv *pp; |
69ad185f | 1193 | union sil24_cmd_block *cb; |
aee10a03 | 1194 | size_t cb_size = sizeof(*cb) * SIL24_MAX_CMDS; |
edb33667 TH |
1195 | dma_addr_t cb_dma; |
1196 | ||
24dc5f33 | 1197 | pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL); |
edb33667 | 1198 | if (!pp) |
24dc5f33 | 1199 | return -ENOMEM; |
edb33667 | 1200 | |
24dc5f33 | 1201 | cb = dmam_alloc_coherent(dev, cb_size, &cb_dma, GFP_KERNEL); |
6037d6bb | 1202 | if (!cb) |
24dc5f33 | 1203 | return -ENOMEM; |
edb33667 TH |
1204 | memset(cb, 0, cb_size); |
1205 | ||
edb33667 TH |
1206 | pp->cmd_block = cb; |
1207 | pp->cmd_block_dma = cb_dma; | |
1208 | ||
1209 | ap->private_data = pp; | |
1210 | ||
350756f6 TH |
1211 | ata_port_pbar_desc(ap, SIL24_HOST_BAR, -1, "host"); |
1212 | ata_port_pbar_desc(ap, SIL24_PORT_BAR, sil24_port_offset(ap), "port"); | |
1213 | ||
edb33667 | 1214 | return 0; |
edb33667 TH |
1215 | } |
1216 | ||
4447d351 | 1217 | static void sil24_init_controller(struct ata_host *host) |
2a41a610 | 1218 | { |
4447d351 | 1219 | void __iomem *host_base = host->iomap[SIL24_HOST_BAR]; |
2a41a610 TH |
1220 | u32 tmp; |
1221 | int i; | |
1222 | ||
1223 | /* GPIO off */ | |
1224 | writel(0, host_base + HOST_FLASH_CMD); | |
1225 | ||
1226 | /* clear global reset & mask interrupts during initialization */ | |
1227 | writel(0, host_base + HOST_CTRL); | |
1228 | ||
1229 | /* init ports */ | |
4447d351 | 1230 | for (i = 0; i < host->n_ports; i++) { |
23818034 | 1231 | struct ata_port *ap = host->ports[i]; |
350756f6 TH |
1232 | void __iomem *port = sil24_port_base(ap); |
1233 | ||
2a41a610 TH |
1234 | |
1235 | /* Initial PHY setting */ | |
1236 | writel(0x20c, port + PORT_PHY_CFG); | |
1237 | ||
1238 | /* Clear port RST */ | |
1239 | tmp = readl(port + PORT_CTRL_STAT); | |
1240 | if (tmp & PORT_CS_PORT_RST) { | |
1241 | writel(PORT_CS_PORT_RST, port + PORT_CTRL_CLR); | |
1242 | tmp = ata_wait_register(port + PORT_CTRL_STAT, | |
1243 | PORT_CS_PORT_RST, | |
1244 | PORT_CS_PORT_RST, 10, 100); | |
1245 | if (tmp & PORT_CS_PORT_RST) | |
4447d351 | 1246 | dev_printk(KERN_ERR, host->dev, |
5796d1c4 | 1247 | "failed to clear port RST\n"); |
2a41a610 TH |
1248 | } |
1249 | ||
23818034 TH |
1250 | /* configure port */ |
1251 | sil24_config_port(ap); | |
2a41a610 TH |
1252 | } |
1253 | ||
1254 | /* Turn on interrupts */ | |
1255 | writel(IRQ_STAT_4PORTS, host_base + HOST_CTRL); | |
1256 | } | |
1257 | ||
edb33667 TH |
1258 | static int sil24_init_one(struct pci_dev *pdev, const struct pci_device_id *ent) |
1259 | { | |
93e2618e | 1260 | extern int __MARKER__sil24_cmd_block_is_sized_wrongly; |
5796d1c4 | 1261 | static int printed_version; |
4447d351 TH |
1262 | struct ata_port_info pi = sil24_port_info[ent->driver_data]; |
1263 | const struct ata_port_info *ppi[] = { &pi, NULL }; | |
1264 | void __iomem * const *iomap; | |
1265 | struct ata_host *host; | |
350756f6 | 1266 | int rc; |
37024e8e | 1267 | u32 tmp; |
edb33667 | 1268 | |
93e2618e TH |
1269 | /* cause link error if sil24_cmd_block is sized wrongly */ |
1270 | if (sizeof(union sil24_cmd_block) != PAGE_SIZE) | |
1271 | __MARKER__sil24_cmd_block_is_sized_wrongly = 1; | |
1272 | ||
edb33667 | 1273 | if (!printed_version++) |
a9524a76 | 1274 | dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n"); |
edb33667 | 1275 | |
4447d351 | 1276 | /* acquire resources */ |
24dc5f33 | 1277 | rc = pcim_enable_device(pdev); |
edb33667 TH |
1278 | if (rc) |
1279 | return rc; | |
1280 | ||
0d5ff566 TH |
1281 | rc = pcim_iomap_regions(pdev, |
1282 | (1 << SIL24_HOST_BAR) | (1 << SIL24_PORT_BAR), | |
1283 | DRV_NAME); | |
edb33667 | 1284 | if (rc) |
24dc5f33 | 1285 | return rc; |
4447d351 | 1286 | iomap = pcim_iomap_table(pdev); |
edb33667 | 1287 | |
4447d351 TH |
1288 | /* apply workaround for completion IRQ loss on PCI-X errata */ |
1289 | if (pi.flags & SIL24_FLAG_PCIX_IRQ_WOC) { | |
1290 | tmp = readl(iomap[SIL24_HOST_BAR] + HOST_CTRL); | |
1291 | if (tmp & (HOST_CTRL_TRDY | HOST_CTRL_STOP | HOST_CTRL_DEVSEL)) | |
1292 | dev_printk(KERN_INFO, &pdev->dev, | |
1293 | "Applying completion IRQ loss on PCI-X " | |
1294 | "errata fix\n"); | |
1295 | else | |
1296 | pi.flags &= ~SIL24_FLAG_PCIX_IRQ_WOC; | |
1297 | } | |
edb33667 | 1298 | |
4447d351 TH |
1299 | /* allocate and fill host */ |
1300 | host = ata_host_alloc_pinfo(&pdev->dev, ppi, | |
1301 | SIL24_FLAG2NPORTS(ppi[0]->flags)); | |
1302 | if (!host) | |
1303 | return -ENOMEM; | |
1304 | host->iomap = iomap; | |
edb33667 | 1305 | |
4447d351 | 1306 | /* configure and activate the device */ |
26ec634c TH |
1307 | if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) { |
1308 | rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK); | |
1309 | if (rc) { | |
1310 | rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK); | |
1311 | if (rc) { | |
1312 | dev_printk(KERN_ERR, &pdev->dev, | |
1313 | "64-bit DMA enable failed\n"); | |
24dc5f33 | 1314 | return rc; |
26ec634c TH |
1315 | } |
1316 | } | |
1317 | } else { | |
1318 | rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK); | |
1319 | if (rc) { | |
1320 | dev_printk(KERN_ERR, &pdev->dev, | |
1321 | "32-bit DMA enable failed\n"); | |
24dc5f33 | 1322 | return rc; |
26ec634c TH |
1323 | } |
1324 | rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK); | |
1325 | if (rc) { | |
1326 | dev_printk(KERN_ERR, &pdev->dev, | |
1327 | "32-bit consistent DMA enable failed\n"); | |
24dc5f33 | 1328 | return rc; |
26ec634c | 1329 | } |
edb33667 TH |
1330 | } |
1331 | ||
e8b3b5e9 TH |
1332 | /* Set max read request size to 4096. This slightly increases |
1333 | * write throughput for pci-e variants. | |
1334 | */ | |
1335 | pcie_set_readrq(pdev, 4096); | |
1336 | ||
4447d351 | 1337 | sil24_init_controller(host); |
edb33667 TH |
1338 | |
1339 | pci_set_master(pdev); | |
4447d351 TH |
1340 | return ata_host_activate(host, pdev->irq, sil24_interrupt, IRQF_SHARED, |
1341 | &sil24_sht); | |
edb33667 TH |
1342 | } |
1343 | ||
281d426c | 1344 | #ifdef CONFIG_PM |
d2298dca TH |
1345 | static int sil24_pci_device_resume(struct pci_dev *pdev) |
1346 | { | |
cca3974e | 1347 | struct ata_host *host = dev_get_drvdata(&pdev->dev); |
0d5ff566 | 1348 | void __iomem *host_base = host->iomap[SIL24_HOST_BAR]; |
553c4aa6 | 1349 | int rc; |
d2298dca | 1350 | |
553c4aa6 TH |
1351 | rc = ata_pci_device_do_resume(pdev); |
1352 | if (rc) | |
1353 | return rc; | |
d2298dca TH |
1354 | |
1355 | if (pdev->dev.power.power_state.event == PM_EVENT_SUSPEND) | |
0d5ff566 | 1356 | writel(HOST_CTRL_GLOBAL_RST, host_base + HOST_CTRL); |
d2298dca | 1357 | |
4447d351 | 1358 | sil24_init_controller(host); |
d2298dca | 1359 | |
cca3974e | 1360 | ata_host_resume(host); |
d2298dca TH |
1361 | |
1362 | return 0; | |
1363 | } | |
3454dc69 TH |
1364 | |
1365 | static int sil24_port_resume(struct ata_port *ap) | |
1366 | { | |
1367 | sil24_config_pmp(ap, ap->nr_pmp_links); | |
1368 | return 0; | |
1369 | } | |
281d426c | 1370 | #endif |
d2298dca | 1371 | |
edb33667 TH |
1372 | static int __init sil24_init(void) |
1373 | { | |
b7887196 | 1374 | return pci_register_driver(&sil24_pci_driver); |
edb33667 TH |
1375 | } |
1376 | ||
1377 | static void __exit sil24_exit(void) | |
1378 | { | |
1379 | pci_unregister_driver(&sil24_pci_driver); | |
1380 | } | |
1381 | ||
1382 | MODULE_AUTHOR("Tejun Heo"); | |
1383 | MODULE_DESCRIPTION("Silicon Image 3124/3132 SATA low-level driver"); | |
1384 | MODULE_LICENSE("GPL"); | |
1385 | MODULE_DEVICE_TABLE(pci, sil24_pci_tbl); | |
1386 | ||
1387 | module_init(sil24_init); | |
1388 | module_exit(sil24_exit); |