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sata_rcar: kill superfluous code in sata_rcar_bmdma_fill_sg()
[linux-block.git] / drivers / ata / sata_rcar.c
CommitLineData
163cf81d
VB		 1/*
2 * Renesas R-Car SATA driver
3 *
4 * Author: Vladimir Barinov <source@cogentembedded.com>
5 * Copyright (C) 2013 Cogent Embedded, Inc.
6 * Copyright (C) 2013 Renesas Solutions Corp.
7 *
8 * This program is free software; you can redistribute it and/or modify it
9 * under the terms of the GNU General Public License as published by the
10 * Free Software Foundation; either version 2 of the License, or (at your
11 * option) any later version.
12 */
13
14#include <linux/kernel.h>
15#include <linux/module.h>
16#include <linux/ata.h>
17#include <linux/libata.h>
18#include <linux/platform_device.h>
19#include <linux/clk.h>
2de1d5e1 20#include <linux/err.h>
163cf81d
VB		 21
22#define DRV_NAME "sata_rcar"
23
24/* SH-Navi2G/ATAPI-ATA compatible task registers */
25#define DATA_REG 0x100
26#define SDEVCON_REG 0x138
27
28/* SH-Navi2G/ATAPI module compatible control registers */
29#define ATAPI_CONTROL1_REG 0x180
30#define ATAPI_STATUS_REG 0x184
31#define ATAPI_INT_ENABLE_REG 0x188
32#define ATAPI_DTB_ADR_REG 0x198
33#define ATAPI_DMA_START_ADR_REG 0x19C
34#define ATAPI_DMA_TRANS_CNT_REG 0x1A0
35#define ATAPI_CONTROL2_REG 0x1A4
36#define ATAPI_SIG_ST_REG 0x1B0
37#define ATAPI_BYTE_SWAP_REG 0x1BC
38
39/* ATAPI control 1 register (ATAPI_CONTROL1) bits */
40#define ATAPI_CONTROL1_ISM BIT(16)
41#define ATAPI_CONTROL1_DTA32M BIT(11)
42#define ATAPI_CONTROL1_RESET BIT(7)
43#define ATAPI_CONTROL1_DESE BIT(3)
44#define ATAPI_CONTROL1_RW BIT(2)
45#define ATAPI_CONTROL1_STOP BIT(1)
46#define ATAPI_CONTROL1_START BIT(0)
47
48/* ATAPI status register (ATAPI_STATUS) bits */
49#define ATAPI_STATUS_SATAINT BIT(11)
50#define ATAPI_STATUS_DNEND BIT(6)
51#define ATAPI_STATUS_DEVTRM BIT(5)
52#define ATAPI_STATUS_DEVINT BIT(4)
53#define ATAPI_STATUS_ERR BIT(2)
54#define ATAPI_STATUS_NEND BIT(1)
55#define ATAPI_STATUS_ACT BIT(0)
56
57/* Interrupt enable register (ATAPI_INT_ENABLE) bits */
58#define ATAPI_INT_ENABLE_SATAINT BIT(11)
59#define ATAPI_INT_ENABLE_DNEND BIT(6)
60#define ATAPI_INT_ENABLE_DEVTRM BIT(5)
61#define ATAPI_INT_ENABLE_DEVINT BIT(4)
62#define ATAPI_INT_ENABLE_ERR BIT(2)
63#define ATAPI_INT_ENABLE_NEND BIT(1)
64#define ATAPI_INT_ENABLE_ACT BIT(0)
65
66/* Access control registers for physical layer control register */
67#define SATAPHYADDR_REG 0x200
68#define SATAPHYWDATA_REG 0x204
69#define SATAPHYACCEN_REG 0x208
70#define SATAPHYRESET_REG 0x20C
71#define SATAPHYRDATA_REG 0x210
72#define SATAPHYACK_REG 0x214
73
74/* Physical layer control address command register (SATAPHYADDR) bits */
75#define SATAPHYADDR_PHYRATEMODE BIT(10)
76#define SATAPHYADDR_PHYCMD_READ BIT(9)
77#define SATAPHYADDR_PHYCMD_WRITE BIT(8)
78
79/* Physical layer control enable register (SATAPHYACCEN) bits */
80#define SATAPHYACCEN_PHYLANE BIT(0)
81
82/* Physical layer control reset register (SATAPHYRESET) bits */
83#define SATAPHYRESET_PHYRST BIT(1)
84#define SATAPHYRESET_PHYSRES BIT(0)
85
86/* Physical layer control acknowledge register (SATAPHYACK) bits */
87#define SATAPHYACK_PHYACK BIT(0)
88
89/* Serial-ATA HOST control registers */
90#define BISTCONF_REG 0x102C
91#define SDATA_REG 0x1100
92#define SSDEVCON_REG 0x1204
93
94#define SCRSSTS_REG 0x1400
95#define SCRSERR_REG 0x1404
96#define SCRSCON_REG 0x1408
97#define SCRSACT_REG 0x140C
98
99#define SATAINTSTAT_REG 0x1508
100#define SATAINTMASK_REG 0x150C
101
102/* SATA INT status register (SATAINTSTAT) bits */
103#define SATAINTSTAT_SERR BIT(3)
104#define SATAINTSTAT_ATA BIT(0)
105
106/* SATA INT mask register (SATAINTSTAT) bits */
107#define SATAINTMASK_SERRMSK BIT(3)
108#define SATAINTMASK_ERRMSK BIT(2)
109#define SATAINTMASK_ERRCRTMSK BIT(1)
110#define SATAINTMASK_ATAMSK BIT(0)
111
112#define SATA_RCAR_INT_MASK (SATAINTMASK_SERRMSK | \
113 SATAINTMASK_ATAMSK)
114
115/* Physical Layer Control Registers */
116#define SATAPCTLR1_REG 0x43
117#define SATAPCTLR2_REG 0x52
118#define SATAPCTLR3_REG 0x5A
119#define SATAPCTLR4_REG 0x60
120
121/* Descriptor table word 0 bit (when DTA32M = 1) */
122#define SATA_RCAR_DTEND BIT(0)
123
124struct sata_rcar_priv {
125 void __iomem *base;
126 struct clk *clk;
127};
128
129static void sata_rcar_phy_initialize(struct sata_rcar_priv *priv)
130{
131 /* idle state */
132 iowrite32(0, priv->base + SATAPHYADDR_REG);
133 /* reset */
134 iowrite32(SATAPHYRESET_PHYRST, priv->base + SATAPHYRESET_REG);
135 udelay(10);
136 /* deassert reset */
137 iowrite32(0, priv->base + SATAPHYRESET_REG);
138}
139
140static void sata_rcar_phy_write(struct sata_rcar_priv *priv, u16 reg, u32 val,
141 int group)
142{
143 int timeout;
144
145 /* deassert reset */
146 iowrite32(0, priv->base + SATAPHYRESET_REG);
147 /* lane 1 */
148 iowrite32(SATAPHYACCEN_PHYLANE, priv->base + SATAPHYACCEN_REG);
149 /* write phy register value */
150 iowrite32(val, priv->base + SATAPHYWDATA_REG);
151 /* set register group */
152 if (group)
153 reg |= SATAPHYADDR_PHYRATEMODE;
154 /* write command */
155 iowrite32(SATAPHYADDR_PHYCMD_WRITE | reg, priv->base + SATAPHYADDR_REG);
156 /* wait for ack */
157 for (timeout = 0; timeout < 100; timeout++) {
158 val = ioread32(priv->base + SATAPHYACK_REG);
159 if (val & SATAPHYACK_PHYACK)
160 break;
161 }
162 if (timeout >= 100)
163 pr_err("%s timeout\n", __func__);
164 /* idle state */
165 iowrite32(0, priv->base + SATAPHYADDR_REG);
166}
167
168static void sata_rcar_freeze(struct ata_port *ap)
169{
170 struct sata_rcar_priv *priv = ap->host->private_data;
171
172 /* mask */
173 iowrite32(0x7ff, priv->base + SATAINTMASK_REG);
174
175 ata_sff_freeze(ap);
176}
177
178static void sata_rcar_thaw(struct ata_port *ap)
179{
180 struct sata_rcar_priv *priv = ap->host->private_data;
181
182 /* ack */
183 iowrite32(~SATA_RCAR_INT_MASK, priv->base + SATAINTSTAT_REG);
184
185 ata_sff_thaw(ap);
186
187 /* unmask */
188 iowrite32(0x7ff & ~SATA_RCAR_INT_MASK, priv->base + SATAINTMASK_REG);
189}
190
191static void sata_rcar_ioread16_rep(void __iomem *reg, void *buffer, int count)
192{
193 u16 *ptr = buffer;
194
195 while (count--) {
196 u16 data = ioread32(reg);
197
198 *ptr++ = data;
199 }
200}
201
202static void sata_rcar_iowrite16_rep(void __iomem *reg, void *buffer, int count)
203{
204 const u16 *ptr = buffer;
205
206 while (count--)
207 iowrite32(*ptr++, reg);
208}
209
210static u8 sata_rcar_check_status(struct ata_port *ap)
211{
212 return ioread32(ap->ioaddr.status_addr);
213}
214
215static u8 sata_rcar_check_altstatus(struct ata_port *ap)
216{
217 return ioread32(ap->ioaddr.altstatus_addr);
218}
219
220static void sata_rcar_set_devctl(struct ata_port *ap, u8 ctl)
221{
222 iowrite32(ctl, ap->ioaddr.ctl_addr);
223}
224
225static void sata_rcar_dev_select(struct ata_port *ap, unsigned int device)
226{
227 iowrite32(ATA_DEVICE_OBS, ap->ioaddr.device_addr);
228 ata_sff_pause(ap); /* needed; also flushes, for mmio */
229}
230
231static unsigned int sata_rcar_ata_devchk(struct ata_port *ap,
232 unsigned int device)
233{
234 struct ata_ioports *ioaddr = &ap->ioaddr;
235 u8 nsect, lbal;
236
237 sata_rcar_dev_select(ap, device);
238
239 iowrite32(0x55, ioaddr->nsect_addr);
240 iowrite32(0xaa, ioaddr->lbal_addr);
241
242 iowrite32(0xaa, ioaddr->nsect_addr);
243 iowrite32(0x55, ioaddr->lbal_addr);
244
245 iowrite32(0x55, ioaddr->nsect_addr);
246 iowrite32(0xaa, ioaddr->lbal_addr);
247
248 nsect = ioread32(ioaddr->nsect_addr);
249 lbal = ioread32(ioaddr->lbal_addr);
250
251 if (nsect == 0x55 && lbal == 0xaa)
252 return 1; /* found a device */
253
254 return 0; /* nothing found */
255}
256
257static int sata_rcar_wait_after_reset(struct ata_link *link,
258 unsigned long deadline)
259{
260 struct ata_port *ap = link->ap;
261
262 ata_msleep(ap, ATA_WAIT_AFTER_RESET);
263
264 return ata_sff_wait_ready(link, deadline);
265}
266
267static int sata_rcar_bus_softreset(struct ata_port *ap, unsigned long deadline)
268{
269 struct ata_ioports *ioaddr = &ap->ioaddr;
270
271 DPRINTK("ata%u: bus reset via SRST\n", ap->print_id);
272
273 /* software reset. causes dev0 to be selected */
274 iowrite32(ap->ctl, ioaddr->ctl_addr);
275 udelay(20);
276 iowrite32(ap->ctl | ATA_SRST, ioaddr->ctl_addr);
277 udelay(20);
278 iowrite32(ap->ctl, ioaddr->ctl_addr);
279 ap->last_ctl = ap->ctl;
280
281 /* wait the port to become ready */
282 return sata_rcar_wait_after_reset(&ap->link, deadline);
283}
284
285static int sata_rcar_softreset(struct ata_link *link, unsigned int *classes,
286 unsigned long deadline)
287{
288 struct ata_port *ap = link->ap;
289 unsigned int devmask = 0;
290 int rc;
291 u8 err;
292
293 /* determine if device 0 is present */
294 if (sata_rcar_ata_devchk(ap, 0))
295 devmask |= 1 << 0;
296
297 /* issue bus reset */
298 DPRINTK("about to softreset, devmask=%x\n", devmask);
299 rc = sata_rcar_bus_softreset(ap, deadline);
300 /* if link is occupied, -ENODEV too is an error */
301 if (rc && (rc != -ENODEV || sata_scr_valid(link))) {
302 ata_link_err(link, "SRST failed (errno=%d)\n", rc);
303 return rc;
304 }
305
306 /* determine by signature whether we have ATA or ATAPI devices */
307 classes[0] = ata_sff_dev_classify(&link->device[0], devmask, &err);
308
309 DPRINTK("classes[0]=%u\n", classes[0]);
310 return 0;
311}
312
313static void sata_rcar_tf_load(struct ata_port *ap,
314 const struct ata_taskfile *tf)
315{
316 struct ata_ioports *ioaddr = &ap->ioaddr;
317 unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR;
318
319 if (tf->ctl != ap->last_ctl) {
320 iowrite32(tf->ctl, ioaddr->ctl_addr);
321 ap->last_ctl = tf->ctl;
322 ata_wait_idle(ap);
323 }
324
325 if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) {
326 iowrite32(tf->hob_feature, ioaddr->feature_addr);
327 iowrite32(tf->hob_nsect, ioaddr->nsect_addr);
328 iowrite32(tf->hob_lbal, ioaddr->lbal_addr);
329 iowrite32(tf->hob_lbam, ioaddr->lbam_addr);
330 iowrite32(tf->hob_lbah, ioaddr->lbah_addr);
331 VPRINTK("hob: feat 0x%X nsect 0x%X, lba 0x%X 0x%X 0x%X\n",
332 tf->hob_feature,
333 tf->hob_nsect,
334 tf->hob_lbal,
335 tf->hob_lbam,
336 tf->hob_lbah);
337 }
338
339 if (is_addr) {
340 iowrite32(tf->feature, ioaddr->feature_addr);
341 iowrite32(tf->nsect, ioaddr->nsect_addr);
342 iowrite32(tf->lbal, ioaddr->lbal_addr);
343 iowrite32(tf->lbam, ioaddr->lbam_addr);
344 iowrite32(tf->lbah, ioaddr->lbah_addr);
345 VPRINTK("feat 0x%X nsect 0x%X lba 0x%X 0x%X 0x%X\n",
346 tf->feature,
347 tf->nsect,
348 tf->lbal,
349 tf->lbam,
350 tf->lbah);
351 }
352
353 if (tf->flags & ATA_TFLAG_DEVICE) {
354 iowrite32(tf->device, ioaddr->device_addr);
355 VPRINTK("device 0x%X\n", tf->device);
356 }
357
358 ata_wait_idle(ap);
359}
360
361static void sata_rcar_tf_read(struct ata_port *ap, struct ata_taskfile *tf)
362{
363 struct ata_ioports *ioaddr = &ap->ioaddr;
364
365 tf->command = sata_rcar_check_status(ap);
366 tf->feature = ioread32(ioaddr->error_addr);
367 tf->nsect = ioread32(ioaddr->nsect_addr);
368 tf->lbal = ioread32(ioaddr->lbal_addr);
369 tf->lbam = ioread32(ioaddr->lbam_addr);
370 tf->lbah = ioread32(ioaddr->lbah_addr);
371 tf->device = ioread32(ioaddr->device_addr);
372
373 if (tf->flags & ATA_TFLAG_LBA48) {
374 iowrite32(tf->ctl | ATA_HOB, ioaddr->ctl_addr);
375 tf->hob_feature = ioread32(ioaddr->error_addr);
376 tf->hob_nsect = ioread32(ioaddr->nsect_addr);
377 tf->hob_lbal = ioread32(ioaddr->lbal_addr);
378 tf->hob_lbam = ioread32(ioaddr->lbam_addr);
379 tf->hob_lbah = ioread32(ioaddr->lbah_addr);
380 iowrite32(tf->ctl, ioaddr->ctl_addr);
381 ap->last_ctl = tf->ctl;
382 }
383}
384
385static void sata_rcar_exec_command(struct ata_port *ap,
386 const struct ata_taskfile *tf)
387{
388 DPRINTK("ata%u: cmd 0x%X\n", ap->print_id, tf->command);
389
390 iowrite32(tf->command, ap->ioaddr.command_addr);
391 ata_sff_pause(ap);
392}
393
394static unsigned int sata_rcar_data_xfer(struct ata_device *dev,
395 unsigned char *buf,
396 unsigned int buflen, int rw)
397{
398 struct ata_port *ap = dev->link->ap;
399 void __iomem *data_addr = ap->ioaddr.data_addr;
400 unsigned int words = buflen >> 1;
401
402 /* Transfer multiple of 2 bytes */
403 if (rw == READ)
404 sata_rcar_ioread16_rep(data_addr, buf, words);
405 else
406 sata_rcar_iowrite16_rep(data_addr, buf, words);
407
408 /* Transfer trailing byte, if any. */
409 if (unlikely(buflen & 0x01)) {
410 unsigned char pad[2] = { };
411
412 /* Point buf to the tail of buffer */
413 buf += buflen - 1;
414
415 /*
416 * Use io*16_rep() accessors here as well to avoid pointlessly
417 * swapping bytes to and from on the big endian machines...
418 */
419 if (rw == READ) {
420 sata_rcar_ioread16_rep(data_addr, pad, 1);
421 *buf = pad[0];
422 } else {
423 pad[0] = *buf;
424 sata_rcar_iowrite16_rep(data_addr, pad, 1);
425 }
426 words++;
427 }
428
429 return words << 1;
430}
431
432static void sata_rcar_drain_fifo(struct ata_queued_cmd *qc)
433{
434 int count;
435 struct ata_port *ap;
436
437 /* We only need to flush incoming data when a command was running */
438 if (qc == NULL || qc->dma_dir == DMA_TO_DEVICE)
439 return;
440
441 ap = qc->ap;
442 /* Drain up to 64K of data before we give up this recovery method */
443 for (count = 0; (ap->ops->sff_check_status(ap) & ATA_DRQ) &&
444 count < 65536; count += 2)
445 ioread32(ap->ioaddr.data_addr);
446
447 /* Can become DEBUG later */
448 if (count)
449 ata_port_dbg(ap, "drained %d bytes to clear DRQ\n", count);
450}
451
452static int sata_rcar_scr_read(struct ata_link *link, unsigned int sc_reg,
453 u32 *val)
454{
455 if (sc_reg > SCR_ACTIVE)
456 return -EINVAL;
457
458 *val = ioread32(link->ap->ioaddr.scr_addr + (sc_reg << 2));
459 return 0;
460}
461
462static int sata_rcar_scr_write(struct ata_link *link, unsigned int sc_reg,
463 u32 val)
464{
465 if (sc_reg > SCR_ACTIVE)
466 return -EINVAL;
467
468 iowrite32(val, link->ap->ioaddr.scr_addr + (sc_reg << 2));
469 return 0;
470}
471
472static void sata_rcar_bmdma_fill_sg(struct ata_queued_cmd *qc)
473{
474 struct ata_port *ap = qc->ap;
475 struct ata_bmdma_prd *prd = ap->bmdma_prd;
476 struct scatterlist *sg;
333279c8 477 unsigned int si;
163cf81d 478
163cf81d 479 for_each_sg(qc->sg, sg, qc->n_elem, si) {
333279c8 480 u32 addr, sg_len;
163cf81d
VB		 481
482 /*
483 * Note: h/w doesn't support 64-bit, so we unconditionally
484 * truncate dma_addr_t to u32.
485 */
486 addr = (u32)sg_dma_address(sg);
487 sg_len = sg_dma_len(sg);
488
333279c8
SS		 489 prd[si].addr = cpu_to_le32(addr);
490 prd[si].flags_len = cpu_to_le32(sg_len);
491 VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", si, addr, sg_len);
163cf81d
VB		 492 }
493
494 /* end-of-table flag */
333279c8 495 prd[si - 1].addr |= cpu_to_le32(SATA_RCAR_DTEND);
163cf81d
VB		 496}
497
498static void sata_rcar_qc_prep(struct ata_queued_cmd *qc)
499{
500 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
501 return;
502
503 sata_rcar_bmdma_fill_sg(qc);
504}
505
506static void sata_rcar_bmdma_setup(struct ata_queued_cmd *qc)
507{
508 struct ata_port *ap = qc->ap;
509 unsigned int rw = qc->tf.flags & ATA_TFLAG_WRITE;
510 u32 dmactl;
511 struct sata_rcar_priv *priv = ap->host->private_data;
512
513 /* load PRD table addr. */
514 mb(); /* make sure PRD table writes are visible to controller */
515 iowrite32(ap->bmdma_prd_dma, priv->base + ATAPI_DTB_ADR_REG);
516
517 /* specify data direction, triple-check start bit is clear */
518 dmactl = ioread32(priv->base + ATAPI_CONTROL1_REG);
519 dmactl &= ~(ATAPI_CONTROL1_RW | ATAPI_CONTROL1_STOP);
520 if (dmactl & ATAPI_CONTROL1_START) {
521 dmactl &= ~ATAPI_CONTROL1_START;
522 dmactl |= ATAPI_CONTROL1_STOP;
523 }
524 if (!rw)
525 dmactl |= ATAPI_CONTROL1_RW;
526 iowrite32(dmactl, priv->base + ATAPI_CONTROL1_REG);
527
528 /* issue r/w command */
529 ap->ops->sff_exec_command(ap, &qc->tf);
530}
531
532static void sata_rcar_bmdma_start(struct ata_queued_cmd *qc)
533{
534 struct ata_port *ap = qc->ap;
535 u32 dmactl;
536 struct sata_rcar_priv *priv = ap->host->private_data;
537
538 /* start host DMA transaction */
539 dmactl = ioread32(priv->base + ATAPI_CONTROL1_REG);
540 dmactl |= ATAPI_CONTROL1_START;
541 iowrite32(dmactl, priv->base + ATAPI_CONTROL1_REG);
542}
543
544static void sata_rcar_bmdma_stop(struct ata_queued_cmd *qc)
545{
546 struct ata_port *ap = qc->ap;
547 struct sata_rcar_priv *priv = ap->host->private_data;
548 u32 dmactl;
549
550 /* force termination of DMA transfer if active */
551 dmactl = ioread32(priv->base + ATAPI_CONTROL1_REG);
552 if (dmactl & ATAPI_CONTROL1_START) {
553 dmactl &= ~ATAPI_CONTROL1_START;
554 dmactl |= ATAPI_CONTROL1_STOP;
555 iowrite32(dmactl, priv->base + ATAPI_CONTROL1_REG);
556 }
557
558 /* one-PIO-cycle guaranteed wait, per spec, for HDMA1:0 transition */
559 ata_sff_dma_pause(ap);
560}
561
562static u8 sata_rcar_bmdma_status(struct ata_port *ap)
563{
564 struct sata_rcar_priv *priv = ap->host->private_data;
565 u32 status;
566 u8 host_stat = 0;
567
568 status = ioread32(priv->base + ATAPI_STATUS_REG);
569 if (status & ATAPI_STATUS_DEVINT)
570 host_stat |= ATA_DMA_INTR;
571 if (status & ATAPI_STATUS_ACT)
572 host_stat |= ATA_DMA_ACTIVE;
573
574 return host_stat;
575}
576
577static struct scsi_host_template sata_rcar_sht = {
578 ATA_BMDMA_SHT(DRV_NAME),
579};
580
581static struct ata_port_operations sata_rcar_port_ops = {
582 .inherits = &ata_bmdma_port_ops,
583
584 .freeze = sata_rcar_freeze,
585 .thaw = sata_rcar_thaw,
586 .softreset = sata_rcar_softreset,
587
588 .scr_read = sata_rcar_scr_read,
589 .scr_write = sata_rcar_scr_write,
590
591 .sff_dev_select = sata_rcar_dev_select,
592 .sff_set_devctl = sata_rcar_set_devctl,
593 .sff_check_status = sata_rcar_check_status,
594 .sff_check_altstatus = sata_rcar_check_altstatus,
595 .sff_tf_load = sata_rcar_tf_load,
596 .sff_tf_read = sata_rcar_tf_read,
597 .sff_exec_command = sata_rcar_exec_command,
598 .sff_data_xfer = sata_rcar_data_xfer,
599 .sff_drain_fifo = sata_rcar_drain_fifo,
600
601 .qc_prep = sata_rcar_qc_prep,
602
603 .bmdma_setup = sata_rcar_bmdma_setup,
604 .bmdma_start = sata_rcar_bmdma_start,
605 .bmdma_stop = sata_rcar_bmdma_stop,
606 .bmdma_status = sata_rcar_bmdma_status,
607};
608
609static int sata_rcar_serr_interrupt(struct ata_port *ap)
610{
611 struct sata_rcar_priv *priv = ap->host->private_data;
612 struct ata_eh_info *ehi = &ap->link.eh_info;
613 int freeze = 0;
614 int handled = 0;
615 u32 serror;
616
617 serror = ioread32(priv->base + SCRSERR_REG);
618 if (!serror)
619 return 0;
620
621 DPRINTK("SError @host_intr: 0x%x\n", serror);
622
623 /* first, analyze and record host port events */
624 ata_ehi_clear_desc(ehi);
625
626 if (serror & (SERR_DEV_XCHG | SERR_PHYRDY_CHG)) {
627 /* Setup a soft-reset EH action */
628 ata_ehi_hotplugged(ehi);
629 ata_ehi_push_desc(ehi, "%s", "hotplug");
630
631 freeze = serror & SERR_COMM_WAKE ? 0 : 1;
632 handled = 1;
633 }
634
635 /* freeze or abort */
636 if (freeze)
637 ata_port_freeze(ap);
638 else
639 ata_port_abort(ap);
640
641 return handled;
642}
643
644static int sata_rcar_ata_interrupt(struct ata_port *ap)
645{
646 struct ata_queued_cmd *qc;
647 int handled = 0;
648
649 qc = ata_qc_from_tag(ap, ap->link.active_tag);
650 if (qc)
651 handled |= ata_bmdma_port_intr(ap, qc);
652
653 return handled;
654}
655
656static irqreturn_t sata_rcar_interrupt(int irq, void *dev_instance)
657{
658 struct ata_host *host = dev_instance;
659 struct sata_rcar_priv *priv = host->private_data;
660 struct ata_port *ap;
661 unsigned int handled = 0;
662 u32 sataintstat;
663 unsigned long flags;
664
665 spin_lock_irqsave(&host->lock, flags);
666
667 sataintstat = ioread32(priv->base + SATAINTSTAT_REG);
668 if (!sataintstat)
669 goto done;
670 /* ack */
671 iowrite32(sataintstat & ~SATA_RCAR_INT_MASK,
672 priv->base + SATAINTSTAT_REG);
673
674 ap = host->ports[0];
675
676 if (sataintstat & SATAINTSTAT_ATA)
677 handled |= sata_rcar_ata_interrupt(ap);
678
679 if (sataintstat & SATAINTSTAT_SERR)
680 handled |= sata_rcar_serr_interrupt(ap);
681
682done:
683 spin_unlock_irqrestore(&host->lock, flags);
684
685 return IRQ_RETVAL(handled);
686}
687
688static void sata_rcar_setup_port(struct ata_host *host)
689{
690 struct ata_port *ap = host->ports[0];
691 struct ata_ioports *ioaddr = &ap->ioaddr;
692 struct sata_rcar_priv *priv = host->private_data;
693
694 ap->ops = &sata_rcar_port_ops;
695 ap->pio_mask = ATA_PIO4;
696 ap->udma_mask = ATA_UDMA6;
697 ap->flags |= ATA_FLAG_SATA;
698
699 ioaddr->cmd_addr = priv->base + SDATA_REG;
700 ioaddr->ctl_addr = priv->base + SSDEVCON_REG;
701 ioaddr->scr_addr = priv->base + SCRSSTS_REG;
702 ioaddr->altstatus_addr = ioaddr->ctl_addr;
703
704 ioaddr->data_addr = ioaddr->cmd_addr + (ATA_REG_DATA << 2);
705 ioaddr->error_addr = ioaddr->cmd_addr + (ATA_REG_ERR << 2);
706 ioaddr->feature_addr = ioaddr->cmd_addr + (ATA_REG_FEATURE << 2);
707 ioaddr->nsect_addr = ioaddr->cmd_addr + (ATA_REG_NSECT << 2);
708 ioaddr->lbal_addr = ioaddr->cmd_addr + (ATA_REG_LBAL << 2);
709 ioaddr->lbam_addr = ioaddr->cmd_addr + (ATA_REG_LBAM << 2);
710 ioaddr->lbah_addr = ioaddr->cmd_addr + (ATA_REG_LBAH << 2);
711 ioaddr->device_addr = ioaddr->cmd_addr + (ATA_REG_DEVICE << 2);
712 ioaddr->status_addr = ioaddr->cmd_addr + (ATA_REG_STATUS << 2);
713 ioaddr->command_addr = ioaddr->cmd_addr + (ATA_REG_CMD << 2);
714}
715
716static void sata_rcar_init_controller(struct ata_host *host)
717{
718 struct sata_rcar_priv *priv = host->private_data;
719 u32 val;
720
721 /* reset and setup phy */
722 sata_rcar_phy_initialize(priv);
723 sata_rcar_phy_write(priv, SATAPCTLR1_REG, 0x00200188, 0);
724 sata_rcar_phy_write(priv, SATAPCTLR1_REG, 0x00200188, 1);
725 sata_rcar_phy_write(priv, SATAPCTLR3_REG, 0x0000A061, 0);
726 sata_rcar_phy_write(priv, SATAPCTLR2_REG, 0x20000000, 0);
727 sata_rcar_phy_write(priv, SATAPCTLR2_REG, 0x20000000, 1);
728 sata_rcar_phy_write(priv, SATAPCTLR4_REG, 0x28E80000, 0);
729
730 /* SATA-IP reset state */
731 val = ioread32(priv->base + ATAPI_CONTROL1_REG);
732 val |= ATAPI_CONTROL1_RESET;
733 iowrite32(val, priv->base + ATAPI_CONTROL1_REG);
734
735 /* ISM mode, PRD mode, DTEND flag at bit 0 */
736 val = ioread32(priv->base + ATAPI_CONTROL1_REG);
737 val |= ATAPI_CONTROL1_ISM;
738 val |= ATAPI_CONTROL1_DESE;
739 val |= ATAPI_CONTROL1_DTA32M;
740 iowrite32(val, priv->base + ATAPI_CONTROL1_REG);
741
742 /* Release the SATA-IP from the reset state */
743 val = ioread32(priv->base + ATAPI_CONTROL1_REG);
744 val &= ~ATAPI_CONTROL1_RESET;
745 iowrite32(val, priv->base + ATAPI_CONTROL1_REG);
746
747 /* ack and mask */
748 iowrite32(0, priv->base + SATAINTSTAT_REG);
749 iowrite32(0x7ff, priv->base + SATAINTMASK_REG);
750 /* enable interrupts */
751 iowrite32(ATAPI_INT_ENABLE_SATAINT, priv->base + ATAPI_INT_ENABLE_REG);
752}
753
754static int sata_rcar_probe(struct platform_device *pdev)
755{
756 struct ata_host *host;
757 struct sata_rcar_priv *priv;
758 struct resource *mem;
759 int irq;
760 int ret = 0;
761
762 mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
763 if (mem == NULL)
764 return -EINVAL;
765
766 irq = platform_get_irq(pdev, 0);
767 if (irq <= 0)
768 return -EINVAL;
769
770 priv = devm_kzalloc(&pdev->dev, sizeof(struct sata_rcar_priv),
771 GFP_KERNEL);
772 if (!priv)
773 return -ENOMEM;
774
775 priv->clk = devm_clk_get(&pdev->dev, NULL);
776 if (IS_ERR(priv->clk)) {
777 dev_err(&pdev->dev, "failed to get access to sata clock\n");
778 return PTR_ERR(priv->clk);
779 }
780 clk_enable(priv->clk);
781
782 host = ata_host_alloc(&pdev->dev, 1);
783 if (!host) {
784 dev_err(&pdev->dev, "ata_host_alloc failed\n");
785 ret = -ENOMEM;
786 goto cleanup;
787 }
788
789 host->private_data = priv;
790
2de1d5e1
SK		 791 priv->base = devm_ioremap_resource(&pdev->dev, mem);
792 if (IS_ERR(priv->base)) {
793 ret = PTR_ERR(priv->base);
163cf81d
VB		 794 goto cleanup;
795 }
796
797 /* setup port */
798 sata_rcar_setup_port(host);
799
800 /* initialize host controller */
801 sata_rcar_init_controller(host);
802
803 ret = ata_host_activate(host, irq, sata_rcar_interrupt, 0,
804 &sata_rcar_sht);
805 if (!ret)
806 return 0;
807
808cleanup:
809 clk_disable(priv->clk);
810
811 return ret;
812}
813
814static int sata_rcar_remove(struct platform_device *pdev)
815{
d89995db 816 struct ata_host *host = platform_get_drvdata(pdev);
163cf81d
VB		 817 struct sata_rcar_priv *priv = host->private_data;
818
819 ata_host_detach(host);
820
821 /* disable interrupts */
822 iowrite32(0, priv->base + ATAPI_INT_ENABLE_REG);
823 /* ack and mask */
824 iowrite32(0, priv->base + SATAINTSTAT_REG);
825 iowrite32(0x7ff, priv->base + SATAINTMASK_REG);
826
827 clk_disable(priv->clk);
828
829 return 0;
830}
831
832#ifdef CONFIG_PM
833static int sata_rcar_suspend(struct device *dev)
834{
835 struct ata_host *host = dev_get_drvdata(dev);
836 struct sata_rcar_priv *priv = host->private_data;
837 int ret;
838
839 ret = ata_host_suspend(host, PMSG_SUSPEND);
840 if (!ret) {
841 /* disable interrupts */
842 iowrite32(0, priv->base + ATAPI_INT_ENABLE_REG);
843 /* mask */
844 iowrite32(0x7ff, priv->base + SATAINTMASK_REG);
845
846 clk_disable(priv->clk);
847 }
848
849 return ret;
850}
851
852static int sata_rcar_resume(struct device *dev)
853{
854 struct ata_host *host = dev_get_drvdata(dev);
855 struct sata_rcar_priv *priv = host->private_data;
856
857 clk_enable(priv->clk);
858
859 /* ack and mask */
860 iowrite32(0, priv->base + SATAINTSTAT_REG);
861 iowrite32(0x7ff, priv->base + SATAINTMASK_REG);
862 /* enable interrupts */
863 iowrite32(ATAPI_INT_ENABLE_SATAINT, priv->base + ATAPI_INT_ENABLE_REG);
864
865 ata_host_resume(host);
866
867 return 0;
868}
869
870static const struct dev_pm_ops sata_rcar_pm_ops = {
871 .suspend = sata_rcar_suspend,
872 .resume = sata_rcar_resume,
873};
874#endif
875
876static struct of_device_id sata_rcar_match[] = {
877 { .compatible = "renesas,rcar-sata", },
878 {},
879};
880MODULE_DEVICE_TABLE(of, sata_rcar_match);
881
882static struct platform_driver sata_rcar_driver = {
883 .probe = sata_rcar_probe,
884 .remove = sata_rcar_remove,
885 .driver = {
886 .name = DRV_NAME,
887 .owner = THIS_MODULE,
888 .of_match_table = sata_rcar_match,
889#ifdef CONFIG_PM
890 .pm = &sata_rcar_pm_ops,
891#endif
892 },
893};
894
895module_platform_driver(sata_rcar_driver);
896
897MODULE_LICENSE("GPL");
898MODULE_AUTHOR("Vladimir Barinov");
899MODULE_DESCRIPTION("Renesas R-Car SATA controller low level driver");
Linux 6.x block layer and io_uring tree(s)