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bb39ba6a | 1 | // SPDX-License-Identifier: GPL-2.0+ |
163cf81d VB |
2 | /* |
3 | * Renesas R-Car SATA driver | |
4 | * | |
5 | * Author: Vladimir Barinov <source@cogentembedded.com> | |
5bc27ef7 MU |
6 | * Copyright (C) 2013-2015 Cogent Embedded, Inc. |
7 | * Copyright (C) 2013-2015 Renesas Solutions Corp. | |
163cf81d VB |
8 | */ |
9 | ||
10 | #include <linux/kernel.h> | |
11 | #include <linux/module.h> | |
12 | #include <linux/ata.h> | |
13 | #include <linux/libata.h> | |
e67adb4e | 14 | #include <linux/of_device.h> |
163cf81d | 15 | #include <linux/platform_device.h> |
1ecd34dd | 16 | #include <linux/pm_runtime.h> |
2de1d5e1 | 17 | #include <linux/err.h> |
163cf81d VB |
18 | |
19 | #define DRV_NAME "sata_rcar" | |
20 | ||
21 | /* SH-Navi2G/ATAPI-ATA compatible task registers */ | |
22 | #define DATA_REG 0x100 | |
23 | #define SDEVCON_REG 0x138 | |
24 | ||
25 | /* SH-Navi2G/ATAPI module compatible control registers */ | |
26 | #define ATAPI_CONTROL1_REG 0x180 | |
27 | #define ATAPI_STATUS_REG 0x184 | |
28 | #define ATAPI_INT_ENABLE_REG 0x188 | |
29 | #define ATAPI_DTB_ADR_REG 0x198 | |
30 | #define ATAPI_DMA_START_ADR_REG 0x19C | |
31 | #define ATAPI_DMA_TRANS_CNT_REG 0x1A0 | |
32 | #define ATAPI_CONTROL2_REG 0x1A4 | |
33 | #define ATAPI_SIG_ST_REG 0x1B0 | |
34 | #define ATAPI_BYTE_SWAP_REG 0x1BC | |
35 | ||
36 | /* ATAPI control 1 register (ATAPI_CONTROL1) bits */ | |
37 | #define ATAPI_CONTROL1_ISM BIT(16) | |
38 | #define ATAPI_CONTROL1_DTA32M BIT(11) | |
39 | #define ATAPI_CONTROL1_RESET BIT(7) | |
40 | #define ATAPI_CONTROL1_DESE BIT(3) | |
41 | #define ATAPI_CONTROL1_RW BIT(2) | |
42 | #define ATAPI_CONTROL1_STOP BIT(1) | |
43 | #define ATAPI_CONTROL1_START BIT(0) | |
44 | ||
45 | /* ATAPI status register (ATAPI_STATUS) bits */ | |
46 | #define ATAPI_STATUS_SATAINT BIT(11) | |
47 | #define ATAPI_STATUS_DNEND BIT(6) | |
48 | #define ATAPI_STATUS_DEVTRM BIT(5) | |
49 | #define ATAPI_STATUS_DEVINT BIT(4) | |
50 | #define ATAPI_STATUS_ERR BIT(2) | |
51 | #define ATAPI_STATUS_NEND BIT(1) | |
52 | #define ATAPI_STATUS_ACT BIT(0) | |
53 | ||
54 | /* Interrupt enable register (ATAPI_INT_ENABLE) bits */ | |
55 | #define ATAPI_INT_ENABLE_SATAINT BIT(11) | |
56 | #define ATAPI_INT_ENABLE_DNEND BIT(6) | |
57 | #define ATAPI_INT_ENABLE_DEVTRM BIT(5) | |
58 | #define ATAPI_INT_ENABLE_DEVINT BIT(4) | |
59 | #define ATAPI_INT_ENABLE_ERR BIT(2) | |
60 | #define ATAPI_INT_ENABLE_NEND BIT(1) | |
61 | #define ATAPI_INT_ENABLE_ACT BIT(0) | |
62 | ||
63 | /* Access control registers for physical layer control register */ | |
64 | #define SATAPHYADDR_REG 0x200 | |
65 | #define SATAPHYWDATA_REG 0x204 | |
66 | #define SATAPHYACCEN_REG 0x208 | |
67 | #define SATAPHYRESET_REG 0x20C | |
68 | #define SATAPHYRDATA_REG 0x210 | |
69 | #define SATAPHYACK_REG 0x214 | |
70 | ||
71 | /* Physical layer control address command register (SATAPHYADDR) bits */ | |
72 | #define SATAPHYADDR_PHYRATEMODE BIT(10) | |
73 | #define SATAPHYADDR_PHYCMD_READ BIT(9) | |
74 | #define SATAPHYADDR_PHYCMD_WRITE BIT(8) | |
75 | ||
76 | /* Physical layer control enable register (SATAPHYACCEN) bits */ | |
77 | #define SATAPHYACCEN_PHYLANE BIT(0) | |
78 | ||
79 | /* Physical layer control reset register (SATAPHYRESET) bits */ | |
80 | #define SATAPHYRESET_PHYRST BIT(1) | |
81 | #define SATAPHYRESET_PHYSRES BIT(0) | |
82 | ||
83 | /* Physical layer control acknowledge register (SATAPHYACK) bits */ | |
84 | #define SATAPHYACK_PHYACK BIT(0) | |
85 | ||
86 | /* Serial-ATA HOST control registers */ | |
87 | #define BISTCONF_REG 0x102C | |
88 | #define SDATA_REG 0x1100 | |
89 | #define SSDEVCON_REG 0x1204 | |
90 | ||
91 | #define SCRSSTS_REG 0x1400 | |
92 | #define SCRSERR_REG 0x1404 | |
93 | #define SCRSCON_REG 0x1408 | |
94 | #define SCRSACT_REG 0x140C | |
95 | ||
96 | #define SATAINTSTAT_REG 0x1508 | |
97 | #define SATAINTMASK_REG 0x150C | |
98 | ||
99 | /* SATA INT status register (SATAINTSTAT) bits */ | |
100 | #define SATAINTSTAT_SERR BIT(3) | |
101 | #define SATAINTSTAT_ATA BIT(0) | |
102 | ||
103 | /* SATA INT mask register (SATAINTSTAT) bits */ | |
104 | #define SATAINTMASK_SERRMSK BIT(3) | |
105 | #define SATAINTMASK_ERRMSK BIT(2) | |
106 | #define SATAINTMASK_ERRCRTMSK BIT(1) | |
107 | #define SATAINTMASK_ATAMSK BIT(0) | |
e207610f WS |
108 | #define SATAINTMASK_ALL_GEN1 0x7ff |
109 | #define SATAINTMASK_ALL_GEN2 0xfff | |
163cf81d VB |
110 | |
111 | #define SATA_RCAR_INT_MASK (SATAINTMASK_SERRMSK | \ | |
112 | SATAINTMASK_ATAMSK) | |
113 | ||
114 | /* Physical Layer Control Registers */ | |
115 | #define SATAPCTLR1_REG 0x43 | |
116 | #define SATAPCTLR2_REG 0x52 | |
117 | #define SATAPCTLR3_REG 0x5A | |
118 | #define SATAPCTLR4_REG 0x60 | |
119 | ||
120 | /* Descriptor table word 0 bit (when DTA32M = 1) */ | |
121 | #define SATA_RCAR_DTEND BIT(0) | |
122 | ||
df9c5909 | 123 | #define SATA_RCAR_DMA_BOUNDARY 0x1FFFFFFFUL |
8bfbeed5 | 124 | |
e67adb4e VB |
125 | /* Gen2 Physical Layer Control Registers */ |
126 | #define RCAR_GEN2_PHY_CTL1_REG 0x1704 | |
127 | #define RCAR_GEN2_PHY_CTL1 0x34180002 | |
128 | #define RCAR_GEN2_PHY_CTL1_SS 0xC180 /* Spread Spectrum */ | |
129 | ||
130 | #define RCAR_GEN2_PHY_CTL2_REG 0x170C | |
131 | #define RCAR_GEN2_PHY_CTL2 0x00002303 | |
132 | ||
133 | #define RCAR_GEN2_PHY_CTL3_REG 0x171C | |
134 | #define RCAR_GEN2_PHY_CTL3 0x000B0194 | |
135 | ||
136 | #define RCAR_GEN2_PHY_CTL4_REG 0x1724 | |
137 | #define RCAR_GEN2_PHY_CTL4 0x00030994 | |
138 | ||
139 | #define RCAR_GEN2_PHY_CTL5_REG 0x1740 | |
140 | #define RCAR_GEN2_PHY_CTL5 0x03004001 | |
141 | #define RCAR_GEN2_PHY_CTL5_DC BIT(1) /* DC connection */ | |
142 | #define RCAR_GEN2_PHY_CTL5_TR BIT(2) /* Termination Resistor */ | |
143 | ||
144 | enum sata_rcar_type { | |
145 | RCAR_GEN1_SATA, | |
146 | RCAR_GEN2_SATA, | |
da77d76b | 147 | RCAR_GEN3_SATA, |
aa1cf258 | 148 | RCAR_R8A7790_ES1_SATA, |
e67adb4e VB |
149 | }; |
150 | ||
163cf81d VB |
151 | struct sata_rcar_priv { |
152 | void __iomem *base; | |
e207610f | 153 | u32 sataint_mask; |
e67adb4e | 154 | enum sata_rcar_type type; |
163cf81d VB |
155 | }; |
156 | ||
e67adb4e | 157 | static void sata_rcar_gen1_phy_preinit(struct sata_rcar_priv *priv) |
163cf81d | 158 | { |
1b20f6a9 SS |
159 | void __iomem *base = priv->base; |
160 | ||
163cf81d | 161 | /* idle state */ |
1b20f6a9 | 162 | iowrite32(0, base + SATAPHYADDR_REG); |
163cf81d | 163 | /* reset */ |
1b20f6a9 | 164 | iowrite32(SATAPHYRESET_PHYRST, base + SATAPHYRESET_REG); |
163cf81d VB |
165 | udelay(10); |
166 | /* deassert reset */ | |
1b20f6a9 | 167 | iowrite32(0, base + SATAPHYRESET_REG); |
163cf81d VB |
168 | } |
169 | ||
e67adb4e VB |
170 | static void sata_rcar_gen1_phy_write(struct sata_rcar_priv *priv, u16 reg, |
171 | u32 val, int group) | |
163cf81d | 172 | { |
1b20f6a9 | 173 | void __iomem *base = priv->base; |
163cf81d VB |
174 | int timeout; |
175 | ||
176 | /* deassert reset */ | |
1b20f6a9 | 177 | iowrite32(0, base + SATAPHYRESET_REG); |
163cf81d | 178 | /* lane 1 */ |
1b20f6a9 | 179 | iowrite32(SATAPHYACCEN_PHYLANE, base + SATAPHYACCEN_REG); |
163cf81d | 180 | /* write phy register value */ |
1b20f6a9 | 181 | iowrite32(val, base + SATAPHYWDATA_REG); |
163cf81d VB |
182 | /* set register group */ |
183 | if (group) | |
184 | reg |= SATAPHYADDR_PHYRATEMODE; | |
185 | /* write command */ | |
1b20f6a9 | 186 | iowrite32(SATAPHYADDR_PHYCMD_WRITE | reg, base + SATAPHYADDR_REG); |
163cf81d VB |
187 | /* wait for ack */ |
188 | for (timeout = 0; timeout < 100; timeout++) { | |
1b20f6a9 | 189 | val = ioread32(base + SATAPHYACK_REG); |
163cf81d VB |
190 | if (val & SATAPHYACK_PHYACK) |
191 | break; | |
192 | } | |
193 | if (timeout >= 100) | |
194 | pr_err("%s timeout\n", __func__); | |
195 | /* idle state */ | |
1b20f6a9 | 196 | iowrite32(0, base + SATAPHYADDR_REG); |
163cf81d VB |
197 | } |
198 | ||
e67adb4e VB |
199 | static void sata_rcar_gen1_phy_init(struct sata_rcar_priv *priv) |
200 | { | |
201 | sata_rcar_gen1_phy_preinit(priv); | |
202 | sata_rcar_gen1_phy_write(priv, SATAPCTLR1_REG, 0x00200188, 0); | |
203 | sata_rcar_gen1_phy_write(priv, SATAPCTLR1_REG, 0x00200188, 1); | |
204 | sata_rcar_gen1_phy_write(priv, SATAPCTLR3_REG, 0x0000A061, 0); | |
205 | sata_rcar_gen1_phy_write(priv, SATAPCTLR2_REG, 0x20000000, 0); | |
206 | sata_rcar_gen1_phy_write(priv, SATAPCTLR2_REG, 0x20000000, 1); | |
207 | sata_rcar_gen1_phy_write(priv, SATAPCTLR4_REG, 0x28E80000, 0); | |
208 | } | |
209 | ||
210 | static void sata_rcar_gen2_phy_init(struct sata_rcar_priv *priv) | |
211 | { | |
212 | void __iomem *base = priv->base; | |
213 | ||
214 | iowrite32(RCAR_GEN2_PHY_CTL1, base + RCAR_GEN2_PHY_CTL1_REG); | |
215 | iowrite32(RCAR_GEN2_PHY_CTL2, base + RCAR_GEN2_PHY_CTL2_REG); | |
216 | iowrite32(RCAR_GEN2_PHY_CTL3, base + RCAR_GEN2_PHY_CTL3_REG); | |
217 | iowrite32(RCAR_GEN2_PHY_CTL4, base + RCAR_GEN2_PHY_CTL4_REG); | |
218 | iowrite32(RCAR_GEN2_PHY_CTL5 | RCAR_GEN2_PHY_CTL5_DC | | |
219 | RCAR_GEN2_PHY_CTL5_TR, base + RCAR_GEN2_PHY_CTL5_REG); | |
220 | } | |
221 | ||
163cf81d VB |
222 | static void sata_rcar_freeze(struct ata_port *ap) |
223 | { | |
224 | struct sata_rcar_priv *priv = ap->host->private_data; | |
225 | ||
226 | /* mask */ | |
e207610f | 227 | iowrite32(priv->sataint_mask, priv->base + SATAINTMASK_REG); |
163cf81d VB |
228 | |
229 | ata_sff_freeze(ap); | |
230 | } | |
231 | ||
232 | static void sata_rcar_thaw(struct ata_port *ap) | |
233 | { | |
234 | struct sata_rcar_priv *priv = ap->host->private_data; | |
1b20f6a9 | 235 | void __iomem *base = priv->base; |
163cf81d VB |
236 | |
237 | /* ack */ | |
5a0a6a4f | 238 | iowrite32(~(u32)SATA_RCAR_INT_MASK, base + SATAINTSTAT_REG); |
163cf81d VB |
239 | |
240 | ata_sff_thaw(ap); | |
241 | ||
242 | /* unmask */ | |
e207610f | 243 | iowrite32(priv->sataint_mask & ~SATA_RCAR_INT_MASK, base + SATAINTMASK_REG); |
163cf81d VB |
244 | } |
245 | ||
246 | static void sata_rcar_ioread16_rep(void __iomem *reg, void *buffer, int count) | |
247 | { | |
248 | u16 *ptr = buffer; | |
249 | ||
250 | while (count--) { | |
251 | u16 data = ioread32(reg); | |
252 | ||
253 | *ptr++ = data; | |
254 | } | |
255 | } | |
256 | ||
257 | static void sata_rcar_iowrite16_rep(void __iomem *reg, void *buffer, int count) | |
258 | { | |
259 | const u16 *ptr = buffer; | |
260 | ||
261 | while (count--) | |
262 | iowrite32(*ptr++, reg); | |
263 | } | |
264 | ||
265 | static u8 sata_rcar_check_status(struct ata_port *ap) | |
266 | { | |
267 | return ioread32(ap->ioaddr.status_addr); | |
268 | } | |
269 | ||
270 | static u8 sata_rcar_check_altstatus(struct ata_port *ap) | |
271 | { | |
272 | return ioread32(ap->ioaddr.altstatus_addr); | |
273 | } | |
274 | ||
275 | static void sata_rcar_set_devctl(struct ata_port *ap, u8 ctl) | |
276 | { | |
277 | iowrite32(ctl, ap->ioaddr.ctl_addr); | |
278 | } | |
279 | ||
280 | static void sata_rcar_dev_select(struct ata_port *ap, unsigned int device) | |
281 | { | |
282 | iowrite32(ATA_DEVICE_OBS, ap->ioaddr.device_addr); | |
283 | ata_sff_pause(ap); /* needed; also flushes, for mmio */ | |
284 | } | |
285 | ||
286 | static unsigned int sata_rcar_ata_devchk(struct ata_port *ap, | |
287 | unsigned int device) | |
288 | { | |
289 | struct ata_ioports *ioaddr = &ap->ioaddr; | |
290 | u8 nsect, lbal; | |
291 | ||
292 | sata_rcar_dev_select(ap, device); | |
293 | ||
294 | iowrite32(0x55, ioaddr->nsect_addr); | |
295 | iowrite32(0xaa, ioaddr->lbal_addr); | |
296 | ||
297 | iowrite32(0xaa, ioaddr->nsect_addr); | |
298 | iowrite32(0x55, ioaddr->lbal_addr); | |
299 | ||
300 | iowrite32(0x55, ioaddr->nsect_addr); | |
301 | iowrite32(0xaa, ioaddr->lbal_addr); | |
302 | ||
303 | nsect = ioread32(ioaddr->nsect_addr); | |
304 | lbal = ioread32(ioaddr->lbal_addr); | |
305 | ||
306 | if (nsect == 0x55 && lbal == 0xaa) | |
307 | return 1; /* found a device */ | |
308 | ||
309 | return 0; /* nothing found */ | |
310 | } | |
311 | ||
312 | static int sata_rcar_wait_after_reset(struct ata_link *link, | |
313 | unsigned long deadline) | |
314 | { | |
315 | struct ata_port *ap = link->ap; | |
316 | ||
317 | ata_msleep(ap, ATA_WAIT_AFTER_RESET); | |
318 | ||
319 | return ata_sff_wait_ready(link, deadline); | |
320 | } | |
321 | ||
322 | static int sata_rcar_bus_softreset(struct ata_port *ap, unsigned long deadline) | |
323 | { | |
324 | struct ata_ioports *ioaddr = &ap->ioaddr; | |
325 | ||
326 | DPRINTK("ata%u: bus reset via SRST\n", ap->print_id); | |
327 | ||
328 | /* software reset. causes dev0 to be selected */ | |
329 | iowrite32(ap->ctl, ioaddr->ctl_addr); | |
330 | udelay(20); | |
331 | iowrite32(ap->ctl | ATA_SRST, ioaddr->ctl_addr); | |
332 | udelay(20); | |
333 | iowrite32(ap->ctl, ioaddr->ctl_addr); | |
334 | ap->last_ctl = ap->ctl; | |
335 | ||
336 | /* wait the port to become ready */ | |
337 | return sata_rcar_wait_after_reset(&ap->link, deadline); | |
338 | } | |
339 | ||
340 | static int sata_rcar_softreset(struct ata_link *link, unsigned int *classes, | |
341 | unsigned long deadline) | |
342 | { | |
343 | struct ata_port *ap = link->ap; | |
344 | unsigned int devmask = 0; | |
345 | int rc; | |
346 | u8 err; | |
347 | ||
348 | /* determine if device 0 is present */ | |
349 | if (sata_rcar_ata_devchk(ap, 0)) | |
350 | devmask |= 1 << 0; | |
351 | ||
352 | /* issue bus reset */ | |
353 | DPRINTK("about to softreset, devmask=%x\n", devmask); | |
354 | rc = sata_rcar_bus_softreset(ap, deadline); | |
355 | /* if link is occupied, -ENODEV too is an error */ | |
356 | if (rc && (rc != -ENODEV || sata_scr_valid(link))) { | |
357 | ata_link_err(link, "SRST failed (errno=%d)\n", rc); | |
358 | return rc; | |
359 | } | |
360 | ||
361 | /* determine by signature whether we have ATA or ATAPI devices */ | |
362 | classes[0] = ata_sff_dev_classify(&link->device[0], devmask, &err); | |
363 | ||
364 | DPRINTK("classes[0]=%u\n", classes[0]); | |
365 | return 0; | |
366 | } | |
367 | ||
368 | static void sata_rcar_tf_load(struct ata_port *ap, | |
369 | const struct ata_taskfile *tf) | |
370 | { | |
371 | struct ata_ioports *ioaddr = &ap->ioaddr; | |
372 | unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR; | |
373 | ||
374 | if (tf->ctl != ap->last_ctl) { | |
375 | iowrite32(tf->ctl, ioaddr->ctl_addr); | |
376 | ap->last_ctl = tf->ctl; | |
377 | ata_wait_idle(ap); | |
378 | } | |
379 | ||
380 | if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) { | |
381 | iowrite32(tf->hob_feature, ioaddr->feature_addr); | |
382 | iowrite32(tf->hob_nsect, ioaddr->nsect_addr); | |
383 | iowrite32(tf->hob_lbal, ioaddr->lbal_addr); | |
384 | iowrite32(tf->hob_lbam, ioaddr->lbam_addr); | |
385 | iowrite32(tf->hob_lbah, ioaddr->lbah_addr); | |
386 | VPRINTK("hob: feat 0x%X nsect 0x%X, lba 0x%X 0x%X 0x%X\n", | |
387 | tf->hob_feature, | |
388 | tf->hob_nsect, | |
389 | tf->hob_lbal, | |
390 | tf->hob_lbam, | |
391 | tf->hob_lbah); | |
392 | } | |
393 | ||
394 | if (is_addr) { | |
395 | iowrite32(tf->feature, ioaddr->feature_addr); | |
396 | iowrite32(tf->nsect, ioaddr->nsect_addr); | |
397 | iowrite32(tf->lbal, ioaddr->lbal_addr); | |
398 | iowrite32(tf->lbam, ioaddr->lbam_addr); | |
399 | iowrite32(tf->lbah, ioaddr->lbah_addr); | |
400 | VPRINTK("feat 0x%X nsect 0x%X lba 0x%X 0x%X 0x%X\n", | |
401 | tf->feature, | |
402 | tf->nsect, | |
403 | tf->lbal, | |
404 | tf->lbam, | |
405 | tf->lbah); | |
406 | } | |
407 | ||
408 | if (tf->flags & ATA_TFLAG_DEVICE) { | |
409 | iowrite32(tf->device, ioaddr->device_addr); | |
410 | VPRINTK("device 0x%X\n", tf->device); | |
411 | } | |
412 | ||
413 | ata_wait_idle(ap); | |
414 | } | |
415 | ||
416 | static void sata_rcar_tf_read(struct ata_port *ap, struct ata_taskfile *tf) | |
417 | { | |
418 | struct ata_ioports *ioaddr = &ap->ioaddr; | |
419 | ||
420 | tf->command = sata_rcar_check_status(ap); | |
421 | tf->feature = ioread32(ioaddr->error_addr); | |
422 | tf->nsect = ioread32(ioaddr->nsect_addr); | |
423 | tf->lbal = ioread32(ioaddr->lbal_addr); | |
424 | tf->lbam = ioread32(ioaddr->lbam_addr); | |
425 | tf->lbah = ioread32(ioaddr->lbah_addr); | |
426 | tf->device = ioread32(ioaddr->device_addr); | |
427 | ||
428 | if (tf->flags & ATA_TFLAG_LBA48) { | |
429 | iowrite32(tf->ctl | ATA_HOB, ioaddr->ctl_addr); | |
430 | tf->hob_feature = ioread32(ioaddr->error_addr); | |
431 | tf->hob_nsect = ioread32(ioaddr->nsect_addr); | |
432 | tf->hob_lbal = ioread32(ioaddr->lbal_addr); | |
433 | tf->hob_lbam = ioread32(ioaddr->lbam_addr); | |
434 | tf->hob_lbah = ioread32(ioaddr->lbah_addr); | |
435 | iowrite32(tf->ctl, ioaddr->ctl_addr); | |
436 | ap->last_ctl = tf->ctl; | |
437 | } | |
438 | } | |
439 | ||
440 | static void sata_rcar_exec_command(struct ata_port *ap, | |
441 | const struct ata_taskfile *tf) | |
442 | { | |
443 | DPRINTK("ata%u: cmd 0x%X\n", ap->print_id, tf->command); | |
444 | ||
445 | iowrite32(tf->command, ap->ioaddr.command_addr); | |
446 | ata_sff_pause(ap); | |
447 | } | |
448 | ||
989e0aac | 449 | static unsigned int sata_rcar_data_xfer(struct ata_queued_cmd *qc, |
163cf81d VB |
450 | unsigned char *buf, |
451 | unsigned int buflen, int rw) | |
452 | { | |
989e0aac | 453 | struct ata_port *ap = qc->dev->link->ap; |
163cf81d VB |
454 | void __iomem *data_addr = ap->ioaddr.data_addr; |
455 | unsigned int words = buflen >> 1; | |
456 | ||
457 | /* Transfer multiple of 2 bytes */ | |
458 | if (rw == READ) | |
459 | sata_rcar_ioread16_rep(data_addr, buf, words); | |
460 | else | |
461 | sata_rcar_iowrite16_rep(data_addr, buf, words); | |
462 | ||
463 | /* Transfer trailing byte, if any. */ | |
464 | if (unlikely(buflen & 0x01)) { | |
465 | unsigned char pad[2] = { }; | |
466 | ||
467 | /* Point buf to the tail of buffer */ | |
468 | buf += buflen - 1; | |
469 | ||
470 | /* | |
471 | * Use io*16_rep() accessors here as well to avoid pointlessly | |
472 | * swapping bytes to and from on the big endian machines... | |
473 | */ | |
474 | if (rw == READ) { | |
475 | sata_rcar_ioread16_rep(data_addr, pad, 1); | |
476 | *buf = pad[0]; | |
477 | } else { | |
478 | pad[0] = *buf; | |
479 | sata_rcar_iowrite16_rep(data_addr, pad, 1); | |
480 | } | |
481 | words++; | |
482 | } | |
483 | ||
484 | return words << 1; | |
485 | } | |
486 | ||
487 | static void sata_rcar_drain_fifo(struct ata_queued_cmd *qc) | |
488 | { | |
489 | int count; | |
490 | struct ata_port *ap; | |
491 | ||
492 | /* We only need to flush incoming data when a command was running */ | |
493 | if (qc == NULL || qc->dma_dir == DMA_TO_DEVICE) | |
494 | return; | |
495 | ||
496 | ap = qc->ap; | |
497 | /* Drain up to 64K of data before we give up this recovery method */ | |
498 | for (count = 0; (ap->ops->sff_check_status(ap) & ATA_DRQ) && | |
499 | count < 65536; count += 2) | |
500 | ioread32(ap->ioaddr.data_addr); | |
501 | ||
502 | /* Can become DEBUG later */ | |
503 | if (count) | |
504 | ata_port_dbg(ap, "drained %d bytes to clear DRQ\n", count); | |
505 | } | |
506 | ||
507 | static int sata_rcar_scr_read(struct ata_link *link, unsigned int sc_reg, | |
508 | u32 *val) | |
509 | { | |
510 | if (sc_reg > SCR_ACTIVE) | |
511 | return -EINVAL; | |
512 | ||
513 | *val = ioread32(link->ap->ioaddr.scr_addr + (sc_reg << 2)); | |
514 | return 0; | |
515 | } | |
516 | ||
517 | static int sata_rcar_scr_write(struct ata_link *link, unsigned int sc_reg, | |
518 | u32 val) | |
519 | { | |
520 | if (sc_reg > SCR_ACTIVE) | |
521 | return -EINVAL; | |
522 | ||
523 | iowrite32(val, link->ap->ioaddr.scr_addr + (sc_reg << 2)); | |
524 | return 0; | |
525 | } | |
526 | ||
527 | static void sata_rcar_bmdma_fill_sg(struct ata_queued_cmd *qc) | |
528 | { | |
529 | struct ata_port *ap = qc->ap; | |
530 | struct ata_bmdma_prd *prd = ap->bmdma_prd; | |
531 | struct scatterlist *sg; | |
333279c8 | 532 | unsigned int si; |
163cf81d | 533 | |
163cf81d | 534 | for_each_sg(qc->sg, sg, qc->n_elem, si) { |
333279c8 | 535 | u32 addr, sg_len; |
163cf81d VB |
536 | |
537 | /* | |
538 | * Note: h/w doesn't support 64-bit, so we unconditionally | |
539 | * truncate dma_addr_t to u32. | |
540 | */ | |
541 | addr = (u32)sg_dma_address(sg); | |
542 | sg_len = sg_dma_len(sg); | |
543 | ||
333279c8 SS |
544 | prd[si].addr = cpu_to_le32(addr); |
545 | prd[si].flags_len = cpu_to_le32(sg_len); | |
546 | VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", si, addr, sg_len); | |
163cf81d VB |
547 | } |
548 | ||
549 | /* end-of-table flag */ | |
333279c8 | 550 | prd[si - 1].addr |= cpu_to_le32(SATA_RCAR_DTEND); |
163cf81d VB |
551 | } |
552 | ||
95364f36 | 553 | static enum ata_completion_errors sata_rcar_qc_prep(struct ata_queued_cmd *qc) |
163cf81d VB |
554 | { |
555 | if (!(qc->flags & ATA_QCFLAG_DMAMAP)) | |
95364f36 | 556 | return AC_ERR_OK; |
163cf81d VB |
557 | |
558 | sata_rcar_bmdma_fill_sg(qc); | |
95364f36 JS |
559 | |
560 | return AC_ERR_OK; | |
163cf81d VB |
561 | } |
562 | ||
563 | static void sata_rcar_bmdma_setup(struct ata_queued_cmd *qc) | |
564 | { | |
565 | struct ata_port *ap = qc->ap; | |
566 | unsigned int rw = qc->tf.flags & ATA_TFLAG_WRITE; | |
163cf81d | 567 | struct sata_rcar_priv *priv = ap->host->private_data; |
1b20f6a9 SS |
568 | void __iomem *base = priv->base; |
569 | u32 dmactl; | |
163cf81d VB |
570 | |
571 | /* load PRD table addr. */ | |
572 | mb(); /* make sure PRD table writes are visible to controller */ | |
1b20f6a9 | 573 | iowrite32(ap->bmdma_prd_dma, base + ATAPI_DTB_ADR_REG); |
163cf81d VB |
574 | |
575 | /* specify data direction, triple-check start bit is clear */ | |
1b20f6a9 | 576 | dmactl = ioread32(base + ATAPI_CONTROL1_REG); |
163cf81d VB |
577 | dmactl &= ~(ATAPI_CONTROL1_RW | ATAPI_CONTROL1_STOP); |
578 | if (dmactl & ATAPI_CONTROL1_START) { | |
579 | dmactl &= ~ATAPI_CONTROL1_START; | |
580 | dmactl |= ATAPI_CONTROL1_STOP; | |
581 | } | |
582 | if (!rw) | |
583 | dmactl |= ATAPI_CONTROL1_RW; | |
1b20f6a9 | 584 | iowrite32(dmactl, base + ATAPI_CONTROL1_REG); |
163cf81d VB |
585 | |
586 | /* issue r/w command */ | |
587 | ap->ops->sff_exec_command(ap, &qc->tf); | |
588 | } | |
589 | ||
590 | static void sata_rcar_bmdma_start(struct ata_queued_cmd *qc) | |
591 | { | |
592 | struct ata_port *ap = qc->ap; | |
163cf81d | 593 | struct sata_rcar_priv *priv = ap->host->private_data; |
1b20f6a9 SS |
594 | void __iomem *base = priv->base; |
595 | u32 dmactl; | |
163cf81d VB |
596 | |
597 | /* start host DMA transaction */ | |
1b20f6a9 | 598 | dmactl = ioread32(base + ATAPI_CONTROL1_REG); |
df7e131f | 599 | dmactl &= ~ATAPI_CONTROL1_STOP; |
163cf81d | 600 | dmactl |= ATAPI_CONTROL1_START; |
1b20f6a9 | 601 | iowrite32(dmactl, base + ATAPI_CONTROL1_REG); |
163cf81d VB |
602 | } |
603 | ||
604 | static void sata_rcar_bmdma_stop(struct ata_queued_cmd *qc) | |
605 | { | |
606 | struct ata_port *ap = qc->ap; | |
607 | struct sata_rcar_priv *priv = ap->host->private_data; | |
1b20f6a9 | 608 | void __iomem *base = priv->base; |
163cf81d VB |
609 | u32 dmactl; |
610 | ||
611 | /* force termination of DMA transfer if active */ | |
1b20f6a9 | 612 | dmactl = ioread32(base + ATAPI_CONTROL1_REG); |
163cf81d VB |
613 | if (dmactl & ATAPI_CONTROL1_START) { |
614 | dmactl &= ~ATAPI_CONTROL1_START; | |
615 | dmactl |= ATAPI_CONTROL1_STOP; | |
1b20f6a9 | 616 | iowrite32(dmactl, base + ATAPI_CONTROL1_REG); |
163cf81d VB |
617 | } |
618 | ||
619 | /* one-PIO-cycle guaranteed wait, per spec, for HDMA1:0 transition */ | |
620 | ata_sff_dma_pause(ap); | |
621 | } | |
622 | ||
623 | static u8 sata_rcar_bmdma_status(struct ata_port *ap) | |
624 | { | |
625 | struct sata_rcar_priv *priv = ap->host->private_data; | |
163cf81d | 626 | u8 host_stat = 0; |
1b20f6a9 | 627 | u32 status; |
163cf81d VB |
628 | |
629 | status = ioread32(priv->base + ATAPI_STATUS_REG); | |
630 | if (status & ATAPI_STATUS_DEVINT) | |
631 | host_stat |= ATA_DMA_INTR; | |
632 | if (status & ATAPI_STATUS_ACT) | |
633 | host_stat |= ATA_DMA_ACTIVE; | |
634 | ||
635 | return host_stat; | |
636 | } | |
637 | ||
638 | static struct scsi_host_template sata_rcar_sht = { | |
8bfbeed5 SS |
639 | ATA_BASE_SHT(DRV_NAME), |
640 | /* | |
641 | * This controller allows transfer chunks up to 512MB which cross 64KB | |
642 | * boundaries, therefore the DMA limits are more relaxed than standard | |
643 | * ATA SFF. | |
644 | */ | |
645 | .sg_tablesize = ATA_MAX_PRD, | |
646 | .dma_boundary = SATA_RCAR_DMA_BOUNDARY, | |
163cf81d VB |
647 | }; |
648 | ||
649 | static struct ata_port_operations sata_rcar_port_ops = { | |
650 | .inherits = &ata_bmdma_port_ops, | |
651 | ||
652 | .freeze = sata_rcar_freeze, | |
653 | .thaw = sata_rcar_thaw, | |
654 | .softreset = sata_rcar_softreset, | |
655 | ||
656 | .scr_read = sata_rcar_scr_read, | |
657 | .scr_write = sata_rcar_scr_write, | |
658 | ||
659 | .sff_dev_select = sata_rcar_dev_select, | |
660 | .sff_set_devctl = sata_rcar_set_devctl, | |
661 | .sff_check_status = sata_rcar_check_status, | |
662 | .sff_check_altstatus = sata_rcar_check_altstatus, | |
663 | .sff_tf_load = sata_rcar_tf_load, | |
664 | .sff_tf_read = sata_rcar_tf_read, | |
665 | .sff_exec_command = sata_rcar_exec_command, | |
666 | .sff_data_xfer = sata_rcar_data_xfer, | |
667 | .sff_drain_fifo = sata_rcar_drain_fifo, | |
668 | ||
669 | .qc_prep = sata_rcar_qc_prep, | |
670 | ||
671 | .bmdma_setup = sata_rcar_bmdma_setup, | |
672 | .bmdma_start = sata_rcar_bmdma_start, | |
673 | .bmdma_stop = sata_rcar_bmdma_stop, | |
674 | .bmdma_status = sata_rcar_bmdma_status, | |
675 | }; | |
676 | ||
52a2a108 | 677 | static void sata_rcar_serr_interrupt(struct ata_port *ap) |
163cf81d VB |
678 | { |
679 | struct sata_rcar_priv *priv = ap->host->private_data; | |
680 | struct ata_eh_info *ehi = &ap->link.eh_info; | |
681 | int freeze = 0; | |
163cf81d VB |
682 | u32 serror; |
683 | ||
684 | serror = ioread32(priv->base + SCRSERR_REG); | |
685 | if (!serror) | |
52a2a108 | 686 | return; |
163cf81d VB |
687 | |
688 | DPRINTK("SError @host_intr: 0x%x\n", serror); | |
689 | ||
690 | /* first, analyze and record host port events */ | |
691 | ata_ehi_clear_desc(ehi); | |
692 | ||
693 | if (serror & (SERR_DEV_XCHG | SERR_PHYRDY_CHG)) { | |
694 | /* Setup a soft-reset EH action */ | |
695 | ata_ehi_hotplugged(ehi); | |
696 | ata_ehi_push_desc(ehi, "%s", "hotplug"); | |
697 | ||
698 | freeze = serror & SERR_COMM_WAKE ? 0 : 1; | |
163cf81d VB |
699 | } |
700 | ||
701 | /* freeze or abort */ | |
702 | if (freeze) | |
703 | ata_port_freeze(ap); | |
704 | else | |
705 | ata_port_abort(ap); | |
163cf81d VB |
706 | } |
707 | ||
52a2a108 | 708 | static void sata_rcar_ata_interrupt(struct ata_port *ap) |
163cf81d VB |
709 | { |
710 | struct ata_queued_cmd *qc; | |
711 | int handled = 0; | |
712 | ||
713 | qc = ata_qc_from_tag(ap, ap->link.active_tag); | |
714 | if (qc) | |
715 | handled |= ata_bmdma_port_intr(ap, qc); | |
716 | ||
52a2a108 SS |
717 | /* be sure to clear ATA interrupt */ |
718 | if (!handled) | |
719 | sata_rcar_check_status(ap); | |
163cf81d VB |
720 | } |
721 | ||
722 | static irqreturn_t sata_rcar_interrupt(int irq, void *dev_instance) | |
723 | { | |
724 | struct ata_host *host = dev_instance; | |
725 | struct sata_rcar_priv *priv = host->private_data; | |
1b20f6a9 | 726 | void __iomem *base = priv->base; |
163cf81d | 727 | unsigned int handled = 0; |
1b20f6a9 | 728 | struct ata_port *ap; |
163cf81d VB |
729 | u32 sataintstat; |
730 | unsigned long flags; | |
731 | ||
732 | spin_lock_irqsave(&host->lock, flags); | |
733 | ||
1b20f6a9 | 734 | sataintstat = ioread32(base + SATAINTSTAT_REG); |
52a2a108 | 735 | sataintstat &= SATA_RCAR_INT_MASK; |
163cf81d VB |
736 | if (!sataintstat) |
737 | goto done; | |
738 | /* ack */ | |
e207610f | 739 | iowrite32(~sataintstat & priv->sataint_mask, base + SATAINTSTAT_REG); |
163cf81d VB |
740 | |
741 | ap = host->ports[0]; | |
742 | ||
743 | if (sataintstat & SATAINTSTAT_ATA) | |
52a2a108 | 744 | sata_rcar_ata_interrupt(ap); |
163cf81d VB |
745 | |
746 | if (sataintstat & SATAINTSTAT_SERR) | |
52a2a108 | 747 | sata_rcar_serr_interrupt(ap); |
163cf81d | 748 | |
52a2a108 | 749 | handled = 1; |
163cf81d VB |
750 | done: |
751 | spin_unlock_irqrestore(&host->lock, flags); | |
752 | ||
753 | return IRQ_RETVAL(handled); | |
754 | } | |
755 | ||
756 | static void sata_rcar_setup_port(struct ata_host *host) | |
757 | { | |
758 | struct ata_port *ap = host->ports[0]; | |
759 | struct ata_ioports *ioaddr = &ap->ioaddr; | |
760 | struct sata_rcar_priv *priv = host->private_data; | |
1b20f6a9 | 761 | void __iomem *base = priv->base; |
163cf81d VB |
762 | |
763 | ap->ops = &sata_rcar_port_ops; | |
764 | ap->pio_mask = ATA_PIO4; | |
765 | ap->udma_mask = ATA_UDMA6; | |
766 | ap->flags |= ATA_FLAG_SATA; | |
767 | ||
aa1cf258 SH |
768 | if (priv->type == RCAR_R8A7790_ES1_SATA) |
769 | ap->flags |= ATA_FLAG_NO_DIPM; | |
770 | ||
1b20f6a9 SS |
771 | ioaddr->cmd_addr = base + SDATA_REG; |
772 | ioaddr->ctl_addr = base + SSDEVCON_REG; | |
773 | ioaddr->scr_addr = base + SCRSSTS_REG; | |
163cf81d VB |
774 | ioaddr->altstatus_addr = ioaddr->ctl_addr; |
775 | ||
776 | ioaddr->data_addr = ioaddr->cmd_addr + (ATA_REG_DATA << 2); | |
777 | ioaddr->error_addr = ioaddr->cmd_addr + (ATA_REG_ERR << 2); | |
778 | ioaddr->feature_addr = ioaddr->cmd_addr + (ATA_REG_FEATURE << 2); | |
779 | ioaddr->nsect_addr = ioaddr->cmd_addr + (ATA_REG_NSECT << 2); | |
780 | ioaddr->lbal_addr = ioaddr->cmd_addr + (ATA_REG_LBAL << 2); | |
781 | ioaddr->lbam_addr = ioaddr->cmd_addr + (ATA_REG_LBAM << 2); | |
782 | ioaddr->lbah_addr = ioaddr->cmd_addr + (ATA_REG_LBAH << 2); | |
783 | ioaddr->device_addr = ioaddr->cmd_addr + (ATA_REG_DEVICE << 2); | |
784 | ioaddr->status_addr = ioaddr->cmd_addr + (ATA_REG_STATUS << 2); | |
785 | ioaddr->command_addr = ioaddr->cmd_addr + (ATA_REG_CMD << 2); | |
786 | } | |
787 | ||
da77d76b | 788 | static void sata_rcar_init_module(struct sata_rcar_priv *priv) |
163cf81d | 789 | { |
1b20f6a9 | 790 | void __iomem *base = priv->base; |
163cf81d VB |
791 | u32 val; |
792 | ||
163cf81d | 793 | /* SATA-IP reset state */ |
1b20f6a9 | 794 | val = ioread32(base + ATAPI_CONTROL1_REG); |
163cf81d | 795 | val |= ATAPI_CONTROL1_RESET; |
1b20f6a9 | 796 | iowrite32(val, base + ATAPI_CONTROL1_REG); |
163cf81d VB |
797 | |
798 | /* ISM mode, PRD mode, DTEND flag at bit 0 */ | |
1b20f6a9 | 799 | val = ioread32(base + ATAPI_CONTROL1_REG); |
163cf81d VB |
800 | val |= ATAPI_CONTROL1_ISM; |
801 | val |= ATAPI_CONTROL1_DESE; | |
802 | val |= ATAPI_CONTROL1_DTA32M; | |
1b20f6a9 | 803 | iowrite32(val, base + ATAPI_CONTROL1_REG); |
163cf81d VB |
804 | |
805 | /* Release the SATA-IP from the reset state */ | |
1b20f6a9 | 806 | val = ioread32(base + ATAPI_CONTROL1_REG); |
163cf81d | 807 | val &= ~ATAPI_CONTROL1_RESET; |
1b20f6a9 | 808 | iowrite32(val, base + ATAPI_CONTROL1_REG); |
163cf81d VB |
809 | |
810 | /* ack and mask */ | |
1b20f6a9 | 811 | iowrite32(0, base + SATAINTSTAT_REG); |
e207610f | 812 | iowrite32(priv->sataint_mask, base + SATAINTMASK_REG); |
da77d76b | 813 | |
163cf81d | 814 | /* enable interrupts */ |
1b20f6a9 | 815 | iowrite32(ATAPI_INT_ENABLE_SATAINT, base + ATAPI_INT_ENABLE_REG); |
163cf81d VB |
816 | } |
817 | ||
da77d76b KN |
818 | static void sata_rcar_init_controller(struct ata_host *host) |
819 | { | |
820 | struct sata_rcar_priv *priv = host->private_data; | |
da77d76b | 821 | |
e207610f WS |
822 | priv->sataint_mask = SATAINTMASK_ALL_GEN2; |
823 | ||
da77d76b KN |
824 | /* reset and setup phy */ |
825 | switch (priv->type) { | |
826 | case RCAR_GEN1_SATA: | |
e207610f | 827 | priv->sataint_mask = SATAINTMASK_ALL_GEN1; |
da77d76b KN |
828 | sata_rcar_gen1_phy_init(priv); |
829 | break; | |
830 | case RCAR_GEN2_SATA: | |
da77d76b KN |
831 | case RCAR_R8A7790_ES1_SATA: |
832 | sata_rcar_gen2_phy_init(priv); | |
833 | break; | |
96b95489 MH |
834 | case RCAR_GEN3_SATA: |
835 | break; | |
da77d76b KN |
836 | default: |
837 | dev_warn(host->dev, "SATA phy is not initialized\n"); | |
838 | break; | |
839 | } | |
840 | ||
841 | sata_rcar_init_module(priv); | |
842 | } | |
843 | ||
a5893870 | 844 | static const struct of_device_id sata_rcar_match[] = { |
e67adb4e VB |
845 | { |
846 | /* Deprecated by "renesas,sata-r8a7779" */ | |
847 | .compatible = "renesas,rcar-sata", | |
848 | .data = (void *)RCAR_GEN1_SATA, | |
849 | }, | |
850 | { | |
851 | .compatible = "renesas,sata-r8a7779", | |
852 | .data = (void *)RCAR_GEN1_SATA, | |
853 | }, | |
854 | { | |
855 | .compatible = "renesas,sata-r8a7790", | |
856 | .data = (void *)RCAR_GEN2_SATA | |
857 | }, | |
aa1cf258 SH |
858 | { |
859 | .compatible = "renesas,sata-r8a7790-es1", | |
860 | .data = (void *)RCAR_R8A7790_ES1_SATA | |
861 | }, | |
e67adb4e VB |
862 | { |
863 | .compatible = "renesas,sata-r8a7791", | |
864 | .data = (void *)RCAR_GEN2_SATA | |
865 | }, | |
e35b9884 KM |
866 | { |
867 | .compatible = "renesas,sata-r8a7793", | |
868 | .data = (void *)RCAR_GEN2_SATA | |
869 | }, | |
fec7bc43 KA |
870 | { |
871 | .compatible = "renesas,sata-r8a7795", | |
da77d76b | 872 | .data = (void *)RCAR_GEN3_SATA |
fec7bc43 | 873 | }, |
6ac1d153 SH |
874 | { |
875 | .compatible = "renesas,rcar-gen2-sata", | |
876 | .data = (void *)RCAR_GEN2_SATA | |
877 | }, | |
878 | { | |
879 | .compatible = "renesas,rcar-gen3-sata", | |
da77d76b | 880 | .data = (void *)RCAR_GEN3_SATA |
6ac1d153 | 881 | }, |
e67adb4e VB |
882 | { }, |
883 | }; | |
884 | MODULE_DEVICE_TABLE(of, sata_rcar_match); | |
885 | ||
163cf81d VB |
886 | static int sata_rcar_probe(struct platform_device *pdev) |
887 | { | |
c01e229f | 888 | struct device *dev = &pdev->dev; |
163cf81d VB |
889 | struct ata_host *host; |
890 | struct sata_rcar_priv *priv; | |
891 | struct resource *mem; | |
892 | int irq; | |
893 | int ret = 0; | |
894 | ||
163cf81d | 895 | irq = platform_get_irq(pdev, 0); |
9f83cfdb SS |
896 | if (irq < 0) |
897 | return irq; | |
898 | if (!irq) | |
163cf81d VB |
899 | return -EINVAL; |
900 | ||
c01e229f | 901 | priv = devm_kzalloc(dev, sizeof(struct sata_rcar_priv), GFP_KERNEL); |
163cf81d VB |
902 | if (!priv) |
903 | return -ENOMEM; | |
904 | ||
c01e229f | 905 | priv->type = (enum sata_rcar_type)of_device_get_match_data(dev); |
5dc63fdc | 906 | |
1ecd34dd GU |
907 | pm_runtime_enable(dev); |
908 | ret = pm_runtime_get_sync(dev); | |
909 | if (ret < 0) | |
eea12388 | 910 | goto err_pm_put; |
163cf81d | 911 | |
c01e229f | 912 | host = ata_host_alloc(dev, 1); |
163cf81d | 913 | if (!host) { |
163cf81d | 914 | ret = -ENOMEM; |
1ecd34dd | 915 | goto err_pm_put; |
163cf81d VB |
916 | } |
917 | ||
918 | host->private_data = priv; | |
919 | ||
4a9b7f9f | 920 | mem = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
c01e229f | 921 | priv->base = devm_ioremap_resource(dev, mem); |
2de1d5e1 SK |
922 | if (IS_ERR(priv->base)) { |
923 | ret = PTR_ERR(priv->base); | |
1ecd34dd | 924 | goto err_pm_put; |
163cf81d VB |
925 | } |
926 | ||
927 | /* setup port */ | |
928 | sata_rcar_setup_port(host); | |
929 | ||
930 | /* initialize host controller */ | |
931 | sata_rcar_init_controller(host); | |
932 | ||
933 | ret = ata_host_activate(host, irq, sata_rcar_interrupt, 0, | |
934 | &sata_rcar_sht); | |
935 | if (!ret) | |
936 | return 0; | |
937 | ||
1ecd34dd GU |
938 | err_pm_put: |
939 | pm_runtime_put(dev); | |
1ecd34dd | 940 | pm_runtime_disable(dev); |
163cf81d VB |
941 | return ret; |
942 | } | |
943 | ||
944 | static int sata_rcar_remove(struct platform_device *pdev) | |
945 | { | |
d89995db | 946 | struct ata_host *host = platform_get_drvdata(pdev); |
163cf81d | 947 | struct sata_rcar_priv *priv = host->private_data; |
1b20f6a9 | 948 | void __iomem *base = priv->base; |
163cf81d VB |
949 | |
950 | ata_host_detach(host); | |
951 | ||
952 | /* disable interrupts */ | |
1b20f6a9 | 953 | iowrite32(0, base + ATAPI_INT_ENABLE_REG); |
163cf81d | 954 | /* ack and mask */ |
1b20f6a9 | 955 | iowrite32(0, base + SATAINTSTAT_REG); |
e207610f | 956 | iowrite32(priv->sataint_mask, base + SATAINTMASK_REG); |
163cf81d | 957 | |
1ecd34dd GU |
958 | pm_runtime_put(&pdev->dev); |
959 | pm_runtime_disable(&pdev->dev); | |
163cf81d VB |
960 | |
961 | return 0; | |
962 | } | |
963 | ||
58eb8cd5 | 964 | #ifdef CONFIG_PM_SLEEP |
163cf81d VB |
965 | static int sata_rcar_suspend(struct device *dev) |
966 | { | |
967 | struct ata_host *host = dev_get_drvdata(dev); | |
968 | struct sata_rcar_priv *priv = host->private_data; | |
1b20f6a9 | 969 | void __iomem *base = priv->base; |
163cf81d VB |
970 | int ret; |
971 | ||
972 | ret = ata_host_suspend(host, PMSG_SUSPEND); | |
973 | if (!ret) { | |
974 | /* disable interrupts */ | |
1b20f6a9 | 975 | iowrite32(0, base + ATAPI_INT_ENABLE_REG); |
163cf81d | 976 | /* mask */ |
e207610f | 977 | iowrite32(priv->sataint_mask, base + SATAINTMASK_REG); |
163cf81d | 978 | |
1ecd34dd | 979 | pm_runtime_put(dev); |
163cf81d VB |
980 | } |
981 | ||
982 | return ret; | |
983 | } | |
984 | ||
985 | static int sata_rcar_resume(struct device *dev) | |
986 | { | |
987 | struct ata_host *host = dev_get_drvdata(dev); | |
988 | struct sata_rcar_priv *priv = host->private_data; | |
1b20f6a9 | 989 | void __iomem *base = priv->base; |
5dc63fdc | 990 | int ret; |
163cf81d | 991 | |
1ecd34dd | 992 | ret = pm_runtime_get_sync(dev); |
eea12388 NE |
993 | if (ret < 0) { |
994 | pm_runtime_put(dev); | |
5dc63fdc | 995 | return ret; |
eea12388 | 996 | } |
163cf81d | 997 | |
da77d76b | 998 | if (priv->type == RCAR_GEN3_SATA) { |
da77d76b KN |
999 | sata_rcar_init_module(priv); |
1000 | } else { | |
1001 | /* ack and mask */ | |
1002 | iowrite32(0, base + SATAINTSTAT_REG); | |
e207610f | 1003 | iowrite32(priv->sataint_mask, base + SATAINTMASK_REG); |
da77d76b KN |
1004 | |
1005 | /* enable interrupts */ | |
1006 | iowrite32(ATAPI_INT_ENABLE_SATAINT, | |
1007 | base + ATAPI_INT_ENABLE_REG); | |
1008 | } | |
163cf81d VB |
1009 | |
1010 | ata_host_resume(host); | |
1011 | ||
1012 | return 0; | |
1013 | } | |
1014 | ||
5bc27ef7 MU |
1015 | static int sata_rcar_restore(struct device *dev) |
1016 | { | |
1017 | struct ata_host *host = dev_get_drvdata(dev); | |
5dc63fdc | 1018 | int ret; |
5bc27ef7 | 1019 | |
1ecd34dd | 1020 | ret = pm_runtime_get_sync(dev); |
eea12388 NE |
1021 | if (ret < 0) { |
1022 | pm_runtime_put(dev); | |
5dc63fdc | 1023 | return ret; |
eea12388 | 1024 | } |
5bc27ef7 MU |
1025 | |
1026 | sata_rcar_setup_port(host); | |
1027 | ||
1028 | /* initialize host controller */ | |
1029 | sata_rcar_init_controller(host); | |
1030 | ||
1031 | ata_host_resume(host); | |
1032 | ||
1033 | return 0; | |
1034 | } | |
1035 | ||
163cf81d VB |
1036 | static const struct dev_pm_ops sata_rcar_pm_ops = { |
1037 | .suspend = sata_rcar_suspend, | |
1038 | .resume = sata_rcar_resume, | |
5bc27ef7 MU |
1039 | .freeze = sata_rcar_suspend, |
1040 | .thaw = sata_rcar_resume, | |
1041 | .poweroff = sata_rcar_suspend, | |
1042 | .restore = sata_rcar_restore, | |
163cf81d VB |
1043 | }; |
1044 | #endif | |
1045 | ||
163cf81d VB |
1046 | static struct platform_driver sata_rcar_driver = { |
1047 | .probe = sata_rcar_probe, | |
1048 | .remove = sata_rcar_remove, | |
1049 | .driver = { | |
1050 | .name = DRV_NAME, | |
163cf81d | 1051 | .of_match_table = sata_rcar_match, |
58eb8cd5 | 1052 | #ifdef CONFIG_PM_SLEEP |
163cf81d VB |
1053 | .pm = &sata_rcar_pm_ops, |
1054 | #endif | |
1055 | }, | |
1056 | }; | |
1057 | ||
1058 | module_platform_driver(sata_rcar_driver); | |
1059 | ||
1060 | MODULE_LICENSE("GPL"); | |
1061 | MODULE_AUTHOR("Vladimir Barinov"); | |
1062 | MODULE_DESCRIPTION("Renesas R-Car SATA controller low level driver"); |