Commit | Line | Data |
---|---|---|
1da177e4 LT |
1 | /* |
2 | * sata_promise.c - Promise SATA | |
3 | * | |
4 | * Maintained by: Jeff Garzik <jgarzik@pobox.com> | |
5595ddf9 | 5 | * Mikael Pettersson <mikpe@it.uu.se> |
1da177e4 LT |
6 | * Please ALWAYS copy linux-ide@vger.kernel.org |
7 | * on emails. | |
8 | * | |
9 | * Copyright 2003-2004 Red Hat, Inc. | |
10 | * | |
1da177e4 | 11 | * |
af36d7f0 JG |
12 | * This program is free software; you can redistribute it and/or modify |
13 | * it under the terms of the GNU General Public License as published by | |
14 | * the Free Software Foundation; either version 2, or (at your option) | |
15 | * any later version. | |
16 | * | |
17 | * This program is distributed in the hope that it will be useful, | |
18 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
19 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
20 | * GNU General Public License for more details. | |
21 | * | |
22 | * You should have received a copy of the GNU General Public License | |
23 | * along with this program; see the file COPYING. If not, write to | |
24 | * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. | |
25 | * | |
26 | * | |
27 | * libata documentation is available via 'make {ps|pdf}docs', | |
28 | * as Documentation/DocBook/libata.* | |
29 | * | |
30 | * Hardware information only available under NDA. | |
1da177e4 LT |
31 | * |
32 | */ | |
33 | ||
34 | #include <linux/kernel.h> | |
35 | #include <linux/module.h> | |
36 | #include <linux/pci.h> | |
37 | #include <linux/init.h> | |
38 | #include <linux/blkdev.h> | |
39 | #include <linux/delay.h> | |
40 | #include <linux/interrupt.h> | |
a9524a76 | 41 | #include <linux/device.h> |
95006188 | 42 | #include <scsi/scsi.h> |
1da177e4 | 43 | #include <scsi/scsi_host.h> |
193515d5 | 44 | #include <scsi/scsi_cmnd.h> |
1da177e4 | 45 | #include <linux/libata.h> |
1da177e4 LT |
46 | #include "sata_promise.h" |
47 | ||
48 | #define DRV_NAME "sata_promise" | |
5595ddf9 | 49 | #define DRV_VERSION "2.11" |
1da177e4 LT |
50 | |
51 | enum { | |
eca25dca | 52 | PDC_MAX_PORTS = 4, |
0d5ff566 | 53 | PDC_MMIO_BAR = 3, |
b9ccd4a9 | 54 | PDC_MAX_PRD = LIBATA_MAX_PRD - 1, /* -1 for ASIC PRD bug workaround */ |
0d5ff566 | 55 | |
95006188 MP |
56 | /* register offsets */ |
57 | PDC_FEATURE = 0x04, /* Feature/Error reg (per port) */ | |
58 | PDC_SECTOR_COUNT = 0x08, /* Sector count reg (per port) */ | |
59 | PDC_SECTOR_NUMBER = 0x0C, /* Sector number reg (per port) */ | |
60 | PDC_CYLINDER_LOW = 0x10, /* Cylinder low reg (per port) */ | |
61 | PDC_CYLINDER_HIGH = 0x14, /* Cylinder high reg (per port) */ | |
62 | PDC_DEVICE = 0x18, /* Device/Head reg (per port) */ | |
63 | PDC_COMMAND = 0x1C, /* Command/status reg (per port) */ | |
73fd456b | 64 | PDC_ALTSTATUS = 0x38, /* Alternate-status/device-control reg (per port) */ |
1da177e4 LT |
65 | PDC_PKT_SUBMIT = 0x40, /* Command packet pointer addr */ |
66 | PDC_INT_SEQMASK = 0x40, /* Mask of asserted SEQ INTs */ | |
1da177e4 | 67 | PDC_FLASH_CTL = 0x44, /* Flash control register */ |
1da177e4 LT |
68 | PDC_GLOBAL_CTL = 0x48, /* Global control/status (per port) */ |
69 | PDC_CTLSTAT = 0x60, /* IDE control and status (per port) */ | |
70 | PDC_SATA_PLUG_CSR = 0x6C, /* SATA Plug control/status reg */ | |
6340f019 | 71 | PDC2_SATA_PLUG_CSR = 0x60, /* SATAII Plug control/status reg */ |
b2d1eee1 MP |
72 | PDC_TBG_MODE = 0x41C, /* TBG mode (not SATAII) */ |
73 | PDC_SLEW_CTL = 0x470, /* slew rate control reg (not SATAII) */ | |
1da177e4 | 74 | |
176efb05 MP |
75 | /* PDC_GLOBAL_CTL bit definitions */ |
76 | PDC_PH_ERR = (1 << 8), /* PCI error while loading packet */ | |
77 | PDC_SH_ERR = (1 << 9), /* PCI error while loading S/G table */ | |
78 | PDC_DH_ERR = (1 << 10), /* PCI error while loading data */ | |
79 | PDC2_HTO_ERR = (1 << 12), /* host bus timeout */ | |
80 | PDC2_ATA_HBA_ERR = (1 << 13), /* error during SATA DATA FIS transmission */ | |
81 | PDC2_ATA_DMA_CNT_ERR = (1 << 14), /* DMA DATA FIS size differs from S/G count */ | |
82 | PDC_OVERRUN_ERR = (1 << 19), /* S/G byte count larger than HD requires */ | |
83 | PDC_UNDERRUN_ERR = (1 << 20), /* S/G byte count less than HD requires */ | |
84 | PDC_DRIVE_ERR = (1 << 21), /* drive error */ | |
85 | PDC_PCI_SYS_ERR = (1 << 22), /* PCI system error */ | |
86 | PDC1_PCI_PARITY_ERR = (1 << 23), /* PCI parity error (from SATA150 driver) */ | |
87 | PDC1_ERR_MASK = PDC1_PCI_PARITY_ERR, | |
5796d1c4 JG |
88 | PDC2_ERR_MASK = PDC2_HTO_ERR | PDC2_ATA_HBA_ERR | |
89 | PDC2_ATA_DMA_CNT_ERR, | |
90 | PDC_ERR_MASK = PDC_PH_ERR | PDC_SH_ERR | PDC_DH_ERR | | |
91 | PDC_OVERRUN_ERR | PDC_UNDERRUN_ERR | | |
92 | PDC_DRIVE_ERR | PDC_PCI_SYS_ERR | | |
93 | PDC1_ERR_MASK | PDC2_ERR_MASK, | |
1da177e4 LT |
94 | |
95 | board_2037x = 0, /* FastTrak S150 TX2plus */ | |
eca25dca TH |
96 | board_2037x_pata = 1, /* FastTrak S150 TX2plus PATA port */ |
97 | board_20319 = 2, /* FastTrak S150 TX4 */ | |
98 | board_20619 = 3, /* FastTrak TX4000 */ | |
99 | board_2057x = 4, /* SATAII150 Tx2plus */ | |
d0e58031 | 100 | board_2057x_pata = 5, /* SATAII150 Tx2plus PATA port */ |
eca25dca | 101 | board_40518 = 6, /* SATAII150 Tx4 */ |
1da177e4 | 102 | |
6340f019 | 103 | PDC_HAS_PATA = (1 << 1), /* PDC20375/20575 has PATA */ |
1da177e4 | 104 | |
95006188 MP |
105 | /* Sequence counter control registers bit definitions */ |
106 | PDC_SEQCNTRL_INT_MASK = (1 << 5), /* Sequence Interrupt Mask */ | |
107 | ||
108 | /* Feature register values */ | |
109 | PDC_FEATURE_ATAPI_PIO = 0x00, /* ATAPI data xfer by PIO */ | |
110 | PDC_FEATURE_ATAPI_DMA = 0x01, /* ATAPI data xfer by DMA */ | |
111 | ||
112 | /* Device/Head register values */ | |
113 | PDC_DEVICE_SATA = 0xE0, /* Device/Head value for SATA devices */ | |
114 | ||
25b93d81 MP |
115 | /* PDC_CTLSTAT bit definitions */ |
116 | PDC_DMA_ENABLE = (1 << 7), | |
117 | PDC_IRQ_DISABLE = (1 << 10), | |
1da177e4 | 118 | PDC_RESET = (1 << 11), /* HDMA reset */ |
50630195 | 119 | |
25b93d81 | 120 | PDC_COMMON_FLAGS = ATA_FLAG_NO_LEGACY | |
95006188 | 121 | ATA_FLAG_MMIO | |
3d0a59c0 | 122 | ATA_FLAG_PIO_POLLING, |
b2d1eee1 | 123 | |
eca25dca TH |
124 | /* ap->flags bits */ |
125 | PDC_FLAG_GEN_II = (1 << 24), | |
126 | PDC_FLAG_SATA_PATA = (1 << 25), /* supports SATA + PATA */ | |
127 | PDC_FLAG_4_PORTS = (1 << 26), /* 4 ports */ | |
1da177e4 LT |
128 | }; |
129 | ||
1da177e4 LT |
130 | struct pdc_port_priv { |
131 | u8 *pkt; | |
132 | dma_addr_t pkt_dma; | |
133 | }; | |
134 | ||
da3dbb17 TH |
135 | static int pdc_sata_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val); |
136 | static int pdc_sata_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val); | |
1da177e4 | 137 | static int pdc_ata_init_one (struct pci_dev *pdev, const struct pci_device_id *ent); |
eca25dca TH |
138 | static int pdc_common_port_start(struct ata_port *ap); |
139 | static int pdc_sata_port_start(struct ata_port *ap); | |
1da177e4 | 140 | static void pdc_qc_prep(struct ata_queued_cmd *qc); |
057ace5e JG |
141 | static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf); |
142 | static void pdc_exec_command_mmio(struct ata_port *ap, const struct ata_taskfile *tf); | |
95006188 | 143 | static int pdc_check_atapi_dma(struct ata_queued_cmd *qc); |
724114a5 | 144 | static int pdc_old_sata_check_atapi_dma(struct ata_queued_cmd *qc); |
1da177e4 | 145 | static void pdc_irq_clear(struct ata_port *ap); |
9a3d9eb0 | 146 | static unsigned int pdc_qc_issue_prot(struct ata_queued_cmd *qc); |
25b93d81 MP |
147 | static void pdc_freeze(struct ata_port *ap); |
148 | static void pdc_thaw(struct ata_port *ap); | |
724114a5 MP |
149 | static void pdc_pata_error_handler(struct ata_port *ap); |
150 | static void pdc_sata_error_handler(struct ata_port *ap); | |
25b93d81 | 151 | static void pdc_post_internal_cmd(struct ata_queued_cmd *qc); |
724114a5 MP |
152 | static int pdc_pata_cable_detect(struct ata_port *ap); |
153 | static int pdc_sata_cable_detect(struct ata_port *ap); | |
374b1873 | 154 | |
193515d5 | 155 | static struct scsi_host_template pdc_ata_sht = { |
1da177e4 LT |
156 | .module = THIS_MODULE, |
157 | .name = DRV_NAME, | |
158 | .ioctl = ata_scsi_ioctl, | |
159 | .queuecommand = ata_scsi_queuecmd, | |
1da177e4 LT |
160 | .can_queue = ATA_DEF_QUEUE, |
161 | .this_id = ATA_SHT_THIS_ID, | |
b9ccd4a9 | 162 | .sg_tablesize = PDC_MAX_PRD, |
1da177e4 LT |
163 | .cmd_per_lun = ATA_SHT_CMD_PER_LUN, |
164 | .emulated = ATA_SHT_EMULATED, | |
165 | .use_clustering = ATA_SHT_USE_CLUSTERING, | |
166 | .proc_name = DRV_NAME, | |
167 | .dma_boundary = ATA_DMA_BOUNDARY, | |
168 | .slave_configure = ata_scsi_slave_config, | |
ccf68c34 | 169 | .slave_destroy = ata_scsi_slave_destroy, |
1da177e4 | 170 | .bios_param = ata_std_bios_param, |
1da177e4 LT |
171 | }; |
172 | ||
057ace5e | 173 | static const struct ata_port_operations pdc_sata_ops = { |
1da177e4 LT |
174 | .tf_load = pdc_tf_load_mmio, |
175 | .tf_read = ata_tf_read, | |
176 | .check_status = ata_check_status, | |
177 | .exec_command = pdc_exec_command_mmio, | |
178 | .dev_select = ata_std_dev_select, | |
95006188 MP |
179 | .check_atapi_dma = pdc_check_atapi_dma, |
180 | ||
181 | .qc_prep = pdc_qc_prep, | |
182 | .qc_issue = pdc_qc_issue_prot, | |
183 | .freeze = pdc_freeze, | |
184 | .thaw = pdc_thaw, | |
724114a5 | 185 | .error_handler = pdc_sata_error_handler, |
95006188 | 186 | .post_internal_cmd = pdc_post_internal_cmd, |
724114a5 | 187 | .cable_detect = pdc_sata_cable_detect, |
0d5ff566 | 188 | .data_xfer = ata_data_xfer, |
95006188 | 189 | .irq_clear = pdc_irq_clear, |
246ce3b6 | 190 | .irq_on = ata_irq_on, |
95006188 MP |
191 | |
192 | .scr_read = pdc_sata_scr_read, | |
193 | .scr_write = pdc_sata_scr_write, | |
eca25dca | 194 | .port_start = pdc_sata_port_start, |
95006188 MP |
195 | }; |
196 | ||
197 | /* First-generation chips need a more restrictive ->check_atapi_dma op */ | |
198 | static const struct ata_port_operations pdc_old_sata_ops = { | |
95006188 MP |
199 | .tf_load = pdc_tf_load_mmio, |
200 | .tf_read = ata_tf_read, | |
201 | .check_status = ata_check_status, | |
202 | .exec_command = pdc_exec_command_mmio, | |
203 | .dev_select = ata_std_dev_select, | |
724114a5 | 204 | .check_atapi_dma = pdc_old_sata_check_atapi_dma, |
2cba582a | 205 | |
1da177e4 LT |
206 | .qc_prep = pdc_qc_prep, |
207 | .qc_issue = pdc_qc_issue_prot, | |
25b93d81 MP |
208 | .freeze = pdc_freeze, |
209 | .thaw = pdc_thaw, | |
724114a5 | 210 | .error_handler = pdc_sata_error_handler, |
25b93d81 | 211 | .post_internal_cmd = pdc_post_internal_cmd, |
724114a5 | 212 | .cable_detect = pdc_sata_cable_detect, |
0d5ff566 | 213 | .data_xfer = ata_data_xfer, |
1da177e4 | 214 | .irq_clear = pdc_irq_clear, |
246ce3b6 | 215 | .irq_on = ata_irq_on, |
2cba582a | 216 | |
1da177e4 LT |
217 | .scr_read = pdc_sata_scr_read, |
218 | .scr_write = pdc_sata_scr_write, | |
eca25dca | 219 | .port_start = pdc_sata_port_start, |
1da177e4 LT |
220 | }; |
221 | ||
057ace5e | 222 | static const struct ata_port_operations pdc_pata_ops = { |
2cba582a JG |
223 | .tf_load = pdc_tf_load_mmio, |
224 | .tf_read = ata_tf_read, | |
225 | .check_status = ata_check_status, | |
226 | .exec_command = pdc_exec_command_mmio, | |
227 | .dev_select = ata_std_dev_select, | |
95006188 | 228 | .check_atapi_dma = pdc_check_atapi_dma, |
2cba582a | 229 | |
2cba582a JG |
230 | .qc_prep = pdc_qc_prep, |
231 | .qc_issue = pdc_qc_issue_prot, | |
5387373b MP |
232 | .freeze = pdc_freeze, |
233 | .thaw = pdc_thaw, | |
724114a5 | 234 | .error_handler = pdc_pata_error_handler, |
540477b4 | 235 | .post_internal_cmd = pdc_post_internal_cmd, |
724114a5 | 236 | .cable_detect = pdc_pata_cable_detect, |
0d5ff566 | 237 | .data_xfer = ata_data_xfer, |
2cba582a | 238 | .irq_clear = pdc_irq_clear, |
246ce3b6 | 239 | .irq_on = ata_irq_on, |
2cba582a | 240 | |
eca25dca | 241 | .port_start = pdc_common_port_start, |
2cba582a JG |
242 | }; |
243 | ||
98ac62de | 244 | static const struct ata_port_info pdc_port_info[] = { |
5595ddf9 | 245 | [board_2037x] = |
1da177e4 | 246 | { |
eca25dca TH |
247 | .flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA | |
248 | PDC_FLAG_SATA_PATA, | |
1da177e4 LT |
249 | .pio_mask = 0x1f, /* pio0-4 */ |
250 | .mwdma_mask = 0x07, /* mwdma0-2 */ | |
469248ab | 251 | .udma_mask = ATA_UDMA6, |
95006188 | 252 | .port_ops = &pdc_old_sata_ops, |
1da177e4 LT |
253 | }, |
254 | ||
5595ddf9 | 255 | [board_2037x_pata] = |
eca25dca TH |
256 | { |
257 | .flags = PDC_COMMON_FLAGS | ATA_FLAG_SLAVE_POSS, | |
258 | .pio_mask = 0x1f, /* pio0-4 */ | |
259 | .mwdma_mask = 0x07, /* mwdma0-2 */ | |
469248ab | 260 | .udma_mask = ATA_UDMA6, |
eca25dca TH |
261 | .port_ops = &pdc_pata_ops, |
262 | }, | |
263 | ||
5595ddf9 | 264 | [board_20319] = |
1da177e4 | 265 | { |
eca25dca TH |
266 | .flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA | |
267 | PDC_FLAG_4_PORTS, | |
1da177e4 LT |
268 | .pio_mask = 0x1f, /* pio0-4 */ |
269 | .mwdma_mask = 0x07, /* mwdma0-2 */ | |
469248ab | 270 | .udma_mask = ATA_UDMA6, |
95006188 | 271 | .port_ops = &pdc_old_sata_ops, |
1da177e4 | 272 | }, |
f497ba73 | 273 | |
5595ddf9 | 274 | [board_20619] = |
f497ba73 | 275 | { |
eca25dca TH |
276 | .flags = PDC_COMMON_FLAGS | ATA_FLAG_SLAVE_POSS | |
277 | PDC_FLAG_4_PORTS, | |
f497ba73 TL |
278 | .pio_mask = 0x1f, /* pio0-4 */ |
279 | .mwdma_mask = 0x07, /* mwdma0-2 */ | |
469248ab | 280 | .udma_mask = ATA_UDMA6, |
2cba582a | 281 | .port_ops = &pdc_pata_ops, |
f497ba73 | 282 | }, |
5a46fe89 | 283 | |
5595ddf9 | 284 | [board_2057x] = |
6340f019 | 285 | { |
eca25dca TH |
286 | .flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA | |
287 | PDC_FLAG_GEN_II | PDC_FLAG_SATA_PATA, | |
6340f019 LK |
288 | .pio_mask = 0x1f, /* pio0-4 */ |
289 | .mwdma_mask = 0x07, /* mwdma0-2 */ | |
469248ab | 290 | .udma_mask = ATA_UDMA6, |
6340f019 LK |
291 | .port_ops = &pdc_sata_ops, |
292 | }, | |
293 | ||
5595ddf9 | 294 | [board_2057x_pata] = |
eca25dca | 295 | { |
bb312235 | 296 | .flags = PDC_COMMON_FLAGS | ATA_FLAG_SLAVE_POSS | |
eca25dca TH |
297 | PDC_FLAG_GEN_II, |
298 | .pio_mask = 0x1f, /* pio0-4 */ | |
299 | .mwdma_mask = 0x07, /* mwdma0-2 */ | |
469248ab | 300 | .udma_mask = ATA_UDMA6, |
eca25dca TH |
301 | .port_ops = &pdc_pata_ops, |
302 | }, | |
303 | ||
5595ddf9 | 304 | [board_40518] = |
6340f019 | 305 | { |
eca25dca TH |
306 | .flags = PDC_COMMON_FLAGS | ATA_FLAG_SATA | |
307 | PDC_FLAG_GEN_II | PDC_FLAG_4_PORTS, | |
6340f019 LK |
308 | .pio_mask = 0x1f, /* pio0-4 */ |
309 | .mwdma_mask = 0x07, /* mwdma0-2 */ | |
469248ab | 310 | .udma_mask = ATA_UDMA6, |
6340f019 LK |
311 | .port_ops = &pdc_sata_ops, |
312 | }, | |
1da177e4 LT |
313 | }; |
314 | ||
3b7d697d | 315 | static const struct pci_device_id pdc_ata_pci_tbl[] = { |
54bb3a94 | 316 | { PCI_VDEVICE(PROMISE, 0x3371), board_2037x }, |
54bb3a94 JG |
317 | { PCI_VDEVICE(PROMISE, 0x3373), board_2037x }, |
318 | { PCI_VDEVICE(PROMISE, 0x3375), board_2037x }, | |
319 | { PCI_VDEVICE(PROMISE, 0x3376), board_2037x }, | |
b2d1eee1 MP |
320 | { PCI_VDEVICE(PROMISE, 0x3570), board_2057x }, |
321 | { PCI_VDEVICE(PROMISE, 0x3571), board_2057x }, | |
54bb3a94 | 322 | { PCI_VDEVICE(PROMISE, 0x3574), board_2057x }, |
d324d462 | 323 | { PCI_VDEVICE(PROMISE, 0x3577), board_2057x }, |
b2d1eee1 | 324 | { PCI_VDEVICE(PROMISE, 0x3d73), board_2057x }, |
54bb3a94 | 325 | { PCI_VDEVICE(PROMISE, 0x3d75), board_2057x }, |
54bb3a94 JG |
326 | |
327 | { PCI_VDEVICE(PROMISE, 0x3318), board_20319 }, | |
328 | { PCI_VDEVICE(PROMISE, 0x3319), board_20319 }, | |
7f9992a2 MP |
329 | { PCI_VDEVICE(PROMISE, 0x3515), board_40518 }, |
330 | { PCI_VDEVICE(PROMISE, 0x3519), board_40518 }, | |
b2d1eee1 | 331 | { PCI_VDEVICE(PROMISE, 0x3d17), board_40518 }, |
54bb3a94 JG |
332 | { PCI_VDEVICE(PROMISE, 0x3d18), board_40518 }, |
333 | ||
334 | { PCI_VDEVICE(PROMISE, 0x6629), board_20619 }, | |
f497ba73 | 335 | |
1da177e4 LT |
336 | { } /* terminate list */ |
337 | }; | |
338 | ||
1da177e4 LT |
339 | static struct pci_driver pdc_ata_pci_driver = { |
340 | .name = DRV_NAME, | |
341 | .id_table = pdc_ata_pci_tbl, | |
342 | .probe = pdc_ata_init_one, | |
343 | .remove = ata_pci_remove_one, | |
344 | }; | |
345 | ||
724114a5 | 346 | static int pdc_common_port_start(struct ata_port *ap) |
1da177e4 | 347 | { |
cca3974e | 348 | struct device *dev = ap->host->dev; |
1da177e4 LT |
349 | struct pdc_port_priv *pp; |
350 | int rc; | |
351 | ||
352 | rc = ata_port_start(ap); | |
353 | if (rc) | |
354 | return rc; | |
355 | ||
24dc5f33 TH |
356 | pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL); |
357 | if (!pp) | |
358 | return -ENOMEM; | |
1da177e4 | 359 | |
24dc5f33 TH |
360 | pp->pkt = dmam_alloc_coherent(dev, 128, &pp->pkt_dma, GFP_KERNEL); |
361 | if (!pp->pkt) | |
362 | return -ENOMEM; | |
1da177e4 LT |
363 | |
364 | ap->private_data = pp; | |
365 | ||
724114a5 MP |
366 | return 0; |
367 | } | |
368 | ||
369 | static int pdc_sata_port_start(struct ata_port *ap) | |
370 | { | |
724114a5 MP |
371 | int rc; |
372 | ||
373 | rc = pdc_common_port_start(ap); | |
374 | if (rc) | |
375 | return rc; | |
376 | ||
599b7202 | 377 | /* fix up PHYMODE4 align timing */ |
eca25dca | 378 | if (ap->flags & PDC_FLAG_GEN_II) { |
59f99880 | 379 | void __iomem *mmio = ap->ioaddr.scr_addr; |
599b7202 MP |
380 | unsigned int tmp; |
381 | ||
382 | tmp = readl(mmio + 0x014); | |
383 | tmp = (tmp & ~3) | 1; /* set bits 1:0 = 0:1 */ | |
384 | writel(tmp, mmio + 0x014); | |
385 | } | |
386 | ||
1da177e4 | 387 | return 0; |
1da177e4 LT |
388 | } |
389 | ||
1da177e4 LT |
390 | static void pdc_reset_port(struct ata_port *ap) |
391 | { | |
0d5ff566 | 392 | void __iomem *mmio = ap->ioaddr.cmd_addr + PDC_CTLSTAT; |
1da177e4 LT |
393 | unsigned int i; |
394 | u32 tmp; | |
395 | ||
396 | for (i = 11; i > 0; i--) { | |
397 | tmp = readl(mmio); | |
398 | if (tmp & PDC_RESET) | |
399 | break; | |
400 | ||
401 | udelay(100); | |
402 | ||
403 | tmp |= PDC_RESET; | |
404 | writel(tmp, mmio); | |
405 | } | |
406 | ||
407 | tmp &= ~PDC_RESET; | |
408 | writel(tmp, mmio); | |
409 | readl(mmio); /* flush */ | |
410 | } | |
411 | ||
724114a5 | 412 | static int pdc_pata_cable_detect(struct ata_port *ap) |
2cba582a | 413 | { |
d3fb4e8d | 414 | u8 tmp; |
59f99880 | 415 | void __iomem *mmio = ap->ioaddr.cmd_addr + PDC_CTLSTAT + 0x03; |
d3fb4e8d | 416 | |
724114a5 MP |
417 | tmp = readb(mmio); |
418 | if (tmp & 0x01) | |
419 | return ATA_CBL_PATA40; | |
420 | return ATA_CBL_PATA80; | |
421 | } | |
422 | ||
423 | static int pdc_sata_cable_detect(struct ata_port *ap) | |
424 | { | |
e2a9752a | 425 | return ATA_CBL_SATA; |
d3fb4e8d | 426 | } |
2cba582a | 427 | |
da3dbb17 | 428 | static int pdc_sata_scr_read(struct ata_port *ap, unsigned int sc_reg, u32 *val) |
1da177e4 | 429 | { |
724114a5 | 430 | if (sc_reg > SCR_CONTROL) |
da3dbb17 TH |
431 | return -EINVAL; |
432 | *val = readl(ap->ioaddr.scr_addr + (sc_reg * 4)); | |
433 | return 0; | |
1da177e4 LT |
434 | } |
435 | ||
da3dbb17 | 436 | static int pdc_sata_scr_write(struct ata_port *ap, unsigned int sc_reg, u32 val) |
1da177e4 | 437 | { |
724114a5 | 438 | if (sc_reg > SCR_CONTROL) |
da3dbb17 | 439 | return -EINVAL; |
0d5ff566 | 440 | writel(val, ap->ioaddr.scr_addr + (sc_reg * 4)); |
da3dbb17 | 441 | return 0; |
1da177e4 LT |
442 | } |
443 | ||
fba6edbd | 444 | static void pdc_atapi_pkt(struct ata_queued_cmd *qc) |
95006188 | 445 | { |
4113bb6b MP |
446 | struct ata_port *ap = qc->ap; |
447 | dma_addr_t sg_table = ap->prd_dma; | |
448 | unsigned int cdb_len = qc->dev->cdb_len; | |
449 | u8 *cdb = qc->cdb; | |
450 | struct pdc_port_priv *pp = ap->private_data; | |
451 | u8 *buf = pp->pkt; | |
95006188 | 452 | u32 *buf32 = (u32 *) buf; |
46a67143 | 453 | unsigned int dev_sel, feature; |
95006188 MP |
454 | |
455 | /* set control bits (byte 0), zero delay seq id (byte 3), | |
456 | * and seq id (byte 2) | |
457 | */ | |
fba6edbd MP |
458 | switch (qc->tf.protocol) { |
459 | case ATA_PROT_ATAPI_DMA: | |
460 | if (!(qc->tf.flags & ATA_TFLAG_WRITE)) | |
461 | buf32[0] = cpu_to_le32(PDC_PKT_READ); | |
462 | else | |
463 | buf32[0] = 0; | |
464 | break; | |
465 | case ATA_PROT_ATAPI_NODATA: | |
466 | buf32[0] = cpu_to_le32(PDC_PKT_NODATA); | |
467 | break; | |
468 | default: | |
469 | BUG(); | |
470 | break; | |
471 | } | |
95006188 MP |
472 | buf32[1] = cpu_to_le32(sg_table); /* S/G table addr */ |
473 | buf32[2] = 0; /* no next-packet */ | |
474 | ||
4113bb6b | 475 | /* select drive */ |
46a67143 | 476 | if (sata_scr_valid(&ap->link)) |
4113bb6b | 477 | dev_sel = PDC_DEVICE_SATA; |
46a67143 TH |
478 | else |
479 | dev_sel = qc->tf.device; | |
480 | ||
4113bb6b MP |
481 | buf[12] = (1 << 5) | ATA_REG_DEVICE; |
482 | buf[13] = dev_sel; | |
483 | buf[14] = (1 << 5) | ATA_REG_DEVICE | PDC_PKT_CLEAR_BSY; | |
484 | buf[15] = dev_sel; /* once more, waiting for BSY to clear */ | |
485 | ||
486 | buf[16] = (1 << 5) | ATA_REG_NSECT; | |
46a67143 | 487 | buf[17] = qc->tf.nsect; |
4113bb6b | 488 | buf[18] = (1 << 5) | ATA_REG_LBAL; |
46a67143 | 489 | buf[19] = qc->tf.lbal; |
4113bb6b MP |
490 | |
491 | /* set feature and byte counter registers */ | |
46a67143 | 492 | if (qc->tf.protocol != ATA_PROT_ATAPI_DMA) |
4113bb6b | 493 | feature = PDC_FEATURE_ATAPI_PIO; |
46a67143 | 494 | else |
4113bb6b | 495 | feature = PDC_FEATURE_ATAPI_DMA; |
46a67143 | 496 | |
4113bb6b MP |
497 | buf[20] = (1 << 5) | ATA_REG_FEATURE; |
498 | buf[21] = feature; | |
499 | buf[22] = (1 << 5) | ATA_REG_BYTEL; | |
46a67143 | 500 | buf[23] = qc->tf.lbam; |
4113bb6b | 501 | buf[24] = (1 << 5) | ATA_REG_BYTEH; |
46a67143 | 502 | buf[25] = qc->tf.lbah; |
4113bb6b MP |
503 | |
504 | /* send ATAPI packet command 0xA0 */ | |
505 | buf[26] = (1 << 5) | ATA_REG_CMD; | |
46a67143 | 506 | buf[27] = qc->tf.command; |
4113bb6b MP |
507 | |
508 | /* select drive and check DRQ */ | |
509 | buf[28] = (1 << 5) | ATA_REG_DEVICE | PDC_PKT_WAIT_DRDY; | |
510 | buf[29] = dev_sel; | |
511 | ||
95006188 MP |
512 | /* we can represent cdb lengths 2/4/6/8/10/12/14/16 */ |
513 | BUG_ON(cdb_len & ~0x1E); | |
514 | ||
4113bb6b MP |
515 | /* append the CDB as the final part */ |
516 | buf[30] = (((cdb_len >> 1) & 7) << 5) | ATA_REG_DATA | PDC_LAST_REG; | |
517 | memcpy(buf+31, cdb, cdb_len); | |
95006188 MP |
518 | } |
519 | ||
b9ccd4a9 MP |
520 | /** |
521 | * pdc_fill_sg - Fill PCI IDE PRD table | |
522 | * @qc: Metadata associated with taskfile to be transferred | |
523 | * | |
524 | * Fill PCI IDE PRD (scatter-gather) table with segments | |
525 | * associated with the current disk command. | |
526 | * Make sure hardware does not choke on it. | |
527 | * | |
528 | * LOCKING: | |
529 | * spin_lock_irqsave(host lock) | |
530 | * | |
531 | */ | |
532 | static void pdc_fill_sg(struct ata_queued_cmd *qc) | |
533 | { | |
534 | struct ata_port *ap = qc->ap; | |
535 | struct scatterlist *sg; | |
536 | unsigned int idx; | |
537 | const u32 SG_COUNT_ASIC_BUG = 41*4; | |
538 | ||
539 | if (!(qc->flags & ATA_QCFLAG_DMAMAP)) | |
540 | return; | |
541 | ||
542 | WARN_ON(qc->__sg == NULL); | |
543 | WARN_ON(qc->n_elem == 0 && qc->pad_len == 0); | |
544 | ||
545 | idx = 0; | |
546 | ata_for_each_sg(sg, qc) { | |
547 | u32 addr, offset; | |
548 | u32 sg_len, len; | |
549 | ||
550 | /* determine if physical DMA addr spans 64K boundary. | |
551 | * Note h/w doesn't support 64-bit, so we unconditionally | |
552 | * truncate dma_addr_t to u32. | |
553 | */ | |
554 | addr = (u32) sg_dma_address(sg); | |
555 | sg_len = sg_dma_len(sg); | |
556 | ||
557 | while (sg_len) { | |
558 | offset = addr & 0xffff; | |
559 | len = sg_len; | |
560 | if ((offset + sg_len) > 0x10000) | |
561 | len = 0x10000 - offset; | |
562 | ||
563 | ap->prd[idx].addr = cpu_to_le32(addr); | |
564 | ap->prd[idx].flags_len = cpu_to_le32(len & 0xffff); | |
565 | VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", idx, addr, len); | |
566 | ||
567 | idx++; | |
568 | sg_len -= len; | |
569 | addr += len; | |
570 | } | |
571 | } | |
572 | ||
573 | if (idx) { | |
574 | u32 len = le32_to_cpu(ap->prd[idx - 1].flags_len); | |
575 | ||
576 | if (len > SG_COUNT_ASIC_BUG) { | |
577 | u32 addr; | |
578 | ||
579 | VPRINTK("Splitting last PRD.\n"); | |
580 | ||
581 | addr = le32_to_cpu(ap->prd[idx - 1].addr); | |
03116d67 | 582 | ap->prd[idx - 1].flags_len = cpu_to_le32(len - SG_COUNT_ASIC_BUG); |
b9ccd4a9 MP |
583 | VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", idx - 1, addr, SG_COUNT_ASIC_BUG); |
584 | ||
585 | addr = addr + len - SG_COUNT_ASIC_BUG; | |
586 | len = SG_COUNT_ASIC_BUG; | |
587 | ap->prd[idx].addr = cpu_to_le32(addr); | |
588 | ap->prd[idx].flags_len = cpu_to_le32(len); | |
589 | VPRINTK("PRD[%u] = (0x%X, 0x%X)\n", idx, addr, len); | |
590 | ||
591 | idx++; | |
592 | } | |
593 | ||
594 | ap->prd[idx - 1].flags_len |= cpu_to_le32(ATA_PRD_EOT); | |
595 | } | |
596 | } | |
597 | ||
1da177e4 LT |
598 | static void pdc_qc_prep(struct ata_queued_cmd *qc) |
599 | { | |
600 | struct pdc_port_priv *pp = qc->ap->private_data; | |
601 | unsigned int i; | |
602 | ||
603 | VPRINTK("ENTER\n"); | |
604 | ||
605 | switch (qc->tf.protocol) { | |
606 | case ATA_PROT_DMA: | |
b9ccd4a9 | 607 | pdc_fill_sg(qc); |
1da177e4 LT |
608 | /* fall through */ |
609 | ||
610 | case ATA_PROT_NODATA: | |
611 | i = pdc_pkt_header(&qc->tf, qc->ap->prd_dma, | |
612 | qc->dev->devno, pp->pkt); | |
613 | ||
614 | if (qc->tf.flags & ATA_TFLAG_LBA48) | |
615 | i = pdc_prep_lba48(&qc->tf, pp->pkt, i); | |
616 | else | |
617 | i = pdc_prep_lba28(&qc->tf, pp->pkt, i); | |
618 | ||
619 | pdc_pkt_footer(&qc->tf, pp->pkt, i); | |
620 | break; | |
621 | ||
95006188 | 622 | case ATA_PROT_ATAPI: |
b9ccd4a9 | 623 | pdc_fill_sg(qc); |
95006188 MP |
624 | break; |
625 | ||
626 | case ATA_PROT_ATAPI_DMA: | |
b9ccd4a9 | 627 | pdc_fill_sg(qc); |
fba6edbd MP |
628 | /*FALLTHROUGH*/ |
629 | case ATA_PROT_ATAPI_NODATA: | |
630 | pdc_atapi_pkt(qc); | |
95006188 MP |
631 | break; |
632 | ||
1da177e4 LT |
633 | default: |
634 | break; | |
635 | } | |
636 | } | |
637 | ||
25b93d81 MP |
638 | static void pdc_freeze(struct ata_port *ap) |
639 | { | |
59f99880 | 640 | void __iomem *mmio = ap->ioaddr.cmd_addr; |
25b93d81 MP |
641 | u32 tmp; |
642 | ||
643 | tmp = readl(mmio + PDC_CTLSTAT); | |
644 | tmp |= PDC_IRQ_DISABLE; | |
645 | tmp &= ~PDC_DMA_ENABLE; | |
646 | writel(tmp, mmio + PDC_CTLSTAT); | |
647 | readl(mmio + PDC_CTLSTAT); /* flush */ | |
648 | } | |
649 | ||
650 | static void pdc_thaw(struct ata_port *ap) | |
651 | { | |
59f99880 | 652 | void __iomem *mmio = ap->ioaddr.cmd_addr; |
25b93d81 MP |
653 | u32 tmp; |
654 | ||
655 | /* clear IRQ */ | |
656 | readl(mmio + PDC_INT_SEQMASK); | |
657 | ||
658 | /* turn IRQ back on */ | |
659 | tmp = readl(mmio + PDC_CTLSTAT); | |
660 | tmp &= ~PDC_IRQ_DISABLE; | |
661 | writel(tmp, mmio + PDC_CTLSTAT); | |
662 | readl(mmio + PDC_CTLSTAT); /* flush */ | |
663 | } | |
664 | ||
724114a5 | 665 | static void pdc_common_error_handler(struct ata_port *ap, ata_reset_fn_t hardreset) |
25b93d81 | 666 | { |
25b93d81 MP |
667 | if (!(ap->pflags & ATA_PFLAG_FROZEN)) |
668 | pdc_reset_port(ap); | |
669 | ||
25b93d81 | 670 | /* perform recovery */ |
e2a9752a | 671 | ata_do_eh(ap, ata_std_prereset, ata_std_softreset, hardreset, |
25b93d81 MP |
672 | ata_std_postreset); |
673 | } | |
674 | ||
724114a5 MP |
675 | static void pdc_pata_error_handler(struct ata_port *ap) |
676 | { | |
677 | pdc_common_error_handler(ap, NULL); | |
678 | } | |
679 | ||
680 | static void pdc_sata_error_handler(struct ata_port *ap) | |
681 | { | |
682 | pdc_common_error_handler(ap, sata_std_hardreset); | |
683 | } | |
684 | ||
25b93d81 MP |
685 | static void pdc_post_internal_cmd(struct ata_queued_cmd *qc) |
686 | { | |
687 | struct ata_port *ap = qc->ap; | |
688 | ||
25b93d81 | 689 | /* make DMA engine forget about the failed command */ |
a51d644a | 690 | if (qc->flags & ATA_QCFLAG_FAILED) |
25b93d81 MP |
691 | pdc_reset_port(ap); |
692 | } | |
693 | ||
176efb05 MP |
694 | static void pdc_error_intr(struct ata_port *ap, struct ata_queued_cmd *qc, |
695 | u32 port_status, u32 err_mask) | |
696 | { | |
9af5c9c9 | 697 | struct ata_eh_info *ehi = &ap->link.eh_info; |
176efb05 MP |
698 | unsigned int ac_err_mask = 0; |
699 | ||
700 | ata_ehi_clear_desc(ehi); | |
701 | ata_ehi_push_desc(ehi, "port_status 0x%08x", port_status); | |
702 | port_status &= err_mask; | |
703 | ||
704 | if (port_status & PDC_DRIVE_ERR) | |
705 | ac_err_mask |= AC_ERR_DEV; | |
706 | if (port_status & (PDC_OVERRUN_ERR | PDC_UNDERRUN_ERR)) | |
707 | ac_err_mask |= AC_ERR_HSM; | |
708 | if (port_status & (PDC2_ATA_HBA_ERR | PDC2_ATA_DMA_CNT_ERR)) | |
709 | ac_err_mask |= AC_ERR_ATA_BUS; | |
710 | if (port_status & (PDC_PH_ERR | PDC_SH_ERR | PDC_DH_ERR | PDC2_HTO_ERR | |
711 | | PDC_PCI_SYS_ERR | PDC1_PCI_PARITY_ERR)) | |
712 | ac_err_mask |= AC_ERR_HOST_BUS; | |
713 | ||
936fd732 | 714 | if (sata_scr_valid(&ap->link)) { |
da3dbb17 TH |
715 | u32 serror; |
716 | ||
717 | pdc_sata_scr_read(ap, SCR_ERROR, &serror); | |
718 | ehi->serror |= serror; | |
719 | } | |
ce2d3abc | 720 | |
176efb05 | 721 | qc->err_mask |= ac_err_mask; |
ce2d3abc MP |
722 | |
723 | pdc_reset_port(ap); | |
8ffcfd9d MP |
724 | |
725 | ata_port_abort(ap); | |
176efb05 MP |
726 | } |
727 | ||
d0e58031 MP |
728 | static inline unsigned int pdc_host_intr(struct ata_port *ap, |
729 | struct ata_queued_cmd *qc) | |
1da177e4 | 730 | { |
a22e2eb0 | 731 | unsigned int handled = 0; |
176efb05 | 732 | void __iomem *port_mmio = ap->ioaddr.cmd_addr; |
176efb05 MP |
733 | u32 port_status, err_mask; |
734 | ||
735 | err_mask = PDC_ERR_MASK; | |
eca25dca | 736 | if (ap->flags & PDC_FLAG_GEN_II) |
176efb05 MP |
737 | err_mask &= ~PDC1_ERR_MASK; |
738 | else | |
739 | err_mask &= ~PDC2_ERR_MASK; | |
740 | port_status = readl(port_mmio + PDC_GLOBAL_CTL); | |
741 | if (unlikely(port_status & err_mask)) { | |
742 | pdc_error_intr(ap, qc, port_status, err_mask); | |
743 | return 1; | |
1da177e4 LT |
744 | } |
745 | ||
746 | switch (qc->tf.protocol) { | |
747 | case ATA_PROT_DMA: | |
748 | case ATA_PROT_NODATA: | |
95006188 | 749 | case ATA_PROT_ATAPI_DMA: |
fba6edbd | 750 | case ATA_PROT_ATAPI_NODATA: |
a22e2eb0 AL |
751 | qc->err_mask |= ac_err_mask(ata_wait_idle(ap)); |
752 | ata_qc_complete(qc); | |
1da177e4 LT |
753 | handled = 1; |
754 | break; | |
755 | ||
d0e58031 | 756 | default: |
ee500aab AL |
757 | ap->stats.idle_irq++; |
758 | break; | |
d0e58031 | 759 | } |
1da177e4 | 760 | |
ee500aab | 761 | return handled; |
1da177e4 LT |
762 | } |
763 | ||
764 | static void pdc_irq_clear(struct ata_port *ap) | |
765 | { | |
cca3974e | 766 | struct ata_host *host = ap->host; |
0d5ff566 | 767 | void __iomem *mmio = host->iomap[PDC_MMIO_BAR]; |
1da177e4 LT |
768 | |
769 | readl(mmio + PDC_INT_SEQMASK); | |
770 | } | |
771 | ||
5796d1c4 | 772 | static int pdc_is_sataii_tx4(unsigned long flags) |
d0e58031 MP |
773 | { |
774 | const unsigned long mask = PDC_FLAG_GEN_II | PDC_FLAG_4_PORTS; | |
775 | return (flags & mask) == mask; | |
776 | } | |
777 | ||
5796d1c4 JG |
778 | static unsigned int pdc_port_no_to_ata_no(unsigned int port_no, |
779 | int is_sataii_tx4) | |
d0e58031 MP |
780 | { |
781 | static const unsigned char sataii_tx4_port_remap[4] = { 3, 1, 0, 2}; | |
782 | return is_sataii_tx4 ? sataii_tx4_port_remap[port_no] : port_no; | |
783 | } | |
784 | ||
5796d1c4 | 785 | static irqreturn_t pdc_interrupt(int irq, void *dev_instance) |
1da177e4 | 786 | { |
cca3974e | 787 | struct ata_host *host = dev_instance; |
1da177e4 LT |
788 | struct ata_port *ap; |
789 | u32 mask = 0; | |
790 | unsigned int i, tmp; | |
791 | unsigned int handled = 0; | |
ea6ba10b | 792 | void __iomem *mmio_base; |
a77720ad MP |
793 | unsigned int hotplug_offset, ata_no; |
794 | u32 hotplug_status; | |
795 | int is_sataii_tx4; | |
1da177e4 LT |
796 | |
797 | VPRINTK("ENTER\n"); | |
798 | ||
0d5ff566 | 799 | if (!host || !host->iomap[PDC_MMIO_BAR]) { |
1da177e4 LT |
800 | VPRINTK("QUICK EXIT\n"); |
801 | return IRQ_NONE; | |
802 | } | |
803 | ||
0d5ff566 | 804 | mmio_base = host->iomap[PDC_MMIO_BAR]; |
1da177e4 | 805 | |
a77720ad MP |
806 | /* read and clear hotplug flags for all ports */ |
807 | if (host->ports[0]->flags & PDC_FLAG_GEN_II) | |
808 | hotplug_offset = PDC2_SATA_PLUG_CSR; | |
809 | else | |
810 | hotplug_offset = PDC_SATA_PLUG_CSR; | |
811 | hotplug_status = readl(mmio_base + hotplug_offset); | |
812 | if (hotplug_status & 0xff) | |
813 | writel(hotplug_status | 0xff, mmio_base + hotplug_offset); | |
814 | hotplug_status &= 0xff; /* clear uninteresting bits */ | |
815 | ||
1da177e4 LT |
816 | /* reading should also clear interrupts */ |
817 | mask = readl(mmio_base + PDC_INT_SEQMASK); | |
818 | ||
a77720ad | 819 | if (mask == 0xffffffff && hotplug_status == 0) { |
1da177e4 LT |
820 | VPRINTK("QUICK EXIT 2\n"); |
821 | return IRQ_NONE; | |
822 | } | |
6340f019 | 823 | |
cca3974e | 824 | spin_lock(&host->lock); |
6340f019 | 825 | |
1da177e4 | 826 | mask &= 0xffff; /* only 16 tags possible */ |
a77720ad | 827 | if (mask == 0 && hotplug_status == 0) { |
1da177e4 | 828 | VPRINTK("QUICK EXIT 3\n"); |
6340f019 | 829 | goto done_irq; |
1da177e4 LT |
830 | } |
831 | ||
1da177e4 LT |
832 | writel(mask, mmio_base + PDC_INT_SEQMASK); |
833 | ||
a77720ad MP |
834 | is_sataii_tx4 = pdc_is_sataii_tx4(host->ports[0]->flags); |
835 | ||
cca3974e | 836 | for (i = 0; i < host->n_ports; i++) { |
1da177e4 | 837 | VPRINTK("port %u\n", i); |
cca3974e | 838 | ap = host->ports[i]; |
a77720ad MP |
839 | |
840 | /* check for a plug or unplug event */ | |
841 | ata_no = pdc_port_no_to_ata_no(i, is_sataii_tx4); | |
842 | tmp = hotplug_status & (0x11 << ata_no); | |
843 | if (tmp && ap && | |
844 | !(ap->flags & ATA_FLAG_DISABLED)) { | |
9af5c9c9 | 845 | struct ata_eh_info *ehi = &ap->link.eh_info; |
a77720ad MP |
846 | ata_ehi_clear_desc(ehi); |
847 | ata_ehi_hotplugged(ehi); | |
848 | ata_ehi_push_desc(ehi, "hotplug_status %#x", tmp); | |
849 | ata_port_freeze(ap); | |
850 | ++handled; | |
851 | continue; | |
852 | } | |
853 | ||
854 | /* check for a packet interrupt */ | |
1da177e4 | 855 | tmp = mask & (1 << (i + 1)); |
c1389503 | 856 | if (tmp && ap && |
029f5468 | 857 | !(ap->flags & ATA_FLAG_DISABLED)) { |
1da177e4 LT |
858 | struct ata_queued_cmd *qc; |
859 | ||
9af5c9c9 | 860 | qc = ata_qc_from_tag(ap, ap->link.active_tag); |
e50362ec | 861 | if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING))) |
1da177e4 LT |
862 | handled += pdc_host_intr(ap, qc); |
863 | } | |
864 | } | |
865 | ||
1da177e4 LT |
866 | VPRINTK("EXIT\n"); |
867 | ||
6340f019 | 868 | done_irq: |
cca3974e | 869 | spin_unlock(&host->lock); |
1da177e4 LT |
870 | return IRQ_RETVAL(handled); |
871 | } | |
872 | ||
873 | static inline void pdc_packet_start(struct ata_queued_cmd *qc) | |
874 | { | |
875 | struct ata_port *ap = qc->ap; | |
876 | struct pdc_port_priv *pp = ap->private_data; | |
0d5ff566 | 877 | void __iomem *mmio = ap->host->iomap[PDC_MMIO_BAR]; |
1da177e4 LT |
878 | unsigned int port_no = ap->port_no; |
879 | u8 seq = (u8) (port_no + 1); | |
880 | ||
881 | VPRINTK("ENTER, ap %p\n", ap); | |
882 | ||
0d5ff566 TH |
883 | writel(0x00000001, mmio + (seq * 4)); |
884 | readl(mmio + (seq * 4)); /* flush */ | |
1da177e4 LT |
885 | |
886 | pp->pkt[2] = seq; | |
887 | wmb(); /* flush PRD, pkt writes */ | |
0d5ff566 TH |
888 | writel(pp->pkt_dma, ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT); |
889 | readl(ap->ioaddr.cmd_addr + PDC_PKT_SUBMIT); /* flush */ | |
1da177e4 LT |
890 | } |
891 | ||
9a3d9eb0 | 892 | static unsigned int pdc_qc_issue_prot(struct ata_queued_cmd *qc) |
1da177e4 LT |
893 | { |
894 | switch (qc->tf.protocol) { | |
fba6edbd MP |
895 | case ATA_PROT_ATAPI_NODATA: |
896 | if (qc->dev->flags & ATA_DFLAG_CDB_INTR) | |
897 | break; | |
898 | /*FALLTHROUGH*/ | |
51b94d2a TH |
899 | case ATA_PROT_NODATA: |
900 | if (qc->tf.flags & ATA_TFLAG_POLLING) | |
901 | break; | |
902 | /*FALLTHROUGH*/ | |
95006188 | 903 | case ATA_PROT_ATAPI_DMA: |
1da177e4 | 904 | case ATA_PROT_DMA: |
1da177e4 LT |
905 | pdc_packet_start(qc); |
906 | return 0; | |
907 | ||
1da177e4 LT |
908 | default: |
909 | break; | |
910 | } | |
911 | ||
912 | return ata_qc_issue_prot(qc); | |
913 | } | |
914 | ||
057ace5e | 915 | static void pdc_tf_load_mmio(struct ata_port *ap, const struct ata_taskfile *tf) |
1da177e4 | 916 | { |
5796d1c4 JG |
917 | WARN_ON(tf->protocol == ATA_PROT_DMA || |
918 | tf->protocol == ATA_PROT_ATAPI_DMA); | |
1da177e4 LT |
919 | ata_tf_load(ap, tf); |
920 | } | |
921 | ||
5796d1c4 JG |
922 | static void pdc_exec_command_mmio(struct ata_port *ap, |
923 | const struct ata_taskfile *tf) | |
1da177e4 | 924 | { |
5796d1c4 JG |
925 | WARN_ON(tf->protocol == ATA_PROT_DMA || |
926 | tf->protocol == ATA_PROT_ATAPI_DMA); | |
1da177e4 LT |
927 | ata_exec_command(ap, tf); |
928 | } | |
929 | ||
95006188 MP |
930 | static int pdc_check_atapi_dma(struct ata_queued_cmd *qc) |
931 | { | |
932 | u8 *scsicmd = qc->scsicmd->cmnd; | |
933 | int pio = 1; /* atapi dma off by default */ | |
934 | ||
935 | /* Whitelist commands that may use DMA. */ | |
936 | switch (scsicmd[0]) { | |
937 | case WRITE_12: | |
938 | case WRITE_10: | |
939 | case WRITE_6: | |
940 | case READ_12: | |
941 | case READ_10: | |
942 | case READ_6: | |
943 | case 0xad: /* READ_DVD_STRUCTURE */ | |
944 | case 0xbe: /* READ_CD */ | |
945 | pio = 0; | |
946 | } | |
947 | /* -45150 (FFFF4FA2) to -1 (FFFFFFFF) shall use PIO mode */ | |
948 | if (scsicmd[0] == WRITE_10) { | |
5796d1c4 JG |
949 | unsigned int lba = |
950 | (scsicmd[2] << 24) | | |
951 | (scsicmd[3] << 16) | | |
952 | (scsicmd[4] << 8) | | |
953 | scsicmd[5]; | |
95006188 MP |
954 | if (lba >= 0xFFFF4FA2) |
955 | pio = 1; | |
956 | } | |
957 | return pio; | |
958 | } | |
959 | ||
724114a5 | 960 | static int pdc_old_sata_check_atapi_dma(struct ata_queued_cmd *qc) |
95006188 | 961 | { |
95006188 | 962 | /* First generation chips cannot use ATAPI DMA on SATA ports */ |
724114a5 | 963 | return 1; |
95006188 | 964 | } |
1da177e4 | 965 | |
eca25dca TH |
966 | static void pdc_ata_setup_port(struct ata_port *ap, |
967 | void __iomem *base, void __iomem *scr_addr) | |
1da177e4 | 968 | { |
eca25dca TH |
969 | ap->ioaddr.cmd_addr = base; |
970 | ap->ioaddr.data_addr = base; | |
971 | ap->ioaddr.feature_addr = | |
972 | ap->ioaddr.error_addr = base + 0x4; | |
973 | ap->ioaddr.nsect_addr = base + 0x8; | |
974 | ap->ioaddr.lbal_addr = base + 0xc; | |
975 | ap->ioaddr.lbam_addr = base + 0x10; | |
976 | ap->ioaddr.lbah_addr = base + 0x14; | |
977 | ap->ioaddr.device_addr = base + 0x18; | |
978 | ap->ioaddr.command_addr = | |
979 | ap->ioaddr.status_addr = base + 0x1c; | |
980 | ap->ioaddr.altstatus_addr = | |
981 | ap->ioaddr.ctl_addr = base + 0x38; | |
982 | ap->ioaddr.scr_addr = scr_addr; | |
1da177e4 LT |
983 | } |
984 | ||
eca25dca | 985 | static void pdc_host_init(struct ata_host *host) |
1da177e4 | 986 | { |
eca25dca TH |
987 | void __iomem *mmio = host->iomap[PDC_MMIO_BAR]; |
988 | int is_gen2 = host->ports[0]->flags & PDC_FLAG_GEN_II; | |
d324d462 | 989 | int hotplug_offset; |
1da177e4 LT |
990 | u32 tmp; |
991 | ||
eca25dca | 992 | if (is_gen2) |
d324d462 MP |
993 | hotplug_offset = PDC2_SATA_PLUG_CSR; |
994 | else | |
995 | hotplug_offset = PDC_SATA_PLUG_CSR; | |
996 | ||
1da177e4 LT |
997 | /* |
998 | * Except for the hotplug stuff, this is voodoo from the | |
999 | * Promise driver. Label this entire section | |
1000 | * "TODO: figure out why we do this" | |
1001 | */ | |
1002 | ||
b2d1eee1 | 1003 | /* enable BMR_BURST, maybe change FIFO_SHD to 8 dwords */ |
1da177e4 | 1004 | tmp = readl(mmio + PDC_FLASH_CTL); |
b2d1eee1 | 1005 | tmp |= 0x02000; /* bit 13 (enable bmr burst) */ |
eca25dca | 1006 | if (!is_gen2) |
b2d1eee1 | 1007 | tmp |= 0x10000; /* bit 16 (fifo threshold at 8 dw) */ |
1da177e4 LT |
1008 | writel(tmp, mmio + PDC_FLASH_CTL); |
1009 | ||
1010 | /* clear plug/unplug flags for all ports */ | |
6340f019 LK |
1011 | tmp = readl(mmio + hotplug_offset); |
1012 | writel(tmp | 0xff, mmio + hotplug_offset); | |
1da177e4 | 1013 | |
a77720ad | 1014 | /* unmask plug/unplug ints */ |
6340f019 | 1015 | tmp = readl(mmio + hotplug_offset); |
a77720ad | 1016 | writel(tmp & ~0xff0000, mmio + hotplug_offset); |
1da177e4 | 1017 | |
b2d1eee1 | 1018 | /* don't initialise TBG or SLEW on 2nd generation chips */ |
eca25dca | 1019 | if (is_gen2) |
b2d1eee1 MP |
1020 | return; |
1021 | ||
1da177e4 LT |
1022 | /* reduce TBG clock to 133 Mhz. */ |
1023 | tmp = readl(mmio + PDC_TBG_MODE); | |
1024 | tmp &= ~0x30000; /* clear bit 17, 16*/ | |
1025 | tmp |= 0x10000; /* set bit 17:16 = 0:1 */ | |
1026 | writel(tmp, mmio + PDC_TBG_MODE); | |
1027 | ||
1028 | readl(mmio + PDC_TBG_MODE); /* flush */ | |
1029 | msleep(10); | |
1030 | ||
1031 | /* adjust slew rate control register. */ | |
1032 | tmp = readl(mmio + PDC_SLEW_CTL); | |
1033 | tmp &= 0xFFFFF03F; /* clear bit 11 ~ 6 */ | |
1034 | tmp |= 0x00000900; /* set bit 11-9 = 100b , bit 8-6 = 100 */ | |
1035 | writel(tmp, mmio + PDC_SLEW_CTL); | |
1036 | } | |
1037 | ||
5796d1c4 JG |
1038 | static int pdc_ata_init_one(struct pci_dev *pdev, |
1039 | const struct pci_device_id *ent) | |
1da177e4 LT |
1040 | { |
1041 | static int printed_version; | |
eca25dca TH |
1042 | const struct ata_port_info *pi = &pdc_port_info[ent->driver_data]; |
1043 | const struct ata_port_info *ppi[PDC_MAX_PORTS]; | |
1044 | struct ata_host *host; | |
0d5ff566 | 1045 | void __iomem *base; |
eca25dca | 1046 | int n_ports, i, rc; |
5ac2fe57 | 1047 | int is_sataii_tx4; |
1da177e4 LT |
1048 | |
1049 | if (!printed_version++) | |
a9524a76 | 1050 | dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n"); |
1da177e4 | 1051 | |
eca25dca | 1052 | /* enable and acquire resources */ |
24dc5f33 | 1053 | rc = pcim_enable_device(pdev); |
1da177e4 LT |
1054 | if (rc) |
1055 | return rc; | |
1056 | ||
0d5ff566 TH |
1057 | rc = pcim_iomap_regions(pdev, 1 << PDC_MMIO_BAR, DRV_NAME); |
1058 | if (rc == -EBUSY) | |
24dc5f33 | 1059 | pcim_pin_device(pdev); |
0d5ff566 | 1060 | if (rc) |
24dc5f33 | 1061 | return rc; |
eca25dca | 1062 | base = pcim_iomap_table(pdev)[PDC_MMIO_BAR]; |
1da177e4 | 1063 | |
eca25dca TH |
1064 | /* determine port configuration and setup host */ |
1065 | n_ports = 2; | |
1066 | if (pi->flags & PDC_FLAG_4_PORTS) | |
1067 | n_ports = 4; | |
1068 | for (i = 0; i < n_ports; i++) | |
1069 | ppi[i] = pi; | |
1da177e4 | 1070 | |
eca25dca TH |
1071 | if (pi->flags & PDC_FLAG_SATA_PATA) { |
1072 | u8 tmp = readb(base + PDC_FLASH_CTL+1); | |
d0e58031 | 1073 | if (!(tmp & 0x80)) |
eca25dca | 1074 | ppi[n_ports++] = pi + 1; |
eca25dca | 1075 | } |
1da177e4 | 1076 | |
eca25dca TH |
1077 | host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports); |
1078 | if (!host) { | |
1079 | dev_printk(KERN_ERR, &pdev->dev, "failed to allocate host\n"); | |
24dc5f33 | 1080 | return -ENOMEM; |
1da177e4 | 1081 | } |
eca25dca | 1082 | host->iomap = pcim_iomap_table(pdev); |
1da177e4 | 1083 | |
d0e58031 | 1084 | is_sataii_tx4 = pdc_is_sataii_tx4(pi->flags); |
5ac2fe57 | 1085 | for (i = 0; i < host->n_ports; i++) { |
cbcdd875 | 1086 | struct ata_port *ap = host->ports[i]; |
d0e58031 | 1087 | unsigned int ata_no = pdc_port_no_to_ata_no(i, is_sataii_tx4); |
cbcdd875 TH |
1088 | unsigned int port_offset = 0x200 + ata_no * 0x80; |
1089 | unsigned int scr_offset = 0x400 + ata_no * 0x100; | |
1090 | ||
1091 | pdc_ata_setup_port(ap, base + port_offset, base + scr_offset); | |
1092 | ||
1093 | ata_port_pbar_desc(ap, PDC_MMIO_BAR, -1, "mmio"); | |
1094 | ata_port_pbar_desc(ap, PDC_MMIO_BAR, port_offset, "port"); | |
5ac2fe57 | 1095 | } |
1da177e4 LT |
1096 | |
1097 | /* initialize adapter */ | |
eca25dca | 1098 | pdc_host_init(host); |
1da177e4 | 1099 | |
eca25dca TH |
1100 | rc = pci_set_dma_mask(pdev, ATA_DMA_MASK); |
1101 | if (rc) | |
1102 | return rc; | |
1103 | rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK); | |
1104 | if (rc) | |
1105 | return rc; | |
1da177e4 | 1106 | |
eca25dca TH |
1107 | /* start host, request IRQ and attach */ |
1108 | pci_set_master(pdev); | |
1109 | return ata_host_activate(host, pdev->irq, pdc_interrupt, IRQF_SHARED, | |
1110 | &pdc_ata_sht); | |
1da177e4 LT |
1111 | } |
1112 | ||
1da177e4 LT |
1113 | static int __init pdc_ata_init(void) |
1114 | { | |
b7887196 | 1115 | return pci_register_driver(&pdc_ata_pci_driver); |
1da177e4 LT |
1116 | } |
1117 | ||
1da177e4 LT |
1118 | static void __exit pdc_ata_exit(void) |
1119 | { | |
1120 | pci_unregister_driver(&pdc_ata_pci_driver); | |
1121 | } | |
1122 | ||
1da177e4 | 1123 | MODULE_AUTHOR("Jeff Garzik"); |
f497ba73 | 1124 | MODULE_DESCRIPTION("Promise ATA TX2/TX4/TX4000 low-level driver"); |
1da177e4 LT |
1125 | MODULE_LICENSE("GPL"); |
1126 | MODULE_DEVICE_TABLE(pci, pdc_ata_pci_tbl); | |
1127 | MODULE_VERSION(DRV_VERSION); | |
1128 | ||
1129 | module_init(pdc_ata_init); | |
1130 | module_exit(pdc_ata_exit); |