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1da177e4 LT |
1 | /* |
2 | * sata_nv.c - NVIDIA nForce SATA | |
3 | * | |
4 | * Copyright 2004 NVIDIA Corp. All rights reserved. | |
5 | * Copyright 2004 Andrew Chew | |
6 | * | |
aa7e16d6 JG |
7 | * |
8 | * This program is free software; you can redistribute it and/or modify | |
9 | * it under the terms of the GNU General Public License as published by | |
10 | * the Free Software Foundation; either version 2, or (at your option) | |
11 | * any later version. | |
12 | * | |
13 | * This program is distributed in the hope that it will be useful, | |
14 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
15 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
16 | * GNU General Public License for more details. | |
17 | * | |
18 | * You should have received a copy of the GNU General Public License | |
19 | * along with this program; see the file COPYING. If not, write to | |
20 | * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. | |
1da177e4 | 21 | * |
af36d7f0 JG |
22 | * |
23 | * libata documentation is available via 'make {ps|pdf}docs', | |
24 | * as Documentation/DocBook/libata.* | |
25 | * | |
26 | * No hardware documentation available outside of NVIDIA. | |
27 | * This driver programs the NVIDIA SATA controller in a similar | |
28 | * fashion as with other PCI IDE BMDMA controllers, with a few | |
29 | * NV-specific details such as register offsets, SATA phy location, | |
30 | * hotplug info, etc. | |
31 | * | |
1da177e4 LT |
32 | */ |
33 | ||
1da177e4 LT |
34 | #include <linux/kernel.h> |
35 | #include <linux/module.h> | |
36 | #include <linux/pci.h> | |
37 | #include <linux/init.h> | |
38 | #include <linux/blkdev.h> | |
39 | #include <linux/delay.h> | |
40 | #include <linux/interrupt.h> | |
a9524a76 | 41 | #include <linux/device.h> |
1da177e4 LT |
42 | #include <scsi/scsi_host.h> |
43 | #include <linux/libata.h> | |
44 | ||
45 | #define DRV_NAME "sata_nv" | |
8676ce07 | 46 | #define DRV_VERSION "2.0" |
1da177e4 | 47 | |
10ad05df JG |
48 | enum { |
49 | NV_PORTS = 2, | |
50 | NV_PIO_MASK = 0x1f, | |
51 | NV_MWDMA_MASK = 0x07, | |
52 | NV_UDMA_MASK = 0x7f, | |
53 | NV_PORT0_SCR_REG_OFFSET = 0x00, | |
54 | NV_PORT1_SCR_REG_OFFSET = 0x40, | |
1da177e4 | 55 | |
27e4b274 | 56 | /* INT_STATUS/ENABLE */ |
10ad05df | 57 | NV_INT_STATUS = 0x10, |
10ad05df | 58 | NV_INT_ENABLE = 0x11, |
27e4b274 | 59 | NV_INT_STATUS_CK804 = 0x440, |
10ad05df | 60 | NV_INT_ENABLE_CK804 = 0x441, |
1da177e4 | 61 | |
27e4b274 TH |
62 | /* INT_STATUS/ENABLE bits */ |
63 | NV_INT_DEV = 0x01, | |
64 | NV_INT_PM = 0x02, | |
65 | NV_INT_ADDED = 0x04, | |
66 | NV_INT_REMOVED = 0x08, | |
67 | ||
68 | NV_INT_PORT_SHIFT = 4, /* each port occupies 4 bits */ | |
69 | ||
39f87582 | 70 | NV_INT_ALL = 0x0f, |
5a44efff TH |
71 | NV_INT_MASK = NV_INT_DEV | |
72 | NV_INT_ADDED | NV_INT_REMOVED, | |
39f87582 | 73 | |
27e4b274 | 74 | /* INT_CONFIG */ |
10ad05df JG |
75 | NV_INT_CONFIG = 0x12, |
76 | NV_INT_CONFIG_METHD = 0x01, // 0 = INT, 1 = SMI | |
1da177e4 | 77 | |
10ad05df JG |
78 | // For PCI config register 20 |
79 | NV_MCP_SATA_CFG_20 = 0x50, | |
80 | NV_MCP_SATA_CFG_20_SATA_SPACE_EN = 0x04, | |
81 | }; | |
1da177e4 LT |
82 | |
83 | static int nv_init_one (struct pci_dev *pdev, const struct pci_device_id *ent); | |
cca3974e | 84 | static void nv_ck804_host_stop(struct ata_host *host); |
7d12e780 DH |
85 | static irqreturn_t nv_generic_interrupt(int irq, void *dev_instance); |
86 | static irqreturn_t nv_nf2_interrupt(int irq, void *dev_instance); | |
87 | static irqreturn_t nv_ck804_interrupt(int irq, void *dev_instance); | |
1da177e4 LT |
88 | static u32 nv_scr_read (struct ata_port *ap, unsigned int sc_reg); |
89 | static void nv_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val); | |
1da177e4 | 90 | |
39f87582 TH |
91 | static void nv_nf2_freeze(struct ata_port *ap); |
92 | static void nv_nf2_thaw(struct ata_port *ap); | |
93 | static void nv_ck804_freeze(struct ata_port *ap); | |
94 | static void nv_ck804_thaw(struct ata_port *ap); | |
95 | static void nv_error_handler(struct ata_port *ap); | |
96 | ||
1da177e4 LT |
97 | enum nv_host_type |
98 | { | |
99 | GENERIC, | |
100 | NFORCE2, | |
27e4b274 | 101 | NFORCE3 = NFORCE2, /* NF2 == NF3 as far as sata_nv is concerned */ |
e710245b | 102 | CK804 |
1da177e4 LT |
103 | }; |
104 | ||
3b7d697d | 105 | static const struct pci_device_id nv_pci_tbl[] = { |
54bb3a94 JG |
106 | { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE2S_SATA), NFORCE2 }, |
107 | { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3S_SATA), NFORCE3 }, | |
108 | { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE3S_SATA2), NFORCE3 }, | |
109 | { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_CK804_SATA), CK804 }, | |
110 | { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_CK804_SATA2), CK804 }, | |
111 | { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_SATA), CK804 }, | |
112 | { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP04_SATA2), CK804 }, | |
113 | { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_SATA), GENERIC }, | |
114 | { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP51_SATA2), GENERIC }, | |
115 | { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_SATA), GENERIC }, | |
116 | { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP55_SATA2), GENERIC }, | |
117 | { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_SATA), GENERIC }, | |
118 | { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_SATA2), GENERIC }, | |
119 | { PCI_VDEVICE(NVIDIA, PCI_DEVICE_ID_NVIDIA_NFORCE_MCP61_SATA3), GENERIC }, | |
120 | { PCI_VDEVICE(NVIDIA, 0x045c), GENERIC }, | |
121 | { PCI_VDEVICE(NVIDIA, 0x045d), GENERIC }, | |
122 | { PCI_VDEVICE(NVIDIA, 0x045e), GENERIC }, | |
123 | { PCI_VDEVICE(NVIDIA, 0x045f), GENERIC }, | |
1da177e4 LT |
124 | { PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, |
125 | PCI_ANY_ID, PCI_ANY_ID, | |
126 | PCI_CLASS_STORAGE_IDE<<8, 0xffff00, GENERIC }, | |
541134cf DD |
127 | { PCI_VENDOR_ID_NVIDIA, PCI_ANY_ID, |
128 | PCI_ANY_ID, PCI_ANY_ID, | |
129 | PCI_CLASS_STORAGE_RAID<<8, 0xffff00, GENERIC }, | |
2d2744fc JG |
130 | |
131 | { } /* terminate list */ | |
1da177e4 LT |
132 | }; |
133 | ||
1da177e4 LT |
134 | static struct pci_driver nv_pci_driver = { |
135 | .name = DRV_NAME, | |
136 | .id_table = nv_pci_tbl, | |
137 | .probe = nv_init_one, | |
138 | .remove = ata_pci_remove_one, | |
139 | }; | |
140 | ||
193515d5 | 141 | static struct scsi_host_template nv_sht = { |
1da177e4 LT |
142 | .module = THIS_MODULE, |
143 | .name = DRV_NAME, | |
144 | .ioctl = ata_scsi_ioctl, | |
145 | .queuecommand = ata_scsi_queuecmd, | |
1da177e4 LT |
146 | .can_queue = ATA_DEF_QUEUE, |
147 | .this_id = ATA_SHT_THIS_ID, | |
148 | .sg_tablesize = LIBATA_MAX_PRD, | |
1da177e4 LT |
149 | .cmd_per_lun = ATA_SHT_CMD_PER_LUN, |
150 | .emulated = ATA_SHT_EMULATED, | |
151 | .use_clustering = ATA_SHT_USE_CLUSTERING, | |
152 | .proc_name = DRV_NAME, | |
153 | .dma_boundary = ATA_DMA_BOUNDARY, | |
154 | .slave_configure = ata_scsi_slave_config, | |
ccf68c34 | 155 | .slave_destroy = ata_scsi_slave_destroy, |
1da177e4 | 156 | .bios_param = ata_std_bios_param, |
1da177e4 LT |
157 | }; |
158 | ||
ada364e8 | 159 | static const struct ata_port_operations nv_generic_ops = { |
1da177e4 LT |
160 | .port_disable = ata_port_disable, |
161 | .tf_load = ata_tf_load, | |
162 | .tf_read = ata_tf_read, | |
163 | .exec_command = ata_exec_command, | |
164 | .check_status = ata_check_status, | |
165 | .dev_select = ata_std_dev_select, | |
1da177e4 LT |
166 | .bmdma_setup = ata_bmdma_setup, |
167 | .bmdma_start = ata_bmdma_start, | |
168 | .bmdma_stop = ata_bmdma_stop, | |
169 | .bmdma_status = ata_bmdma_status, | |
170 | .qc_prep = ata_qc_prep, | |
171 | .qc_issue = ata_qc_issue_prot, | |
39f87582 TH |
172 | .freeze = ata_bmdma_freeze, |
173 | .thaw = ata_bmdma_thaw, | |
174 | .error_handler = nv_error_handler, | |
175 | .post_internal_cmd = ata_bmdma_post_internal_cmd, | |
a6b2c5d4 | 176 | .data_xfer = ata_pio_data_xfer, |
ada364e8 | 177 | .irq_handler = nv_generic_interrupt, |
1da177e4 LT |
178 | .irq_clear = ata_bmdma_irq_clear, |
179 | .scr_read = nv_scr_read, | |
180 | .scr_write = nv_scr_write, | |
181 | .port_start = ata_port_start, | |
182 | .port_stop = ata_port_stop, | |
e6faf082 | 183 | .host_stop = ata_pci_host_stop, |
1da177e4 LT |
184 | }; |
185 | ||
ada364e8 TH |
186 | static const struct ata_port_operations nv_nf2_ops = { |
187 | .port_disable = ata_port_disable, | |
188 | .tf_load = ata_tf_load, | |
189 | .tf_read = ata_tf_read, | |
190 | .exec_command = ata_exec_command, | |
191 | .check_status = ata_check_status, | |
192 | .dev_select = ata_std_dev_select, | |
ada364e8 TH |
193 | .bmdma_setup = ata_bmdma_setup, |
194 | .bmdma_start = ata_bmdma_start, | |
195 | .bmdma_stop = ata_bmdma_stop, | |
196 | .bmdma_status = ata_bmdma_status, | |
197 | .qc_prep = ata_qc_prep, | |
198 | .qc_issue = ata_qc_issue_prot, | |
39f87582 TH |
199 | .freeze = nv_nf2_freeze, |
200 | .thaw = nv_nf2_thaw, | |
201 | .error_handler = nv_error_handler, | |
202 | .post_internal_cmd = ata_bmdma_post_internal_cmd, | |
ada364e8 TH |
203 | .data_xfer = ata_pio_data_xfer, |
204 | .irq_handler = nv_nf2_interrupt, | |
205 | .irq_clear = ata_bmdma_irq_clear, | |
206 | .scr_read = nv_scr_read, | |
207 | .scr_write = nv_scr_write, | |
208 | .port_start = ata_port_start, | |
209 | .port_stop = ata_port_stop, | |
210 | .host_stop = ata_pci_host_stop, | |
211 | }; | |
212 | ||
213 | static const struct ata_port_operations nv_ck804_ops = { | |
214 | .port_disable = ata_port_disable, | |
215 | .tf_load = ata_tf_load, | |
216 | .tf_read = ata_tf_read, | |
217 | .exec_command = ata_exec_command, | |
218 | .check_status = ata_check_status, | |
219 | .dev_select = ata_std_dev_select, | |
ada364e8 TH |
220 | .bmdma_setup = ata_bmdma_setup, |
221 | .bmdma_start = ata_bmdma_start, | |
222 | .bmdma_stop = ata_bmdma_stop, | |
223 | .bmdma_status = ata_bmdma_status, | |
224 | .qc_prep = ata_qc_prep, | |
225 | .qc_issue = ata_qc_issue_prot, | |
39f87582 TH |
226 | .freeze = nv_ck804_freeze, |
227 | .thaw = nv_ck804_thaw, | |
228 | .error_handler = nv_error_handler, | |
229 | .post_internal_cmd = ata_bmdma_post_internal_cmd, | |
ada364e8 TH |
230 | .data_xfer = ata_pio_data_xfer, |
231 | .irq_handler = nv_ck804_interrupt, | |
232 | .irq_clear = ata_bmdma_irq_clear, | |
233 | .scr_read = nv_scr_read, | |
234 | .scr_write = nv_scr_write, | |
235 | .port_start = ata_port_start, | |
236 | .port_stop = ata_port_stop, | |
237 | .host_stop = nv_ck804_host_stop, | |
238 | }; | |
239 | ||
ada364e8 TH |
240 | static struct ata_port_info nv_port_info[] = { |
241 | /* generic */ | |
242 | { | |
243 | .sht = &nv_sht, | |
cca3974e | 244 | .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY, |
ada364e8 TH |
245 | .pio_mask = NV_PIO_MASK, |
246 | .mwdma_mask = NV_MWDMA_MASK, | |
247 | .udma_mask = NV_UDMA_MASK, | |
248 | .port_ops = &nv_generic_ops, | |
249 | }, | |
250 | /* nforce2/3 */ | |
251 | { | |
252 | .sht = &nv_sht, | |
cca3974e | 253 | .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY, |
ada364e8 TH |
254 | .pio_mask = NV_PIO_MASK, |
255 | .mwdma_mask = NV_MWDMA_MASK, | |
256 | .udma_mask = NV_UDMA_MASK, | |
257 | .port_ops = &nv_nf2_ops, | |
258 | }, | |
259 | /* ck804 */ | |
260 | { | |
261 | .sht = &nv_sht, | |
cca3974e | 262 | .flags = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY, |
ada364e8 TH |
263 | .pio_mask = NV_PIO_MASK, |
264 | .mwdma_mask = NV_MWDMA_MASK, | |
265 | .udma_mask = NV_UDMA_MASK, | |
266 | .port_ops = &nv_ck804_ops, | |
267 | }, | |
1da177e4 LT |
268 | }; |
269 | ||
270 | MODULE_AUTHOR("NVIDIA"); | |
271 | MODULE_DESCRIPTION("low-level driver for NVIDIA nForce SATA controller"); | |
272 | MODULE_LICENSE("GPL"); | |
273 | MODULE_DEVICE_TABLE(pci, nv_pci_tbl); | |
274 | MODULE_VERSION(DRV_VERSION); | |
275 | ||
7d12e780 | 276 | static irqreturn_t nv_generic_interrupt(int irq, void *dev_instance) |
1da177e4 | 277 | { |
cca3974e | 278 | struct ata_host *host = dev_instance; |
1da177e4 LT |
279 | unsigned int i; |
280 | unsigned int handled = 0; | |
281 | unsigned long flags; | |
282 | ||
cca3974e | 283 | spin_lock_irqsave(&host->lock, flags); |
1da177e4 | 284 | |
cca3974e | 285 | for (i = 0; i < host->n_ports; i++) { |
1da177e4 LT |
286 | struct ata_port *ap; |
287 | ||
cca3974e | 288 | ap = host->ports[i]; |
c1389503 | 289 | if (ap && |
029f5468 | 290 | !(ap->flags & ATA_FLAG_DISABLED)) { |
1da177e4 LT |
291 | struct ata_queued_cmd *qc; |
292 | ||
293 | qc = ata_qc_from_tag(ap, ap->active_tag); | |
e50362ec | 294 | if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING))) |
1da177e4 | 295 | handled += ata_host_intr(ap, qc); |
b887030a AC |
296 | else |
297 | // No request pending? Clear interrupt status | |
298 | // anyway, in case there's one pending. | |
299 | ap->ops->check_status(ap); | |
1da177e4 LT |
300 | } |
301 | ||
302 | } | |
303 | ||
cca3974e | 304 | spin_unlock_irqrestore(&host->lock, flags); |
1da177e4 LT |
305 | |
306 | return IRQ_RETVAL(handled); | |
307 | } | |
308 | ||
ada364e8 TH |
309 | static int nv_host_intr(struct ata_port *ap, u8 irq_stat) |
310 | { | |
311 | struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->active_tag); | |
312 | int handled; | |
313 | ||
5a44efff TH |
314 | /* freeze if hotplugged */ |
315 | if (unlikely(irq_stat & (NV_INT_ADDED | NV_INT_REMOVED))) { | |
316 | ata_port_freeze(ap); | |
317 | return 1; | |
318 | } | |
319 | ||
ada364e8 TH |
320 | /* bail out if not our interrupt */ |
321 | if (!(irq_stat & NV_INT_DEV)) | |
322 | return 0; | |
323 | ||
324 | /* DEV interrupt w/ no active qc? */ | |
325 | if (unlikely(!qc || (qc->tf.flags & ATA_TFLAG_POLLING))) { | |
326 | ata_check_status(ap); | |
327 | return 1; | |
328 | } | |
329 | ||
330 | /* handle interrupt */ | |
331 | handled = ata_host_intr(ap, qc); | |
332 | if (unlikely(!handled)) { | |
333 | /* spurious, clear it */ | |
334 | ata_check_status(ap); | |
335 | } | |
336 | ||
337 | return 1; | |
338 | } | |
339 | ||
cca3974e | 340 | static irqreturn_t nv_do_interrupt(struct ata_host *host, u8 irq_stat) |
ada364e8 TH |
341 | { |
342 | int i, handled = 0; | |
343 | ||
cca3974e JG |
344 | for (i = 0; i < host->n_ports; i++) { |
345 | struct ata_port *ap = host->ports[i]; | |
ada364e8 TH |
346 | |
347 | if (ap && !(ap->flags & ATA_FLAG_DISABLED)) | |
348 | handled += nv_host_intr(ap, irq_stat); | |
349 | ||
350 | irq_stat >>= NV_INT_PORT_SHIFT; | |
351 | } | |
352 | ||
353 | return IRQ_RETVAL(handled); | |
354 | } | |
355 | ||
7d12e780 | 356 | static irqreturn_t nv_nf2_interrupt(int irq, void *dev_instance) |
ada364e8 | 357 | { |
cca3974e | 358 | struct ata_host *host = dev_instance; |
ada364e8 TH |
359 | u8 irq_stat; |
360 | irqreturn_t ret; | |
361 | ||
cca3974e JG |
362 | spin_lock(&host->lock); |
363 | irq_stat = inb(host->ports[0]->ioaddr.scr_addr + NV_INT_STATUS); | |
364 | ret = nv_do_interrupt(host, irq_stat); | |
365 | spin_unlock(&host->lock); | |
ada364e8 TH |
366 | |
367 | return ret; | |
368 | } | |
369 | ||
7d12e780 | 370 | static irqreturn_t nv_ck804_interrupt(int irq, void *dev_instance) |
ada364e8 | 371 | { |
cca3974e | 372 | struct ata_host *host = dev_instance; |
ada364e8 TH |
373 | u8 irq_stat; |
374 | irqreturn_t ret; | |
375 | ||
cca3974e JG |
376 | spin_lock(&host->lock); |
377 | irq_stat = readb(host->mmio_base + NV_INT_STATUS_CK804); | |
378 | ret = nv_do_interrupt(host, irq_stat); | |
379 | spin_unlock(&host->lock); | |
ada364e8 TH |
380 | |
381 | return ret; | |
382 | } | |
383 | ||
1da177e4 LT |
384 | static u32 nv_scr_read (struct ata_port *ap, unsigned int sc_reg) |
385 | { | |
1da177e4 LT |
386 | if (sc_reg > SCR_CONTROL) |
387 | return 0xffffffffU; | |
388 | ||
02cbd926 | 389 | return ioread32((void __iomem *)ap->ioaddr.scr_addr + (sc_reg * 4)); |
1da177e4 LT |
390 | } |
391 | ||
392 | static void nv_scr_write (struct ata_port *ap, unsigned int sc_reg, u32 val) | |
393 | { | |
1da177e4 LT |
394 | if (sc_reg > SCR_CONTROL) |
395 | return; | |
396 | ||
02cbd926 | 397 | iowrite32(val, (void __iomem *)ap->ioaddr.scr_addr + (sc_reg * 4)); |
1da177e4 LT |
398 | } |
399 | ||
39f87582 TH |
400 | static void nv_nf2_freeze(struct ata_port *ap) |
401 | { | |
cca3974e | 402 | unsigned long scr_addr = ap->host->ports[0]->ioaddr.scr_addr; |
39f87582 TH |
403 | int shift = ap->port_no * NV_INT_PORT_SHIFT; |
404 | u8 mask; | |
405 | ||
406 | mask = inb(scr_addr + NV_INT_ENABLE); | |
407 | mask &= ~(NV_INT_ALL << shift); | |
408 | outb(mask, scr_addr + NV_INT_ENABLE); | |
409 | } | |
410 | ||
411 | static void nv_nf2_thaw(struct ata_port *ap) | |
412 | { | |
cca3974e | 413 | unsigned long scr_addr = ap->host->ports[0]->ioaddr.scr_addr; |
39f87582 TH |
414 | int shift = ap->port_no * NV_INT_PORT_SHIFT; |
415 | u8 mask; | |
416 | ||
417 | outb(NV_INT_ALL << shift, scr_addr + NV_INT_STATUS); | |
418 | ||
419 | mask = inb(scr_addr + NV_INT_ENABLE); | |
420 | mask |= (NV_INT_MASK << shift); | |
421 | outb(mask, scr_addr + NV_INT_ENABLE); | |
422 | } | |
423 | ||
424 | static void nv_ck804_freeze(struct ata_port *ap) | |
425 | { | |
cca3974e | 426 | void __iomem *mmio_base = ap->host->mmio_base; |
39f87582 TH |
427 | int shift = ap->port_no * NV_INT_PORT_SHIFT; |
428 | u8 mask; | |
429 | ||
430 | mask = readb(mmio_base + NV_INT_ENABLE_CK804); | |
431 | mask &= ~(NV_INT_ALL << shift); | |
432 | writeb(mask, mmio_base + NV_INT_ENABLE_CK804); | |
433 | } | |
434 | ||
435 | static void nv_ck804_thaw(struct ata_port *ap) | |
436 | { | |
cca3974e | 437 | void __iomem *mmio_base = ap->host->mmio_base; |
39f87582 TH |
438 | int shift = ap->port_no * NV_INT_PORT_SHIFT; |
439 | u8 mask; | |
440 | ||
441 | writeb(NV_INT_ALL << shift, mmio_base + NV_INT_STATUS_CK804); | |
442 | ||
443 | mask = readb(mmio_base + NV_INT_ENABLE_CK804); | |
444 | mask |= (NV_INT_MASK << shift); | |
445 | writeb(mask, mmio_base + NV_INT_ENABLE_CK804); | |
446 | } | |
447 | ||
448 | static int nv_hardreset(struct ata_port *ap, unsigned int *class) | |
449 | { | |
450 | unsigned int dummy; | |
451 | ||
452 | /* SATA hardreset fails to retrieve proper device signature on | |
453 | * some controllers. Don't classify on hardreset. For more | |
454 | * info, see http://bugme.osdl.org/show_bug.cgi?id=3352 | |
455 | */ | |
456 | return sata_std_hardreset(ap, &dummy); | |
457 | } | |
458 | ||
459 | static void nv_error_handler(struct ata_port *ap) | |
460 | { | |
461 | ata_bmdma_drive_eh(ap, ata_std_prereset, ata_std_softreset, | |
462 | nv_hardreset, ata_std_postreset); | |
463 | } | |
464 | ||
1da177e4 LT |
465 | static int nv_init_one (struct pci_dev *pdev, const struct pci_device_id *ent) |
466 | { | |
467 | static int printed_version = 0; | |
29da9f6d | 468 | struct ata_port_info *ppi[2]; |
1da177e4 LT |
469 | struct ata_probe_ent *probe_ent; |
470 | int pci_dev_busy = 0; | |
471 | int rc; | |
472 | u32 bar; | |
02cbd926 | 473 | unsigned long base; |
1da177e4 LT |
474 | |
475 | // Make sure this is a SATA controller by counting the number of bars | |
476 | // (NVIDIA SATA controllers will always have six bars). Otherwise, | |
477 | // it's an IDE controller and we ignore it. | |
478 | for (bar=0; bar<6; bar++) | |
479 | if (pci_resource_start(pdev, bar) == 0) | |
480 | return -ENODEV; | |
481 | ||
482 | if (!printed_version++) | |
a9524a76 | 483 | dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n"); |
1da177e4 LT |
484 | |
485 | rc = pci_enable_device(pdev); | |
486 | if (rc) | |
487 | goto err_out; | |
488 | ||
489 | rc = pci_request_regions(pdev, DRV_NAME); | |
490 | if (rc) { | |
491 | pci_dev_busy = 1; | |
492 | goto err_out_disable; | |
493 | } | |
494 | ||
495 | rc = pci_set_dma_mask(pdev, ATA_DMA_MASK); | |
496 | if (rc) | |
497 | goto err_out_regions; | |
498 | rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK); | |
499 | if (rc) | |
500 | goto err_out_regions; | |
501 | ||
502 | rc = -ENOMEM; | |
503 | ||
29da9f6d JG |
504 | ppi[0] = ppi[1] = &nv_port_info[ent->driver_data]; |
505 | probe_ent = ata_pci_init_native_mode(pdev, ppi, ATA_PORT_PRIMARY | ATA_PORT_SECONDARY); | |
1da177e4 LT |
506 | if (!probe_ent) |
507 | goto err_out_regions; | |
508 | ||
02cbd926 JG |
509 | probe_ent->mmio_base = pci_iomap(pdev, 5, 0); |
510 | if (!probe_ent->mmio_base) { | |
511 | rc = -EIO; | |
e6faf082 | 512 | goto err_out_free_ent; |
02cbd926 | 513 | } |
1da177e4 | 514 | |
02cbd926 | 515 | base = (unsigned long)probe_ent->mmio_base; |
1da177e4 | 516 | |
02cbd926 JG |
517 | probe_ent->port[0].scr_addr = base + NV_PORT0_SCR_REG_OFFSET; |
518 | probe_ent->port[1].scr_addr = base + NV_PORT1_SCR_REG_OFFSET; | |
1da177e4 | 519 | |
ada364e8 TH |
520 | /* enable SATA space for CK804 */ |
521 | if (ent->driver_data == CK804) { | |
522 | u8 regval; | |
523 | ||
524 | pci_read_config_byte(pdev, NV_MCP_SATA_CFG_20, ®val); | |
525 | regval |= NV_MCP_SATA_CFG_20_SATA_SPACE_EN; | |
526 | pci_write_config_byte(pdev, NV_MCP_SATA_CFG_20, regval); | |
527 | } | |
528 | ||
1da177e4 LT |
529 | pci_set_master(pdev); |
530 | ||
531 | rc = ata_device_add(probe_ent); | |
532 | if (rc != NV_PORTS) | |
533 | goto err_out_iounmap; | |
534 | ||
1da177e4 LT |
535 | kfree(probe_ent); |
536 | ||
537 | return 0; | |
538 | ||
539 | err_out_iounmap: | |
02cbd926 | 540 | pci_iounmap(pdev, probe_ent->mmio_base); |
1da177e4 LT |
541 | err_out_free_ent: |
542 | kfree(probe_ent); | |
543 | err_out_regions: | |
544 | pci_release_regions(pdev); | |
545 | err_out_disable: | |
546 | if (!pci_dev_busy) | |
547 | pci_disable_device(pdev); | |
548 | err_out: | |
549 | return rc; | |
550 | } | |
551 | ||
cca3974e | 552 | static void nv_ck804_host_stop(struct ata_host *host) |
ada364e8 | 553 | { |
cca3974e | 554 | struct pci_dev *pdev = to_pci_dev(host->dev); |
ada364e8 TH |
555 | u8 regval; |
556 | ||
557 | /* disable SATA space for CK804 */ | |
558 | pci_read_config_byte(pdev, NV_MCP_SATA_CFG_20, ®val); | |
559 | regval &= ~NV_MCP_SATA_CFG_20_SATA_SPACE_EN; | |
560 | pci_write_config_byte(pdev, NV_MCP_SATA_CFG_20, regval); | |
561 | ||
cca3974e | 562 | ata_pci_host_stop(host); |
ada364e8 TH |
563 | } |
564 | ||
1da177e4 LT |
565 | static int __init nv_init(void) |
566 | { | |
b7887196 | 567 | return pci_register_driver(&nv_pci_driver); |
1da177e4 LT |
568 | } |
569 | ||
570 | static void __exit nv_exit(void) | |
571 | { | |
572 | pci_unregister_driver(&nv_pci_driver); | |
573 | } | |
574 | ||
575 | module_init(nv_init); | |
576 | module_exit(nv_exit); |