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sata_mv: cosmetic preparations for IRQ coalescing
[linux-2.6-block.git] / drivers / ata / sata_mv.c
CommitLineData
20f733e7
BR		 1/*
2 * sata_mv.c - Marvell SATA support
3 *
40f21b11 4 * Copyright 2008-2009: Marvell Corporation, all rights reserved.
8b260248 5 * Copyright 2005: EMC Corporation, all rights reserved.
e2b1be56 6 * Copyright 2005 Red Hat, Inc. All rights reserved.
20f733e7 7 *
40f21b11
ML		 8 * Originally written by Brett Russ.
9 * Extensive overhaul and enhancement by Mark Lord <mlord@pobox.com>.
10 *
20f733e7
BR		 11 * Please ALWAYS copy linux-ide@vger.kernel.org on emails.
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; version 2 of the License.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25 *
26 */
27
4a05e209 28/*
85afb934
ML		 29 * sata_mv TODO list:
30 *
85afb934
ML		 31 * --> More errata workarounds for PCI-X.
32 *
33 * --> Complete a full errata audit for all chipsets to identify others.
34 *
85afb934
ML		 35 * --> Develop a low-power-consumption strategy, and implement it.
36 *
37 * --> [Experiment, low priority] Investigate interrupt coalescing.
38 * Quite often, especially with PCI Message Signalled Interrupts (MSI),
39 * the overhead reduced by interrupt mitigation is quite often not
40 * worth the latency cost.
41 *
42 * --> [Experiment, Marvell value added] Is it possible to use target
43 * mode to cross-connect two Linux boxes with Marvell cards? If so,
44 * creating LibATA target mode support would be very interesting.
45 *
46 * Target mode, for those without docs, is the ability to directly
47 * connect two SATA ports.
48 */
4a05e209 49
20f733e7
BR		 50#include <linux/kernel.h>
51#include <linux/module.h>
52#include <linux/pci.h>
53#include <linux/init.h>
54#include <linux/blkdev.h>
55#include <linux/delay.h>
56#include <linux/interrupt.h>
8d8b6004 57#include <linux/dmapool.h>
20f733e7 58#include <linux/dma-mapping.h>
a9524a76 59#include <linux/device.h>
f351b2d6
SB		 60#include <linux/platform_device.h>
61#include <linux/ata_platform.h>
15a32632 62#include <linux/mbus.h>
c46938cc 63#include <linux/bitops.h>
20f733e7 64#include <scsi/scsi_host.h>
193515d5 65#include <scsi/scsi_cmnd.h>
6c08772e 66#include <scsi/scsi_device.h>
20f733e7 67#include <linux/libata.h>
20f733e7
BR		 68
69#define DRV_NAME "sata_mv"
da14265e 70#define DRV_VERSION "1.26"
20f733e7 71
40f21b11
ML		 72/*
73 * module options
74 */
75
76static int msi;
77#ifdef CONFIG_PCI
78module_param(msi, int, S_IRUGO);
79MODULE_PARM_DESC(msi, "Enable use of PCI MSI (0=off, 1=on)");
80#endif
81
20f733e7
BR		 82enum {
83 /* BAR's are enumerated in terms of pci_resource_start() terms */
84 MV_PRIMARY_BAR = 0, /* offset 0x10: memory space */
85 MV_IO_BAR = 2, /* offset 0x18: IO space */
86 MV_MISC_BAR = 3, /* offset 0x1c: FLASH, NVRAM, SRAM */
87
88 MV_MAJOR_REG_AREA_SZ = 0x10000, /* 64KB */
89 MV_MINOR_REG_AREA_SZ = 0x2000, /* 8KB */
90
91 MV_PCI_REG_BASE = 0,
615ab953 92
20f733e7 93 MV_SATAHC0_REG_BASE = 0x20000,
8e7decdb
ML		 94 MV_FLASH_CTL_OFS = 0x1046c,
95 MV_GPIO_PORT_CTL_OFS = 0x104f0,
96 MV_RESET_CFG_OFS = 0x180d8,
20f733e7
BR		 97
98 MV_PCI_REG_SZ = MV_MAJOR_REG_AREA_SZ,
99 MV_SATAHC_REG_SZ = MV_MAJOR_REG_AREA_SZ,
100 MV_SATAHC_ARBTR_REG_SZ = MV_MINOR_REG_AREA_SZ, /* arbiter */
101 MV_PORT_REG_SZ = MV_MINOR_REG_AREA_SZ,
102
31961943
BR		 103 MV_MAX_Q_DEPTH = 32,
104 MV_MAX_Q_DEPTH_MASK = MV_MAX_Q_DEPTH - 1,
105
106 /* CRQB needs alignment on a 1KB boundary. Size == 1KB
107 * CRPB needs alignment on a 256B boundary. Size == 256B
31961943
BR		 108 * ePRD (SG) entries need alignment on a 16B boundary. Size == 16B
109 */
110 MV_CRQB_Q_SZ = (32 * MV_MAX_Q_DEPTH),
111 MV_CRPB_Q_SZ = (8 * MV_MAX_Q_DEPTH),
da2fa9ba 112 MV_MAX_SG_CT = 256,
31961943 113 MV_SG_TBL_SZ = (16 * MV_MAX_SG_CT),
31961943 114
352fab70 115 /* Determine hc from 0-7 port: hc = port >> MV_PORT_HC_SHIFT */
20f733e7 116 MV_PORT_HC_SHIFT = 2,
352fab70
ML		 117 MV_PORTS_PER_HC = (1 << MV_PORT_HC_SHIFT), /* 4 */
118 /* Determine hc port from 0-7 port: hardport = port & MV_PORT_MASK */
119 MV_PORT_MASK = (MV_PORTS_PER_HC - 1), /* 3 */
20f733e7
BR		 120
121 /* Host Flags */
122 MV_FLAG_DUAL_HC = (1 << 30), /* two SATA Host Controllers */
7bb3c529 123
c5d3e45a 124 MV_COMMON_FLAGS = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
91b1a84c 125 ATA_FLAG_MMIO | ATA_FLAG_PIO_POLLING,
ad3aef51 126
91b1a84c 127 MV_GEN_I_FLAGS = MV_COMMON_FLAGS | ATA_FLAG_NO_ATAPI,
20f733e7 128
40f21b11
ML		 129 MV_GEN_II_FLAGS = MV_COMMON_FLAGS | ATA_FLAG_NCQ |
130 ATA_FLAG_PMP | ATA_FLAG_ACPI_SATA,
91b1a84c
ML		 131
132 MV_GEN_IIE_FLAGS = MV_GEN_II_FLAGS | ATA_FLAG_AN,
ad3aef51 133
31961943
BR		 134 CRQB_FLAG_READ = (1 << 0),
135 CRQB_TAG_SHIFT = 1,
c5d3e45a 136 CRQB_IOID_SHIFT = 6, /* CRQB Gen-II/IIE IO Id shift */
e12bef50 137 CRQB_PMP_SHIFT = 12, /* CRQB Gen-II/IIE PMP shift */
c5d3e45a 138 CRQB_HOSTQ_SHIFT = 17, /* CRQB Gen-II/IIE HostQueTag shift */
31961943
BR		 139 CRQB_CMD_ADDR_SHIFT = 8,
140 CRQB_CMD_CS = (0x2 << 11),
141 CRQB_CMD_LAST = (1 << 15),
142
143 CRPB_FLAG_STATUS_SHIFT = 8,
c5d3e45a
JG		 144 CRPB_IOID_SHIFT_6 = 5, /* CRPB Gen-II IO Id shift */
145 CRPB_IOID_SHIFT_7 = 7, /* CRPB Gen-IIE IO Id shift */
31961943
BR		 146
147 EPRD_FLAG_END_OF_TBL = (1 << 31),
148
20f733e7
BR		 149 /* PCI interface registers */
150
31961943 151 PCI_COMMAND_OFS = 0xc00,
8e7decdb 152 PCI_COMMAND_MRDTRIG = (1 << 7), /* PCI Master Read Trigger */
31961943 153
20f733e7
BR		 154 PCI_MAIN_CMD_STS_OFS = 0xd30,
155 STOP_PCI_MASTER = (1 << 2),
156 PCI_MASTER_EMPTY = (1 << 3),
157 GLOB_SFT_RST = (1 << 4),
158
8e7decdb
ML		 159 MV_PCI_MODE_OFS = 0xd00,
160 MV_PCI_MODE_MASK = 0x30,
161
522479fb
JG		 162 MV_PCI_EXP_ROM_BAR_CTL = 0xd2c,
163 MV_PCI_DISC_TIMER = 0xd04,
164 MV_PCI_MSI_TRIGGER = 0xc38,
165 MV_PCI_SERR_MASK = 0xc28,
8e7decdb 166 MV_PCI_XBAR_TMOUT_OFS = 0x1d04,
522479fb
JG		 167 MV_PCI_ERR_LOW_ADDRESS = 0x1d40,
168 MV_PCI_ERR_HIGH_ADDRESS = 0x1d44,
169 MV_PCI_ERR_ATTRIBUTE = 0x1d48,
170 MV_PCI_ERR_COMMAND = 0x1d50,
171
02a121da
ML		 172 PCI_IRQ_CAUSE_OFS = 0x1d58,
173 PCI_IRQ_MASK_OFS = 0x1d5c,
20f733e7
BR		 174 PCI_UNMASK_ALL_IRQS = 0x7fffff, /* bits 22-0 */
175
02a121da
ML		 176 PCIE_IRQ_CAUSE_OFS = 0x1900,
177 PCIE_IRQ_MASK_OFS = 0x1910,
646a4da5 178 PCIE_UNMASK_ALL_IRQS = 0x40a, /* assorted bits */
02a121da 179
7368f919
ML		 180 /* Host Controller Main Interrupt Cause/Mask registers (1 per-chip) */
181 PCI_HC_MAIN_IRQ_CAUSE_OFS = 0x1d60,
182 PCI_HC_MAIN_IRQ_MASK_OFS = 0x1d64,
183 SOC_HC_MAIN_IRQ_CAUSE_OFS = 0x20020,
184 SOC_HC_MAIN_IRQ_MASK_OFS = 0x20024,
40f21b11
ML		 185 ERR_IRQ = (1 << 0), /* shift by (2 * port #) */
186 DONE_IRQ = (1 << 1), /* shift by (2 * port #) */
20f733e7
BR		 187 HC0_IRQ_PEND = 0x1ff, /* bits 0-8 = HC0's ports */
188 HC_SHIFT = 9, /* bits 9-17 = HC1's ports */
189 PCI_ERR = (1 << 18),
40f21b11
ML		 190 TRAN_COAL_LO_DONE = (1 << 19), /* transaction coalescing */
191 TRAN_COAL_HI_DONE = (1 << 20), /* transaction coalescing */
192 PORTS_0_3_COAL_DONE = (1 << 8), /* HC0 IRQ coalescing */
193 PORTS_4_7_COAL_DONE = (1 << 17), /* HC1 IRQ coalescing */
194 ALL_PORTS_COAL_DONE = (1 << 21), /* GEN_II(E) IRQ coalescing */
20f733e7
BR		 195 GPIO_INT = (1 << 22),
196 SELF_INT = (1 << 23),
197 TWSI_INT = (1 << 24),
198 HC_MAIN_RSVD = (0x7f << 25), /* bits 31-25 */
fb621e2f 199 HC_MAIN_RSVD_5 = (0x1fff << 19), /* bits 31-19 */
e12bef50 200 HC_MAIN_RSVD_SOC = (0x3fffffb << 6), /* bits 31-9, 7-6 */
20f733e7
BR		 201
202 /* SATAHC registers */
203 HC_CFG_OFS = 0,
204
205 HC_IRQ_CAUSE_OFS = 0x14,
352fab70
ML		 206 DMA_IRQ = (1 << 0), /* shift by port # */
207 HC_COAL_IRQ = (1 << 4), /* IRQ coalescing */
20f733e7
BR		 208 DEV_IRQ = (1 << 8), /* shift by port # */
209
210 /* Shadow block registers */
31961943
BR		 211 SHD_BLK_OFS = 0x100,
212 SHD_CTL_AST_OFS = 0x20, /* ofs from SHD_BLK_OFS */
20f733e7
BR		 213
214 /* SATA registers */
215 SATA_STATUS_OFS = 0x300, /* ctrl, err regs follow status */
216 SATA_ACTIVE_OFS = 0x350,
0c58912e 217 SATA_FIS_IRQ_CAUSE_OFS = 0x364,
c443c500 218 SATA_FIS_IRQ_AN = (1 << 9), /* async notification */
17c5aab5 219
e12bef50 220 LTMODE_OFS = 0x30c,
17c5aab5
ML		 221 LTMODE_BIT8 = (1 << 8), /* unknown, but necessary */
222
47c2b677 223 PHY_MODE3 = 0x310,
bca1c4eb 224 PHY_MODE4 = 0x314,
ba069e37
ML		 225 PHY_MODE4_CFG_MASK = 0x00000003, /* phy internal config field */
226 PHY_MODE4_CFG_VALUE = 0x00000001, /* phy internal config field */
227 PHY_MODE4_RSVD_ZEROS = 0x5de3fffa, /* Gen2e always write zeros */
228 PHY_MODE4_RSVD_ONES = 0x00000005, /* Gen2e always write ones */
229
bca1c4eb 230 PHY_MODE2 = 0x330,
e12bef50 231 SATA_IFCTL_OFS = 0x344,
8e7decdb 232 SATA_TESTCTL_OFS = 0x348,
e12bef50
ML		 233 SATA_IFSTAT_OFS = 0x34c,
234 VENDOR_UNIQUE_FIS_OFS = 0x35c,
17c5aab5 235
8e7decdb
ML		 236 FISCFG_OFS = 0x360,
237 FISCFG_WAIT_DEV_ERR = (1 << 8), /* wait for host on DevErr */
238 FISCFG_SINGLE_SYNC = (1 << 16), /* SYNC on DMA activation */
17c5aab5 239
c9d39130 240 MV5_PHY_MODE = 0x74,
8e7decdb
ML		 241 MV5_LTMODE_OFS = 0x30,
242 MV5_PHY_CTL_OFS = 0x0C,
243 SATA_INTERFACE_CFG_OFS = 0x050,
bca1c4eb
JG		 244
245 MV_M2_PREAMP_MASK = 0x7e0,
20f733e7
BR		 246
247 /* Port registers */
248 EDMA_CFG_OFS = 0,
0c58912e
ML		 249 EDMA_CFG_Q_DEPTH = 0x1f, /* max device queue depth */
250 EDMA_CFG_NCQ = (1 << 5), /* for R/W FPDMA queued */
251 EDMA_CFG_NCQ_GO_ON_ERR = (1 << 14), /* continue on error */
252 EDMA_CFG_RD_BRST_EXT = (1 << 11), /* read burst 512B */
253 EDMA_CFG_WR_BUFF_LEN = (1 << 13), /* write buffer 512B */
e12bef50
ML		 254 EDMA_CFG_EDMA_FBS = (1 << 16), /* EDMA FIS-Based Switching */
255 EDMA_CFG_FBS = (1 << 26), /* FIS-Based Switching */
20f733e7
BR		 256
257 EDMA_ERR_IRQ_CAUSE_OFS = 0x8,
258 EDMA_ERR_IRQ_MASK_OFS = 0xc,
6c1153e0
JG		 259 EDMA_ERR_D_PAR = (1 << 0), /* UDMA data parity err */
260 EDMA_ERR_PRD_PAR = (1 << 1), /* UDMA PRD parity err */
261 EDMA_ERR_DEV = (1 << 2), /* device error */
262 EDMA_ERR_DEV_DCON = (1 << 3), /* device disconnect */
263 EDMA_ERR_DEV_CON = (1 << 4), /* device connected */
264 EDMA_ERR_SERR = (1 << 5), /* SError bits [WBDST] raised */
c5d3e45a
JG		 265 EDMA_ERR_SELF_DIS = (1 << 7), /* Gen II/IIE self-disable */
266 EDMA_ERR_SELF_DIS_5 = (1 << 8), /* Gen I self-disable */
6c1153e0 267 EDMA_ERR_BIST_ASYNC = (1 << 8), /* BIST FIS or Async Notify */
c5d3e45a 268 EDMA_ERR_TRANS_IRQ_7 = (1 << 8), /* Gen IIE transprt layer irq */
6c1153e0
JG		 269 EDMA_ERR_CRQB_PAR = (1 << 9), /* CRQB parity error */
270 EDMA_ERR_CRPB_PAR = (1 << 10), /* CRPB parity error */
271 EDMA_ERR_INTRL_PAR = (1 << 11), /* internal parity error */
272 EDMA_ERR_IORDY = (1 << 12), /* IORdy timeout */
646a4da5 273
6c1153e0 274 EDMA_ERR_LNK_CTRL_RX = (0xf << 13), /* link ctrl rx error */
646a4da5
ML		 275 EDMA_ERR_LNK_CTRL_RX_0 = (1 << 13), /* transient: CRC err */
276 EDMA_ERR_LNK_CTRL_RX_1 = (1 << 14), /* transient: FIFO err */
277 EDMA_ERR_LNK_CTRL_RX_2 = (1 << 15), /* fatal: caught SYNC */
278 EDMA_ERR_LNK_CTRL_RX_3 = (1 << 16), /* transient: FIS rx err */
279
6c1153e0 280 EDMA_ERR_LNK_DATA_RX = (0xf << 17), /* link data rx error */
646a4da5 281
6c1153e0 282 EDMA_ERR_LNK_CTRL_TX = (0x1f << 21), /* link ctrl tx error */
646a4da5
ML		 283 EDMA_ERR_LNK_CTRL_TX_0 = (1 << 21), /* transient: CRC err */
284 EDMA_ERR_LNK_CTRL_TX_1 = (1 << 22), /* transient: FIFO err */
285 EDMA_ERR_LNK_CTRL_TX_2 = (1 << 23), /* transient: caught SYNC */
286 EDMA_ERR_LNK_CTRL_TX_3 = (1 << 24), /* transient: caught DMAT */
287 EDMA_ERR_LNK_CTRL_TX_4 = (1 << 25), /* transient: FIS collision */
288
6c1153e0 289 EDMA_ERR_LNK_DATA_TX = (0x1f << 26), /* link data tx error */
646a4da5 290
6c1153e0 291 EDMA_ERR_TRANS_PROTO = (1 << 31), /* transport protocol error */
c5d3e45a
JG		 292 EDMA_ERR_OVERRUN_5 = (1 << 5),
293 EDMA_ERR_UNDERRUN_5 = (1 << 6),
646a4da5
ML		 294
295 EDMA_ERR_IRQ_TRANSIENT = EDMA_ERR_LNK_CTRL_RX_0 |
296 EDMA_ERR_LNK_CTRL_RX_1 |
297 EDMA_ERR_LNK_CTRL_RX_3 |
85afb934 298 EDMA_ERR_LNK_CTRL_TX,
646a4da5 299
bdd4ddde
JG		 300 EDMA_EH_FREEZE = EDMA_ERR_D_PAR |
301 EDMA_ERR_PRD_PAR |
302 EDMA_ERR_DEV_DCON |
303 EDMA_ERR_DEV_CON |
304 EDMA_ERR_SERR |
305 EDMA_ERR_SELF_DIS |
6c1153e0 306 EDMA_ERR_CRQB_PAR |
bdd4ddde
JG		 307 EDMA_ERR_CRPB_PAR |
308 EDMA_ERR_INTRL_PAR |
309 EDMA_ERR_IORDY |
310 EDMA_ERR_LNK_CTRL_RX_2 |
311 EDMA_ERR_LNK_DATA_RX |
312 EDMA_ERR_LNK_DATA_TX |
313 EDMA_ERR_TRANS_PROTO,
e12bef50 314
bdd4ddde
JG		 315 EDMA_EH_FREEZE_5 = EDMA_ERR_D_PAR |
316 EDMA_ERR_PRD_PAR |
317 EDMA_ERR_DEV_DCON |
318 EDMA_ERR_DEV_CON |
319 EDMA_ERR_OVERRUN_5 |
320 EDMA_ERR_UNDERRUN_5 |
321 EDMA_ERR_SELF_DIS_5 |
6c1153e0 322 EDMA_ERR_CRQB_PAR |
bdd4ddde
JG		 323 EDMA_ERR_CRPB_PAR |
324 EDMA_ERR_INTRL_PAR |
325 EDMA_ERR_IORDY,
20f733e7 326
31961943
BR		 327 EDMA_REQ_Q_BASE_HI_OFS = 0x10,
328 EDMA_REQ_Q_IN_PTR_OFS = 0x14, /* also contains BASE_LO */
31961943
BR		 329
330 EDMA_REQ_Q_OUT_PTR_OFS = 0x18,
331 EDMA_REQ_Q_PTR_SHIFT = 5,
332
333 EDMA_RSP_Q_BASE_HI_OFS = 0x1c,
334 EDMA_RSP_Q_IN_PTR_OFS = 0x20,
335 EDMA_RSP_Q_OUT_PTR_OFS = 0x24, /* also contains BASE_LO */
31961943
BR		 336 EDMA_RSP_Q_PTR_SHIFT = 3,
337
0ea9e179
JG		 338 EDMA_CMD_OFS = 0x28, /* EDMA command register */
339 EDMA_EN = (1 << 0), /* enable EDMA */
340 EDMA_DS = (1 << 1), /* disable EDMA; self-negated */
8e7decdb
ML		 341 EDMA_RESET = (1 << 2), /* reset eng/trans/link/phy */
342
343 EDMA_STATUS_OFS = 0x30, /* EDMA engine status */
344 EDMA_STATUS_CACHE_EMPTY = (1 << 6), /* GenIIe command cache empty */
345 EDMA_STATUS_IDLE = (1 << 7), /* GenIIe EDMA enabled/idle */
20f733e7 346
8e7decdb
ML		 347 EDMA_IORDY_TMOUT_OFS = 0x34,
348 EDMA_ARB_CFG_OFS = 0x38,
349
350 EDMA_HALTCOND_OFS = 0x60, /* GenIIe halt conditions */
c01e8a23 351 EDMA_UNKNOWN_RSVD_OFS = 0x6C, /* GenIIe unknown/reserved */
da14265e
ML		 352
353 BMDMA_CMD_OFS = 0x224, /* bmdma command register */
354 BMDMA_STATUS_OFS = 0x228, /* bmdma status register */
355 BMDMA_PRD_LOW_OFS = 0x22c, /* bmdma PRD addr 31:0 */
356 BMDMA_PRD_HIGH_OFS = 0x230, /* bmdma PRD addr 63:32 */
357
31961943
BR		 358 /* Host private flags (hp_flags) */
359 MV_HP_FLAG_MSI = (1 << 0),
47c2b677
JG		 360 MV_HP_ERRATA_50XXB0 = (1 << 1),
361 MV_HP_ERRATA_50XXB2 = (1 << 2),
362 MV_HP_ERRATA_60X1B2 = (1 << 3),
363 MV_HP_ERRATA_60X1C0 = (1 << 4),
0ea9e179
JG		 364 MV_HP_GEN_I = (1 << 6), /* Generation I: 50xx */
365 MV_HP_GEN_II = (1 << 7), /* Generation II: 60xx */
366 MV_HP_GEN_IIE = (1 << 8), /* Generation IIE: 6042/7042 */
02a121da 367 MV_HP_PCIE = (1 << 9), /* PCIe bus/regs: 7042 */
616d4a98 368 MV_HP_CUT_THROUGH = (1 << 10), /* can use EDMA cut-through */
1f398472 369 MV_HP_FLAG_SOC = (1 << 11), /* SystemOnChip, no PCI */
20f733e7 370
31961943 371 /* Port private flags (pp_flags) */
0ea9e179 372 MV_PP_FLAG_EDMA_EN = (1 << 0), /* is EDMA engine enabled? */
72109168 373 MV_PP_FLAG_NCQ_EN = (1 << 1), /* is EDMA set up for NCQ? */
00f42eab 374 MV_PP_FLAG_FBS_EN = (1 << 2), /* is EDMA set up for FBS? */
29d187bb 375 MV_PP_FLAG_DELAYED_EH = (1 << 3), /* delayed dev err handling */
d16ab3f6 376 MV_PP_FLAG_FAKE_ATA_BUSY = (1 << 4), /* ignore initial ATA_DRDY */
20f733e7
BR		 377};
378
ee9ccdf7
JG		 379#define IS_GEN_I(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_I)
380#define IS_GEN_II(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_II)
e4e7b892 381#define IS_GEN_IIE(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_IIE)
8e7decdb 382#define IS_PCIE(hpriv) ((hpriv)->hp_flags & MV_HP_PCIE)
1f398472 383#define IS_SOC(hpriv) ((hpriv)->hp_flags & MV_HP_FLAG_SOC)
bca1c4eb 384
15a32632
LB		 385#define WINDOW_CTRL(i) (0x20030 + ((i) << 4))
386#define WINDOW_BASE(i) (0x20034 + ((i) << 4))
387
095fec88 388enum {
baf14aa1
JG		 389 /* DMA boundary 0xffff is required by the s/g splitting
390 * we need on /length/ in mv_fill-sg().
391 */
392 MV_DMA_BOUNDARY = 0xffffU,
095fec88 393
0ea9e179
JG		 394 /* mask of register bits containing lower 32 bits
395 * of EDMA request queue DMA address
396 */
095fec88
JG		 397 EDMA_REQ_Q_BASE_LO_MASK = 0xfffffc00U,
398
0ea9e179 399 /* ditto, for response queue */
095fec88
JG		 400 EDMA_RSP_Q_BASE_LO_MASK = 0xffffff00U,
401};
402
522479fb
JG		 403enum chip_type {
404 chip_504x,
405 chip_508x,
406 chip_5080,
407 chip_604x,
408 chip_608x,
e4e7b892
JG		 409 chip_6042,
410 chip_7042,
f351b2d6 411 chip_soc,
522479fb
JG		 412};
413
31961943
BR		 414/* Command ReQuest Block: 32B */
415struct mv_crqb {
e1469874
ML		 416 __le32 sg_addr;
417 __le32 sg_addr_hi;
418 __le16 ctrl_flags;
419 __le16 ata_cmd[11];
31961943 420};
20f733e7 421
e4e7b892 422struct mv_crqb_iie {
e1469874
ML		 423 __le32 addr;
424 __le32 addr_hi;
425 __le32 flags;
426 __le32 len;
427 __le32 ata_cmd[4];
e4e7b892
JG		 428};
429
31961943
BR		 430/* Command ResPonse Block: 8B */
431struct mv_crpb {
e1469874
ML		 432 __le16 id;
433 __le16 flags;
434 __le32 tmstmp;
20f733e7
BR		 435};
436
31961943
BR		 437/* EDMA Physical Region Descriptor (ePRD); A.K.A. SG */
438struct mv_sg {
e1469874
ML		 439 __le32 addr;
440 __le32 flags_size;
441 __le32 addr_hi;
442 __le32 reserved;
31961943 443};
20f733e7 444
08da1759
ML		 445/*
446 * We keep a local cache of a few frequently accessed port
447 * registers here, to avoid having to read them (very slow)
448 * when switching between EDMA and non-EDMA modes.
449 */
450struct mv_cached_regs {
451 u32 fiscfg;
452 u32 ltmode;
453 u32 haltcond;
c01e8a23 454 u32 unknown_rsvd;
08da1759
ML		 455};
456
31961943
BR		 457struct mv_port_priv {
458 struct mv_crqb *crqb;
459 dma_addr_t crqb_dma;
460 struct mv_crpb *crpb;
461 dma_addr_t crpb_dma;
eb73d558
ML		 462 struct mv_sg *sg_tbl[MV_MAX_Q_DEPTH];
463 dma_addr_t sg_tbl_dma[MV_MAX_Q_DEPTH];
bdd4ddde
JG		 464
465 unsigned int req_idx;
466 unsigned int resp_idx;
467
31961943 468 u32 pp_flags;
08da1759 469 struct mv_cached_regs cached;
29d187bb 470 unsigned int delayed_eh_pmp_map;
31961943
BR		 471};
472
bca1c4eb
JG		 473struct mv_port_signal {
474 u32 amps;
475 u32 pre;
476};
477
02a121da
ML		 478struct mv_host_priv {
479 u32 hp_flags;
96e2c487 480 u32 main_irq_mask;
02a121da
ML		 481 struct mv_port_signal signal[8];
482 const struct mv_hw_ops *ops;
f351b2d6
SB		 483 int n_ports;
484 void __iomem *base;
7368f919
ML		 485 void __iomem *main_irq_cause_addr;
486 void __iomem *main_irq_mask_addr;
02a121da
ML		 487 u32 irq_cause_ofs;
488 u32 irq_mask_ofs;
489 u32 unmask_all_irqs;
da2fa9ba
ML		 490 /*
491 * These consistent DMA memory pools give us guaranteed
492 * alignment for hardware-accessed data structures,
493 * and less memory waste in accomplishing the alignment.
494 */
495 struct dma_pool *crqb_pool;
496 struct dma_pool *crpb_pool;
497 struct dma_pool *sg_tbl_pool;
02a121da
ML		 498};
499
47c2b677 500struct mv_hw_ops {
2a47ce06
JG		 501 void (*phy_errata)(struct mv_host_priv *hpriv, void __iomem *mmio,
502 unsigned int port);
47c2b677
JG		 503 void (*enable_leds)(struct mv_host_priv *hpriv, void __iomem *mmio);
504 void (*read_preamp)(struct mv_host_priv *hpriv, int idx,
505 void __iomem *mmio);
c9d39130
JG		 506 int (*reset_hc)(struct mv_host_priv *hpriv, void __iomem *mmio,
507 unsigned int n_hc);
522479fb 508 void (*reset_flash)(struct mv_host_priv *hpriv, void __iomem *mmio);
7bb3c529 509 void (*reset_bus)(struct ata_host *host, void __iomem *mmio);
47c2b677
JG		 510};
511
82ef04fb
TH		 512static int mv_scr_read(struct ata_link *link, unsigned int sc_reg_in, u32 *val);
513static int mv_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val);
514static int mv5_scr_read(struct ata_link *link, unsigned int sc_reg_in, u32 *val);
515static int mv5_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val);
31961943
BR		 516static int mv_port_start(struct ata_port *ap);
517static void mv_port_stop(struct ata_port *ap);
3e4a1391 518static int mv_qc_defer(struct ata_queued_cmd *qc);
31961943 519static void mv_qc_prep(struct ata_queued_cmd *qc);
e4e7b892 520static void mv_qc_prep_iie(struct ata_queued_cmd *qc);
9a3d9eb0 521static unsigned int mv_qc_issue(struct ata_queued_cmd *qc);
a1efdaba
TH		 522static int mv_hardreset(struct ata_link *link, unsigned int *class,
523 unsigned long deadline);
bdd4ddde
JG		 524static void mv_eh_freeze(struct ata_port *ap);
525static void mv_eh_thaw(struct ata_port *ap);
f273827e 526static void mv6_dev_config(struct ata_device *dev);
20f733e7 527
2a47ce06
JG		 528static void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
529 unsigned int port);
47c2b677
JG		 530static void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio);
531static void mv5_read_preamp(struct mv_host_priv *hpriv, int idx,
532 void __iomem *mmio);
c9d39130
JG		 533static int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
534 unsigned int n_hc);
522479fb 535static void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio);
7bb3c529 536static void mv5_reset_bus(struct ata_host *host, void __iomem *mmio);
47c2b677 537
2a47ce06
JG		 538static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
539 unsigned int port);
47c2b677
JG		 540static void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio);
541static void mv6_read_preamp(struct mv_host_priv *hpriv, int idx,
542 void __iomem *mmio);
c9d39130
JG		 543static int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
544 unsigned int n_hc);
522479fb 545static void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio);
f351b2d6
SB		 546static void mv_soc_enable_leds(struct mv_host_priv *hpriv,
547 void __iomem *mmio);
548static void mv_soc_read_preamp(struct mv_host_priv *hpriv, int idx,
549 void __iomem *mmio);
550static int mv_soc_reset_hc(struct mv_host_priv *hpriv,
551 void __iomem *mmio, unsigned int n_hc);
552static void mv_soc_reset_flash(struct mv_host_priv *hpriv,
553 void __iomem *mmio);
554static void mv_soc_reset_bus(struct ata_host *host, void __iomem *mmio);
7bb3c529 555static void mv_reset_pci_bus(struct ata_host *host, void __iomem *mmio);
e12bef50 556static void mv_reset_channel(struct mv_host_priv *hpriv, void __iomem *mmio,
c9d39130 557 unsigned int port_no);
e12bef50 558static int mv_stop_edma(struct ata_port *ap);
b562468c 559static int mv_stop_edma_engine(void __iomem *port_mmio);
00b81235 560static void mv_edma_cfg(struct ata_port *ap, int want_ncq, int want_edma);
47c2b677 561
e49856d8
ML		 562static void mv_pmp_select(struct ata_port *ap, int pmp);
563static int mv_pmp_hardreset(struct ata_link *link, unsigned int *class,
564 unsigned long deadline);
565static int mv_softreset(struct ata_link *link, unsigned int *class,
566 unsigned long deadline);
29d187bb 567static void mv_pmp_error_handler(struct ata_port *ap);
4c299ca3
ML		 568static void mv_process_crpb_entries(struct ata_port *ap,
569 struct mv_port_priv *pp);
47c2b677 570
da14265e
ML		 571static void mv_sff_irq_clear(struct ata_port *ap);
572static int mv_check_atapi_dma(struct ata_queued_cmd *qc);
573static void mv_bmdma_setup(struct ata_queued_cmd *qc);
574static void mv_bmdma_start(struct ata_queued_cmd *qc);
575static void mv_bmdma_stop(struct ata_queued_cmd *qc);
576static u8 mv_bmdma_status(struct ata_port *ap);
d16ab3f6 577static u8 mv_sff_check_status(struct ata_port *ap);
da14265e 578
eb73d558
ML		 579/* .sg_tablesize is (MV_MAX_SG_CT / 2) in the structures below
580 * because we have to allow room for worst case splitting of
581 * PRDs for 64K boundaries in mv_fill_sg().
582 */
c5d3e45a 583static struct scsi_host_template mv5_sht = {
68d1d07b 584 ATA_BASE_SHT(DRV_NAME),
baf14aa1 585 .sg_tablesize = MV_MAX_SG_CT / 2,
c5d3e45a 586 .dma_boundary = MV_DMA_BOUNDARY,
c5d3e45a
JG		 587};
588
589static struct scsi_host_template mv6_sht = {
68d1d07b 590 ATA_NCQ_SHT(DRV_NAME),
138bfdd0 591 .can_queue = MV_MAX_Q_DEPTH - 1,
baf14aa1 592 .sg_tablesize = MV_MAX_SG_CT / 2,
20f733e7 593 .dma_boundary = MV_DMA_BOUNDARY,
20f733e7
BR		 594};
595
029cfd6b
TH		 596static struct ata_port_operations mv5_ops = {
597 .inherits = &ata_sff_port_ops,
c9d39130 598
3e4a1391 599 .qc_defer = mv_qc_defer,
c9d39130
JG		 600 .qc_prep = mv_qc_prep,
601 .qc_issue = mv_qc_issue,
c9d39130 602
bdd4ddde
JG		 603 .freeze = mv_eh_freeze,
604 .thaw = mv_eh_thaw,
a1efdaba 605 .hardreset = mv_hardreset,
a1efdaba 606 .error_handler = ata_std_error_handler, /* avoid SFF EH */
029cfd6b 607 .post_internal_cmd = ATA_OP_NULL,
bdd4ddde 608
c9d39130
JG		 609 .scr_read = mv5_scr_read,
610 .scr_write = mv5_scr_write,
611
612 .port_start = mv_port_start,
613 .port_stop = mv_port_stop,
c9d39130
JG		 614};
615
029cfd6b
TH		 616static struct ata_port_operations mv6_ops = {
617 .inherits = &mv5_ops,
f273827e 618 .dev_config = mv6_dev_config,
20f733e7
BR		 619 .scr_read = mv_scr_read,
620 .scr_write = mv_scr_write,
621
e49856d8
ML		 622 .pmp_hardreset = mv_pmp_hardreset,
623 .pmp_softreset = mv_softreset,
624 .softreset = mv_softreset,
29d187bb 625 .error_handler = mv_pmp_error_handler,
da14265e 626
40f21b11 627 .sff_check_status = mv_sff_check_status,
da14265e
ML		 628 .sff_irq_clear = mv_sff_irq_clear,
629 .check_atapi_dma = mv_check_atapi_dma,
630 .bmdma_setup = mv_bmdma_setup,
631 .bmdma_start = mv_bmdma_start,
632 .bmdma_stop = mv_bmdma_stop,
633 .bmdma_status = mv_bmdma_status,
20f733e7
BR		 634};
635
029cfd6b
TH		 636static struct ata_port_operations mv_iie_ops = {
637 .inherits = &mv6_ops,
638 .dev_config = ATA_OP_NULL,
e4e7b892 639 .qc_prep = mv_qc_prep_iie,
e4e7b892
JG		 640};
641
98ac62de 642static const struct ata_port_info mv_port_info[] = {
20f733e7 643 { /* chip_504x */
91b1a84c 644 .flags = MV_GEN_I_FLAGS,
31961943 645 .pio_mask = 0x1f, /* pio0-4 */
bf6263a8 646 .udma_mask = ATA_UDMA6,
c9d39130 647 .port_ops = &mv5_ops,
20f733e7
BR		 648 },
649 { /* chip_508x */
91b1a84c 650 .flags = MV_GEN_I_FLAGS | MV_FLAG_DUAL_HC,
31961943 651 .pio_mask = 0x1f, /* pio0-4 */
bf6263a8 652 .udma_mask = ATA_UDMA6,
c9d39130 653 .port_ops = &mv5_ops,
20f733e7 654 },
47c2b677 655 { /* chip_5080 */
91b1a84c 656 .flags = MV_GEN_I_FLAGS | MV_FLAG_DUAL_HC,
47c2b677 657 .pio_mask = 0x1f, /* pio0-4 */
bf6263a8 658 .udma_mask = ATA_UDMA6,
c9d39130 659 .port_ops = &mv5_ops,
47c2b677 660 },
20f733e7 661 { /* chip_604x */
91b1a84c 662 .flags = MV_GEN_II_FLAGS,
31961943 663 .pio_mask = 0x1f, /* pio0-4 */
bf6263a8 664 .udma_mask = ATA_UDMA6,
c9d39130 665 .port_ops = &mv6_ops,
20f733e7
BR		 666 },
667 { /* chip_608x */
91b1a84c 668 .flags = MV_GEN_II_FLAGS | MV_FLAG_DUAL_HC,
31961943 669 .pio_mask = 0x1f, /* pio0-4 */
bf6263a8 670 .udma_mask = ATA_UDMA6,
c9d39130 671 .port_ops = &mv6_ops,
20f733e7 672 },
e4e7b892 673 { /* chip_6042 */
91b1a84c 674 .flags = MV_GEN_IIE_FLAGS,
e4e7b892 675 .pio_mask = 0x1f, /* pio0-4 */
bf6263a8 676 .udma_mask = ATA_UDMA6,
e4e7b892
JG		 677 .port_ops = &mv_iie_ops,
678 },
679 { /* chip_7042 */
91b1a84c 680 .flags = MV_GEN_IIE_FLAGS,
e4e7b892 681 .pio_mask = 0x1f, /* pio0-4 */
bf6263a8 682 .udma_mask = ATA_UDMA6,
e4e7b892
JG		 683 .port_ops = &mv_iie_ops,
684 },
f351b2d6 685 { /* chip_soc */
91b1a84c 686 .flags = MV_GEN_IIE_FLAGS,
17c5aab5
ML		 687 .pio_mask = 0x1f, /* pio0-4 */
688 .udma_mask = ATA_UDMA6,
689 .port_ops = &mv_iie_ops,
f351b2d6 690 },
20f733e7
BR		 691};
692
3b7d697d 693static const struct pci_device_id mv_pci_tbl[] = {
2d2744fc
JG		 694 { PCI_VDEVICE(MARVELL, 0x5040), chip_504x },
695 { PCI_VDEVICE(MARVELL, 0x5041), chip_504x },
696 { PCI_VDEVICE(MARVELL, 0x5080), chip_5080 },
697 { PCI_VDEVICE(MARVELL, 0x5081), chip_508x },
46c5784c
ML		 698 /* RocketRAID 1720/174x have different identifiers */
699 { PCI_VDEVICE(TTI, 0x1720), chip_6042 },
4462254a
ML		 700 { PCI_VDEVICE(TTI, 0x1740), chip_6042 },
701 { PCI_VDEVICE(TTI, 0x1742), chip_6042 },
2d2744fc
JG		 702
703 { PCI_VDEVICE(MARVELL, 0x6040), chip_604x },
704 { PCI_VDEVICE(MARVELL, 0x6041), chip_604x },
705 { PCI_VDEVICE(MARVELL, 0x6042), chip_6042 },
706 { PCI_VDEVICE(MARVELL, 0x6080), chip_608x },
707 { PCI_VDEVICE(MARVELL, 0x6081), chip_608x },
708
709 { PCI_VDEVICE(ADAPTEC2, 0x0241), chip_604x },
710
d9f9c6bc
FA		 711 /* Adaptec 1430SA */
712 { PCI_VDEVICE(ADAPTEC2, 0x0243), chip_7042 },
713
02a121da 714 /* Marvell 7042 support */
6a3d586d
MT		 715 { PCI_VDEVICE(MARVELL, 0x7042), chip_7042 },
716
02a121da
ML		 717 /* Highpoint RocketRAID PCIe series */
718 { PCI_VDEVICE(TTI, 0x2300), chip_7042 },
719 { PCI_VDEVICE(TTI, 0x2310), chip_7042 },
720
2d2744fc 721 { } /* terminate list */
20f733e7
BR		 722};
723
47c2b677
JG		 724static const struct mv_hw_ops mv5xxx_ops = {
725 .phy_errata = mv5_phy_errata,
726 .enable_leds = mv5_enable_leds,
727 .read_preamp = mv5_read_preamp,
728 .reset_hc = mv5_reset_hc,
522479fb
JG		 729 .reset_flash = mv5_reset_flash,
730 .reset_bus = mv5_reset_bus,
47c2b677
JG		 731};
732
733static const struct mv_hw_ops mv6xxx_ops = {
734 .phy_errata = mv6_phy_errata,
735 .enable_leds = mv6_enable_leds,
736 .read_preamp = mv6_read_preamp,
737 .reset_hc = mv6_reset_hc,
522479fb
JG		 738 .reset_flash = mv6_reset_flash,
739 .reset_bus = mv_reset_pci_bus,
47c2b677
JG		 740};
741
f351b2d6
SB		 742static const struct mv_hw_ops mv_soc_ops = {
743 .phy_errata = mv6_phy_errata,
744 .enable_leds = mv_soc_enable_leds,
745 .read_preamp = mv_soc_read_preamp,
746 .reset_hc = mv_soc_reset_hc,
747 .reset_flash = mv_soc_reset_flash,
748 .reset_bus = mv_soc_reset_bus,
749};
750
20f733e7
BR		 751/*
752 * Functions
753 */
754
755static inline void writelfl(unsigned long data, void __iomem *addr)
756{
757 writel(data, addr);
758 (void) readl(addr); /* flush to avoid PCI posted write */
759}
760
c9d39130
JG		 761static inline unsigned int mv_hc_from_port(unsigned int port)
762{
763 return port >> MV_PORT_HC_SHIFT;
764}
765
766static inline unsigned int mv_hardport_from_port(unsigned int port)
767{
768 return port & MV_PORT_MASK;
769}
770
1cfd19ae
ML		 771/*
772 * Consolidate some rather tricky bit shift calculations.
773 * This is hot-path stuff, so not a function.
774 * Simple code, with two return values, so macro rather than inline.
775 *
776 * port is the sole input, in range 0..7.
7368f919
ML		 777 * shift is one output, for use with main_irq_cause / main_irq_mask registers.
778 * hardport is the other output, in range 0..3.
1cfd19ae
ML		 779 *
780 * Note that port and hardport may be the same variable in some cases.
781 */
782#define MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport) \
783{ \
784 shift = mv_hc_from_port(port) * HC_SHIFT; \
785 hardport = mv_hardport_from_port(port); \
786 shift += hardport * 2; \
787}
788
352fab70
ML		 789static inline void __iomem *mv_hc_base(void __iomem *base, unsigned int hc)
790{
791 return (base + MV_SATAHC0_REG_BASE + (hc * MV_SATAHC_REG_SZ));
792}
793
c9d39130
JG		 794static inline void __iomem *mv_hc_base_from_port(void __iomem *base,
795 unsigned int port)
796{
797 return mv_hc_base(base, mv_hc_from_port(port));
798}
799
20f733e7
BR		 800static inline void __iomem *mv_port_base(void __iomem *base, unsigned int port)
801{
c9d39130 802 return mv_hc_base_from_port(base, port) +
8b260248 803 MV_SATAHC_ARBTR_REG_SZ +
c9d39130 804 (mv_hardport_from_port(port) * MV_PORT_REG_SZ);
20f733e7
BR		 805}
806
e12bef50
ML		 807static void __iomem *mv5_phy_base(void __iomem *mmio, unsigned int port)
808{
809 void __iomem *hc_mmio = mv_hc_base_from_port(mmio, port);
810 unsigned long ofs = (mv_hardport_from_port(port) + 1) * 0x100UL;
811
812 return hc_mmio + ofs;
813}
814
f351b2d6
SB		 815static inline void __iomem *mv_host_base(struct ata_host *host)
816{
817 struct mv_host_priv *hpriv = host->private_data;
818 return hpriv->base;
819}
820
20f733e7
BR		 821static inline void __iomem *mv_ap_base(struct ata_port *ap)
822{
f351b2d6 823 return mv_port_base(mv_host_base(ap->host), ap->port_no);
20f733e7
BR		 824}
825
cca3974e 826static inline int mv_get_hc_count(unsigned long port_flags)
31961943 827{
cca3974e 828 return ((port_flags & MV_FLAG_DUAL_HC) ? 2 : 1);
31961943
BR		 829}
830
08da1759
ML		 831/**
832 * mv_save_cached_regs - (re-)initialize cached port registers
833 * @ap: the port whose registers we are caching
834 *
835 * Initialize the local cache of port registers,
836 * so that reading them over and over again can
837 * be avoided on the hotter paths of this driver.
838 * This saves a few microseconds each time we switch
839 * to/from EDMA mode to perform (eg.) a drive cache flush.
840 */
841static void mv_save_cached_regs(struct ata_port *ap)
842{
843 void __iomem *port_mmio = mv_ap_base(ap);
844 struct mv_port_priv *pp = ap->private_data;
845
846 pp->cached.fiscfg = readl(port_mmio + FISCFG_OFS);
847 pp->cached.ltmode = readl(port_mmio + LTMODE_OFS);
848 pp->cached.haltcond = readl(port_mmio + EDMA_HALTCOND_OFS);
c01e8a23 849 pp->cached.unknown_rsvd = readl(port_mmio + EDMA_UNKNOWN_RSVD_OFS);
08da1759
ML		 850}
851
852/**
853 * mv_write_cached_reg - write to a cached port register
854 * @addr: hardware address of the register
855 * @old: pointer to cached value of the register
856 * @new: new value for the register
857 *
858 * Write a new value to a cached register,
859 * but only if the value is different from before.
860 */
861static inline void mv_write_cached_reg(void __iomem *addr, u32 *old, u32 new)
862{
863 if (new != *old) {
864 *old = new;
865 writel(new, addr);
866 }
867}
868
c5d3e45a
JG		 869static void mv_set_edma_ptrs(void __iomem *port_mmio,
870 struct mv_host_priv *hpriv,
871 struct mv_port_priv *pp)
872{
bdd4ddde
JG		 873 u32 index;
874
c5d3e45a
JG		 875 /*
876 * initialize request queue
877 */
fcfb1f77
ML		 878 pp->req_idx &= MV_MAX_Q_DEPTH_MASK; /* paranoia */
879 index = pp->req_idx << EDMA_REQ_Q_PTR_SHIFT;
bdd4ddde 880
c5d3e45a
JG		 881 WARN_ON(pp->crqb_dma & 0x3ff);
882 writel((pp->crqb_dma >> 16) >> 16, port_mmio + EDMA_REQ_Q_BASE_HI_OFS);
bdd4ddde 883 writelfl((pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK) | index,
c5d3e45a 884 port_mmio + EDMA_REQ_Q_IN_PTR_OFS);
5cf73bfb 885 writelfl(index, port_mmio + EDMA_REQ_Q_OUT_PTR_OFS);
c5d3e45a
JG		 886
887 /*
888 * initialize response queue
889 */
fcfb1f77
ML		 890 pp->resp_idx &= MV_MAX_Q_DEPTH_MASK; /* paranoia */
891 index = pp->resp_idx << EDMA_RSP_Q_PTR_SHIFT;
bdd4ddde 892
c5d3e45a
JG		 893 WARN_ON(pp->crpb_dma & 0xff);
894 writel((pp->crpb_dma >> 16) >> 16, port_mmio + EDMA_RSP_Q_BASE_HI_OFS);
5cf73bfb 895 writelfl(index, port_mmio + EDMA_RSP_Q_IN_PTR_OFS);
bdd4ddde 896 writelfl((pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK) | index,
c5d3e45a 897 port_mmio + EDMA_RSP_Q_OUT_PTR_OFS);
c5d3e45a
JG		 898}
899
c4de573b
ML		 900static void mv_set_main_irq_mask(struct ata_host *host,
901 u32 disable_bits, u32 enable_bits)
902{
903 struct mv_host_priv *hpriv = host->private_data;
904 u32 old_mask, new_mask;
905
96e2c487 906 old_mask = hpriv->main_irq_mask;
c4de573b 907 new_mask = (old_mask & ~disable_bits) | enable_bits;
96e2c487
ML		 908 if (new_mask != old_mask) {
909 hpriv->main_irq_mask = new_mask;
c4de573b 910 writelfl(new_mask, hpriv->main_irq_mask_addr);
96e2c487 911 }
c4de573b
ML		 912}
913
914static void mv_enable_port_irqs(struct ata_port *ap,
915 unsigned int port_bits)
916{
917 unsigned int shift, hardport, port = ap->port_no;
918 u32 disable_bits, enable_bits;
919
920 MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport);
921
922 disable_bits = (DONE_IRQ | ERR_IRQ) << shift;
923 enable_bits = port_bits << shift;
924 mv_set_main_irq_mask(ap->host, disable_bits, enable_bits);
925}
926
00b81235
ML		 927static void mv_clear_and_enable_port_irqs(struct ata_port *ap,
928 void __iomem *port_mmio,
929 unsigned int port_irqs)
930{
931 struct mv_host_priv *hpriv = ap->host->private_data;
932 int hardport = mv_hardport_from_port(ap->port_no);
933 void __iomem *hc_mmio = mv_hc_base_from_port(
934 mv_host_base(ap->host), ap->port_no);
935 u32 hc_irq_cause;
936
937 /* clear EDMA event indicators, if any */
938 writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
939
940 /* clear pending irq events */
941 hc_irq_cause = ~((DEV_IRQ | DMA_IRQ) << hardport);
942 writelfl(hc_irq_cause, hc_mmio + HC_IRQ_CAUSE_OFS);
943
944 /* clear FIS IRQ Cause */
945 if (IS_GEN_IIE(hpriv))
946 writelfl(0, port_mmio + SATA_FIS_IRQ_CAUSE_OFS);
947
948 mv_enable_port_irqs(ap, port_irqs);
949}
950
05b308e1 951/**
00b81235 952 * mv_start_edma - Enable eDMA engine
05b308e1
BR		 953 * @base: port base address
954 * @pp: port private data
955 *
beec7dbc
TH		 956 * Verify the local cache of the eDMA state is accurate with a
957 * WARN_ON.
05b308e1
BR		 958 *
959 * LOCKING:
960 * Inherited from caller.
961 */
00b81235 962static void mv_start_edma(struct ata_port *ap, void __iomem *port_mmio,
72109168 963 struct mv_port_priv *pp, u8 protocol)
20f733e7 964{
72109168
ML		 965 int want_ncq = (protocol == ATA_PROT_NCQ);
966
967 if (pp->pp_flags & MV_PP_FLAG_EDMA_EN) {
968 int using_ncq = ((pp->pp_flags & MV_PP_FLAG_NCQ_EN) != 0);
969 if (want_ncq != using_ncq)
b562468c 970 mv_stop_edma(ap);
72109168 971 }
c5d3e45a 972 if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN)) {
0c58912e 973 struct mv_host_priv *hpriv = ap->host->private_data;
0c58912e 974
00b81235 975 mv_edma_cfg(ap, want_ncq, 1);
0c58912e 976
f630d562 977 mv_set_edma_ptrs(port_mmio, hpriv, pp);
00b81235 978 mv_clear_and_enable_port_irqs(ap, port_mmio, DONE_IRQ|ERR_IRQ);
bdd4ddde 979
f630d562 980 writelfl(EDMA_EN, port_mmio + EDMA_CMD_OFS);
afb0edd9
BR		 981 pp->pp_flags |= MV_PP_FLAG_EDMA_EN;
982 }
20f733e7
BR		 983}
984
9b2c4e0b
ML		 985static void mv_wait_for_edma_empty_idle(struct ata_port *ap)
986{
987 void __iomem *port_mmio = mv_ap_base(ap);
988 const u32 empty_idle = (EDMA_STATUS_CACHE_EMPTY | EDMA_STATUS_IDLE);
989 const int per_loop = 5, timeout = (15 * 1000 / per_loop);
990 int i;
991
992 /*
993 * Wait for the EDMA engine to finish transactions in progress.
c46938cc
ML		 994 * No idea what a good "timeout" value might be, but measurements
995 * indicate that it often requires hundreds of microseconds
996 * with two drives in-use. So we use the 15msec value above
997 * as a rough guess at what even more drives might require.
9b2c4e0b
ML		 998 */
999 for (i = 0; i < timeout; ++i) {
1000 u32 edma_stat = readl(port_mmio + EDMA_STATUS_OFS);
1001 if ((edma_stat & empty_idle) == empty_idle)
1002 break;
1003 udelay(per_loop);
1004 }
1005 /* ata_port_printk(ap, KERN_INFO, "%s: %u+ usecs\n", __func__, i); */
1006}
1007
05b308e1 1008/**
e12bef50 1009 * mv_stop_edma_engine - Disable eDMA engine
b562468c 1010 * @port_mmio: io base address
05b308e1
BR		 1011 *
1012 * LOCKING:
1013 * Inherited from caller.
1014 */
b562468c 1015static int mv_stop_edma_engine(void __iomem *port_mmio)
20f733e7 1016{
b562468c 1017 int i;
31961943 1018
b562468c
ML		 1019 /* Disable eDMA. The disable bit auto clears. */
1020 writelfl(EDMA_DS, port_mmio + EDMA_CMD_OFS);
8b260248 1021
b562468c
ML		 1022 /* Wait for the chip to confirm eDMA is off. */
1023 for (i = 10000; i > 0; i--) {
1024 u32 reg = readl(port_mmio + EDMA_CMD_OFS);
4537deb5 1025 if (!(reg & EDMA_EN))
b562468c
ML		 1026 return 0;
1027 udelay(10);
31961943 1028 }
b562468c 1029 return -EIO;
20f733e7
BR		 1030}
1031
e12bef50 1032static int mv_stop_edma(struct ata_port *ap)
0ea9e179 1033{
b562468c
ML		 1034 void __iomem *port_mmio = mv_ap_base(ap);
1035 struct mv_port_priv *pp = ap->private_data;
66e57a2c 1036 int err = 0;
0ea9e179 1037
b562468c
ML		 1038 if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN))
1039 return 0;
1040 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
9b2c4e0b 1041 mv_wait_for_edma_empty_idle(ap);
b562468c
ML		 1042 if (mv_stop_edma_engine(port_mmio)) {
1043 ata_port_printk(ap, KERN_ERR, "Unable to stop eDMA\n");
66e57a2c 1044 err = -EIO;
b562468c 1045 }
66e57a2c
ML		 1046 mv_edma_cfg(ap, 0, 0);
1047 return err;
0ea9e179
JG		 1048}
1049
8a70f8dc 1050#ifdef ATA_DEBUG
31961943 1051static void mv_dump_mem(void __iomem *start, unsigned bytes)
20f733e7 1052{
31961943
BR		 1053 int b, w;
1054 for (b = 0; b < bytes; ) {
1055 DPRINTK("%p: ", start + b);
1056 for (w = 0; b < bytes && w < 4; w++) {
2dcb407e 1057 printk("%08x ", readl(start + b));
31961943
BR		 1058 b += sizeof(u32);
1059 }
1060 printk("\n");
1061 }
31961943 1062}
8a70f8dc
JG		 1063#endif
1064
31961943
BR		 1065static void mv_dump_pci_cfg(struct pci_dev *pdev, unsigned bytes)
1066{
1067#ifdef ATA_DEBUG
1068 int b, w;
1069 u32 dw;
1070 for (b = 0; b < bytes; ) {
1071 DPRINTK("%02x: ", b);
1072 for (w = 0; b < bytes && w < 4; w++) {
2dcb407e
JG		 1073 (void) pci_read_config_dword(pdev, b, &dw);
1074 printk("%08x ", dw);
31961943
BR		 1075 b += sizeof(u32);
1076 }
1077 printk("\n");
1078 }
1079#endif
1080}
1081static void mv_dump_all_regs(void __iomem *mmio_base, int port,
1082 struct pci_dev *pdev)
1083{
1084#ifdef ATA_DEBUG
8b260248 1085 void __iomem *hc_base = mv_hc_base(mmio_base,
31961943
BR		 1086 port >> MV_PORT_HC_SHIFT);
1087 void __iomem *port_base;
1088 int start_port, num_ports, p, start_hc, num_hcs, hc;
1089
1090 if (0 > port) {
1091 start_hc = start_port = 0;
1092 num_ports = 8; /* shld be benign for 4 port devs */
1093 num_hcs = 2;
1094 } else {
1095 start_hc = port >> MV_PORT_HC_SHIFT;
1096 start_port = port;
1097 num_ports = num_hcs = 1;
1098 }
8b260248 1099 DPRINTK("All registers for port(s) %u-%u:\n", start_port,
31961943
BR		 1100 num_ports > 1 ? num_ports - 1 : start_port);
1101
1102 if (NULL != pdev) {
1103 DPRINTK("PCI config space regs:\n");
1104 mv_dump_pci_cfg(pdev, 0x68);
1105 }
1106 DPRINTK("PCI regs:\n");
1107 mv_dump_mem(mmio_base+0xc00, 0x3c);
1108 mv_dump_mem(mmio_base+0xd00, 0x34);
1109 mv_dump_mem(mmio_base+0xf00, 0x4);
1110 mv_dump_mem(mmio_base+0x1d00, 0x6c);
1111 for (hc = start_hc; hc < start_hc + num_hcs; hc++) {
d220c37e 1112 hc_base = mv_hc_base(mmio_base, hc);
31961943
BR		 1113 DPRINTK("HC regs (HC %i):\n", hc);
1114 mv_dump_mem(hc_base, 0x1c);
1115 }
1116 for (p = start_port; p < start_port + num_ports; p++) {
1117 port_base = mv_port_base(mmio_base, p);
2dcb407e 1118 DPRINTK("EDMA regs (port %i):\n", p);
31961943 1119 mv_dump_mem(port_base, 0x54);
2dcb407e 1120 DPRINTK("SATA regs (port %i):\n", p);
31961943
BR		 1121 mv_dump_mem(port_base+0x300, 0x60);
1122 }
1123#endif
20f733e7
BR		 1124}
1125
1126static unsigned int mv_scr_offset(unsigned int sc_reg_in)
1127{
1128 unsigned int ofs;
1129
1130 switch (sc_reg_in) {
1131 case SCR_STATUS:
1132 case SCR_CONTROL:
1133 case SCR_ERROR:
1134 ofs = SATA_STATUS_OFS + (sc_reg_in * sizeof(u32));
1135 break;
1136 case SCR_ACTIVE:
1137 ofs = SATA_ACTIVE_OFS; /* active is not with the others */
1138 break;
1139 default:
1140 ofs = 0xffffffffU;
1141 break;
1142 }
1143 return ofs;
1144}
1145
82ef04fb 1146static int mv_scr_read(struct ata_link *link, unsigned int sc_reg_in, u32 *val)
20f733e7
BR		 1147{
1148 unsigned int ofs = mv_scr_offset(sc_reg_in);
1149
da3dbb17 1150 if (ofs != 0xffffffffU) {
82ef04fb 1151 *val = readl(mv_ap_base(link->ap) + ofs);
da3dbb17
TH		 1152 return 0;
1153 } else
1154 return -EINVAL;
20f733e7
BR		 1155}
1156
82ef04fb 1157static int mv_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val)
20f733e7
BR		 1158{
1159 unsigned int ofs = mv_scr_offset(sc_reg_in);
1160
da3dbb17 1161 if (ofs != 0xffffffffU) {
82ef04fb 1162 writelfl(val, mv_ap_base(link->ap) + ofs);
da3dbb17
TH		 1163 return 0;
1164 } else
1165 return -EINVAL;
20f733e7
BR		 1166}
1167
f273827e
ML		 1168static void mv6_dev_config(struct ata_device *adev)
1169{
1170 /*
e49856d8
ML		 1171 * Deal with Gen-II ("mv6") hardware quirks/restrictions:
1172 *
1173 * Gen-II does not support NCQ over a port multiplier
1174 * (no FIS-based switching).
f273827e 1175 */
e49856d8 1176 if (adev->flags & ATA_DFLAG_NCQ) {
352fab70 1177 if (sata_pmp_attached(adev->link->ap)) {
e49856d8 1178 adev->flags &= ~ATA_DFLAG_NCQ;
352fab70
ML		 1179 ata_dev_printk(adev, KERN_INFO,
1180 "NCQ disabled for command-based switching\n");
352fab70 1181 }
e49856d8 1182 }
f273827e
ML		 1183}
1184
3e4a1391
ML		 1185static int mv_qc_defer(struct ata_queued_cmd *qc)
1186{
1187 struct ata_link *link = qc->dev->link;
1188 struct ata_port *ap = link->ap;
1189 struct mv_port_priv *pp = ap->private_data;
1190
29d187bb
ML		 1191 /*
1192 * Don't allow new commands if we're in a delayed EH state
1193 * for NCQ and/or FIS-based switching.
1194 */
1195 if (pp->pp_flags & MV_PP_FLAG_DELAYED_EH)
1196 return ATA_DEFER_PORT;
3e4a1391
ML		 1197 /*
1198 * If the port is completely idle, then allow the new qc.
1199 */
1200 if (ap->nr_active_links == 0)
1201 return 0;
1202
4bdee6c5
TH		 1203 /*
1204 * The port is operating in host queuing mode (EDMA) with NCQ
1205 * enabled, allow multiple NCQ commands. EDMA also allows
1206 * queueing multiple DMA commands but libata core currently
1207 * doesn't allow it.
1208 */
1209 if ((pp->pp_flags & MV_PP_FLAG_EDMA_EN) &&
1210 (pp->pp_flags & MV_PP_FLAG_NCQ_EN) && ata_is_ncq(qc->tf.protocol))
1211 return 0;
1212
3e4a1391
ML		 1213 return ATA_DEFER_PORT;
1214}
1215
08da1759 1216static void mv_config_fbs(struct ata_port *ap, int want_ncq, int want_fbs)
e49856d8 1217{
08da1759
ML		 1218 struct mv_port_priv *pp = ap->private_data;
1219 void __iomem *port_mmio;
00f42eab 1220
08da1759
ML		 1221 u32 fiscfg, *old_fiscfg = &pp->cached.fiscfg;
1222 u32 ltmode, *old_ltmode = &pp->cached.ltmode;
1223 u32 haltcond, *old_haltcond = &pp->cached.haltcond;
00f42eab 1224
08da1759
ML		 1225 ltmode = *old_ltmode & ~LTMODE_BIT8;
1226 haltcond = *old_haltcond | EDMA_ERR_DEV;
00f42eab
ML		 1227
1228 if (want_fbs) {
08da1759
ML		 1229 fiscfg = *old_fiscfg | FISCFG_SINGLE_SYNC;
1230 ltmode = *old_ltmode | LTMODE_BIT8;
4c299ca3 1231 if (want_ncq)
08da1759 1232 haltcond &= ~EDMA_ERR_DEV;
4c299ca3 1233 else
08da1759
ML		 1234 fiscfg |= FISCFG_WAIT_DEV_ERR;
1235 } else {
1236 fiscfg = *old_fiscfg & ~(FISCFG_SINGLE_SYNC | FISCFG_WAIT_DEV_ERR);
e49856d8 1237 }
00f42eab 1238
08da1759
ML		 1239 port_mmio = mv_ap_base(ap);
1240 mv_write_cached_reg(port_mmio + FISCFG_OFS, old_fiscfg, fiscfg);
1241 mv_write_cached_reg(port_mmio + LTMODE_OFS, old_ltmode, ltmode);
1242 mv_write_cached_reg(port_mmio + EDMA_HALTCOND_OFS, old_haltcond, haltcond);
f273827e
ML		 1243}
1244
dd2890f6
ML		 1245static void mv_60x1_errata_sata25(struct ata_port *ap, int want_ncq)
1246{
1247 struct mv_host_priv *hpriv = ap->host->private_data;
1248 u32 old, new;
1249
1250 /* workaround for 88SX60x1 FEr SATA#25 (part 1) */
1251 old = readl(hpriv->base + MV_GPIO_PORT_CTL_OFS);
1252 if (want_ncq)
1253 new = old | (1 << 22);
1254 else
1255 new = old & ~(1 << 22);
1256 if (new != old)
1257 writel(new, hpriv->base + MV_GPIO_PORT_CTL_OFS);
1258}
1259
c01e8a23 1260/**
40f21b11
ML		 1261 * mv_bmdma_enable - set a magic bit on GEN_IIE to allow bmdma
1262 * @ap: Port being initialized
c01e8a23
ML		 1263 *
1264 * There are two DMA modes on these chips: basic DMA, and EDMA.
1265 *
1266 * Bit-0 of the "EDMA RESERVED" register enables/disables use
1267 * of basic DMA on the GEN_IIE versions of the chips.
1268 *
1269 * This bit survives EDMA resets, and must be set for basic DMA
1270 * to function, and should be cleared when EDMA is active.
1271 */
1272static void mv_bmdma_enable_iie(struct ata_port *ap, int enable_bmdma)
1273{
1274 struct mv_port_priv *pp = ap->private_data;
1275 u32 new, *old = &pp->cached.unknown_rsvd;
1276
1277 if (enable_bmdma)
1278 new = *old | 1;
1279 else
1280 new = *old & ~1;
1281 mv_write_cached_reg(mv_ap_base(ap) + EDMA_UNKNOWN_RSVD_OFS, old, new);
1282}
1283
00b81235 1284static void mv_edma_cfg(struct ata_port *ap, int want_ncq, int want_edma)
e4e7b892 1285{
0c58912e 1286 u32 cfg;
e12bef50
ML		 1287 struct mv_port_priv *pp = ap->private_data;
1288 struct mv_host_priv *hpriv = ap->host->private_data;
1289 void __iomem *port_mmio = mv_ap_base(ap);
e4e7b892
JG		 1290
1291 /* set up non-NCQ EDMA configuration */
0c58912e 1292 cfg = EDMA_CFG_Q_DEPTH; /* always 0x1f for *all* chips */
d16ab3f6
ML		 1293 pp->pp_flags &=
1294 ~(MV_PP_FLAG_FBS_EN | MV_PP_FLAG_NCQ_EN | MV_PP_FLAG_FAKE_ATA_BUSY);
e4e7b892 1295
0c58912e 1296 if (IS_GEN_I(hpriv))
e4e7b892
JG		 1297 cfg |= (1 << 8); /* enab config burst size mask */
1298
dd2890f6 1299 else if (IS_GEN_II(hpriv)) {
e4e7b892 1300 cfg |= EDMA_CFG_RD_BRST_EXT | EDMA_CFG_WR_BUFF_LEN;
dd2890f6 1301 mv_60x1_errata_sata25(ap, want_ncq);
e4e7b892 1302
dd2890f6 1303 } else if (IS_GEN_IIE(hpriv)) {
00f42eab
ML		 1304 int want_fbs = sata_pmp_attached(ap);
1305 /*
1306 * Possible future enhancement:
1307 *
1308 * The chip can use FBS with non-NCQ, if we allow it,
1309 * But first we need to have the error handling in place
1310 * for this mode (datasheet section 7.3.15.4.2.3).
1311 * So disallow non-NCQ FBS for now.
1312 */
1313 want_fbs &= want_ncq;
1314
08da1759 1315 mv_config_fbs(ap, want_ncq, want_fbs);
00f42eab
ML		 1316
1317 if (want_fbs) {
1318 pp->pp_flags |= MV_PP_FLAG_FBS_EN;
1319 cfg |= EDMA_CFG_EDMA_FBS; /* FIS-based switching */
1320 }
1321
e728eabe 1322 cfg |= (1 << 23); /* do not mask PM field in rx'd FIS */
00b81235
ML		 1323 if (want_edma) {
1324 cfg |= (1 << 22); /* enab 4-entry host queue cache */
1325 if (!IS_SOC(hpriv))
1326 cfg |= (1 << 18); /* enab early completion */
1327 }
616d4a98
ML		 1328 if (hpriv->hp_flags & MV_HP_CUT_THROUGH)
1329 cfg |= (1 << 17); /* enab cut-thru (dis stor&forwrd) */
c01e8a23 1330 mv_bmdma_enable_iie(ap, !want_edma);
e4e7b892
JG		 1331 }
1332
72109168
ML		 1333 if (want_ncq) {
1334 cfg |= EDMA_CFG_NCQ;
1335 pp->pp_flags |= MV_PP_FLAG_NCQ_EN;
00b81235 1336 }
72109168 1337
e4e7b892
JG		 1338 writelfl(cfg, port_mmio + EDMA_CFG_OFS);
1339}
1340
da2fa9ba
ML		 1341static void mv_port_free_dma_mem(struct ata_port *ap)
1342{
1343 struct mv_host_priv *hpriv = ap->host->private_data;
1344 struct mv_port_priv *pp = ap->private_data;
eb73d558 1345 int tag;
da2fa9ba
ML		 1346
1347 if (pp->crqb) {
1348 dma_pool_free(hpriv->crqb_pool, pp->crqb, pp->crqb_dma);
1349 pp->crqb = NULL;
1350 }
1351 if (pp->crpb) {
1352 dma_pool_free(hpriv->crpb_pool, pp->crpb, pp->crpb_dma);
1353 pp->crpb = NULL;
1354 }
eb73d558
ML		 1355 /*
1356 * For GEN_I, there's no NCQ, so we have only a single sg_tbl.
1357 * For later hardware, we have one unique sg_tbl per NCQ tag.
1358 */
1359 for (tag = 0; tag < MV_MAX_Q_DEPTH; ++tag) {
1360 if (pp->sg_tbl[tag]) {
1361 if (tag == 0 || !IS_GEN_I(hpriv))
1362 dma_pool_free(hpriv->sg_tbl_pool,
1363 pp->sg_tbl[tag],
1364 pp->sg_tbl_dma[tag]);
1365 pp->sg_tbl[tag] = NULL;
1366 }
da2fa9ba
ML		 1367 }
1368}
1369
05b308e1
BR		 1370/**
1371 * mv_port_start - Port specific init/start routine.
1372 * @ap: ATA channel to manipulate
1373 *
1374 * Allocate and point to DMA memory, init port private memory,
1375 * zero indices.
1376 *
1377 * LOCKING:
1378 * Inherited from caller.
1379 */
31961943
BR		 1380static int mv_port_start(struct ata_port *ap)
1381{
cca3974e
JG		 1382 struct device *dev = ap->host->dev;
1383 struct mv_host_priv *hpriv = ap->host->private_data;
31961943 1384 struct mv_port_priv *pp;
dde20207 1385 int tag;
31961943 1386
24dc5f33 1387 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
6037d6bb 1388 if (!pp)
24dc5f33 1389 return -ENOMEM;
da2fa9ba 1390 ap->private_data = pp;
31961943 1391
da2fa9ba
ML		 1392 pp->crqb = dma_pool_alloc(hpriv->crqb_pool, GFP_KERNEL, &pp->crqb_dma);
1393 if (!pp->crqb)
1394 return -ENOMEM;
1395 memset(pp->crqb, 0, MV_CRQB_Q_SZ);
31961943 1396
da2fa9ba
ML		 1397 pp->crpb = dma_pool_alloc(hpriv->crpb_pool, GFP_KERNEL, &pp->crpb_dma);
1398 if (!pp->crpb)
1399 goto out_port_free_dma_mem;
1400 memset(pp->crpb, 0, MV_CRPB_Q_SZ);
31961943 1401
3bd0a70e
ML		 1402 /* 6041/6081 Rev. "C0" (and newer) are okay with async notify */
1403 if (hpriv->hp_flags & MV_HP_ERRATA_60X1C0)
1404 ap->flags |= ATA_FLAG_AN;
eb73d558
ML		 1405 /*
1406 * For GEN_I, there's no NCQ, so we only allocate a single sg_tbl.
1407 * For later hardware, we need one unique sg_tbl per NCQ tag.
1408 */
1409 for (tag = 0; tag < MV_MAX_Q_DEPTH; ++tag) {
1410 if (tag == 0 || !IS_GEN_I(hpriv)) {
1411 pp->sg_tbl[tag] = dma_pool_alloc(hpriv->sg_tbl_pool,
1412 GFP_KERNEL, &pp->sg_tbl_dma[tag]);
1413 if (!pp->sg_tbl[tag])
1414 goto out_port_free_dma_mem;
1415 } else {
1416 pp->sg_tbl[tag] = pp->sg_tbl[0];
1417 pp->sg_tbl_dma[tag] = pp->sg_tbl_dma[0];
1418 }
1419 }
08da1759 1420 mv_save_cached_regs(ap);
66e57a2c 1421 mv_edma_cfg(ap, 0, 0);
31961943 1422 return 0;
da2fa9ba
ML		 1423
1424out_port_free_dma_mem:
1425 mv_port_free_dma_mem(ap);
1426 return -ENOMEM;
31961943
BR		 1427}
1428
05b308e1
BR		 1429/**
1430 * mv_port_stop - Port specific cleanup/stop routine.
1431 * @ap: ATA channel to manipulate
1432 *
1433 * Stop DMA, cleanup port memory.
1434 *
1435 * LOCKING:
cca3974e 1436 * This routine uses the host lock to protect the DMA stop.
05b308e1 1437 */
31961943
BR		 1438static void mv_port_stop(struct ata_port *ap)
1439{
e12bef50 1440 mv_stop_edma(ap);
88e675e1 1441 mv_enable_port_irqs(ap, 0);
da2fa9ba 1442 mv_port_free_dma_mem(ap);
31961943
BR		 1443}
1444
05b308e1
BR		 1445/**
1446 * mv_fill_sg - Fill out the Marvell ePRD (scatter gather) entries
1447 * @qc: queued command whose SG list to source from
1448 *
1449 * Populate the SG list and mark the last entry.
1450 *
1451 * LOCKING:
1452 * Inherited from caller.
1453 */
6c08772e 1454static void mv_fill_sg(struct ata_queued_cmd *qc)
31961943
BR		 1455{
1456 struct mv_port_priv *pp = qc->ap->private_data;
972c26bd 1457 struct scatterlist *sg;
3be6cbd7 1458 struct mv_sg *mv_sg, *last_sg = NULL;
ff2aeb1e 1459 unsigned int si;
31961943 1460
eb73d558 1461 mv_sg = pp->sg_tbl[qc->tag];
ff2aeb1e 1462 for_each_sg(qc->sg, sg, qc->n_elem, si) {
d88184fb
JG		 1463 dma_addr_t addr = sg_dma_address(sg);
1464 u32 sg_len = sg_dma_len(sg);
22374677 1465
4007b493
OJ		 1466 while (sg_len) {
1467 u32 offset = addr & 0xffff;
1468 u32 len = sg_len;
22374677 1469
32cd11a6 1470 if (offset + len > 0x10000)
4007b493
OJ		 1471 len = 0x10000 - offset;
1472
1473 mv_sg->addr = cpu_to_le32(addr & 0xffffffff);
1474 mv_sg->addr_hi = cpu_to_le32((addr >> 16) >> 16);
6c08772e 1475 mv_sg->flags_size = cpu_to_le32(len & 0xffff);
32cd11a6 1476 mv_sg->reserved = 0;
4007b493
OJ		 1477
1478 sg_len -= len;
1479 addr += len;
1480
3be6cbd7 1481 last_sg = mv_sg;
4007b493 1482 mv_sg++;
4007b493 1483 }
31961943 1484 }
3be6cbd7
JG		 1485
1486 if (likely(last_sg))
1487 last_sg->flags_size |= cpu_to_le32(EPRD_FLAG_END_OF_TBL);
32cd11a6 1488 mb(); /* ensure data structure is visible to the chipset */
31961943
BR		 1489}
1490
5796d1c4 1491static void mv_crqb_pack_cmd(__le16 *cmdw, u8 data, u8 addr, unsigned last)
31961943 1492{
559eedad 1493 u16 tmp = data | (addr << CRQB_CMD_ADDR_SHIFT) | CRQB_CMD_CS |
31961943 1494 (last ? CRQB_CMD_LAST : 0);
559eedad 1495 *cmdw = cpu_to_le16(tmp);
31961943
BR		 1496}
1497
da14265e
ML		 1498/**
1499 * mv_sff_irq_clear - Clear hardware interrupt after DMA.
1500 * @ap: Port associated with this ATA transaction.
1501 *
1502 * We need this only for ATAPI bmdma transactions,
1503 * as otherwise we experience spurious interrupts
1504 * after libata-sff handles the bmdma interrupts.
1505 */
1506static void mv_sff_irq_clear(struct ata_port *ap)
1507{
1508 mv_clear_and_enable_port_irqs(ap, mv_ap_base(ap), ERR_IRQ);
1509}
1510
1511/**
1512 * mv_check_atapi_dma - Filter ATAPI cmds which are unsuitable for DMA.
1513 * @qc: queued command to check for chipset/DMA compatibility.
1514 *
1515 * The bmdma engines cannot handle speculative data sizes
1516 * (bytecount under/over flow). So only allow DMA for
1517 * data transfer commands with known data sizes.
1518 *
1519 * LOCKING:
1520 * Inherited from caller.
1521 */
1522static int mv_check_atapi_dma(struct ata_queued_cmd *qc)
1523{
1524 struct scsi_cmnd *scmd = qc->scsicmd;
1525
1526 if (scmd) {
1527 switch (scmd->cmnd[0]) {
1528 case READ_6:
1529 case READ_10:
1530 case READ_12:
1531 case WRITE_6:
1532 case WRITE_10:
1533 case WRITE_12:
1534 case GPCMD_READ_CD:
1535 case GPCMD_SEND_DVD_STRUCTURE:
1536 case GPCMD_SEND_CUE_SHEET:
1537 return 0; /* DMA is safe */
1538 }
1539 }
1540 return -EOPNOTSUPP; /* use PIO instead */
1541}
1542
1543/**
1544 * mv_bmdma_setup - Set up BMDMA transaction
1545 * @qc: queued command to prepare DMA for.
1546 *
1547 * LOCKING:
1548 * Inherited from caller.
1549 */
1550static void mv_bmdma_setup(struct ata_queued_cmd *qc)
1551{
1552 struct ata_port *ap = qc->ap;
1553 void __iomem *port_mmio = mv_ap_base(ap);
1554 struct mv_port_priv *pp = ap->private_data;
1555
1556 mv_fill_sg(qc);
1557
1558 /* clear all DMA cmd bits */
1559 writel(0, port_mmio + BMDMA_CMD_OFS);
1560
1561 /* load PRD table addr. */
1562 writel((pp->sg_tbl_dma[qc->tag] >> 16) >> 16,
1563 port_mmio + BMDMA_PRD_HIGH_OFS);
1564 writelfl(pp->sg_tbl_dma[qc->tag],
1565 port_mmio + BMDMA_PRD_LOW_OFS);
1566
1567 /* issue r/w command */
1568 ap->ops->sff_exec_command(ap, &qc->tf);
1569}
1570
1571/**
1572 * mv_bmdma_start - Start a BMDMA transaction
1573 * @qc: queued command to start DMA on.
1574 *
1575 * LOCKING:
1576 * Inherited from caller.
1577 */
1578static void mv_bmdma_start(struct ata_queued_cmd *qc)
1579{
1580 struct ata_port *ap = qc->ap;
1581 void __iomem *port_mmio = mv_ap_base(ap);
1582 unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE);
1583 u32 cmd = (rw ? 0 : ATA_DMA_WR) | ATA_DMA_START;
1584
1585 /* start host DMA transaction */
1586 writelfl(cmd, port_mmio + BMDMA_CMD_OFS);
1587}
1588
1589/**
1590 * mv_bmdma_stop - Stop BMDMA transfer
1591 * @qc: queued command to stop DMA on.
1592 *
1593 * Clears the ATA_DMA_START flag in the bmdma control register
1594 *
1595 * LOCKING:
1596 * Inherited from caller.
1597 */
1598static void mv_bmdma_stop(struct ata_queued_cmd *qc)
1599{
1600 struct ata_port *ap = qc->ap;
1601 void __iomem *port_mmio = mv_ap_base(ap);
1602 u32 cmd;
1603
1604 /* clear start/stop bit */
1605 cmd = readl(port_mmio + BMDMA_CMD_OFS);
1606 cmd &= ~ATA_DMA_START;
1607 writelfl(cmd, port_mmio + BMDMA_CMD_OFS);
1608
1609 /* one-PIO-cycle guaranteed wait, per spec, for HDMA1:0 transition */
1610 ata_sff_dma_pause(ap);
1611}
1612
1613/**
1614 * mv_bmdma_status - Read BMDMA status
1615 * @ap: port for which to retrieve DMA status.
1616 *
1617 * Read and return equivalent of the sff BMDMA status register.
1618 *
1619 * LOCKING:
1620 * Inherited from caller.
1621 */
1622static u8 mv_bmdma_status(struct ata_port *ap)
1623{
1624 void __iomem *port_mmio = mv_ap_base(ap);
1625 u32 reg, status;
1626
1627 /*
1628 * Other bits are valid only if ATA_DMA_ACTIVE==0,
1629 * and the ATA_DMA_INTR bit doesn't exist.
1630 */
1631 reg = readl(port_mmio + BMDMA_STATUS_OFS);
1632 if (reg & ATA_DMA_ACTIVE)
1633 status = ATA_DMA_ACTIVE;
1634 else
1635 status = (reg & ATA_DMA_ERR) | ATA_DMA_INTR;
1636 return status;
1637}
1638
05b308e1
BR		 1639/**
1640 * mv_qc_prep - Host specific command preparation.
1641 * @qc: queued command to prepare
1642 *
1643 * This routine simply redirects to the general purpose routine
1644 * if command is not DMA. Else, it handles prep of the CRQB
1645 * (command request block), does some sanity checking, and calls
1646 * the SG load routine.
1647 *
1648 * LOCKING:
1649 * Inherited from caller.
1650 */
31961943
BR		 1651static void mv_qc_prep(struct ata_queued_cmd *qc)
1652{
1653 struct ata_port *ap = qc->ap;
1654 struct mv_port_priv *pp = ap->private_data;
e1469874 1655 __le16 *cw;
31961943
BR		 1656 struct ata_taskfile *tf;
1657 u16 flags = 0;
a6432436 1658 unsigned in_index;
31961943 1659
138bfdd0
ML		 1660 if ((qc->tf.protocol != ATA_PROT_DMA) &&
1661 (qc->tf.protocol != ATA_PROT_NCQ))
31961943 1662 return;
20f733e7 1663
31961943
BR		 1664 /* Fill in command request block
1665 */
e4e7b892 1666 if (!(qc->tf.flags & ATA_TFLAG_WRITE))
31961943 1667 flags |= CRQB_FLAG_READ;
beec7dbc 1668 WARN_ON(MV_MAX_Q_DEPTH <= qc->tag);
31961943 1669 flags |= qc->tag << CRQB_TAG_SHIFT;
e49856d8 1670 flags |= (qc->dev->link->pmp & 0xf) << CRQB_PMP_SHIFT;
31961943 1671
bdd4ddde 1672 /* get current queue index from software */
fcfb1f77 1673 in_index = pp->req_idx;
a6432436
ML		 1674
1675 pp->crqb[in_index].sg_addr =
eb73d558 1676 cpu_to_le32(pp->sg_tbl_dma[qc->tag] & 0xffffffff);
a6432436 1677 pp->crqb[in_index].sg_addr_hi =
eb73d558 1678 cpu_to_le32((pp->sg_tbl_dma[qc->tag] >> 16) >> 16);
a6432436 1679 pp->crqb[in_index].ctrl_flags = cpu_to_le16(flags);
31961943 1680
a6432436 1681 cw = &pp->crqb[in_index].ata_cmd[0];
31961943
BR		 1682 tf = &qc->tf;
1683
1684 /* Sadly, the CRQB cannot accomodate all registers--there are
1685 * only 11 bytes...so we must pick and choose required
1686 * registers based on the command. So, we drop feature and
1687 * hob_feature for [RW] DMA commands, but they are needed for
cd12e1f7
ML		 1688 * NCQ. NCQ will drop hob_nsect, which is not needed there
1689 * (nsect is used only for the tag; feat/hob_feat hold true nsect).
20f733e7 1690 */
31961943
BR		 1691 switch (tf->command) {
1692 case ATA_CMD_READ:
1693 case ATA_CMD_READ_EXT:
1694 case ATA_CMD_WRITE:
1695 case ATA_CMD_WRITE_EXT:
c15d85c8 1696 case ATA_CMD_WRITE_FUA_EXT:
31961943
BR		 1697 mv_crqb_pack_cmd(cw++, tf->hob_nsect, ATA_REG_NSECT, 0);
1698 break;
31961943
BR		 1699 case ATA_CMD_FPDMA_READ:
1700 case ATA_CMD_FPDMA_WRITE:
8b260248 1701 mv_crqb_pack_cmd(cw++, tf->hob_feature, ATA_REG_FEATURE, 0);
31961943
BR		 1702 mv_crqb_pack_cmd(cw++, tf->feature, ATA_REG_FEATURE, 0);
1703 break;
31961943
BR		 1704 default:
1705 /* The only other commands EDMA supports in non-queued and
1706 * non-NCQ mode are: [RW] STREAM DMA and W DMA FUA EXT, none
1707 * of which are defined/used by Linux. If we get here, this
1708 * driver needs work.
1709 *
1710 * FIXME: modify libata to give qc_prep a return value and
1711 * return error here.
1712 */
1713 BUG_ON(tf->command);
1714 break;
1715 }
1716 mv_crqb_pack_cmd(cw++, tf->nsect, ATA_REG_NSECT, 0);
1717 mv_crqb_pack_cmd(cw++, tf->hob_lbal, ATA_REG_LBAL, 0);
1718 mv_crqb_pack_cmd(cw++, tf->lbal, ATA_REG_LBAL, 0);
1719 mv_crqb_pack_cmd(cw++, tf->hob_lbam, ATA_REG_LBAM, 0);
1720 mv_crqb_pack_cmd(cw++, tf->lbam, ATA_REG_LBAM, 0);
1721 mv_crqb_pack_cmd(cw++, tf->hob_lbah, ATA_REG_LBAH, 0);
1722 mv_crqb_pack_cmd(cw++, tf->lbah, ATA_REG_LBAH, 0);
1723 mv_crqb_pack_cmd(cw++, tf->device, ATA_REG_DEVICE, 0);
1724 mv_crqb_pack_cmd(cw++, tf->command, ATA_REG_CMD, 1); /* last */
1725
e4e7b892
JG		 1726 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
1727 return;
1728 mv_fill_sg(qc);
1729}
1730
1731/**
1732 * mv_qc_prep_iie - Host specific command preparation.
1733 * @qc: queued command to prepare
1734 *
1735 * This routine simply redirects to the general purpose routine
1736 * if command is not DMA. Else, it handles prep of the CRQB
1737 * (command request block), does some sanity checking, and calls
1738 * the SG load routine.
1739 *
1740 * LOCKING:
1741 * Inherited from caller.
1742 */
1743static void mv_qc_prep_iie(struct ata_queued_cmd *qc)
1744{
1745 struct ata_port *ap = qc->ap;
1746 struct mv_port_priv *pp = ap->private_data;
1747 struct mv_crqb_iie *crqb;
1748 struct ata_taskfile *tf;
a6432436 1749 unsigned in_index;
e4e7b892
JG		 1750 u32 flags = 0;
1751
138bfdd0
ML		 1752 if ((qc->tf.protocol != ATA_PROT_DMA) &&
1753 (qc->tf.protocol != ATA_PROT_NCQ))
e4e7b892
JG		 1754 return;
1755
e12bef50 1756 /* Fill in Gen IIE command request block */
e4e7b892
JG		 1757 if (!(qc->tf.flags & ATA_TFLAG_WRITE))
1758 flags |= CRQB_FLAG_READ;
1759
beec7dbc 1760 WARN_ON(MV_MAX_Q_DEPTH <= qc->tag);
e4e7b892 1761 flags |= qc->tag << CRQB_TAG_SHIFT;
8c0aeb4a 1762 flags |= qc->tag << CRQB_HOSTQ_SHIFT;
e49856d8 1763 flags |= (qc->dev->link->pmp & 0xf) << CRQB_PMP_SHIFT;
e4e7b892 1764
bdd4ddde 1765 /* get current queue index from software */
fcfb1f77 1766 in_index = pp->req_idx;
a6432436
ML		 1767
1768 crqb = (struct mv_crqb_iie *) &pp->crqb[in_index];
eb73d558
ML		 1769 crqb->addr = cpu_to_le32(pp->sg_tbl_dma[qc->tag] & 0xffffffff);
1770 crqb->addr_hi = cpu_to_le32((pp->sg_tbl_dma[qc->tag] >> 16) >> 16);
e4e7b892
JG		 1771 crqb->flags = cpu_to_le32(flags);
1772
1773 tf = &qc->tf;
1774 crqb->ata_cmd[0] = cpu_to_le32(
1775 (tf->command << 16) |
1776 (tf->feature << 24)
1777 );
1778 crqb->ata_cmd[1] = cpu_to_le32(
1779 (tf->lbal << 0) |
1780 (tf->lbam << 8) |
1781 (tf->lbah << 16) |
1782 (tf->device << 24)
1783 );
1784 crqb->ata_cmd[2] = cpu_to_le32(
1785 (tf->hob_lbal << 0) |
1786 (tf->hob_lbam << 8) |
1787 (tf->hob_lbah << 16) |
1788 (tf->hob_feature << 24)
1789 );
1790 crqb->ata_cmd[3] = cpu_to_le32(
1791 (tf->nsect << 0) |
1792 (tf->hob_nsect << 8)
1793 );
1794
1795 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
31961943 1796 return;
31961943
BR		 1797 mv_fill_sg(qc);
1798}
1799
d16ab3f6
ML		 1800/**
1801 * mv_sff_check_status - fetch device status, if valid
1802 * @ap: ATA port to fetch status from
1803 *
1804 * When using command issue via mv_qc_issue_fis(),
1805 * the initial ATA_BUSY state does not show up in the
1806 * ATA status (shadow) register. This can confuse libata!
1807 *
1808 * So we have a hook here to fake ATA_BUSY for that situation,
1809 * until the first time a BUSY, DRQ, or ERR bit is seen.
1810 *
1811 * The rest of the time, it simply returns the ATA status register.
1812 */
1813static u8 mv_sff_check_status(struct ata_port *ap)
1814{
1815 u8 stat = ioread8(ap->ioaddr.status_addr);
1816 struct mv_port_priv *pp = ap->private_data;
1817
1818 if (pp->pp_flags & MV_PP_FLAG_FAKE_ATA_BUSY) {
1819 if (stat & (ATA_BUSY | ATA_DRQ | ATA_ERR))
1820 pp->pp_flags &= ~MV_PP_FLAG_FAKE_ATA_BUSY;
1821 else
1822 stat = ATA_BUSY;
1823 }
1824 return stat;
1825}
1826
70f8b79c
ML		 1827/**
1828 * mv_send_fis - Send a FIS, using the "Vendor-Unique FIS" register
1829 * @fis: fis to be sent
1830 * @nwords: number of 32-bit words in the fis
1831 */
1832static unsigned int mv_send_fis(struct ata_port *ap, u32 *fis, int nwords)
1833{
1834 void __iomem *port_mmio = mv_ap_base(ap);
1835 u32 ifctl, old_ifctl, ifstat;
1836 int i, timeout = 200, final_word = nwords - 1;
1837
1838 /* Initiate FIS transmission mode */
1839 old_ifctl = readl(port_mmio + SATA_IFCTL_OFS);
1840 ifctl = 0x100 | (old_ifctl & 0xf);
1841 writelfl(ifctl, port_mmio + SATA_IFCTL_OFS);
1842
1843 /* Send all words of the FIS except for the final word */
1844 for (i = 0; i < final_word; ++i)
1845 writel(fis[i], port_mmio + VENDOR_UNIQUE_FIS_OFS);
1846
1847 /* Flag end-of-transmission, and then send the final word */
1848 writelfl(ifctl | 0x200, port_mmio + SATA_IFCTL_OFS);
1849 writelfl(fis[final_word], port_mmio + VENDOR_UNIQUE_FIS_OFS);
1850
1851 /*
1852 * Wait for FIS transmission to complete.
1853 * This typically takes just a single iteration.
1854 */
1855 do {
1856 ifstat = readl(port_mmio + SATA_IFSTAT_OFS);
1857 } while (!(ifstat & 0x1000) && --timeout);
1858
1859 /* Restore original port configuration */
1860 writelfl(old_ifctl, port_mmio + SATA_IFCTL_OFS);
1861
1862 /* See if it worked */
1863 if ((ifstat & 0x3000) != 0x1000) {
1864 ata_port_printk(ap, KERN_WARNING,
1865 "%s transmission error, ifstat=%08x\n",
1866 __func__, ifstat);
1867 return AC_ERR_OTHER;
1868 }
1869 return 0;
1870}
1871
1872/**
1873 * mv_qc_issue_fis - Issue a command directly as a FIS
1874 * @qc: queued command to start
1875 *
1876 * Note that the ATA shadow registers are not updated
1877 * after command issue, so the device will appear "READY"
1878 * if polled, even while it is BUSY processing the command.
1879 *
1880 * So we use a status hook to fake ATA_BUSY until the drive changes state.
1881 *
1882 * Note: we don't get updated shadow regs on *completion*
1883 * of non-data commands. So avoid sending them via this function,
1884 * as they will appear to have completed immediately.
1885 *
1886 * GEN_IIE has special registers that we could get the result tf from,
1887 * but earlier chipsets do not. For now, we ignore those registers.
1888 */
1889static unsigned int mv_qc_issue_fis(struct ata_queued_cmd *qc)
1890{
1891 struct ata_port *ap = qc->ap;
1892 struct mv_port_priv *pp = ap->private_data;
1893 struct ata_link *link = qc->dev->link;
1894 u32 fis[5];
1895 int err = 0;
1896
1897 ata_tf_to_fis(&qc->tf, link->pmp, 1, (void *)fis);
1898 err = mv_send_fis(ap, fis, sizeof(fis) / sizeof(fis[0]));
1899 if (err)
1900 return err;
1901
1902 switch (qc->tf.protocol) {
1903 case ATAPI_PROT_PIO:
1904 pp->pp_flags |= MV_PP_FLAG_FAKE_ATA_BUSY;
1905 /* fall through */
1906 case ATAPI_PROT_NODATA:
1907 ap->hsm_task_state = HSM_ST_FIRST;
1908 break;
1909 case ATA_PROT_PIO:
1910 pp->pp_flags |= MV_PP_FLAG_FAKE_ATA_BUSY;
1911 if (qc->tf.flags & ATA_TFLAG_WRITE)
1912 ap->hsm_task_state = HSM_ST_FIRST;
1913 else
1914 ap->hsm_task_state = HSM_ST;
1915 break;
1916 default:
1917 ap->hsm_task_state = HSM_ST_LAST;
1918 break;
1919 }
1920
1921 if (qc->tf.flags & ATA_TFLAG_POLLING)
1922 ata_pio_queue_task(ap, qc, 0);
1923 return 0;
1924}
1925
05b308e1
BR		 1926/**
1927 * mv_qc_issue - Initiate a command to the host
1928 * @qc: queued command to start
1929 *
1930 * This routine simply redirects to the general purpose routine
1931 * if command is not DMA. Else, it sanity checks our local
1932 * caches of the request producer/consumer indices then enables
1933 * DMA and bumps the request producer index.
1934 *
1935 * LOCKING:
1936 * Inherited from caller.
1937 */
9a3d9eb0 1938static unsigned int mv_qc_issue(struct ata_queued_cmd *qc)
31961943 1939{
f48765cc 1940 static int limit_warnings = 10;
c5d3e45a
JG		 1941 struct ata_port *ap = qc->ap;
1942 void __iomem *port_mmio = mv_ap_base(ap);
1943 struct mv_port_priv *pp = ap->private_data;
bdd4ddde 1944 u32 in_index;
42ed893d 1945 unsigned int port_irqs;
f48765cc 1946
d16ab3f6
ML		 1947 pp->pp_flags &= ~MV_PP_FLAG_FAKE_ATA_BUSY; /* paranoia */
1948
f48765cc
ML		 1949 switch (qc->tf.protocol) {
1950 case ATA_PROT_DMA:
1951 case ATA_PROT_NCQ:
1952 mv_start_edma(ap, port_mmio, pp, qc->tf.protocol);
1953 pp->req_idx = (pp->req_idx + 1) & MV_MAX_Q_DEPTH_MASK;
1954 in_index = pp->req_idx << EDMA_REQ_Q_PTR_SHIFT;
1955
1956 /* Write the request in pointer to kick the EDMA to life */
1957 writelfl((pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK) | in_index,
1958 port_mmio + EDMA_REQ_Q_IN_PTR_OFS);
1959 return 0;
31961943 1960
f48765cc 1961 case ATA_PROT_PIO:
c6112bd8
ML		 1962 /*
1963 * Errata SATA#16, SATA#24: warn if multiple DRQs expected.
1964 *
1965 * Someday, we might implement special polling workarounds
1966 * for these, but it all seems rather unnecessary since we
1967 * normally use only DMA for commands which transfer more
1968 * than a single block of data.
1969 *
1970 * Much of the time, this could just work regardless.
1971 * So for now, just log the incident, and allow the attempt.
1972 */
c7843e8f 1973 if (limit_warnings > 0 && (qc->nbytes / qc->sect_size) > 1) {
c6112bd8
ML		 1974 --limit_warnings;
1975 ata_link_printk(qc->dev->link, KERN_WARNING, DRV_NAME
1976 ": attempting PIO w/multiple DRQ: "
1977 "this may fail due to h/w errata\n");
1978 }
f48765cc 1979 /* drop through */
42ed893d 1980 case ATA_PROT_NODATA:
f48765cc 1981 case ATAPI_PROT_PIO:
42ed893d
ML		 1982 case ATAPI_PROT_NODATA:
1983 if (ap->flags & ATA_FLAG_PIO_POLLING)
1984 qc->tf.flags |= ATA_TFLAG_POLLING;
1985 break;
31961943 1986 }
42ed893d
ML		 1987
1988 if (qc->tf.flags & ATA_TFLAG_POLLING)
1989 port_irqs = ERR_IRQ; /* mask device interrupt when polling */
1990 else
1991 port_irqs = ERR_IRQ | DONE_IRQ; /* unmask all interrupts */
1992
1993 /*
1994 * We're about to send a non-EDMA capable command to the
1995 * port. Turn off EDMA so there won't be problems accessing
1996 * shadow block, etc registers.
1997 */
1998 mv_stop_edma(ap);
1999 mv_clear_and_enable_port_irqs(ap, mv_ap_base(ap), port_irqs);
2000 mv_pmp_select(ap, qc->dev->link->pmp);
70f8b79c
ML		 2001
2002 if (qc->tf.command == ATA_CMD_READ_LOG_EXT) {
2003 struct mv_host_priv *hpriv = ap->host->private_data;
2004 /*
2005 * Workaround for 88SX60x1 FEr SATA#25 (part 2).
40f21b11 2006 *
70f8b79c
ML		 2007 * After any NCQ error, the READ_LOG_EXT command
2008 * from libata-eh *must* use mv_qc_issue_fis().
2009 * Otherwise it might fail, due to chip errata.
2010 *
2011 * Rather than special-case it, we'll just *always*
2012 * use this method here for READ_LOG_EXT, making for
2013 * easier testing.
2014 */
2015 if (IS_GEN_II(hpriv))
2016 return mv_qc_issue_fis(qc);
2017 }
42ed893d 2018 return ata_sff_qc_issue(qc);
31961943
BR		 2019}
2020
8f767f8a
ML		 2021static struct ata_queued_cmd *mv_get_active_qc(struct ata_port *ap)
2022{
2023 struct mv_port_priv *pp = ap->private_data;
2024 struct ata_queued_cmd *qc;
2025
2026 if (pp->pp_flags & MV_PP_FLAG_NCQ_EN)
2027 return NULL;
2028 qc = ata_qc_from_tag(ap, ap->link.active_tag);
95db5051
ML		 2029 if (qc) {
2030 if (qc->tf.flags & ATA_TFLAG_POLLING)
2031 qc = NULL;
2032 else if (!(qc->flags & ATA_QCFLAG_ACTIVE))
2033 qc = NULL;
2034 }
8f767f8a
ML		 2035 return qc;
2036}
2037
29d187bb
ML		 2038static void mv_pmp_error_handler(struct ata_port *ap)
2039{
2040 unsigned int pmp, pmp_map;
2041 struct mv_port_priv *pp = ap->private_data;
2042
2043 if (pp->pp_flags & MV_PP_FLAG_DELAYED_EH) {
2044 /*
2045 * Perform NCQ error analysis on failed PMPs
2046 * before we freeze the port entirely.
2047 *
2048 * The failed PMPs are marked earlier by mv_pmp_eh_prep().
2049 */
2050 pmp_map = pp->delayed_eh_pmp_map;
2051 pp->pp_flags &= ~MV_PP_FLAG_DELAYED_EH;
2052 for (pmp = 0; pmp_map != 0; pmp++) {
2053 unsigned int this_pmp = (1 << pmp);
2054 if (pmp_map & this_pmp) {
2055 struct ata_link *link = &ap->pmp_link[pmp];
2056 pmp_map &= ~this_pmp;
2057 ata_eh_analyze_ncq_error(link);
2058 }
2059 }
2060 ata_port_freeze(ap);
2061 }
2062 sata_pmp_error_handler(ap);
2063}
2064
4c299ca3
ML		 2065static unsigned int mv_get_err_pmp_map(struct ata_port *ap)
2066{
2067 void __iomem *port_mmio = mv_ap_base(ap);
2068
2069 return readl(port_mmio + SATA_TESTCTL_OFS) >> 16;
2070}
2071
4c299ca3
ML		 2072static void mv_pmp_eh_prep(struct ata_port *ap, unsigned int pmp_map)
2073{
2074 struct ata_eh_info *ehi;
2075 unsigned int pmp;
2076
2077 /*
2078 * Initialize EH info for PMPs which saw device errors
2079 */
2080 ehi = &ap->link.eh_info;
2081 for (pmp = 0; pmp_map != 0; pmp++) {
2082 unsigned int this_pmp = (1 << pmp);
2083 if (pmp_map & this_pmp) {
2084 struct ata_link *link = &ap->pmp_link[pmp];
2085
2086 pmp_map &= ~this_pmp;
2087 ehi = &link->eh_info;
2088 ata_ehi_clear_desc(ehi);
2089 ata_ehi_push_desc(ehi, "dev err");
2090 ehi->err_mask |= AC_ERR_DEV;
2091 ehi->action |= ATA_EH_RESET;
2092 ata_link_abort(link);
2093 }
2094 }
2095}
2096
06aaca3f
ML		 2097static int mv_req_q_empty(struct ata_port *ap)
2098{
2099 void __iomem *port_mmio = mv_ap_base(ap);
2100 u32 in_ptr, out_ptr;
2101
2102 in_ptr = (readl(port_mmio + EDMA_REQ_Q_IN_PTR_OFS)
2103 >> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK;
2104 out_ptr = (readl(port_mmio + EDMA_REQ_Q_OUT_PTR_OFS)
2105 >> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK;
2106 return (in_ptr == out_ptr); /* 1 == queue_is_empty */
2107}
2108
4c299ca3
ML		 2109static int mv_handle_fbs_ncq_dev_err(struct ata_port *ap)
2110{
2111 struct mv_port_priv *pp = ap->private_data;
2112 int failed_links;
2113 unsigned int old_map, new_map;
2114
2115 /*
2116 * Device error during FBS+NCQ operation:
2117 *
2118 * Set a port flag to prevent further I/O being enqueued.
2119 * Leave the EDMA running to drain outstanding commands from this port.
2120 * Perform the post-mortem/EH only when all responses are complete.
2121 * Follow recovery sequence from 6042/7042 datasheet (7.3.15.4.2.2).
2122 */
2123 if (!(pp->pp_flags & MV_PP_FLAG_DELAYED_EH)) {
2124 pp->pp_flags |= MV_PP_FLAG_DELAYED_EH;
2125 pp->delayed_eh_pmp_map = 0;
2126 }
2127 old_map = pp->delayed_eh_pmp_map;
2128 new_map = old_map | mv_get_err_pmp_map(ap);
2129
2130 if (old_map != new_map) {
2131 pp->delayed_eh_pmp_map = new_map;
2132 mv_pmp_eh_prep(ap, new_map & ~old_map);
2133 }
c46938cc 2134 failed_links = hweight16(new_map);
4c299ca3
ML		 2135
2136 ata_port_printk(ap, KERN_INFO, "%s: pmp_map=%04x qc_map=%04x "
2137 "failed_links=%d nr_active_links=%d\n",
2138 __func__, pp->delayed_eh_pmp_map,
2139 ap->qc_active, failed_links,
2140 ap->nr_active_links);
2141
06aaca3f 2142 if (ap->nr_active_links <= failed_links && mv_req_q_empty(ap)) {
4c299ca3
ML		 2143 mv_process_crpb_entries(ap, pp);
2144 mv_stop_edma(ap);
2145 mv_eh_freeze(ap);
2146 ata_port_printk(ap, KERN_INFO, "%s: done\n", __func__);
2147 return 1; /* handled */
2148 }
2149 ata_port_printk(ap, KERN_INFO, "%s: waiting\n", __func__);
2150 return 1; /* handled */
2151}
2152
2153static int mv_handle_fbs_non_ncq_dev_err(struct ata_port *ap)
2154{
2155 /*
2156 * Possible future enhancement:
2157 *
2158 * FBS+non-NCQ operation is not yet implemented.
2159 * See related notes in mv_edma_cfg().
2160 *
2161 * Device error during FBS+non-NCQ operation:
2162 *
2163 * We need to snapshot the shadow registers for each failed command.
2164 * Follow recovery sequence from 6042/7042 datasheet (7.3.15.4.2.3).
2165 */
2166 return 0; /* not handled */
2167}
2168
2169static int mv_handle_dev_err(struct ata_port *ap, u32 edma_err_cause)
2170{
2171 struct mv_port_priv *pp = ap->private_data;
2172
2173 if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN))
2174 return 0; /* EDMA was not active: not handled */
2175 if (!(pp->pp_flags & MV_PP_FLAG_FBS_EN))
2176 return 0; /* FBS was not active: not handled */
2177
2178 if (!(edma_err_cause & EDMA_ERR_DEV))
2179 return 0; /* non DEV error: not handled */
2180 edma_err_cause &= ~EDMA_ERR_IRQ_TRANSIENT;
2181 if (edma_err_cause & ~(EDMA_ERR_DEV | EDMA_ERR_SELF_DIS))
2182 return 0; /* other problems: not handled */
2183
2184 if (pp->pp_flags & MV_PP_FLAG_NCQ_EN) {
2185 /*
2186 * EDMA should NOT have self-disabled for this case.
2187 * If it did, then something is wrong elsewhere,
2188 * and we cannot handle it here.
2189 */
2190 if (edma_err_cause & EDMA_ERR_SELF_DIS) {
2191 ata_port_printk(ap, KERN_WARNING,
2192 "%s: err_cause=0x%x pp_flags=0x%x\n",
2193 __func__, edma_err_cause, pp->pp_flags);
2194 return 0; /* not handled */
2195 }
2196 return mv_handle_fbs_ncq_dev_err(ap);
2197 } else {
2198 /*
2199 * EDMA should have self-disabled for this case.
2200 * If it did not, then something is wrong elsewhere,
2201 * and we cannot handle it here.
2202 */
2203 if (!(edma_err_cause & EDMA_ERR_SELF_DIS)) {
2204 ata_port_printk(ap, KERN_WARNING,
2205 "%s: err_cause=0x%x pp_flags=0x%x\n",
2206 __func__, edma_err_cause, pp->pp_flags);
2207 return 0; /* not handled */
2208 }
2209 return mv_handle_fbs_non_ncq_dev_err(ap);
2210 }
2211 return 0; /* not handled */
2212}
2213
a9010329 2214static void mv_unexpected_intr(struct ata_port *ap, int edma_was_enabled)
8f767f8a 2215{
8f767f8a 2216 struct ata_eh_info *ehi = &ap->link.eh_info;
a9010329 2217 char *when = "idle";
8f767f8a 2218
8f767f8a 2219 ata_ehi_clear_desc(ehi);
a9010329
ML		 2220 if (!ap || (ap->flags & ATA_FLAG_DISABLED)) {
2221 when = "disabled";
2222 } else if (edma_was_enabled) {
2223 when = "EDMA enabled";
8f767f8a
ML		 2224 } else {
2225 struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->link.active_tag);
2226 if (qc && (qc->tf.flags & ATA_TFLAG_POLLING))
a9010329 2227 when = "polling";
8f767f8a 2228 }
a9010329 2229 ata_ehi_push_desc(ehi, "unexpected device interrupt while %s", when);
8f767f8a
ML		 2230 ehi->err_mask |= AC_ERR_OTHER;
2231 ehi->action |= ATA_EH_RESET;
2232 ata_port_freeze(ap);
2233}
2234
05b308e1
BR		 2235/**
2236 * mv_err_intr - Handle error interrupts on the port
2237 * @ap: ATA channel to manipulate
2238 *
8d07379d
ML		 2239 * Most cases require a full reset of the chip's state machine,
2240 * which also performs a COMRESET.
2241 * Also, if the port disabled DMA, update our cached copy to match.
05b308e1
BR		 2242 *
2243 * LOCKING:
2244 * Inherited from caller.
2245 */
37b9046a 2246static void mv_err_intr(struct ata_port *ap)
31961943
BR		 2247{
2248 void __iomem *port_mmio = mv_ap_base(ap);
bdd4ddde 2249 u32 edma_err_cause, eh_freeze_mask, serr = 0;
e4006077 2250 u32 fis_cause = 0;
bdd4ddde
JG		 2251 struct mv_port_priv *pp = ap->private_data;
2252 struct mv_host_priv *hpriv = ap->host->private_data;
bdd4ddde 2253 unsigned int action = 0, err_mask = 0;
9af5c9c9 2254 struct ata_eh_info *ehi = &ap->link.eh_info;
37b9046a
ML		 2255 struct ata_queued_cmd *qc;
2256 int abort = 0;
20f733e7 2257
8d07379d 2258 /*
37b9046a 2259 * Read and clear the SError and err_cause bits.
e4006077
ML		 2260 * For GenIIe, if EDMA_ERR_TRANS_IRQ_7 is set, we also must read/clear
2261 * the FIS_IRQ_CAUSE register before clearing edma_err_cause.
8d07379d 2262 */
37b9046a
ML		 2263 sata_scr_read(&ap->link, SCR_ERROR, &serr);
2264 sata_scr_write_flush(&ap->link, SCR_ERROR, serr);
2265
bdd4ddde 2266 edma_err_cause = readl(port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
e4006077
ML		 2267 if (IS_GEN_IIE(hpriv) && (edma_err_cause & EDMA_ERR_TRANS_IRQ_7)) {
2268 fis_cause = readl(port_mmio + SATA_FIS_IRQ_CAUSE_OFS);
2269 writelfl(~fis_cause, port_mmio + SATA_FIS_IRQ_CAUSE_OFS);
2270 }
8d07379d 2271 writelfl(~edma_err_cause, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
bdd4ddde 2272
4c299ca3
ML		 2273 if (edma_err_cause & EDMA_ERR_DEV) {
2274 /*
2275 * Device errors during FIS-based switching operation
2276 * require special handling.
2277 */
2278 if (mv_handle_dev_err(ap, edma_err_cause))
2279 return;
2280 }
2281
37b9046a
ML		 2282 qc = mv_get_active_qc(ap);
2283 ata_ehi_clear_desc(ehi);
2284 ata_ehi_push_desc(ehi, "edma_err_cause=%08x pp_flags=%08x",
2285 edma_err_cause, pp->pp_flags);
e4006077 2286
c443c500 2287 if (IS_GEN_IIE(hpriv) && (edma_err_cause & EDMA_ERR_TRANS_IRQ_7)) {
e4006077 2288 ata_ehi_push_desc(ehi, "fis_cause=%08x", fis_cause);
c443c500
ML		 2289 if (fis_cause & SATA_FIS_IRQ_AN) {
2290 u32 ec = edma_err_cause &
2291 ~(EDMA_ERR_TRANS_IRQ_7 | EDMA_ERR_IRQ_TRANSIENT);
2292 sata_async_notification(ap);
2293 if (!ec)
2294 return; /* Just an AN; no need for the nukes */
2295 ata_ehi_push_desc(ehi, "SDB notify");
2296 }
2297 }
bdd4ddde 2298 /*
352fab70 2299 * All generations share these EDMA error cause bits:
bdd4ddde 2300 */
37b9046a 2301 if (edma_err_cause & EDMA_ERR_DEV) {
bdd4ddde 2302 err_mask |= AC_ERR_DEV;
37b9046a
ML		 2303 action |= ATA_EH_RESET;
2304 ata_ehi_push_desc(ehi, "dev error");
2305 }
bdd4ddde 2306 if (edma_err_cause & (EDMA_ERR_D_PAR | EDMA_ERR_PRD_PAR |
6c1153e0 2307 EDMA_ERR_CRQB_PAR | EDMA_ERR_CRPB_PAR |
bdd4ddde
JG		 2308 EDMA_ERR_INTRL_PAR)) {
2309 err_mask |= AC_ERR_ATA_BUS;
cf480626 2310 action |= ATA_EH_RESET;
b64bbc39 2311 ata_ehi_push_desc(ehi, "parity error");
bdd4ddde
JG		 2312 }
2313 if (edma_err_cause & (EDMA_ERR_DEV_DCON | EDMA_ERR_DEV_CON)) {
2314 ata_ehi_hotplugged(ehi);
2315 ata_ehi_push_desc(ehi, edma_err_cause & EDMA_ERR_DEV_DCON ?
b64bbc39 2316 "dev disconnect" : "dev connect");
cf480626 2317 action |= ATA_EH_RESET;
bdd4ddde
JG		 2318 }
2319
352fab70
ML		 2320 /*
2321 * Gen-I has a different SELF_DIS bit,
2322 * different FREEZE bits, and no SERR bit:
2323 */
ee9ccdf7 2324 if (IS_GEN_I(hpriv)) {
bdd4ddde 2325 eh_freeze_mask = EDMA_EH_FREEZE_5;
bdd4ddde 2326 if (edma_err_cause & EDMA_ERR_SELF_DIS_5) {
bdd4ddde 2327 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
b64bbc39 2328 ata_ehi_push_desc(ehi, "EDMA self-disable");
bdd4ddde
JG		 2329 }
2330 } else {
2331 eh_freeze_mask = EDMA_EH_FREEZE;
bdd4ddde 2332 if (edma_err_cause & EDMA_ERR_SELF_DIS) {
bdd4ddde 2333 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
b64bbc39 2334 ata_ehi_push_desc(ehi, "EDMA self-disable");
bdd4ddde 2335 }
bdd4ddde 2336 if (edma_err_cause & EDMA_ERR_SERR) {
8d07379d
ML		 2337 ata_ehi_push_desc(ehi, "SError=%08x", serr);
2338 err_mask |= AC_ERR_ATA_BUS;
cf480626 2339 action |= ATA_EH_RESET;
bdd4ddde 2340 }
afb0edd9 2341 }
20f733e7 2342
bdd4ddde
JG		 2343 if (!err_mask) {
2344 err_mask = AC_ERR_OTHER;
cf480626 2345 action |= ATA_EH_RESET;
bdd4ddde
JG		 2346 }
2347
2348 ehi->serror |= serr;
2349 ehi->action |= action;
2350
2351 if (qc)
2352 qc->err_mask |= err_mask;
2353 else
2354 ehi->err_mask |= err_mask;
2355
37b9046a
ML		 2356 if (err_mask == AC_ERR_DEV) {
2357 /*
2358 * Cannot do ata_port_freeze() here,
2359 * because it would kill PIO access,
2360 * which is needed for further diagnosis.
2361 */
2362 mv_eh_freeze(ap);
2363 abort = 1;
2364 } else if (edma_err_cause & eh_freeze_mask) {
2365 /*
2366 * Note to self: ata_port_freeze() calls ata_port_abort()
2367 */
bdd4ddde 2368 ata_port_freeze(ap);
37b9046a
ML		 2369 } else {
2370 abort = 1;
2371 }
2372
2373 if (abort) {
2374 if (qc)
2375 ata_link_abort(qc->dev->link);
2376 else
2377 ata_port_abort(ap);
2378 }
bdd4ddde
JG		 2379}
2380
fcfb1f77
ML		 2381static void mv_process_crpb_response(struct ata_port *ap,
2382 struct mv_crpb *response, unsigned int tag, int ncq_enabled)
2383{
2384 struct ata_queued_cmd *qc = ata_qc_from_tag(ap, tag);
2385
2386 if (qc) {
2387 u8 ata_status;
2388 u16 edma_status = le16_to_cpu(response->flags);
2389 /*
2390 * edma_status from a response queue entry:
2391 * LSB is from EDMA_ERR_IRQ_CAUSE_OFS (non-NCQ only).
2392 * MSB is saved ATA status from command completion.
2393 */
2394 if (!ncq_enabled) {
2395 u8 err_cause = edma_status & 0xff & ~EDMA_ERR_DEV;
2396 if (err_cause) {
2397 /*
2398 * Error will be seen/handled by mv_err_intr().
2399 * So do nothing at all here.
2400 */
2401 return;
2402 }
2403 }
2404 ata_status = edma_status >> CRPB_FLAG_STATUS_SHIFT;
37b9046a
ML		 2405 if (!ac_err_mask(ata_status))
2406 ata_qc_complete(qc);
2407 /* else: leave it for mv_err_intr() */
fcfb1f77
ML		 2408 } else {
2409 ata_port_printk(ap, KERN_ERR, "%s: no qc for tag=%d\n",
2410 __func__, tag);
2411 }
2412}
2413
2414static void mv_process_crpb_entries(struct ata_port *ap, struct mv_port_priv *pp)
bdd4ddde
JG		 2415{
2416 void __iomem *port_mmio = mv_ap_base(ap);
2417 struct mv_host_priv *hpriv = ap->host->private_data;
fcfb1f77 2418 u32 in_index;
bdd4ddde 2419 bool work_done = false;
fcfb1f77 2420 int ncq_enabled = (pp->pp_flags & MV_PP_FLAG_NCQ_EN);
bdd4ddde 2421
fcfb1f77 2422 /* Get the hardware queue position index */
bdd4ddde
JG		 2423 in_index = (readl(port_mmio + EDMA_RSP_Q_IN_PTR_OFS)
2424 >> EDMA_RSP_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK;
2425
fcfb1f77
ML		 2426 /* Process new responses from since the last time we looked */
2427 while (in_index != pp->resp_idx) {
6c1153e0 2428 unsigned int tag;
fcfb1f77 2429 struct mv_crpb *response = &pp->crpb[pp->resp_idx];
bdd4ddde 2430
fcfb1f77 2431 pp->resp_idx = (pp->resp_idx + 1) & MV_MAX_Q_DEPTH_MASK;
bdd4ddde 2432
fcfb1f77
ML		 2433 if (IS_GEN_I(hpriv)) {
2434 /* 50xx: no NCQ, only one command active at a time */
9af5c9c9 2435 tag = ap->link.active_tag;
fcfb1f77
ML		 2436 } else {
2437 /* Gen II/IIE: get command tag from CRPB entry */
2438 tag = le16_to_cpu(response->id) & 0x1f;
bdd4ddde 2439 }
fcfb1f77 2440 mv_process_crpb_response(ap, response, tag, ncq_enabled);
bdd4ddde 2441 work_done = true;
bdd4ddde
JG		 2442 }
2443
352fab70 2444 /* Update the software queue position index in hardware */
bdd4ddde
JG		 2445 if (work_done)
2446 writelfl((pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK) |
fcfb1f77 2447 (pp->resp_idx << EDMA_RSP_Q_PTR_SHIFT),
bdd4ddde 2448 port_mmio + EDMA_RSP_Q_OUT_PTR_OFS);
20f733e7
BR		 2449}
2450
a9010329
ML		 2451static void mv_port_intr(struct ata_port *ap, u32 port_cause)
2452{
2453 struct mv_port_priv *pp;
2454 int edma_was_enabled;
2455
2456 if (!ap || (ap->flags & ATA_FLAG_DISABLED)) {
2457 mv_unexpected_intr(ap, 0);
2458 return;
2459 }
2460 /*
2461 * Grab a snapshot of the EDMA_EN flag setting,
2462 * so that we have a consistent view for this port,
2463 * even if something we call of our routines changes it.
2464 */
2465 pp = ap->private_data;
2466 edma_was_enabled = (pp->pp_flags & MV_PP_FLAG_EDMA_EN);
2467 /*
2468 * Process completed CRPB response(s) before other events.
2469 */
2470 if (edma_was_enabled && (port_cause & DONE_IRQ)) {
2471 mv_process_crpb_entries(ap, pp);
4c299ca3
ML		 2472 if (pp->pp_flags & MV_PP_FLAG_DELAYED_EH)
2473 mv_handle_fbs_ncq_dev_err(ap);
a9010329
ML		 2474 }
2475 /*
2476 * Handle chip-reported errors, or continue on to handle PIO.
2477 */
2478 if (unlikely(port_cause & ERR_IRQ)) {
2479 mv_err_intr(ap);
2480 } else if (!edma_was_enabled) {
2481 struct ata_queued_cmd *qc = mv_get_active_qc(ap);
2482 if (qc)
2483 ata_sff_host_intr(ap, qc);
2484 else
2485 mv_unexpected_intr(ap, edma_was_enabled);
2486 }
2487}
2488
05b308e1
BR		 2489/**
2490 * mv_host_intr - Handle all interrupts on the given host controller
cca3974e 2491 * @host: host specific structure
7368f919 2492 * @main_irq_cause: Main interrupt cause register for the chip.
05b308e1
BR		 2493 *
2494 * LOCKING:
2495 * Inherited from caller.
2496 */
7368f919 2497static int mv_host_intr(struct ata_host *host, u32 main_irq_cause)
20f733e7 2498{
f351b2d6 2499 struct mv_host_priv *hpriv = host->private_data;
eabd5eb1 2500 void __iomem *mmio = hpriv->base, *hc_mmio;
a3718c1f 2501 unsigned int handled = 0, port;
20f733e7 2502
a3718c1f 2503 for (port = 0; port < hpriv->n_ports; port++) {
cca3974e 2504 struct ata_port *ap = host->ports[port];
eabd5eb1
ML		 2505 unsigned int p, shift, hardport, port_cause;
2506
a3718c1f 2507 MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport);
a3718c1f 2508 /*
eabd5eb1
ML		 2509 * Each hc within the host has its own hc_irq_cause register,
2510 * where the interrupting ports bits get ack'd.
a3718c1f 2511 */
eabd5eb1
ML		 2512 if (hardport == 0) { /* first port on this hc ? */
2513 u32 hc_cause = (main_irq_cause >> shift) & HC0_IRQ_PEND;
2514 u32 port_mask, ack_irqs;
2515 /*
2516 * Skip this entire hc if nothing pending for any ports
2517 */
2518 if (!hc_cause) {
2519 port += MV_PORTS_PER_HC - 1;
2520 continue;
2521 }
2522 /*
2523 * We don't need/want to read the hc_irq_cause register,
2524 * because doing so hurts performance, and
2525 * main_irq_cause already gives us everything we need.
2526 *
2527 * But we do have to *write* to the hc_irq_cause to ack
2528 * the ports that we are handling this time through.
2529 *
2530 * This requires that we create a bitmap for those
2531 * ports which interrupted us, and use that bitmap
2532 * to ack (only) those ports via hc_irq_cause.
2533 */
2534 ack_irqs = 0;
2535 for (p = 0; p < MV_PORTS_PER_HC; ++p) {
2536 if ((port + p) >= hpriv->n_ports)
2537 break;
2538 port_mask = (DONE_IRQ | ERR_IRQ) << (p * 2);
2539 if (hc_cause & port_mask)
2540 ack_irqs |= (DMA_IRQ | DEV_IRQ) << p;
2541 }
a3718c1f 2542 hc_mmio = mv_hc_base_from_port(mmio, port);
eabd5eb1 2543 writelfl(~ack_irqs, hc_mmio + HC_IRQ_CAUSE_OFS);
a3718c1f
ML		 2544 handled = 1;
2545 }
8f767f8a 2546 /*
a9010329 2547 * Handle interrupts signalled for this port:
8f767f8a 2548 */
a9010329
ML		 2549 port_cause = (main_irq_cause >> shift) & (DONE_IRQ | ERR_IRQ);
2550 if (port_cause)
2551 mv_port_intr(ap, port_cause);
20f733e7 2552 }
a3718c1f 2553 return handled;
20f733e7
BR		 2554}
2555
a3718c1f 2556static int mv_pci_error(struct ata_host *host, void __iomem *mmio)
bdd4ddde 2557{
02a121da 2558 struct mv_host_priv *hpriv = host->private_data;
bdd4ddde
JG		 2559 struct ata_port *ap;
2560 struct ata_queued_cmd *qc;
2561 struct ata_eh_info *ehi;
2562 unsigned int i, err_mask, printed = 0;
2563 u32 err_cause;
2564
02a121da 2565 err_cause = readl(mmio + hpriv->irq_cause_ofs);
bdd4ddde
JG		 2566
2567 dev_printk(KERN_ERR, host->dev, "PCI ERROR; PCI IRQ cause=0x%08x\n",
2568 err_cause);
2569
2570 DPRINTK("All regs @ PCI error\n");
2571 mv_dump_all_regs(mmio, -1, to_pci_dev(host->dev));
2572
02a121da 2573 writelfl(0, mmio + hpriv->irq_cause_ofs);
bdd4ddde
JG		 2574
2575 for (i = 0; i < host->n_ports; i++) {
2576 ap = host->ports[i];
936fd732 2577 if (!ata_link_offline(&ap->link)) {
9af5c9c9 2578 ehi = &ap->link.eh_info;
bdd4ddde
JG		 2579 ata_ehi_clear_desc(ehi);
2580 if (!printed++)
2581 ata_ehi_push_desc(ehi,
2582 "PCI err cause 0x%08x", err_cause);
2583 err_mask = AC_ERR_HOST_BUS;
cf480626 2584 ehi->action = ATA_EH_RESET;
9af5c9c9 2585 qc = ata_qc_from_tag(ap, ap->link.active_tag);
bdd4ddde
JG		 2586 if (qc)
2587 qc->err_mask |= err_mask;
2588 else
2589 ehi->err_mask |= err_mask;
2590
2591 ata_port_freeze(ap);
2592 }
2593 }
a3718c1f 2594 return 1; /* handled */
bdd4ddde
JG		 2595}
2596
05b308e1 2597/**
c5d3e45a 2598 * mv_interrupt - Main interrupt event handler
05b308e1
BR		 2599 * @irq: unused
2600 * @dev_instance: private data; in this case the host structure
05b308e1
BR		 2601 *
2602 * Read the read only register to determine if any host
2603 * controllers have pending interrupts. If so, call lower level
2604 * routine to handle. Also check for PCI errors which are only
2605 * reported here.
2606 *
8b260248 2607 * LOCKING:
cca3974e 2608 * This routine holds the host lock while processing pending
05b308e1
BR		 2609 * interrupts.
2610 */
7d12e780 2611static irqreturn_t mv_interrupt(int irq, void *dev_instance)
20f733e7 2612{
cca3974e 2613 struct ata_host *host = dev_instance;
f351b2d6 2614 struct mv_host_priv *hpriv = host->private_data;
a3718c1f 2615 unsigned int handled = 0;
6d3c30ef 2616 int using_msi = hpriv->hp_flags & MV_HP_FLAG_MSI;
96e2c487 2617 u32 main_irq_cause, pending_irqs;
20f733e7 2618
646a4da5 2619 spin_lock(&host->lock);
6d3c30ef
ML		 2620
2621 /* for MSI: block new interrupts while in here */
2622 if (using_msi)
2623 writel(0, hpriv->main_irq_mask_addr);
2624
7368f919 2625 main_irq_cause = readl(hpriv->main_irq_cause_addr);
96e2c487 2626 pending_irqs = main_irq_cause & hpriv->main_irq_mask;
352fab70
ML		 2627 /*
2628 * Deal with cases where we either have nothing pending, or have read
2629 * a bogus register value which can indicate HW removal or PCI fault.
20f733e7 2630 */
a44253d2 2631 if (pending_irqs && main_irq_cause != 0xffffffffU) {
1f398472 2632 if (unlikely((pending_irqs & PCI_ERR) && !IS_SOC(hpriv)))
a3718c1f
ML		 2633 handled = mv_pci_error(host, hpriv->base);
2634 else
a44253d2 2635 handled = mv_host_intr(host, pending_irqs);
bdd4ddde 2636 }
6d3c30ef
ML		 2637
2638 /* for MSI: unmask; interrupt cause bits will retrigger now */
2639 if (using_msi)
2640 writel(hpriv->main_irq_mask, hpriv->main_irq_mask_addr);
2641
9d51af7b
ML		 2642 spin_unlock(&host->lock);
2643
20f733e7
BR		 2644 return IRQ_RETVAL(handled);
2645}
2646
c9d39130
JG		 2647static unsigned int mv5_scr_offset(unsigned int sc_reg_in)
2648{
2649 unsigned int ofs;
2650
2651 switch (sc_reg_in) {
2652 case SCR_STATUS:
2653 case SCR_ERROR:
2654 case SCR_CONTROL:
2655 ofs = sc_reg_in * sizeof(u32);
2656 break;
2657 default:
2658 ofs = 0xffffffffU;
2659 break;
2660 }
2661 return ofs;
2662}
2663
82ef04fb 2664static int mv5_scr_read(struct ata_link *link, unsigned int sc_reg_in, u32 *val)
c9d39130 2665{
82ef04fb 2666 struct mv_host_priv *hpriv = link->ap->host->private_data;
f351b2d6 2667 void __iomem *mmio = hpriv->base;
82ef04fb 2668 void __iomem *addr = mv5_phy_base(mmio, link->ap->port_no);
c9d39130
JG		 2669 unsigned int ofs = mv5_scr_offset(sc_reg_in);
2670
da3dbb17
TH		 2671 if (ofs != 0xffffffffU) {
2672 *val = readl(addr + ofs);
2673 return 0;
2674 } else
2675 return -EINVAL;
c9d39130
JG		 2676}
2677
82ef04fb 2678static int mv5_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val)
c9d39130 2679{
82ef04fb 2680 struct mv_host_priv *hpriv = link->ap->host->private_data;
f351b2d6 2681 void __iomem *mmio = hpriv->base;
82ef04fb 2682 void __iomem *addr = mv5_phy_base(mmio, link->ap->port_no);
c9d39130
JG		 2683 unsigned int ofs = mv5_scr_offset(sc_reg_in);
2684
da3dbb17 2685 if (ofs != 0xffffffffU) {
0d5ff566 2686 writelfl(val, addr + ofs);
da3dbb17
TH		 2687 return 0;
2688 } else
2689 return -EINVAL;
c9d39130
JG		 2690}
2691
7bb3c529 2692static void mv5_reset_bus(struct ata_host *host, void __iomem *mmio)
522479fb 2693{
7bb3c529 2694 struct pci_dev *pdev = to_pci_dev(host->dev);
522479fb
JG		 2695 int early_5080;
2696
44c10138 2697 early_5080 = (pdev->device == 0x5080) && (pdev->revision == 0);
522479fb
JG		 2698
2699 if (!early_5080) {
2700 u32 tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL);
2701 tmp |= (1 << 0);
2702 writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL);
2703 }
2704
7bb3c529 2705 mv_reset_pci_bus(host, mmio);
522479fb
JG		 2706}
2707
2708static void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio)
2709{
8e7decdb 2710 writel(0x0fcfffff, mmio + MV_FLASH_CTL_OFS);
522479fb
JG		 2711}
2712
47c2b677 2713static void mv5_read_preamp(struct mv_host_priv *hpriv, int idx,
ba3fe8fb
JG		 2714 void __iomem *mmio)
2715{
c9d39130
JG		 2716 void __iomem *phy_mmio = mv5_phy_base(mmio, idx);
2717 u32 tmp;
2718
2719 tmp = readl(phy_mmio + MV5_PHY_MODE);
2720
2721 hpriv->signal[idx].pre = tmp & 0x1800; /* bits 12:11 */
2722 hpriv->signal[idx].amps = tmp & 0xe0; /* bits 7:5 */
ba3fe8fb
JG		 2723}
2724
47c2b677 2725static void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio)
ba3fe8fb 2726{
522479fb
JG		 2727 u32 tmp;
2728
8e7decdb 2729 writel(0, mmio + MV_GPIO_PORT_CTL_OFS);
522479fb
JG		 2730
2731 /* FIXME: handle MV_HP_ERRATA_50XXB2 errata */
2732
2733 tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL);
2734 tmp |= ~(1 << 0);
2735 writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL);
ba3fe8fb
JG		 2736}
2737
2a47ce06
JG		 2738static void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
2739 unsigned int port)
bca1c4eb 2740{
c9d39130
JG		 2741 void __iomem *phy_mmio = mv5_phy_base(mmio, port);
2742 const u32 mask = (1<<12) | (1<<11) | (1<<7) | (1<<6) | (1<<5);
2743 u32 tmp;
2744 int fix_apm_sq = (hpriv->hp_flags & MV_HP_ERRATA_50XXB0);
2745
2746 if (fix_apm_sq) {
8e7decdb 2747 tmp = readl(phy_mmio + MV5_LTMODE_OFS);
c9d39130 2748 tmp |= (1 << 19);
8e7decdb 2749 writel(tmp, phy_mmio + MV5_LTMODE_OFS);
c9d39130 2750
8e7decdb 2751 tmp = readl(phy_mmio + MV5_PHY_CTL_OFS);
c9d39130
JG		 2752 tmp &= ~0x3;
2753 tmp |= 0x1;
8e7decdb 2754 writel(tmp, phy_mmio + MV5_PHY_CTL_OFS);
c9d39130
JG		 2755 }
2756
2757 tmp = readl(phy_mmio + MV5_PHY_MODE);
2758 tmp &= ~mask;
2759 tmp |= hpriv->signal[port].pre;
2760 tmp |= hpriv->signal[port].amps;
2761 writel(tmp, phy_mmio + MV5_PHY_MODE);
bca1c4eb
JG		 2762}
2763
c9d39130
JG		 2764
2765#undef ZERO
2766#define ZERO(reg) writel(0, port_mmio + (reg))
2767static void mv5_reset_hc_port(struct mv_host_priv *hpriv, void __iomem *mmio,
2768 unsigned int port)
2769{
2770 void __iomem *port_mmio = mv_port_base(mmio, port);
2771
e12bef50 2772 mv_reset_channel(hpriv, mmio, port);
c9d39130
JG		 2773
2774 ZERO(0x028); /* command */
2775 writel(0x11f, port_mmio + EDMA_CFG_OFS);
2776 ZERO(0x004); /* timer */
2777 ZERO(0x008); /* irq err cause */
2778 ZERO(0x00c); /* irq err mask */
2779 ZERO(0x010); /* rq bah */
2780 ZERO(0x014); /* rq inp */
2781 ZERO(0x018); /* rq outp */
2782 ZERO(0x01c); /* respq bah */
2783 ZERO(0x024); /* respq outp */
2784 ZERO(0x020); /* respq inp */
2785 ZERO(0x02c); /* test control */
8e7decdb 2786 writel(0xbc, port_mmio + EDMA_IORDY_TMOUT_OFS);
c9d39130
JG		 2787}
2788#undef ZERO
2789
2790#define ZERO(reg) writel(0, hc_mmio + (reg))
2791static void mv5_reset_one_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
2792 unsigned int hc)
47c2b677 2793{
c9d39130
JG		 2794 void __iomem *hc_mmio = mv_hc_base(mmio, hc);
2795 u32 tmp;
2796
2797 ZERO(0x00c);
2798 ZERO(0x010);
2799 ZERO(0x014);
2800 ZERO(0x018);
2801
2802 tmp = readl(hc_mmio + 0x20);
2803 tmp &= 0x1c1c1c1c;
2804 tmp |= 0x03030303;
2805 writel(tmp, hc_mmio + 0x20);
2806}
2807#undef ZERO
2808
2809static int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
2810 unsigned int n_hc)
2811{
2812 unsigned int hc, port;
2813
2814 for (hc = 0; hc < n_hc; hc++) {
2815 for (port = 0; port < MV_PORTS_PER_HC; port++)
2816 mv5_reset_hc_port(hpriv, mmio,
2817 (hc * MV_PORTS_PER_HC) + port);
2818
2819 mv5_reset_one_hc(hpriv, mmio, hc);
2820 }
2821
2822 return 0;
47c2b677
JG		 2823}
2824
101ffae2
JG		 2825#undef ZERO
2826#define ZERO(reg) writel(0, mmio + (reg))
7bb3c529 2827static void mv_reset_pci_bus(struct ata_host *host, void __iomem *mmio)
101ffae2 2828{
02a121da 2829 struct mv_host_priv *hpriv = host->private_data;
101ffae2
JG		 2830 u32 tmp;
2831
8e7decdb 2832 tmp = readl(mmio + MV_PCI_MODE_OFS);
101ffae2 2833 tmp &= 0xff00ffff;
8e7decdb 2834 writel(tmp, mmio + MV_PCI_MODE_OFS);
101ffae2
JG		 2835
2836 ZERO(MV_PCI_DISC_TIMER);
2837 ZERO(MV_PCI_MSI_TRIGGER);
8e7decdb 2838 writel(0x000100ff, mmio + MV_PCI_XBAR_TMOUT_OFS);
101ffae2 2839 ZERO(MV_PCI_SERR_MASK);
02a121da
ML		 2840 ZERO(hpriv->irq_cause_ofs);
2841 ZERO(hpriv->irq_mask_ofs);
101ffae2
JG		 2842 ZERO(MV_PCI_ERR_LOW_ADDRESS);
2843 ZERO(MV_PCI_ERR_HIGH_ADDRESS);
2844 ZERO(MV_PCI_ERR_ATTRIBUTE);
2845 ZERO(MV_PCI_ERR_COMMAND);
2846}
2847#undef ZERO
2848
2849static void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio)
2850{
2851 u32 tmp;
2852
2853 mv5_reset_flash(hpriv, mmio);
2854
8e7decdb 2855 tmp = readl(mmio + MV_GPIO_PORT_CTL_OFS);
101ffae2
JG		 2856 tmp &= 0x3;
2857 tmp |= (1 << 5) | (1 << 6);
8e7decdb 2858 writel(tmp, mmio + MV_GPIO_PORT_CTL_OFS);
101ffae2
JG		 2859}
2860
2861/**
2862 * mv6_reset_hc - Perform the 6xxx global soft reset
2863 * @mmio: base address of the HBA
2864 *
2865 * This routine only applies to 6xxx parts.
2866 *
2867 * LOCKING:
2868 * Inherited from caller.
2869 */
c9d39130
JG		 2870static int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
2871 unsigned int n_hc)
101ffae2
JG		 2872{
2873 void __iomem *reg = mmio + PCI_MAIN_CMD_STS_OFS;
2874 int i, rc = 0;
2875 u32 t;
2876
2877 /* Following procedure defined in PCI "main command and status
2878 * register" table.
2879 */
2880 t = readl(reg);
2881 writel(t | STOP_PCI_MASTER, reg);
2882
2883 for (i = 0; i < 1000; i++) {
2884 udelay(1);
2885 t = readl(reg);
2dcb407e 2886 if (PCI_MASTER_EMPTY & t)
101ffae2 2887 break;
101ffae2
JG		 2888 }
2889 if (!(PCI_MASTER_EMPTY & t)) {
2890 printk(KERN_ERR DRV_NAME ": PCI master won't flush\n");
2891 rc = 1;
2892 goto done;
2893 }
2894
2895 /* set reset */
2896 i = 5;
2897 do {
2898 writel(t | GLOB_SFT_RST, reg);
2899 t = readl(reg);
2900 udelay(1);
2901 } while (!(GLOB_SFT_RST & t) && (i-- > 0));
2902
2903 if (!(GLOB_SFT_RST & t)) {
2904 printk(KERN_ERR DRV_NAME ": can't set global reset\n");
2905 rc = 1;
2906 goto done;
2907 }
2908
2909 /* clear reset and *reenable the PCI master* (not mentioned in spec) */
2910 i = 5;
2911 do {
2912 writel(t & ~(GLOB_SFT_RST | STOP_PCI_MASTER), reg);
2913 t = readl(reg);
2914 udelay(1);
2915 } while ((GLOB_SFT_RST & t) && (i-- > 0));
2916
2917 if (GLOB_SFT_RST & t) {
2918 printk(KERN_ERR DRV_NAME ": can't clear global reset\n");
2919 rc = 1;
2920 }
2921done:
2922 return rc;
2923}
2924
47c2b677 2925static void mv6_read_preamp(struct mv_host_priv *hpriv, int idx,
ba3fe8fb
JG		 2926 void __iomem *mmio)
2927{
2928 void __iomem *port_mmio;
2929 u32 tmp;
2930
8e7decdb 2931 tmp = readl(mmio + MV_RESET_CFG_OFS);
ba3fe8fb 2932 if ((tmp & (1 << 0)) == 0) {
47c2b677 2933 hpriv->signal[idx].amps = 0x7 << 8;
ba3fe8fb
JG		 2934 hpriv->signal[idx].pre = 0x1 << 5;
2935 return;
2936 }
2937
2938 port_mmio = mv_port_base(mmio, idx);
2939 tmp = readl(port_mmio + PHY_MODE2);
2940
2941 hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */
2942 hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */
2943}
2944
47c2b677 2945static void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio)
ba3fe8fb 2946{
8e7decdb 2947 writel(0x00000060, mmio + MV_GPIO_PORT_CTL_OFS);
ba3fe8fb
JG		 2948}
2949
c9d39130 2950static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
2a47ce06 2951 unsigned int port)
bca1c4eb 2952{
c9d39130
JG		 2953 void __iomem *port_mmio = mv_port_base(mmio, port);
2954
bca1c4eb 2955 u32 hp_flags = hpriv->hp_flags;
47c2b677
JG		 2956 int fix_phy_mode2 =
2957 hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0);
bca1c4eb 2958 int fix_phy_mode4 =
47c2b677 2959 hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0);
8c30a8b9 2960 u32 m2, m3;
47c2b677
JG		 2961
2962 if (fix_phy_mode2) {
2963 m2 = readl(port_mmio + PHY_MODE2);
2964 m2 &= ~(1 << 16);
2965 m2 |= (1 << 31);
2966 writel(m2, port_mmio + PHY_MODE2);
2967
2968 udelay(200);
2969
2970 m2 = readl(port_mmio + PHY_MODE2);
2971 m2 &= ~((1 << 16) | (1 << 31));
2972 writel(m2, port_mmio + PHY_MODE2);
2973
2974 udelay(200);
2975 }
2976
8c30a8b9
ML		 2977 /*
2978 * Gen-II/IIe PHY_MODE3 errata RM#2:
2979 * Achieves better receiver noise performance than the h/w default:
2980 */
2981 m3 = readl(port_mmio + PHY_MODE3);
2982 m3 = (m3 & 0x1f) | (0x5555601 << 5);
bca1c4eb 2983
0388a8c0
ML		 2984 /* Guideline 88F5182 (GL# SATA-S11) */
2985 if (IS_SOC(hpriv))
2986 m3 &= ~0x1c;
2987
bca1c4eb 2988 if (fix_phy_mode4) {
ba069e37
ML		 2989 u32 m4 = readl(port_mmio + PHY_MODE4);
2990 /*
2991 * Enforce reserved-bit restrictions on GenIIe devices only.
2992 * For earlier chipsets, force only the internal config field
2993 * (workaround for errata FEr SATA#10 part 1).
2994 */
8c30a8b9 2995 if (IS_GEN_IIE(hpriv))
ba069e37
ML		 2996 m4 = (m4 & ~PHY_MODE4_RSVD_ZEROS) | PHY_MODE4_RSVD_ONES;
2997 else
2998 m4 = (m4 & ~PHY_MODE4_CFG_MASK) | PHY_MODE4_CFG_VALUE;
8c30a8b9 2999 writel(m4, port_mmio + PHY_MODE4);
bca1c4eb 3000 }
b406c7a6
ML		 3001 /*
3002 * Workaround for 60x1-B2 errata SATA#13:
3003 * Any write to PHY_MODE4 (above) may corrupt PHY_MODE3,
3004 * so we must always rewrite PHY_MODE3 after PHY_MODE4.
3005 */
3006 writel(m3, port_mmio + PHY_MODE3);
bca1c4eb
JG		 3007
3008 /* Revert values of pre-emphasis and signal amps to the saved ones */
3009 m2 = readl(port_mmio + PHY_MODE2);
3010
3011 m2 &= ~MV_M2_PREAMP_MASK;
2a47ce06
JG		 3012 m2 |= hpriv->signal[port].amps;
3013 m2 |= hpriv->signal[port].pre;
47c2b677 3014 m2 &= ~(1 << 16);
bca1c4eb 3015
e4e7b892
JG		 3016 /* according to mvSata 3.6.1, some IIE values are fixed */
3017 if (IS_GEN_IIE(hpriv)) {
3018 m2 &= ~0xC30FF01F;
3019 m2 |= 0x0000900F;
3020 }
3021
bca1c4eb
JG		 3022 writel(m2, port_mmio + PHY_MODE2);
3023}
3024
f351b2d6
SB		 3025/* TODO: use the generic LED interface to configure the SATA Presence */
3026/* & Acitivy LEDs on the board */
3027static void mv_soc_enable_leds(struct mv_host_priv *hpriv,
3028 void __iomem *mmio)
3029{
3030 return;
3031}
3032
3033static void mv_soc_read_preamp(struct mv_host_priv *hpriv, int idx,
3034 void __iomem *mmio)
3035{
3036 void __iomem *port_mmio;
3037 u32 tmp;
3038
3039 port_mmio = mv_port_base(mmio, idx);
3040 tmp = readl(port_mmio + PHY_MODE2);
3041
3042 hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */
3043 hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */
3044}
3045
3046#undef ZERO
3047#define ZERO(reg) writel(0, port_mmio + (reg))
3048static void mv_soc_reset_hc_port(struct mv_host_priv *hpriv,
3049 void __iomem *mmio, unsigned int port)
3050{
3051 void __iomem *port_mmio = mv_port_base(mmio, port);
3052
e12bef50 3053 mv_reset_channel(hpriv, mmio, port);
f351b2d6
SB		 3054
3055 ZERO(0x028); /* command */
3056 writel(0x101f, port_mmio + EDMA_CFG_OFS);
3057 ZERO(0x004); /* timer */
3058 ZERO(0x008); /* irq err cause */
3059 ZERO(0x00c); /* irq err mask */
3060 ZERO(0x010); /* rq bah */
3061 ZERO(0x014); /* rq inp */
3062 ZERO(0x018); /* rq outp */
3063 ZERO(0x01c); /* respq bah */
3064 ZERO(0x024); /* respq outp */
3065 ZERO(0x020); /* respq inp */
3066 ZERO(0x02c); /* test control */
8e7decdb 3067 writel(0xbc, port_mmio + EDMA_IORDY_TMOUT_OFS);
f351b2d6
SB		 3068}
3069
3070#undef ZERO
3071
3072#define ZERO(reg) writel(0, hc_mmio + (reg))
3073static void mv_soc_reset_one_hc(struct mv_host_priv *hpriv,
3074 void __iomem *mmio)
3075{
3076 void __iomem *hc_mmio = mv_hc_base(mmio, 0);
3077
3078 ZERO(0x00c);
3079 ZERO(0x010);
3080 ZERO(0x014);
3081
3082}
3083
3084#undef ZERO
3085
3086static int mv_soc_reset_hc(struct mv_host_priv *hpriv,
3087 void __iomem *mmio, unsigned int n_hc)
3088{
3089 unsigned int port;
3090
3091 for (port = 0; port < hpriv->n_ports; port++)
3092 mv_soc_reset_hc_port(hpriv, mmio, port);
3093
3094 mv_soc_reset_one_hc(hpriv, mmio);
3095
3096 return 0;
3097}
3098
3099static void mv_soc_reset_flash(struct mv_host_priv *hpriv,
3100 void __iomem *mmio)
3101{
3102 return;
3103}
3104
3105static void mv_soc_reset_bus(struct ata_host *host, void __iomem *mmio)
3106{
3107 return;
3108}
3109
8e7decdb 3110static void mv_setup_ifcfg(void __iomem *port_mmio, int want_gen2i)
b67a1064 3111{
8e7decdb 3112 u32 ifcfg = readl(port_mmio + SATA_INTERFACE_CFG_OFS);
b67a1064 3113
8e7decdb 3114 ifcfg = (ifcfg & 0xf7f) | 0x9b1000; /* from chip spec */
b67a1064 3115 if (want_gen2i)
8e7decdb
ML		 3116 ifcfg |= (1 << 7); /* enable gen2i speed */
3117 writelfl(ifcfg, port_mmio + SATA_INTERFACE_CFG_OFS);
b67a1064
ML		 3118}
3119
e12bef50 3120static void mv_reset_channel(struct mv_host_priv *hpriv, void __iomem *mmio,
c9d39130
JG		 3121 unsigned int port_no)
3122{
3123 void __iomem *port_mmio = mv_port_base(mmio, port_no);
3124
8e7decdb
ML		 3125 /*
3126 * The datasheet warns against setting EDMA_RESET when EDMA is active
3127 * (but doesn't say what the problem might be). So we first try
3128 * to disable the EDMA engine before doing the EDMA_RESET operation.
3129 */
0d8be5cb 3130 mv_stop_edma_engine(port_mmio);
8e7decdb 3131 writelfl(EDMA_RESET, port_mmio + EDMA_CMD_OFS);
c9d39130 3132
b67a1064 3133 if (!IS_GEN_I(hpriv)) {
8e7decdb
ML		 3134 /* Enable 3.0gb/s link speed: this survives EDMA_RESET */
3135 mv_setup_ifcfg(port_mmio, 1);
c9d39130 3136 }
b67a1064 3137 /*
8e7decdb 3138 * Strobing EDMA_RESET here causes a hard reset of the SATA transport,
b67a1064
ML		 3139 * link, and physical layers. It resets all SATA interface registers
3140 * (except for SATA_INTERFACE_CFG), and issues a COMRESET to the dev.
c9d39130 3141 */
8e7decdb 3142 writelfl(EDMA_RESET, port_mmio + EDMA_CMD_OFS);
b67a1064 3143 udelay(25); /* allow reset propagation */
c9d39130
JG		 3144 writelfl(0, port_mmio + EDMA_CMD_OFS);
3145
3146 hpriv->ops->phy_errata(hpriv, mmio, port_no);
3147
ee9ccdf7 3148 if (IS_GEN_I(hpriv))
c9d39130
JG		 3149 mdelay(1);
3150}
3151
e49856d8 3152static void mv_pmp_select(struct ata_port *ap, int pmp)
20f733e7 3153{
e49856d8
ML		 3154 if (sata_pmp_supported(ap)) {
3155 void __iomem *port_mmio = mv_ap_base(ap);
3156 u32 reg = readl(port_mmio + SATA_IFCTL_OFS);
3157 int old = reg & 0xf;
22374677 3158
e49856d8
ML		 3159 if (old != pmp) {
3160 reg = (reg & ~0xf) | pmp;
3161 writelfl(reg, port_mmio + SATA_IFCTL_OFS);
3162 }
22374677 3163 }
20f733e7
BR		 3164}
3165
e49856d8
ML		 3166static int mv_pmp_hardreset(struct ata_link *link, unsigned int *class,
3167 unsigned long deadline)
22374677 3168{
e49856d8
ML		 3169 mv_pmp_select(link->ap, sata_srst_pmp(link));
3170 return sata_std_hardreset(link, class, deadline);
3171}
bdd4ddde 3172
e49856d8
ML		 3173static int mv_softreset(struct ata_link *link, unsigned int *class,
3174 unsigned long deadline)
3175{
3176 mv_pmp_select(link->ap, sata_srst_pmp(link));
3177 return ata_sff_softreset(link, class, deadline);
22374677
JG		 3178}
3179
cc0680a5 3180static int mv_hardreset(struct ata_link *link, unsigned int *class,
bdd4ddde 3181 unsigned long deadline)
31961943 3182{
cc0680a5 3183 struct ata_port *ap = link->ap;
bdd4ddde 3184 struct mv_host_priv *hpriv = ap->host->private_data;
b562468c 3185 struct mv_port_priv *pp = ap->private_data;
f351b2d6 3186 void __iomem *mmio = hpriv->base;
0d8be5cb
ML		 3187 int rc, attempts = 0, extra = 0;
3188 u32 sstatus;
3189 bool online;
31961943 3190
e12bef50 3191 mv_reset_channel(hpriv, mmio, ap->port_no);
b562468c 3192 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
d16ab3f6
ML		 3193 pp->pp_flags &=
3194 ~(MV_PP_FLAG_FBS_EN | MV_PP_FLAG_NCQ_EN | MV_PP_FLAG_FAKE_ATA_BUSY);
bdd4ddde 3195
0d8be5cb
ML		 3196 /* Workaround for errata FEr SATA#10 (part 2) */
3197 do {
17c5aab5
ML		 3198 const unsigned long *timing =
3199 sata_ehc_deb_timing(&link->eh_context);
bdd4ddde 3200
17c5aab5
ML		 3201 rc = sata_link_hardreset(link, timing, deadline + extra,
3202 &online, NULL);
9dcffd99 3203 rc = online ? -EAGAIN : rc;
17c5aab5 3204 if (rc)
0d8be5cb 3205 return rc;
0d8be5cb
ML		 3206 sata_scr_read(link, SCR_STATUS, &sstatus);
3207 if (!IS_GEN_I(hpriv) && ++attempts >= 5 && sstatus == 0x121) {
3208 /* Force 1.5gb/s link speed and try again */
8e7decdb 3209 mv_setup_ifcfg(mv_ap_base(ap), 0);
0d8be5cb
ML		 3210 if (time_after(jiffies + HZ, deadline))
3211 extra = HZ; /* only extend it once, max */
3212 }
3213 } while (sstatus != 0x0 && sstatus != 0x113 && sstatus != 0x123);
08da1759 3214 mv_save_cached_regs(ap);
66e57a2c 3215 mv_edma_cfg(ap, 0, 0);
bdd4ddde 3216
17c5aab5 3217 return rc;
bdd4ddde
JG		 3218}
3219
bdd4ddde
JG		 3220static void mv_eh_freeze(struct ata_port *ap)
3221{
1cfd19ae 3222 mv_stop_edma(ap);
c4de573b 3223 mv_enable_port_irqs(ap, 0);
bdd4ddde
JG		 3224}
3225
3226static void mv_eh_thaw(struct ata_port *ap)
3227{
f351b2d6 3228 struct mv_host_priv *hpriv = ap->host->private_data;
c4de573b
ML		 3229 unsigned int port = ap->port_no;
3230 unsigned int hardport = mv_hardport_from_port(port);
1cfd19ae 3231 void __iomem *hc_mmio = mv_hc_base_from_port(hpriv->base, port);
bdd4ddde 3232 void __iomem *port_mmio = mv_ap_base(ap);
c4de573b 3233 u32 hc_irq_cause;
bdd4ddde 3234
bdd4ddde
JG		 3235 /* clear EDMA errors on this port */
3236 writel(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
3237
3238 /* clear pending irq events */
cae6edc3 3239 hc_irq_cause = ~((DEV_IRQ | DMA_IRQ) << hardport);
1cfd19ae 3240 writelfl(hc_irq_cause, hc_mmio + HC_IRQ_CAUSE_OFS);
bdd4ddde 3241
88e675e1 3242 mv_enable_port_irqs(ap, ERR_IRQ);
31961943
BR		 3243}
3244
05b308e1
BR		 3245/**
3246 * mv_port_init - Perform some early initialization on a single port.
3247 * @port: libata data structure storing shadow register addresses
3248 * @port_mmio: base address of the port
3249 *
3250 * Initialize shadow register mmio addresses, clear outstanding
3251 * interrupts on the port, and unmask interrupts for the future
3252 * start of the port.
3253 *
3254 * LOCKING:
3255 * Inherited from caller.
3256 */
31961943 3257static void mv_port_init(struct ata_ioports *port, void __iomem *port_mmio)
20f733e7 3258{
0d5ff566 3259 void __iomem *shd_base = port_mmio + SHD_BLK_OFS;
31961943
BR		 3260 unsigned serr_ofs;
3261
8b260248 3262 /* PIO related setup
31961943
BR		 3263 */
3264 port->data_addr = shd_base + (sizeof(u32) * ATA_REG_DATA);
8b260248 3265 port->error_addr =
31961943
BR		 3266 port->feature_addr = shd_base + (sizeof(u32) * ATA_REG_ERR);
3267 port->nsect_addr = shd_base + (sizeof(u32) * ATA_REG_NSECT);
3268 port->lbal_addr = shd_base + (sizeof(u32) * ATA_REG_LBAL);
3269 port->lbam_addr = shd_base + (sizeof(u32) * ATA_REG_LBAM);
3270 port->lbah_addr = shd_base + (sizeof(u32) * ATA_REG_LBAH);
3271 port->device_addr = shd_base + (sizeof(u32) * ATA_REG_DEVICE);
8b260248 3272 port->status_addr =
31961943
BR		 3273 port->command_addr = shd_base + (sizeof(u32) * ATA_REG_STATUS);
3274 /* special case: control/altstatus doesn't have ATA_REG_ address */
3275 port->altstatus_addr = port->ctl_addr = shd_base + SHD_CTL_AST_OFS;
3276
3277 /* unused: */
8d9db2d2 3278 port->cmd_addr = port->bmdma_addr = port->scr_addr = NULL;
20f733e7 3279
31961943
BR		 3280 /* Clear any currently outstanding port interrupt conditions */
3281 serr_ofs = mv_scr_offset(SCR_ERROR);
3282 writelfl(readl(port_mmio + serr_ofs), port_mmio + serr_ofs);
3283 writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
3284
646a4da5
ML		 3285 /* unmask all non-transient EDMA error interrupts */
3286 writelfl(~EDMA_ERR_IRQ_TRANSIENT, port_mmio + EDMA_ERR_IRQ_MASK_OFS);
20f733e7 3287
8b260248 3288 VPRINTK("EDMA cfg=0x%08x EDMA IRQ err cause/mask=0x%08x/0x%08x\n",
31961943
BR		 3289 readl(port_mmio + EDMA_CFG_OFS),
3290 readl(port_mmio + EDMA_ERR_IRQ_CAUSE_OFS),
3291 readl(port_mmio + EDMA_ERR_IRQ_MASK_OFS));
20f733e7
BR		 3292}
3293
616d4a98
ML		 3294static unsigned int mv_in_pcix_mode(struct ata_host *host)
3295{
3296 struct mv_host_priv *hpriv = host->private_data;
3297 void __iomem *mmio = hpriv->base;
3298 u32 reg;
3299
1f398472 3300 if (IS_SOC(hpriv) || !IS_PCIE(hpriv))
616d4a98
ML		 3301 return 0; /* not PCI-X capable */
3302 reg = readl(mmio + MV_PCI_MODE_OFS);
3303 if ((reg & MV_PCI_MODE_MASK) == 0)
3304 return 0; /* conventional PCI mode */
3305 return 1; /* chip is in PCI-X mode */
3306}
3307
3308static int mv_pci_cut_through_okay(struct ata_host *host)
3309{
3310 struct mv_host_priv *hpriv = host->private_data;
3311 void __iomem *mmio = hpriv->base;
3312 u32 reg;
3313
3314 if (!mv_in_pcix_mode(host)) {
3315 reg = readl(mmio + PCI_COMMAND_OFS);
3316 if (reg & PCI_COMMAND_MRDTRIG)
3317 return 0; /* not okay */
3318 }
3319 return 1; /* okay */
3320}
3321
4447d351 3322static int mv_chip_id(struct ata_host *host, unsigned int board_idx)
bca1c4eb 3323{
4447d351
TH		 3324 struct pci_dev *pdev = to_pci_dev(host->dev);
3325 struct mv_host_priv *hpriv = host->private_data;
bca1c4eb
JG		 3326 u32 hp_flags = hpriv->hp_flags;
3327
5796d1c4 3328 switch (board_idx) {
47c2b677
JG		 3329 case chip_5080:
3330 hpriv->ops = &mv5xxx_ops;
ee9ccdf7 3331 hp_flags |= MV_HP_GEN_I;
47c2b677 3332
44c10138 3333 switch (pdev->revision) {
47c2b677
JG		 3334 case 0x1:
3335 hp_flags |= MV_HP_ERRATA_50XXB0;
3336 break;
3337 case 0x3:
3338 hp_flags |= MV_HP_ERRATA_50XXB2;
3339 break;
3340 default:
3341 dev_printk(KERN_WARNING, &pdev->dev,
3342 "Applying 50XXB2 workarounds to unknown rev\n");
3343 hp_flags |= MV_HP_ERRATA_50XXB2;
3344 break;
3345 }
3346 break;
3347
bca1c4eb
JG		 3348 case chip_504x:
3349 case chip_508x:
47c2b677 3350 hpriv->ops = &mv5xxx_ops;
ee9ccdf7 3351 hp_flags |= MV_HP_GEN_I;
bca1c4eb 3352
44c10138 3353 switch (pdev->revision) {
47c2b677
JG		 3354 case 0x0:
3355 hp_flags |= MV_HP_ERRATA_50XXB0;
3356 break;
3357 case 0x3:
3358 hp_flags |= MV_HP_ERRATA_50XXB2;
3359 break;
3360 default:
3361 dev_printk(KERN_WARNING, &pdev->dev,
3362 "Applying B2 workarounds to unknown rev\n");
3363 hp_flags |= MV_HP_ERRATA_50XXB2;
3364 break;
bca1c4eb
JG		 3365 }
3366 break;
3367
3368 case chip_604x:
3369 case chip_608x:
47c2b677 3370 hpriv->ops = &mv6xxx_ops;
ee9ccdf7 3371 hp_flags |= MV_HP_GEN_II;
47c2b677 3372
44c10138 3373 switch (pdev->revision) {
47c2b677
JG		 3374 case 0x7:
3375 hp_flags |= MV_HP_ERRATA_60X1B2;
3376 break;
3377 case 0x9:
3378 hp_flags |= MV_HP_ERRATA_60X1C0;
bca1c4eb
JG		 3379 break;
3380 default:
3381 dev_printk(KERN_WARNING, &pdev->dev,
47c2b677
JG		 3382 "Applying B2 workarounds to unknown rev\n");
3383 hp_flags |= MV_HP_ERRATA_60X1B2;
bca1c4eb
JG		 3384 break;
3385 }
3386 break;
3387
e4e7b892 3388 case chip_7042:
616d4a98 3389 hp_flags |= MV_HP_PCIE | MV_HP_CUT_THROUGH;
306b30f7
ML		 3390 if (pdev->vendor == PCI_VENDOR_ID_TTI &&
3391 (pdev->device == 0x2300 || pdev->device == 0x2310))
3392 {
4e520033
ML		 3393 /*
3394 * Highpoint RocketRAID PCIe 23xx series cards:
3395 *
3396 * Unconfigured drives are treated as "Legacy"
3397 * by the BIOS, and it overwrites sector 8 with
3398 * a "Lgcy" metadata block prior to Linux boot.
3399 *
3400 * Configured drives (RAID or JBOD) leave sector 8
3401 * alone, but instead overwrite a high numbered
3402 * sector for the RAID metadata. This sector can
3403 * be determined exactly, by truncating the physical
3404 * drive capacity to a nice even GB value.
3405 *
3406 * RAID metadata is at: (dev->n_sectors & ~0xfffff)
3407 *
3408 * Warn the user, lest they think we're just buggy.
3409 */
3410 printk(KERN_WARNING DRV_NAME ": Highpoint RocketRAID"
3411 " BIOS CORRUPTS DATA on all attached drives,"
3412 " regardless of if/how they are configured."
3413 " BEWARE!\n");
3414 printk(KERN_WARNING DRV_NAME ": For data safety, do not"
3415 " use sectors 8-9 on \"Legacy\" drives,"
3416 " and avoid the final two gigabytes on"
3417 " all RocketRAID BIOS initialized drives.\n");
306b30f7 3418 }
8e7decdb 3419 /* drop through */
e4e7b892
JG		 3420 case chip_6042:
3421 hpriv->ops = &mv6xxx_ops;
e4e7b892 3422 hp_flags |= MV_HP_GEN_IIE;
616d4a98
ML		 3423 if (board_idx == chip_6042 && mv_pci_cut_through_okay(host))
3424 hp_flags |= MV_HP_CUT_THROUGH;
e4e7b892 3425
44c10138 3426 switch (pdev->revision) {
5cf73bfb 3427 case 0x2: /* Rev.B0: the first/only public release */
e4e7b892
JG		 3428 hp_flags |= MV_HP_ERRATA_60X1C0;
3429 break;
3430 default:
3431 dev_printk(KERN_WARNING, &pdev->dev,
3432 "Applying 60X1C0 workarounds to unknown rev\n");
3433 hp_flags |= MV_HP_ERRATA_60X1C0;
3434 break;
3435 }
3436 break;
f351b2d6
SB		 3437 case chip_soc:
3438 hpriv->ops = &mv_soc_ops;
eb3a55a9
SB		 3439 hp_flags |= MV_HP_FLAG_SOC | MV_HP_GEN_IIE |
3440 MV_HP_ERRATA_60X1C0;
f351b2d6 3441 break;
e4e7b892 3442
bca1c4eb 3443 default:
f351b2d6 3444 dev_printk(KERN_ERR, host->dev,
5796d1c4 3445 "BUG: invalid board index %u\n", board_idx);
bca1c4eb
JG		 3446 return 1;
3447 }
3448
3449 hpriv->hp_flags = hp_flags;
02a121da
ML		 3450 if (hp_flags & MV_HP_PCIE) {
3451 hpriv->irq_cause_ofs = PCIE_IRQ_CAUSE_OFS;
3452 hpriv->irq_mask_ofs = PCIE_IRQ_MASK_OFS;
3453 hpriv->unmask_all_irqs = PCIE_UNMASK_ALL_IRQS;
3454 } else {
3455 hpriv->irq_cause_ofs = PCI_IRQ_CAUSE_OFS;
3456 hpriv->irq_mask_ofs = PCI_IRQ_MASK_OFS;
3457 hpriv->unmask_all_irqs = PCI_UNMASK_ALL_IRQS;
3458 }
bca1c4eb
JG		 3459
3460 return 0;
3461}
3462
05b308e1 3463/**
47c2b677 3464 * mv_init_host - Perform some early initialization of the host.
4447d351
TH		 3465 * @host: ATA host to initialize
3466 * @board_idx: controller index
05b308e1
BR		 3467 *
3468 * If possible, do an early global reset of the host. Then do
3469 * our port init and clear/unmask all/relevant host interrupts.
3470 *
3471 * LOCKING:
3472 * Inherited from caller.
3473 */
4447d351 3474static int mv_init_host(struct ata_host *host, unsigned int board_idx)
20f733e7
BR		 3475{
3476 int rc = 0, n_hc, port, hc;
4447d351 3477 struct mv_host_priv *hpriv = host->private_data;
f351b2d6 3478 void __iomem *mmio = hpriv->base;
47c2b677 3479
4447d351 3480 rc = mv_chip_id(host, board_idx);
bca1c4eb 3481 if (rc)
352fab70 3482 goto done;
f351b2d6 3483
1f398472 3484 if (IS_SOC(hpriv)) {
7368f919
ML		 3485 hpriv->main_irq_cause_addr = mmio + SOC_HC_MAIN_IRQ_CAUSE_OFS;
3486 hpriv->main_irq_mask_addr = mmio + SOC_HC_MAIN_IRQ_MASK_OFS;
1f398472
ML		 3487 } else {
3488 hpriv->main_irq_cause_addr = mmio + PCI_HC_MAIN_IRQ_CAUSE_OFS;
3489 hpriv->main_irq_mask_addr = mmio + PCI_HC_MAIN_IRQ_MASK_OFS;
f351b2d6 3490 }
352fab70 3491
5d0fb2e7
TR		 3492 /* initialize shadow irq mask with register's value */
3493 hpriv->main_irq_mask = readl(hpriv->main_irq_mask_addr);
3494
352fab70 3495 /* global interrupt mask: 0 == mask everything */
c4de573b 3496 mv_set_main_irq_mask(host, ~0, 0);
bca1c4eb 3497
4447d351 3498 n_hc = mv_get_hc_count(host->ports[0]->flags);
bca1c4eb 3499
4447d351 3500 for (port = 0; port < host->n_ports; port++)
47c2b677 3501 hpriv->ops->read_preamp(hpriv, port, mmio);
20f733e7 3502
c9d39130 3503 rc = hpriv->ops->reset_hc(hpriv, mmio, n_hc);
47c2b677 3504 if (rc)
20f733e7 3505 goto done;
20f733e7 3506
522479fb 3507 hpriv->ops->reset_flash(hpriv, mmio);
7bb3c529 3508 hpriv->ops->reset_bus(host, mmio);
47c2b677 3509 hpriv->ops->enable_leds(hpriv, mmio);
20f733e7 3510
4447d351 3511 for (port = 0; port < host->n_ports; port++) {
cbcdd875 3512 struct ata_port *ap = host->ports[port];
2a47ce06 3513 void __iomem *port_mmio = mv_port_base(mmio, port);
cbcdd875
TH		 3514
3515 mv_port_init(&ap->ioaddr, port_mmio);
3516
7bb3c529 3517#ifdef CONFIG_PCI
1f398472 3518 if (!IS_SOC(hpriv)) {
f351b2d6
SB		 3519 unsigned int offset = port_mmio - mmio;
3520 ata_port_pbar_desc(ap, MV_PRIMARY_BAR, -1, "mmio");
3521 ata_port_pbar_desc(ap, MV_PRIMARY_BAR, offset, "port");
3522 }
7bb3c529 3523#endif
20f733e7
BR		 3524 }
3525
3526 for (hc = 0; hc < n_hc; hc++) {
31961943
BR		 3527 void __iomem *hc_mmio = mv_hc_base(mmio, hc);
3528
3529 VPRINTK("HC%i: HC config=0x%08x HC IRQ cause "
3530 "(before clear)=0x%08x\n", hc,
3531 readl(hc_mmio + HC_CFG_OFS),
3532 readl(hc_mmio + HC_IRQ_CAUSE_OFS));
3533
3534 /* Clear any currently outstanding hc interrupt conditions */
3535 writelfl(0, hc_mmio + HC_IRQ_CAUSE_OFS);
20f733e7
BR		 3536 }
3537
6be96ac1
ML		 3538 /* Clear any currently outstanding host interrupt conditions */
3539 writelfl(0, mmio + hpriv->irq_cause_ofs);
31961943 3540
6be96ac1
ML		 3541 /* and unmask interrupt generation for host regs */
3542 writelfl(hpriv->unmask_all_irqs, mmio + hpriv->irq_mask_ofs);
51de32d2 3543
6be96ac1
ML		 3544 /*
3545 * enable only global host interrupts for now.
3546 * The per-port interrupts get done later as ports are set up.
3547 */
3548 mv_set_main_irq_mask(host, 0, PCI_ERR);
f351b2d6
SB		 3549done:
3550 return rc;
3551}
fb621e2f 3552
fbf14e2f
BB		 3553static int mv_create_dma_pools(struct mv_host_priv *hpriv, struct device *dev)
3554{
3555 hpriv->crqb_pool = dmam_pool_create("crqb_q", dev, MV_CRQB_Q_SZ,
3556 MV_CRQB_Q_SZ, 0);
3557 if (!hpriv->crqb_pool)
3558 return -ENOMEM;
3559
3560 hpriv->crpb_pool = dmam_pool_create("crpb_q", dev, MV_CRPB_Q_SZ,
3561 MV_CRPB_Q_SZ, 0);
3562 if (!hpriv->crpb_pool)
3563 return -ENOMEM;
3564
3565 hpriv->sg_tbl_pool = dmam_pool_create("sg_tbl", dev, MV_SG_TBL_SZ,
3566 MV_SG_TBL_SZ, 0);
3567 if (!hpriv->sg_tbl_pool)
3568 return -ENOMEM;
3569
3570 return 0;
3571}
3572
15a32632
LB		 3573static void mv_conf_mbus_windows(struct mv_host_priv *hpriv,
3574 struct mbus_dram_target_info *dram)
3575{
3576 int i;
3577
3578 for (i = 0; i < 4; i++) {
3579 writel(0, hpriv->base + WINDOW_CTRL(i));
3580 writel(0, hpriv->base + WINDOW_BASE(i));
3581 }
3582
3583 for (i = 0; i < dram->num_cs; i++) {
3584 struct mbus_dram_window *cs = dram->cs + i;
3585
3586 writel(((cs->size - 1) & 0xffff0000) |
3587 (cs->mbus_attr << 8) |
3588 (dram->mbus_dram_target_id << 4) | 1,
3589 hpriv->base + WINDOW_CTRL(i));
3590 writel(cs->base, hpriv->base + WINDOW_BASE(i));
3591 }
3592}
3593
f351b2d6
SB		 3594/**
3595 * mv_platform_probe - handle a positive probe of an soc Marvell
3596 * host
3597 * @pdev: platform device found
3598 *
3599 * LOCKING:
3600 * Inherited from caller.
3601 */
3602static int mv_platform_probe(struct platform_device *pdev)
3603{
3604 static int printed_version;
3605 const struct mv_sata_platform_data *mv_platform_data;
3606 const struct ata_port_info *ppi[] =
3607 { &mv_port_info[chip_soc], NULL };
3608 struct ata_host *host;
3609 struct mv_host_priv *hpriv;
3610 struct resource *res;
3611 int n_ports, rc;
20f733e7 3612
f351b2d6
SB		 3613 if (!printed_version++)
3614 dev_printk(KERN_INFO, &pdev->dev, "version " DRV_VERSION "\n");
bca1c4eb 3615
f351b2d6
SB		 3616 /*
3617 * Simple resource validation ..
3618 */
3619 if (unlikely(pdev->num_resources != 2)) {
3620 dev_err(&pdev->dev, "invalid number of resources\n");
3621 return -EINVAL;
3622 }
3623
3624 /*
3625 * Get the register base first
3626 */
3627 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3628 if (res == NULL)
3629 return -EINVAL;
3630
3631 /* allocate host */
3632 mv_platform_data = pdev->dev.platform_data;
3633 n_ports = mv_platform_data->n_ports;
3634
3635 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
3636 hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL);
3637
3638 if (!host || !hpriv)
3639 return -ENOMEM;
3640 host->private_data = hpriv;
3641 hpriv->n_ports = n_ports;
3642
3643 host->iomap = NULL;
f1cb0ea1
SB		 3644 hpriv->base = devm_ioremap(&pdev->dev, res->start,
3645 res->end - res->start + 1);
f351b2d6
SB		 3646 hpriv->base -= MV_SATAHC0_REG_BASE;
3647
15a32632
LB		 3648 /*
3649 * (Re-)program MBUS remapping windows if we are asked to.
3650 */
3651 if (mv_platform_data->dram != NULL)
3652 mv_conf_mbus_windows(hpriv, mv_platform_data->dram);
3653
fbf14e2f
BB		 3654 rc = mv_create_dma_pools(hpriv, &pdev->dev);
3655 if (rc)
3656 return rc;
3657
f351b2d6
SB		 3658 /* initialize adapter */
3659 rc = mv_init_host(host, chip_soc);
3660 if (rc)
3661 return rc;
3662
3663 dev_printk(KERN_INFO, &pdev->dev,
3664 "slots %u ports %d\n", (unsigned)MV_MAX_Q_DEPTH,
3665 host->n_ports);
3666
3667 return ata_host_activate(host, platform_get_irq(pdev, 0), mv_interrupt,
3668 IRQF_SHARED, &mv6_sht);
3669}
3670
3671/*
3672 *
3673 * mv_platform_remove - unplug a platform interface
3674 * @pdev: platform device
3675 *
3676 * A platform bus SATA device has been unplugged. Perform the needed
3677 * cleanup. Also called on module unload for any active devices.
3678 */
3679static int __devexit mv_platform_remove(struct platform_device *pdev)
3680{
3681 struct device *dev = &pdev->dev;
3682 struct ata_host *host = dev_get_drvdata(dev);
f351b2d6
SB		 3683
3684 ata_host_detach(host);
f351b2d6 3685 return 0;
20f733e7
BR		 3686}
3687
f351b2d6
SB		 3688static struct platform_driver mv_platform_driver = {
3689 .probe = mv_platform_probe,
3690 .remove = __devexit_p(mv_platform_remove),
3691 .driver = {
3692 .name = DRV_NAME,
3693 .owner = THIS_MODULE,
3694 },
3695};
3696
3697
7bb3c529 3698#ifdef CONFIG_PCI
f351b2d6
SB		 3699static int mv_pci_init_one(struct pci_dev *pdev,
3700 const struct pci_device_id *ent);
3701
7bb3c529
SB		 3702
3703static struct pci_driver mv_pci_driver = {
3704 .name = DRV_NAME,
3705 .id_table = mv_pci_tbl,
f351b2d6 3706 .probe = mv_pci_init_one,
7bb3c529
SB		 3707 .remove = ata_pci_remove_one,
3708};
3709
7bb3c529
SB		 3710/* move to PCI layer or libata core? */
3711static int pci_go_64(struct pci_dev *pdev)
3712{
3713 int rc;
3714
3715 if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
3716 rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
3717 if (rc) {
3718 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
3719 if (rc) {
3720 dev_printk(KERN_ERR, &pdev->dev,
3721 "64-bit DMA enable failed\n");
3722 return rc;
3723 }
3724 }
3725 } else {
3726 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
3727 if (rc) {
3728 dev_printk(KERN_ERR, &pdev->dev,
3729 "32-bit DMA enable failed\n");
3730 return rc;
3731 }
3732 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
3733 if (rc) {
3734 dev_printk(KERN_ERR, &pdev->dev,
3735 "32-bit consistent DMA enable failed\n");
3736 return rc;
3737 }
3738 }
3739
3740 return rc;
3741}
3742
05b308e1
BR		 3743/**
3744 * mv_print_info - Dump key info to kernel log for perusal.
4447d351 3745 * @host: ATA host to print info about
05b308e1
BR		 3746 *
3747 * FIXME: complete this.
3748 *
3749 * LOCKING:
3750 * Inherited from caller.
3751 */
4447d351 3752static void mv_print_info(struct ata_host *host)
31961943 3753{
4447d351
TH		 3754 struct pci_dev *pdev = to_pci_dev(host->dev);
3755 struct mv_host_priv *hpriv = host->private_data;
44c10138 3756 u8 scc;
c1e4fe71 3757 const char *scc_s, *gen;
31961943
BR		 3758
3759 /* Use this to determine the HW stepping of the chip so we know
3760 * what errata to workaround
3761 */
31961943
BR		 3762 pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &scc);
3763 if (scc == 0)
3764 scc_s = "SCSI";
3765 else if (scc == 0x01)
3766 scc_s = "RAID";
3767 else
c1e4fe71
JG		 3768 scc_s = "?";
3769
3770 if (IS_GEN_I(hpriv))
3771 gen = "I";
3772 else if (IS_GEN_II(hpriv))
3773 gen = "II";
3774 else if (IS_GEN_IIE(hpriv))
3775 gen = "IIE";
3776 else
3777 gen = "?";
31961943 3778
a9524a76 3779 dev_printk(KERN_INFO, &pdev->dev,
c1e4fe71
JG		 3780 "Gen-%s %u slots %u ports %s mode IRQ via %s\n",
3781 gen, (unsigned)MV_MAX_Q_DEPTH, host->n_ports,
31961943
BR		 3782 scc_s, (MV_HP_FLAG_MSI & hpriv->hp_flags) ? "MSI" : "INTx");
3783}
3784
05b308e1 3785/**
f351b2d6 3786 * mv_pci_init_one - handle a positive probe of a PCI Marvell host
05b308e1
BR		 3787 * @pdev: PCI device found
3788 * @ent: PCI device ID entry for the matched host
3789 *
3790 * LOCKING:
3791 * Inherited from caller.
3792 */
f351b2d6
SB		 3793static int mv_pci_init_one(struct pci_dev *pdev,
3794 const struct pci_device_id *ent)
20f733e7 3795{
2dcb407e 3796 static int printed_version;
20f733e7 3797 unsigned int board_idx = (unsigned int)ent->driver_data;
4447d351
TH		 3798 const struct ata_port_info *ppi[] = { &mv_port_info[board_idx], NULL };
3799 struct ata_host *host;
3800 struct mv_host_priv *hpriv;
3801 int n_ports, rc;
20f733e7 3802
a9524a76
JG		 3803 if (!printed_version++)
3804 dev_printk(KERN_INFO, &pdev->dev, "version " DRV_VERSION "\n");
20f733e7 3805
4447d351
TH		 3806 /* allocate host */
3807 n_ports = mv_get_hc_count(ppi[0]->flags) * MV_PORTS_PER_HC;
3808
3809 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
3810 hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL);
3811 if (!host || !hpriv)
3812 return -ENOMEM;
3813 host->private_data = hpriv;
f351b2d6 3814 hpriv->n_ports = n_ports;
4447d351
TH		 3815
3816 /* acquire resources */
24dc5f33
TH		 3817 rc = pcim_enable_device(pdev);
3818 if (rc)
20f733e7 3819 return rc;
20f733e7 3820
0d5ff566
TH		 3821 rc = pcim_iomap_regions(pdev, 1 << MV_PRIMARY_BAR, DRV_NAME);
3822 if (rc == -EBUSY)
24dc5f33 3823 pcim_pin_device(pdev);
0d5ff566 3824 if (rc)
24dc5f33 3825 return rc;
4447d351 3826 host->iomap = pcim_iomap_table(pdev);
f351b2d6 3827 hpriv->base = host->iomap[MV_PRIMARY_BAR];
20f733e7 3828
d88184fb
JG		 3829 rc = pci_go_64(pdev);
3830 if (rc)
3831 return rc;
3832
da2fa9ba
ML		 3833 rc = mv_create_dma_pools(hpriv, &pdev->dev);
3834 if (rc)
3835 return rc;
3836
20f733e7 3837 /* initialize adapter */
4447d351 3838 rc = mv_init_host(host, board_idx);
24dc5f33
TH		 3839 if (rc)
3840 return rc;
20f733e7 3841
6d3c30ef
ML		 3842 /* Enable message-switched interrupts, if requested */
3843 if (msi && pci_enable_msi(pdev) == 0)
3844 hpriv->hp_flags |= MV_HP_FLAG_MSI;
20f733e7 3845
31961943 3846 mv_dump_pci_cfg(pdev, 0x68);
4447d351 3847 mv_print_info(host);
20f733e7 3848
4447d351 3849 pci_set_master(pdev);
ea8b4db9 3850 pci_try_set_mwi(pdev);
4447d351 3851 return ata_host_activate(host, pdev->irq, mv_interrupt, IRQF_SHARED,
c5d3e45a 3852 IS_GEN_I(hpriv) ? &mv5_sht : &mv6_sht);
20f733e7 3853}
7bb3c529 3854#endif
20f733e7 3855
f351b2d6
SB		 3856static int mv_platform_probe(struct platform_device *pdev);
3857static int __devexit mv_platform_remove(struct platform_device *pdev);
3858
20f733e7
BR		 3859static int __init mv_init(void)
3860{
7bb3c529
SB		 3861 int rc = -ENODEV;
3862#ifdef CONFIG_PCI
3863 rc = pci_register_driver(&mv_pci_driver);
f351b2d6
SB		 3864 if (rc < 0)
3865 return rc;
3866#endif
3867 rc = platform_driver_register(&mv_platform_driver);
3868
3869#ifdef CONFIG_PCI
3870 if (rc < 0)
3871 pci_unregister_driver(&mv_pci_driver);
7bb3c529
SB		 3872#endif
3873 return rc;
20f733e7
BR		 3874}
3875
3876static void __exit mv_exit(void)
3877{
7bb3c529 3878#ifdef CONFIG_PCI
20f733e7 3879 pci_unregister_driver(&mv_pci_driver);
7bb3c529 3880#endif
f351b2d6 3881 platform_driver_unregister(&mv_platform_driver);
20f733e7
BR		 3882}
3883
3884MODULE_AUTHOR("Brett Russ");
3885MODULE_DESCRIPTION("SCSI low-level driver for Marvell SATA controllers");
3886MODULE_LICENSE("GPL");
3887MODULE_DEVICE_TABLE(pci, mv_pci_tbl);
3888MODULE_VERSION(DRV_VERSION);
17c5aab5 3889MODULE_ALIAS("platform:" DRV_NAME);
20f733e7
BR		 3890
3891module_init(mv_init);
3892module_exit(mv_exit);
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