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Merge git://git.kernel.org/pub/scm/linux/kernel/git/davem/net-2.6
[linux-2.6-block.git] / drivers / ata / sata_mv.c
CommitLineData
20f733e7
BR		 1/*
2 * sata_mv.c - Marvell SATA support
3 *
e12bef50 4 * Copyright 2008: Marvell Corporation, all rights reserved.
8b260248 5 * Copyright 2005: EMC Corporation, all rights reserved.
e2b1be56 6 * Copyright 2005 Red Hat, Inc. All rights reserved.
20f733e7
BR		 7 *
8 * Please ALWAYS copy linux-ide@vger.kernel.org on emails.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; version 2 of the License.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 *
23 */
24
4a05e209 25/*
85afb934
ML		 26 * sata_mv TODO list:
27 *
28 * --> Errata workaround for NCQ device errors.
29 *
30 * --> More errata workarounds for PCI-X.
31 *
32 * --> Complete a full errata audit for all chipsets to identify others.
33 *
34 * --> ATAPI support (Marvell claims the 60xx/70xx chips can do it).
35 *
36 * --> Investigate problems with PCI Message Signalled Interrupts (MSI).
37 *
38 * --> Cache frequently-accessed registers in mv_port_priv to reduce overhead.
39 *
40 * --> Develop a low-power-consumption strategy, and implement it.
41 *
42 * --> [Experiment, low priority] Investigate interrupt coalescing.
43 * Quite often, especially with PCI Message Signalled Interrupts (MSI),
44 * the overhead reduced by interrupt mitigation is quite often not
45 * worth the latency cost.
46 *
47 * --> [Experiment, Marvell value added] Is it possible to use target
48 * mode to cross-connect two Linux boxes with Marvell cards? If so,
49 * creating LibATA target mode support would be very interesting.
50 *
51 * Target mode, for those without docs, is the ability to directly
52 * connect two SATA ports.
53 */
4a05e209 54
20f733e7
BR		 55#include <linux/kernel.h>
56#include <linux/module.h>
57#include <linux/pci.h>
58#include <linux/init.h>
59#include <linux/blkdev.h>
60#include <linux/delay.h>
61#include <linux/interrupt.h>
8d8b6004 62#include <linux/dmapool.h>
20f733e7 63#include <linux/dma-mapping.h>
a9524a76 64#include <linux/device.h>
f351b2d6
SB		 65#include <linux/platform_device.h>
66#include <linux/ata_platform.h>
15a32632 67#include <linux/mbus.h>
c46938cc 68#include <linux/bitops.h>
20f733e7 69#include <scsi/scsi_host.h>
193515d5 70#include <scsi/scsi_cmnd.h>
6c08772e 71#include <scsi/scsi_device.h>
20f733e7 72#include <linux/libata.h>
20f733e7
BR		 73
74#define DRV_NAME "sata_mv"
06aaca3f 75#define DRV_VERSION "1.21"
20f733e7
BR		 76
77enum {
78 /* BAR's are enumerated in terms of pci_resource_start() terms */
79 MV_PRIMARY_BAR = 0, /* offset 0x10: memory space */
80 MV_IO_BAR = 2, /* offset 0x18: IO space */
81 MV_MISC_BAR = 3, /* offset 0x1c: FLASH, NVRAM, SRAM */
82
83 MV_MAJOR_REG_AREA_SZ = 0x10000, /* 64KB */
84 MV_MINOR_REG_AREA_SZ = 0x2000, /* 8KB */
85
86 MV_PCI_REG_BASE = 0,
87 MV_IRQ_COAL_REG_BASE = 0x18000, /* 6xxx part only */
615ab953
ML		 88 MV_IRQ_COAL_CAUSE = (MV_IRQ_COAL_REG_BASE + 0x08),
89 MV_IRQ_COAL_CAUSE_LO = (MV_IRQ_COAL_REG_BASE + 0x88),
90 MV_IRQ_COAL_CAUSE_HI = (MV_IRQ_COAL_REG_BASE + 0x8c),
91 MV_IRQ_COAL_THRESHOLD = (MV_IRQ_COAL_REG_BASE + 0xcc),
92 MV_IRQ_COAL_TIME_THRESHOLD = (MV_IRQ_COAL_REG_BASE + 0xd0),
93
20f733e7 94 MV_SATAHC0_REG_BASE = 0x20000,
8e7decdb
ML		 95 MV_FLASH_CTL_OFS = 0x1046c,
96 MV_GPIO_PORT_CTL_OFS = 0x104f0,
97 MV_RESET_CFG_OFS = 0x180d8,
20f733e7
BR		 98
99 MV_PCI_REG_SZ = MV_MAJOR_REG_AREA_SZ,
100 MV_SATAHC_REG_SZ = MV_MAJOR_REG_AREA_SZ,
101 MV_SATAHC_ARBTR_REG_SZ = MV_MINOR_REG_AREA_SZ, /* arbiter */
102 MV_PORT_REG_SZ = MV_MINOR_REG_AREA_SZ,
103
31961943
BR		 104 MV_MAX_Q_DEPTH = 32,
105 MV_MAX_Q_DEPTH_MASK = MV_MAX_Q_DEPTH - 1,
106
107 /* CRQB needs alignment on a 1KB boundary. Size == 1KB
108 * CRPB needs alignment on a 256B boundary. Size == 256B
31961943
BR		 109 * ePRD (SG) entries need alignment on a 16B boundary. Size == 16B
110 */
111 MV_CRQB_Q_SZ = (32 * MV_MAX_Q_DEPTH),
112 MV_CRPB_Q_SZ = (8 * MV_MAX_Q_DEPTH),
da2fa9ba 113 MV_MAX_SG_CT = 256,
31961943 114 MV_SG_TBL_SZ = (16 * MV_MAX_SG_CT),
31961943 115
352fab70 116 /* Determine hc from 0-7 port: hc = port >> MV_PORT_HC_SHIFT */
20f733e7 117 MV_PORT_HC_SHIFT = 2,
352fab70
ML		 118 MV_PORTS_PER_HC = (1 << MV_PORT_HC_SHIFT), /* 4 */
119 /* Determine hc port from 0-7 port: hardport = port & MV_PORT_MASK */
120 MV_PORT_MASK = (MV_PORTS_PER_HC - 1), /* 3 */
20f733e7
BR		 121
122 /* Host Flags */
123 MV_FLAG_DUAL_HC = (1 << 30), /* two SATA Host Controllers */
124 MV_FLAG_IRQ_COALESCE = (1 << 29), /* IRQ coalescing capability */
7bb3c529 125 /* SoC integrated controllers, no PCI interface */
e12bef50 126 MV_FLAG_SOC = (1 << 28),
7bb3c529 127
c5d3e45a 128 MV_COMMON_FLAGS = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
bdd4ddde
JG		 129 ATA_FLAG_MMIO | ATA_FLAG_NO_ATAPI |
130 ATA_FLAG_PIO_POLLING,
ad3aef51 131
47c2b677 132 MV_6XXX_FLAGS = MV_FLAG_IRQ_COALESCE,
20f733e7 133
ad3aef51
ML		 134 MV_GENIIE_FLAGS = MV_COMMON_FLAGS | MV_6XXX_FLAGS |
135 ATA_FLAG_PMP | ATA_FLAG_ACPI_SATA |
c443c500 136 ATA_FLAG_NCQ | ATA_FLAG_AN,
ad3aef51 137
31961943
BR		 138 CRQB_FLAG_READ = (1 << 0),
139 CRQB_TAG_SHIFT = 1,
c5d3e45a 140 CRQB_IOID_SHIFT = 6, /* CRQB Gen-II/IIE IO Id shift */
e12bef50 141 CRQB_PMP_SHIFT = 12, /* CRQB Gen-II/IIE PMP shift */
c5d3e45a 142 CRQB_HOSTQ_SHIFT = 17, /* CRQB Gen-II/IIE HostQueTag shift */
31961943
BR		 143 CRQB_CMD_ADDR_SHIFT = 8,
144 CRQB_CMD_CS = (0x2 << 11),
145 CRQB_CMD_LAST = (1 << 15),
146
147 CRPB_FLAG_STATUS_SHIFT = 8,
c5d3e45a
JG		 148 CRPB_IOID_SHIFT_6 = 5, /* CRPB Gen-II IO Id shift */
149 CRPB_IOID_SHIFT_7 = 7, /* CRPB Gen-IIE IO Id shift */
31961943
BR		 150
151 EPRD_FLAG_END_OF_TBL = (1 << 31),
152
20f733e7
BR		 153 /* PCI interface registers */
154
31961943 155 PCI_COMMAND_OFS = 0xc00,
8e7decdb 156 PCI_COMMAND_MRDTRIG = (1 << 7), /* PCI Master Read Trigger */
31961943 157
20f733e7
BR		 158 PCI_MAIN_CMD_STS_OFS = 0xd30,
159 STOP_PCI_MASTER = (1 << 2),
160 PCI_MASTER_EMPTY = (1 << 3),
161 GLOB_SFT_RST = (1 << 4),
162
8e7decdb
ML		 163 MV_PCI_MODE_OFS = 0xd00,
164 MV_PCI_MODE_MASK = 0x30,
165
522479fb
JG		 166 MV_PCI_EXP_ROM_BAR_CTL = 0xd2c,
167 MV_PCI_DISC_TIMER = 0xd04,
168 MV_PCI_MSI_TRIGGER = 0xc38,
169 MV_PCI_SERR_MASK = 0xc28,
8e7decdb 170 MV_PCI_XBAR_TMOUT_OFS = 0x1d04,
522479fb
JG		 171 MV_PCI_ERR_LOW_ADDRESS = 0x1d40,
172 MV_PCI_ERR_HIGH_ADDRESS = 0x1d44,
173 MV_PCI_ERR_ATTRIBUTE = 0x1d48,
174 MV_PCI_ERR_COMMAND = 0x1d50,
175
02a121da
ML		 176 PCI_IRQ_CAUSE_OFS = 0x1d58,
177 PCI_IRQ_MASK_OFS = 0x1d5c,
20f733e7
BR		 178 PCI_UNMASK_ALL_IRQS = 0x7fffff, /* bits 22-0 */
179
02a121da
ML		 180 PCIE_IRQ_CAUSE_OFS = 0x1900,
181 PCIE_IRQ_MASK_OFS = 0x1910,
646a4da5 182 PCIE_UNMASK_ALL_IRQS = 0x40a, /* assorted bits */
02a121da 183
7368f919
ML		 184 /* Host Controller Main Interrupt Cause/Mask registers (1 per-chip) */
185 PCI_HC_MAIN_IRQ_CAUSE_OFS = 0x1d60,
186 PCI_HC_MAIN_IRQ_MASK_OFS = 0x1d64,
187 SOC_HC_MAIN_IRQ_CAUSE_OFS = 0x20020,
188 SOC_HC_MAIN_IRQ_MASK_OFS = 0x20024,
352fab70
ML		 189 ERR_IRQ = (1 << 0), /* shift by port # */
190 DONE_IRQ = (1 << 1), /* shift by port # */
20f733e7
BR		 191 HC0_IRQ_PEND = 0x1ff, /* bits 0-8 = HC0's ports */
192 HC_SHIFT = 9, /* bits 9-17 = HC1's ports */
193 PCI_ERR = (1 << 18),
194 TRAN_LO_DONE = (1 << 19), /* 6xxx: IRQ coalescing */
195 TRAN_HI_DONE = (1 << 20), /* 6xxx: IRQ coalescing */
fb621e2f
JG		 196 PORTS_0_3_COAL_DONE = (1 << 8),
197 PORTS_4_7_COAL_DONE = (1 << 17),
20f733e7
BR		 198 PORTS_0_7_COAL_DONE = (1 << 21), /* 6xxx: IRQ coalescing */
199 GPIO_INT = (1 << 22),
200 SELF_INT = (1 << 23),
201 TWSI_INT = (1 << 24),
202 HC_MAIN_RSVD = (0x7f << 25), /* bits 31-25 */
fb621e2f 203 HC_MAIN_RSVD_5 = (0x1fff << 19), /* bits 31-19 */
e12bef50 204 HC_MAIN_RSVD_SOC = (0x3fffffb << 6), /* bits 31-9, 7-6 */
20f733e7
BR		 205
206 /* SATAHC registers */
207 HC_CFG_OFS = 0,
208
209 HC_IRQ_CAUSE_OFS = 0x14,
352fab70
ML		 210 DMA_IRQ = (1 << 0), /* shift by port # */
211 HC_COAL_IRQ = (1 << 4), /* IRQ coalescing */
20f733e7
BR		 212 DEV_IRQ = (1 << 8), /* shift by port # */
213
214 /* Shadow block registers */
31961943
BR		 215 SHD_BLK_OFS = 0x100,
216 SHD_CTL_AST_OFS = 0x20, /* ofs from SHD_BLK_OFS */
20f733e7
BR		 217
218 /* SATA registers */
219 SATA_STATUS_OFS = 0x300, /* ctrl, err regs follow status */
220 SATA_ACTIVE_OFS = 0x350,
0c58912e 221 SATA_FIS_IRQ_CAUSE_OFS = 0x364,
c443c500 222 SATA_FIS_IRQ_AN = (1 << 9), /* async notification */
17c5aab5 223
e12bef50 224 LTMODE_OFS = 0x30c,
17c5aab5
ML		 225 LTMODE_BIT8 = (1 << 8), /* unknown, but necessary */
226
47c2b677 227 PHY_MODE3 = 0x310,
bca1c4eb
JG		 228 PHY_MODE4 = 0x314,
229 PHY_MODE2 = 0x330,
e12bef50 230 SATA_IFCTL_OFS = 0x344,
8e7decdb 231 SATA_TESTCTL_OFS = 0x348,
e12bef50
ML		 232 SATA_IFSTAT_OFS = 0x34c,
233 VENDOR_UNIQUE_FIS_OFS = 0x35c,
17c5aab5 234
8e7decdb
ML		 235 FISCFG_OFS = 0x360,
236 FISCFG_WAIT_DEV_ERR = (1 << 8), /* wait for host on DevErr */
237 FISCFG_SINGLE_SYNC = (1 << 16), /* SYNC on DMA activation */
17c5aab5 238
c9d39130 239 MV5_PHY_MODE = 0x74,
8e7decdb
ML		 240 MV5_LTMODE_OFS = 0x30,
241 MV5_PHY_CTL_OFS = 0x0C,
242 SATA_INTERFACE_CFG_OFS = 0x050,
bca1c4eb
JG		 243
244 MV_M2_PREAMP_MASK = 0x7e0,
20f733e7
BR		 245
246 /* Port registers */
247 EDMA_CFG_OFS = 0,
0c58912e
ML		 248 EDMA_CFG_Q_DEPTH = 0x1f, /* max device queue depth */
249 EDMA_CFG_NCQ = (1 << 5), /* for R/W FPDMA queued */
250 EDMA_CFG_NCQ_GO_ON_ERR = (1 << 14), /* continue on error */
251 EDMA_CFG_RD_BRST_EXT = (1 << 11), /* read burst 512B */
252 EDMA_CFG_WR_BUFF_LEN = (1 << 13), /* write buffer 512B */
e12bef50
ML		 253 EDMA_CFG_EDMA_FBS = (1 << 16), /* EDMA FIS-Based Switching */
254 EDMA_CFG_FBS = (1 << 26), /* FIS-Based Switching */
20f733e7
BR		 255
256 EDMA_ERR_IRQ_CAUSE_OFS = 0x8,
257 EDMA_ERR_IRQ_MASK_OFS = 0xc,
6c1153e0
JG		 258 EDMA_ERR_D_PAR = (1 << 0), /* UDMA data parity err */
259 EDMA_ERR_PRD_PAR = (1 << 1), /* UDMA PRD parity err */
260 EDMA_ERR_DEV = (1 << 2), /* device error */
261 EDMA_ERR_DEV_DCON = (1 << 3), /* device disconnect */
262 EDMA_ERR_DEV_CON = (1 << 4), /* device connected */
263 EDMA_ERR_SERR = (1 << 5), /* SError bits [WBDST] raised */
c5d3e45a
JG		 264 EDMA_ERR_SELF_DIS = (1 << 7), /* Gen II/IIE self-disable */
265 EDMA_ERR_SELF_DIS_5 = (1 << 8), /* Gen I self-disable */
6c1153e0 266 EDMA_ERR_BIST_ASYNC = (1 << 8), /* BIST FIS or Async Notify */
c5d3e45a 267 EDMA_ERR_TRANS_IRQ_7 = (1 << 8), /* Gen IIE transprt layer irq */
6c1153e0
JG		 268 EDMA_ERR_CRQB_PAR = (1 << 9), /* CRQB parity error */
269 EDMA_ERR_CRPB_PAR = (1 << 10), /* CRPB parity error */
270 EDMA_ERR_INTRL_PAR = (1 << 11), /* internal parity error */
271 EDMA_ERR_IORDY = (1 << 12), /* IORdy timeout */
646a4da5 272
6c1153e0 273 EDMA_ERR_LNK_CTRL_RX = (0xf << 13), /* link ctrl rx error */
646a4da5
ML		 274 EDMA_ERR_LNK_CTRL_RX_0 = (1 << 13), /* transient: CRC err */
275 EDMA_ERR_LNK_CTRL_RX_1 = (1 << 14), /* transient: FIFO err */
276 EDMA_ERR_LNK_CTRL_RX_2 = (1 << 15), /* fatal: caught SYNC */
277 EDMA_ERR_LNK_CTRL_RX_3 = (1 << 16), /* transient: FIS rx err */
278
6c1153e0 279 EDMA_ERR_LNK_DATA_RX = (0xf << 17), /* link data rx error */
646a4da5 280
6c1153e0 281 EDMA_ERR_LNK_CTRL_TX = (0x1f << 21), /* link ctrl tx error */
646a4da5
ML		 282 EDMA_ERR_LNK_CTRL_TX_0 = (1 << 21), /* transient: CRC err */
283 EDMA_ERR_LNK_CTRL_TX_1 = (1 << 22), /* transient: FIFO err */
284 EDMA_ERR_LNK_CTRL_TX_2 = (1 << 23), /* transient: caught SYNC */
285 EDMA_ERR_LNK_CTRL_TX_3 = (1 << 24), /* transient: caught DMAT */
286 EDMA_ERR_LNK_CTRL_TX_4 = (1 << 25), /* transient: FIS collision */
287
6c1153e0 288 EDMA_ERR_LNK_DATA_TX = (0x1f << 26), /* link data tx error */
646a4da5 289
6c1153e0 290 EDMA_ERR_TRANS_PROTO = (1 << 31), /* transport protocol error */
c5d3e45a
JG		 291 EDMA_ERR_OVERRUN_5 = (1 << 5),
292 EDMA_ERR_UNDERRUN_5 = (1 << 6),
646a4da5
ML		 293
294 EDMA_ERR_IRQ_TRANSIENT = EDMA_ERR_LNK_CTRL_RX_0 |
295 EDMA_ERR_LNK_CTRL_RX_1 |
296 EDMA_ERR_LNK_CTRL_RX_3 |
85afb934 297 EDMA_ERR_LNK_CTRL_TX,
646a4da5 298
bdd4ddde
JG		 299 EDMA_EH_FREEZE = EDMA_ERR_D_PAR |
300 EDMA_ERR_PRD_PAR |
301 EDMA_ERR_DEV_DCON |
302 EDMA_ERR_DEV_CON |
303 EDMA_ERR_SERR |
304 EDMA_ERR_SELF_DIS |
6c1153e0 305 EDMA_ERR_CRQB_PAR |
bdd4ddde
JG		 306 EDMA_ERR_CRPB_PAR |
307 EDMA_ERR_INTRL_PAR |
308 EDMA_ERR_IORDY |
309 EDMA_ERR_LNK_CTRL_RX_2 |
310 EDMA_ERR_LNK_DATA_RX |
311 EDMA_ERR_LNK_DATA_TX |
312 EDMA_ERR_TRANS_PROTO,
e12bef50 313
bdd4ddde
JG		 314 EDMA_EH_FREEZE_5 = EDMA_ERR_D_PAR |
315 EDMA_ERR_PRD_PAR |
316 EDMA_ERR_DEV_DCON |
317 EDMA_ERR_DEV_CON |
318 EDMA_ERR_OVERRUN_5 |
319 EDMA_ERR_UNDERRUN_5 |
320 EDMA_ERR_SELF_DIS_5 |
6c1153e0 321 EDMA_ERR_CRQB_PAR |
bdd4ddde
JG		 322 EDMA_ERR_CRPB_PAR |
323 EDMA_ERR_INTRL_PAR |
324 EDMA_ERR_IORDY,
20f733e7 325
31961943
BR		 326 EDMA_REQ_Q_BASE_HI_OFS = 0x10,
327 EDMA_REQ_Q_IN_PTR_OFS = 0x14, /* also contains BASE_LO */
31961943
BR		 328
329 EDMA_REQ_Q_OUT_PTR_OFS = 0x18,
330 EDMA_REQ_Q_PTR_SHIFT = 5,
331
332 EDMA_RSP_Q_BASE_HI_OFS = 0x1c,
333 EDMA_RSP_Q_IN_PTR_OFS = 0x20,
334 EDMA_RSP_Q_OUT_PTR_OFS = 0x24, /* also contains BASE_LO */
31961943
BR		 335 EDMA_RSP_Q_PTR_SHIFT = 3,
336
0ea9e179
JG		 337 EDMA_CMD_OFS = 0x28, /* EDMA command register */
338 EDMA_EN = (1 << 0), /* enable EDMA */
339 EDMA_DS = (1 << 1), /* disable EDMA; self-negated */
8e7decdb
ML		 340 EDMA_RESET = (1 << 2), /* reset eng/trans/link/phy */
341
342 EDMA_STATUS_OFS = 0x30, /* EDMA engine status */
343 EDMA_STATUS_CACHE_EMPTY = (1 << 6), /* GenIIe command cache empty */
344 EDMA_STATUS_IDLE = (1 << 7), /* GenIIe EDMA enabled/idle */
20f733e7 345
8e7decdb
ML		 346 EDMA_IORDY_TMOUT_OFS = 0x34,
347 EDMA_ARB_CFG_OFS = 0x38,
348
349 EDMA_HALTCOND_OFS = 0x60, /* GenIIe halt conditions */
bca1c4eb 350
352fab70
ML		 351 GEN_II_NCQ_MAX_SECTORS = 256, /* max sects/io on Gen2 w/NCQ */
352
31961943
BR		 353 /* Host private flags (hp_flags) */
354 MV_HP_FLAG_MSI = (1 << 0),
47c2b677
JG		 355 MV_HP_ERRATA_50XXB0 = (1 << 1),
356 MV_HP_ERRATA_50XXB2 = (1 << 2),
357 MV_HP_ERRATA_60X1B2 = (1 << 3),
358 MV_HP_ERRATA_60X1C0 = (1 << 4),
e4e7b892 359 MV_HP_ERRATA_XX42A0 = (1 << 5),
0ea9e179
JG		 360 MV_HP_GEN_I = (1 << 6), /* Generation I: 50xx */
361 MV_HP_GEN_II = (1 << 7), /* Generation II: 60xx */
362 MV_HP_GEN_IIE = (1 << 8), /* Generation IIE: 6042/7042 */
02a121da 363 MV_HP_PCIE = (1 << 9), /* PCIe bus/regs: 7042 */
616d4a98 364 MV_HP_CUT_THROUGH = (1 << 10), /* can use EDMA cut-through */
20f733e7 365
31961943 366 /* Port private flags (pp_flags) */
0ea9e179 367 MV_PP_FLAG_EDMA_EN = (1 << 0), /* is EDMA engine enabled? */
72109168 368 MV_PP_FLAG_NCQ_EN = (1 << 1), /* is EDMA set up for NCQ? */
00f42eab 369 MV_PP_FLAG_FBS_EN = (1 << 2), /* is EDMA set up for FBS? */
29d187bb 370 MV_PP_FLAG_DELAYED_EH = (1 << 3), /* delayed dev err handling */
20f733e7
BR		 371};
372
ee9ccdf7
JG		 373#define IS_GEN_I(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_I)
374#define IS_GEN_II(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_II)
e4e7b892 375#define IS_GEN_IIE(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_IIE)
8e7decdb 376#define IS_PCIE(hpriv) ((hpriv)->hp_flags & MV_HP_PCIE)
7bb3c529 377#define HAS_PCI(host) (!((host)->ports[0]->flags & MV_FLAG_SOC))
bca1c4eb 378
15a32632
LB		 379#define WINDOW_CTRL(i) (0x20030 + ((i) << 4))
380#define WINDOW_BASE(i) (0x20034 + ((i) << 4))
381
095fec88 382enum {
baf14aa1
JG		 383 /* DMA boundary 0xffff is required by the s/g splitting
384 * we need on /length/ in mv_fill-sg().
385 */
386 MV_DMA_BOUNDARY = 0xffffU,
095fec88 387
0ea9e179
JG		 388 /* mask of register bits containing lower 32 bits
389 * of EDMA request queue DMA address
390 */
095fec88
JG		 391 EDMA_REQ_Q_BASE_LO_MASK = 0xfffffc00U,
392
0ea9e179 393 /* ditto, for response queue */
095fec88
JG		 394 EDMA_RSP_Q_BASE_LO_MASK = 0xffffff00U,
395};
396
522479fb
JG		 397enum chip_type {
398 chip_504x,
399 chip_508x,
400 chip_5080,
401 chip_604x,
402 chip_608x,
e4e7b892
JG		 403 chip_6042,
404 chip_7042,
f351b2d6 405 chip_soc,
522479fb
JG		 406};
407
31961943
BR		 408/* Command ReQuest Block: 32B */
409struct mv_crqb {
e1469874
ML		 410 __le32 sg_addr;
411 __le32 sg_addr_hi;
412 __le16 ctrl_flags;
413 __le16 ata_cmd[11];
31961943 414};
20f733e7 415
e4e7b892 416struct mv_crqb_iie {
e1469874
ML		 417 __le32 addr;
418 __le32 addr_hi;
419 __le32 flags;
420 __le32 len;
421 __le32 ata_cmd[4];
e4e7b892
JG		 422};
423
31961943
BR		 424/* Command ResPonse Block: 8B */
425struct mv_crpb {
e1469874
ML		 426 __le16 id;
427 __le16 flags;
428 __le32 tmstmp;
20f733e7
BR		 429};
430
31961943
BR		 431/* EDMA Physical Region Descriptor (ePRD); A.K.A. SG */
432struct mv_sg {
e1469874
ML		 433 __le32 addr;
434 __le32 flags_size;
435 __le32 addr_hi;
436 __le32 reserved;
31961943 437};
20f733e7 438
31961943
BR		 439struct mv_port_priv {
440 struct mv_crqb *crqb;
441 dma_addr_t crqb_dma;
442 struct mv_crpb *crpb;
443 dma_addr_t crpb_dma;
eb73d558
ML		 444 struct mv_sg *sg_tbl[MV_MAX_Q_DEPTH];
445 dma_addr_t sg_tbl_dma[MV_MAX_Q_DEPTH];
bdd4ddde
JG		 446
447 unsigned int req_idx;
448 unsigned int resp_idx;
449
31961943 450 u32 pp_flags;
29d187bb 451 unsigned int delayed_eh_pmp_map;
31961943
BR		 452};
453
bca1c4eb
JG		 454struct mv_port_signal {
455 u32 amps;
456 u32 pre;
457};
458
02a121da
ML		 459struct mv_host_priv {
460 u32 hp_flags;
96e2c487 461 u32 main_irq_mask;
02a121da
ML		 462 struct mv_port_signal signal[8];
463 const struct mv_hw_ops *ops;
f351b2d6
SB		 464 int n_ports;
465 void __iomem *base;
7368f919
ML		 466 void __iomem *main_irq_cause_addr;
467 void __iomem *main_irq_mask_addr;
02a121da
ML		 468 u32 irq_cause_ofs;
469 u32 irq_mask_ofs;
470 u32 unmask_all_irqs;
da2fa9ba
ML		 471 /*
472 * These consistent DMA memory pools give us guaranteed
473 * alignment for hardware-accessed data structures,
474 * and less memory waste in accomplishing the alignment.
475 */
476 struct dma_pool *crqb_pool;
477 struct dma_pool *crpb_pool;
478 struct dma_pool *sg_tbl_pool;
02a121da
ML		 479};
480
47c2b677 481struct mv_hw_ops {
2a47ce06
JG		 482 void (*phy_errata)(struct mv_host_priv *hpriv, void __iomem *mmio,
483 unsigned int port);
47c2b677
JG		 484 void (*enable_leds)(struct mv_host_priv *hpriv, void __iomem *mmio);
485 void (*read_preamp)(struct mv_host_priv *hpriv, int idx,
486 void __iomem *mmio);
c9d39130
JG		 487 int (*reset_hc)(struct mv_host_priv *hpriv, void __iomem *mmio,
488 unsigned int n_hc);
522479fb 489 void (*reset_flash)(struct mv_host_priv *hpriv, void __iomem *mmio);
7bb3c529 490 void (*reset_bus)(struct ata_host *host, void __iomem *mmio);
47c2b677
JG		 491};
492
da3dbb17
TH		 493static int mv_scr_read(struct ata_port *ap, unsigned int sc_reg_in, u32 *val);
494static int mv_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val);
495static int mv5_scr_read(struct ata_port *ap, unsigned int sc_reg_in, u32 *val);
496static int mv5_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val);
31961943
BR		 497static int mv_port_start(struct ata_port *ap);
498static void mv_port_stop(struct ata_port *ap);
3e4a1391 499static int mv_qc_defer(struct ata_queued_cmd *qc);
31961943 500static void mv_qc_prep(struct ata_queued_cmd *qc);
e4e7b892 501static void mv_qc_prep_iie(struct ata_queued_cmd *qc);
9a3d9eb0 502static unsigned int mv_qc_issue(struct ata_queued_cmd *qc);
a1efdaba
TH		 503static int mv_hardreset(struct ata_link *link, unsigned int *class,
504 unsigned long deadline);
bdd4ddde
JG		 505static void mv_eh_freeze(struct ata_port *ap);
506static void mv_eh_thaw(struct ata_port *ap);
f273827e 507static void mv6_dev_config(struct ata_device *dev);
20f733e7 508
2a47ce06
JG		 509static void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
510 unsigned int port);
47c2b677
JG		 511static void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio);
512static void mv5_read_preamp(struct mv_host_priv *hpriv, int idx,
513 void __iomem *mmio);
c9d39130
JG		 514static int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
515 unsigned int n_hc);
522479fb 516static void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio);
7bb3c529 517static void mv5_reset_bus(struct ata_host *host, void __iomem *mmio);
47c2b677 518
2a47ce06
JG		 519static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
520 unsigned int port);
47c2b677
JG		 521static void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio);
522static void mv6_read_preamp(struct mv_host_priv *hpriv, int idx,
523 void __iomem *mmio);
c9d39130
JG		 524static int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
525 unsigned int n_hc);
522479fb 526static void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio);
f351b2d6
SB		 527static void mv_soc_enable_leds(struct mv_host_priv *hpriv,
528 void __iomem *mmio);
529static void mv_soc_read_preamp(struct mv_host_priv *hpriv, int idx,
530 void __iomem *mmio);
531static int mv_soc_reset_hc(struct mv_host_priv *hpriv,
532 void __iomem *mmio, unsigned int n_hc);
533static void mv_soc_reset_flash(struct mv_host_priv *hpriv,
534 void __iomem *mmio);
535static void mv_soc_reset_bus(struct ata_host *host, void __iomem *mmio);
7bb3c529 536static void mv_reset_pci_bus(struct ata_host *host, void __iomem *mmio);
e12bef50 537static void mv_reset_channel(struct mv_host_priv *hpriv, void __iomem *mmio,
c9d39130 538 unsigned int port_no);
e12bef50 539static int mv_stop_edma(struct ata_port *ap);
b562468c 540static int mv_stop_edma_engine(void __iomem *port_mmio);
e12bef50 541static void mv_edma_cfg(struct ata_port *ap, int want_ncq);
47c2b677 542
e49856d8
ML		 543static void mv_pmp_select(struct ata_port *ap, int pmp);
544static int mv_pmp_hardreset(struct ata_link *link, unsigned int *class,
545 unsigned long deadline);
546static int mv_softreset(struct ata_link *link, unsigned int *class,
547 unsigned long deadline);
29d187bb 548static void mv_pmp_error_handler(struct ata_port *ap);
4c299ca3
ML		 549static void mv_process_crpb_entries(struct ata_port *ap,
550 struct mv_port_priv *pp);
47c2b677 551
eb73d558
ML		 552/* .sg_tablesize is (MV_MAX_SG_CT / 2) in the structures below
553 * because we have to allow room for worst case splitting of
554 * PRDs for 64K boundaries in mv_fill_sg().
555 */
c5d3e45a 556static struct scsi_host_template mv5_sht = {
68d1d07b 557 ATA_BASE_SHT(DRV_NAME),
baf14aa1 558 .sg_tablesize = MV_MAX_SG_CT / 2,
c5d3e45a 559 .dma_boundary = MV_DMA_BOUNDARY,
c5d3e45a
JG		 560};
561
562static struct scsi_host_template mv6_sht = {
68d1d07b 563 ATA_NCQ_SHT(DRV_NAME),
138bfdd0 564 .can_queue = MV_MAX_Q_DEPTH - 1,
baf14aa1 565 .sg_tablesize = MV_MAX_SG_CT / 2,
20f733e7 566 .dma_boundary = MV_DMA_BOUNDARY,
20f733e7
BR		 567};
568
029cfd6b
TH		 569static struct ata_port_operations mv5_ops = {
570 .inherits = &ata_sff_port_ops,
c9d39130 571
3e4a1391 572 .qc_defer = mv_qc_defer,
c9d39130
JG		 573 .qc_prep = mv_qc_prep,
574 .qc_issue = mv_qc_issue,
c9d39130 575
bdd4ddde
JG		 576 .freeze = mv_eh_freeze,
577 .thaw = mv_eh_thaw,
a1efdaba 578 .hardreset = mv_hardreset,
a1efdaba 579 .error_handler = ata_std_error_handler, /* avoid SFF EH */
029cfd6b 580 .post_internal_cmd = ATA_OP_NULL,
bdd4ddde 581
c9d39130
JG		 582 .scr_read = mv5_scr_read,
583 .scr_write = mv5_scr_write,
584
585 .port_start = mv_port_start,
586 .port_stop = mv_port_stop,
c9d39130
JG		 587};
588
029cfd6b
TH		 589static struct ata_port_operations mv6_ops = {
590 .inherits = &mv5_ops,
f273827e 591 .dev_config = mv6_dev_config,
20f733e7
BR		 592 .scr_read = mv_scr_read,
593 .scr_write = mv_scr_write,
594
e49856d8
ML		 595 .pmp_hardreset = mv_pmp_hardreset,
596 .pmp_softreset = mv_softreset,
597 .softreset = mv_softreset,
29d187bb 598 .error_handler = mv_pmp_error_handler,
20f733e7
BR		 599};
600
029cfd6b
TH		 601static struct ata_port_operations mv_iie_ops = {
602 .inherits = &mv6_ops,
603 .dev_config = ATA_OP_NULL,
e4e7b892 604 .qc_prep = mv_qc_prep_iie,
e4e7b892
JG		 605};
606
98ac62de 607static const struct ata_port_info mv_port_info[] = {
20f733e7 608 { /* chip_504x */
cca3974e 609 .flags = MV_COMMON_FLAGS,
31961943 610 .pio_mask = 0x1f, /* pio0-4 */
bf6263a8 611 .udma_mask = ATA_UDMA6,
c9d39130 612 .port_ops = &mv5_ops,
20f733e7
BR		 613 },
614 { /* chip_508x */
c5d3e45a 615 .flags = MV_COMMON_FLAGS | MV_FLAG_DUAL_HC,
31961943 616 .pio_mask = 0x1f, /* pio0-4 */
bf6263a8 617 .udma_mask = ATA_UDMA6,
c9d39130 618 .port_ops = &mv5_ops,
20f733e7 619 },
47c2b677 620 { /* chip_5080 */
c5d3e45a 621 .flags = MV_COMMON_FLAGS | MV_FLAG_DUAL_HC,
47c2b677 622 .pio_mask = 0x1f, /* pio0-4 */
bf6263a8 623 .udma_mask = ATA_UDMA6,
c9d39130 624 .port_ops = &mv5_ops,
47c2b677 625 },
20f733e7 626 { /* chip_604x */
138bfdd0 627 .flags = MV_COMMON_FLAGS | MV_6XXX_FLAGS |
e49856d8 628 ATA_FLAG_PMP | ATA_FLAG_ACPI_SATA |
138bfdd0 629 ATA_FLAG_NCQ,
31961943 630 .pio_mask = 0x1f, /* pio0-4 */
bf6263a8 631 .udma_mask = ATA_UDMA6,
c9d39130 632 .port_ops = &mv6_ops,
20f733e7
BR		 633 },
634 { /* chip_608x */
c5d3e45a 635 .flags = MV_COMMON_FLAGS | MV_6XXX_FLAGS |
e49856d8 636 ATA_FLAG_PMP | ATA_FLAG_ACPI_SATA |
138bfdd0 637 ATA_FLAG_NCQ | MV_FLAG_DUAL_HC,
31961943 638 .pio_mask = 0x1f, /* pio0-4 */
bf6263a8 639 .udma_mask = ATA_UDMA6,
c9d39130 640 .port_ops = &mv6_ops,
20f733e7 641 },
e4e7b892 642 { /* chip_6042 */
ad3aef51 643 .flags = MV_GENIIE_FLAGS,
e4e7b892 644 .pio_mask = 0x1f, /* pio0-4 */
bf6263a8 645 .udma_mask = ATA_UDMA6,
e4e7b892
JG		 646 .port_ops = &mv_iie_ops,
647 },
648 { /* chip_7042 */
ad3aef51 649 .flags = MV_GENIIE_FLAGS,
e4e7b892 650 .pio_mask = 0x1f, /* pio0-4 */
bf6263a8 651 .udma_mask = ATA_UDMA6,
e4e7b892
JG		 652 .port_ops = &mv_iie_ops,
653 },
f351b2d6 654 { /* chip_soc */
ad3aef51 655 .flags = MV_GENIIE_FLAGS | MV_FLAG_SOC,
17c5aab5
ML		 656 .pio_mask = 0x1f, /* pio0-4 */
657 .udma_mask = ATA_UDMA6,
658 .port_ops = &mv_iie_ops,
f351b2d6 659 },
20f733e7
BR		 660};
661
3b7d697d 662static const struct pci_device_id mv_pci_tbl[] = {
2d2744fc
JG		 663 { PCI_VDEVICE(MARVELL, 0x5040), chip_504x },
664 { PCI_VDEVICE(MARVELL, 0x5041), chip_504x },
665 { PCI_VDEVICE(MARVELL, 0x5080), chip_5080 },
666 { PCI_VDEVICE(MARVELL, 0x5081), chip_508x },
cfbf723e
AC		 667 /* RocketRAID 1740/174x have different identifiers */
668 { PCI_VDEVICE(TTI, 0x1740), chip_508x },
669 { PCI_VDEVICE(TTI, 0x1742), chip_508x },
2d2744fc
JG		 670
671 { PCI_VDEVICE(MARVELL, 0x6040), chip_604x },
672 { PCI_VDEVICE(MARVELL, 0x6041), chip_604x },
673 { PCI_VDEVICE(MARVELL, 0x6042), chip_6042 },
674 { PCI_VDEVICE(MARVELL, 0x6080), chip_608x },
675 { PCI_VDEVICE(MARVELL, 0x6081), chip_608x },
676
677 { PCI_VDEVICE(ADAPTEC2, 0x0241), chip_604x },
678
d9f9c6bc
FA		 679 /* Adaptec 1430SA */
680 { PCI_VDEVICE(ADAPTEC2, 0x0243), chip_7042 },
681
02a121da 682 /* Marvell 7042 support */
6a3d586d
MT		 683 { PCI_VDEVICE(MARVELL, 0x7042), chip_7042 },
684
02a121da
ML		 685 /* Highpoint RocketRAID PCIe series */
686 { PCI_VDEVICE(TTI, 0x2300), chip_7042 },
687 { PCI_VDEVICE(TTI, 0x2310), chip_7042 },
688
2d2744fc 689 { } /* terminate list */
20f733e7
BR		 690};
691
47c2b677
JG		 692static const struct mv_hw_ops mv5xxx_ops = {
693 .phy_errata = mv5_phy_errata,
694 .enable_leds = mv5_enable_leds,
695 .read_preamp = mv5_read_preamp,
696 .reset_hc = mv5_reset_hc,
522479fb
JG		 697 .reset_flash = mv5_reset_flash,
698 .reset_bus = mv5_reset_bus,
47c2b677
JG		 699};
700
701static const struct mv_hw_ops mv6xxx_ops = {
702 .phy_errata = mv6_phy_errata,
703 .enable_leds = mv6_enable_leds,
704 .read_preamp = mv6_read_preamp,
705 .reset_hc = mv6_reset_hc,
522479fb
JG		 706 .reset_flash = mv6_reset_flash,
707 .reset_bus = mv_reset_pci_bus,
47c2b677
JG		 708};
709
f351b2d6
SB		 710static const struct mv_hw_ops mv_soc_ops = {
711 .phy_errata = mv6_phy_errata,
712 .enable_leds = mv_soc_enable_leds,
713 .read_preamp = mv_soc_read_preamp,
714 .reset_hc = mv_soc_reset_hc,
715 .reset_flash = mv_soc_reset_flash,
716 .reset_bus = mv_soc_reset_bus,
717};
718
20f733e7
BR		 719/*
720 * Functions
721 */
722
723static inline void writelfl(unsigned long data, void __iomem *addr)
724{
725 writel(data, addr);
726 (void) readl(addr); /* flush to avoid PCI posted write */
727}
728
c9d39130
JG		 729static inline unsigned int mv_hc_from_port(unsigned int port)
730{
731 return port >> MV_PORT_HC_SHIFT;
732}
733
734static inline unsigned int mv_hardport_from_port(unsigned int port)
735{
736 return port & MV_PORT_MASK;
737}
738
1cfd19ae
ML		 739/*
740 * Consolidate some rather tricky bit shift calculations.
741 * This is hot-path stuff, so not a function.
742 * Simple code, with two return values, so macro rather than inline.
743 *
744 * port is the sole input, in range 0..7.
7368f919
ML		 745 * shift is one output, for use with main_irq_cause / main_irq_mask registers.
746 * hardport is the other output, in range 0..3.
1cfd19ae
ML		 747 *
748 * Note that port and hardport may be the same variable in some cases.
749 */
750#define MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport) \
751{ \
752 shift = mv_hc_from_port(port) * HC_SHIFT; \
753 hardport = mv_hardport_from_port(port); \
754 shift += hardport * 2; \
755}
756
352fab70
ML		 757static inline void __iomem *mv_hc_base(void __iomem *base, unsigned int hc)
758{
759 return (base + MV_SATAHC0_REG_BASE + (hc * MV_SATAHC_REG_SZ));
760}
761
c9d39130
JG		 762static inline void __iomem *mv_hc_base_from_port(void __iomem *base,
763 unsigned int port)
764{
765 return mv_hc_base(base, mv_hc_from_port(port));
766}
767
20f733e7
BR		 768static inline void __iomem *mv_port_base(void __iomem *base, unsigned int port)
769{
c9d39130 770 return mv_hc_base_from_port(base, port) +
8b260248 771 MV_SATAHC_ARBTR_REG_SZ +
c9d39130 772 (mv_hardport_from_port(port) * MV_PORT_REG_SZ);
20f733e7
BR		 773}
774
e12bef50
ML		 775static void __iomem *mv5_phy_base(void __iomem *mmio, unsigned int port)
776{
777 void __iomem *hc_mmio = mv_hc_base_from_port(mmio, port);
778 unsigned long ofs = (mv_hardport_from_port(port) + 1) * 0x100UL;
779
780 return hc_mmio + ofs;
781}
782
f351b2d6
SB		 783static inline void __iomem *mv_host_base(struct ata_host *host)
784{
785 struct mv_host_priv *hpriv = host->private_data;
786 return hpriv->base;
787}
788
20f733e7
BR		 789static inline void __iomem *mv_ap_base(struct ata_port *ap)
790{
f351b2d6 791 return mv_port_base(mv_host_base(ap->host), ap->port_no);
20f733e7
BR		 792}
793
cca3974e 794static inline int mv_get_hc_count(unsigned long port_flags)
31961943 795{
cca3974e 796 return ((port_flags & MV_FLAG_DUAL_HC) ? 2 : 1);
31961943
BR		 797}
798
c5d3e45a
JG		 799static void mv_set_edma_ptrs(void __iomem *port_mmio,
800 struct mv_host_priv *hpriv,
801 struct mv_port_priv *pp)
802{
bdd4ddde
JG		 803 u32 index;
804
c5d3e45a
JG		 805 /*
806 * initialize request queue
807 */
fcfb1f77
ML		 808 pp->req_idx &= MV_MAX_Q_DEPTH_MASK; /* paranoia */
809 index = pp->req_idx << EDMA_REQ_Q_PTR_SHIFT;
bdd4ddde 810
c5d3e45a
JG		 811 WARN_ON(pp->crqb_dma & 0x3ff);
812 writel((pp->crqb_dma >> 16) >> 16, port_mmio + EDMA_REQ_Q_BASE_HI_OFS);
bdd4ddde 813 writelfl((pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK) | index,
c5d3e45a
JG		 814 port_mmio + EDMA_REQ_Q_IN_PTR_OFS);
815
816 if (hpriv->hp_flags & MV_HP_ERRATA_XX42A0)
bdd4ddde 817 writelfl((pp->crqb_dma & 0xffffffff) | index,
c5d3e45a
JG		 818 port_mmio + EDMA_REQ_Q_OUT_PTR_OFS);
819 else
bdd4ddde 820 writelfl(index, port_mmio + EDMA_REQ_Q_OUT_PTR_OFS);
c5d3e45a
JG		 821
822 /*
823 * initialize response queue
824 */
fcfb1f77
ML		 825 pp->resp_idx &= MV_MAX_Q_DEPTH_MASK; /* paranoia */
826 index = pp->resp_idx << EDMA_RSP_Q_PTR_SHIFT;
bdd4ddde 827
c5d3e45a
JG		 828 WARN_ON(pp->crpb_dma & 0xff);
829 writel((pp->crpb_dma >> 16) >> 16, port_mmio + EDMA_RSP_Q_BASE_HI_OFS);
830
831 if (hpriv->hp_flags & MV_HP_ERRATA_XX42A0)
bdd4ddde 832 writelfl((pp->crpb_dma & 0xffffffff) | index,
c5d3e45a
JG		 833 port_mmio + EDMA_RSP_Q_IN_PTR_OFS);
834 else
bdd4ddde 835 writelfl(index, port_mmio + EDMA_RSP_Q_IN_PTR_OFS);
c5d3e45a 836
bdd4ddde 837 writelfl((pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK) | index,
c5d3e45a 838 port_mmio + EDMA_RSP_Q_OUT_PTR_OFS);
c5d3e45a
JG		 839}
840
c4de573b
ML		 841static void mv_set_main_irq_mask(struct ata_host *host,
842 u32 disable_bits, u32 enable_bits)
843{
844 struct mv_host_priv *hpriv = host->private_data;
845 u32 old_mask, new_mask;
846
96e2c487 847 old_mask = hpriv->main_irq_mask;
c4de573b 848 new_mask = (old_mask & ~disable_bits) | enable_bits;
96e2c487
ML		 849 if (new_mask != old_mask) {
850 hpriv->main_irq_mask = new_mask;
c4de573b 851 writelfl(new_mask, hpriv->main_irq_mask_addr);
96e2c487 852 }
c4de573b
ML		 853}
854
855static void mv_enable_port_irqs(struct ata_port *ap,
856 unsigned int port_bits)
857{
858 unsigned int shift, hardport, port = ap->port_no;
859 u32 disable_bits, enable_bits;
860
861 MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport);
862
863 disable_bits = (DONE_IRQ | ERR_IRQ) << shift;
864 enable_bits = port_bits << shift;
865 mv_set_main_irq_mask(ap->host, disable_bits, enable_bits);
866}
867
05b308e1
BR		 868/**
869 * mv_start_dma - Enable eDMA engine
870 * @base: port base address
871 * @pp: port private data
872 *
beec7dbc
TH		 873 * Verify the local cache of the eDMA state is accurate with a
874 * WARN_ON.
05b308e1
BR		 875 *
876 * LOCKING:
877 * Inherited from caller.
878 */
0c58912e 879static void mv_start_dma(struct ata_port *ap, void __iomem *port_mmio,
72109168 880 struct mv_port_priv *pp, u8 protocol)
20f733e7 881{
72109168
ML		 882 int want_ncq = (protocol == ATA_PROT_NCQ);
883
884 if (pp->pp_flags & MV_PP_FLAG_EDMA_EN) {
885 int using_ncq = ((pp->pp_flags & MV_PP_FLAG_NCQ_EN) != 0);
886 if (want_ncq != using_ncq)
b562468c 887 mv_stop_edma(ap);
72109168 888 }
c5d3e45a 889 if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN)) {
0c58912e 890 struct mv_host_priv *hpriv = ap->host->private_data;
352fab70 891 int hardport = mv_hardport_from_port(ap->port_no);
0c58912e 892 void __iomem *hc_mmio = mv_hc_base_from_port(
352fab70 893 mv_host_base(ap->host), hardport);
0c58912e
ML		 894 u32 hc_irq_cause, ipending;
895
bdd4ddde 896 /* clear EDMA event indicators, if any */
f630d562 897 writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
bdd4ddde 898
0c58912e
ML		 899 /* clear EDMA interrupt indicator, if any */
900 hc_irq_cause = readl(hc_mmio + HC_IRQ_CAUSE_OFS);
352fab70 901 ipending = (DEV_IRQ | DMA_IRQ) << hardport;
0c58912e
ML		 902 if (hc_irq_cause & ipending) {
903 writelfl(hc_irq_cause & ~ipending,
904 hc_mmio + HC_IRQ_CAUSE_OFS);
905 }
906
e12bef50 907 mv_edma_cfg(ap, want_ncq);
0c58912e
ML		 908
909 /* clear FIS IRQ Cause */
e4006077
ML		 910 if (IS_GEN_IIE(hpriv))
911 writelfl(0, port_mmio + SATA_FIS_IRQ_CAUSE_OFS);
0c58912e 912
f630d562 913 mv_set_edma_ptrs(port_mmio, hpriv, pp);
88e675e1 914 mv_enable_port_irqs(ap, DONE_IRQ|ERR_IRQ);
bdd4ddde 915
f630d562 916 writelfl(EDMA_EN, port_mmio + EDMA_CMD_OFS);
afb0edd9
BR		 917 pp->pp_flags |= MV_PP_FLAG_EDMA_EN;
918 }
20f733e7
BR		 919}
920
9b2c4e0b
ML		 921static void mv_wait_for_edma_empty_idle(struct ata_port *ap)
922{
923 void __iomem *port_mmio = mv_ap_base(ap);
924 const u32 empty_idle = (EDMA_STATUS_CACHE_EMPTY | EDMA_STATUS_IDLE);
925 const int per_loop = 5, timeout = (15 * 1000 / per_loop);
926 int i;
927
928 /*
929 * Wait for the EDMA engine to finish transactions in progress.
c46938cc
ML		 930 * No idea what a good "timeout" value might be, but measurements
931 * indicate that it often requires hundreds of microseconds
932 * with two drives in-use. So we use the 15msec value above
933 * as a rough guess at what even more drives might require.
9b2c4e0b
ML		 934 */
935 for (i = 0; i < timeout; ++i) {
936 u32 edma_stat = readl(port_mmio + EDMA_STATUS_OFS);
937 if ((edma_stat & empty_idle) == empty_idle)
938 break;
939 udelay(per_loop);
940 }
941 /* ata_port_printk(ap, KERN_INFO, "%s: %u+ usecs\n", __func__, i); */
942}
943
05b308e1 944/**
e12bef50 945 * mv_stop_edma_engine - Disable eDMA engine
b562468c 946 * @port_mmio: io base address
05b308e1
BR		 947 *
948 * LOCKING:
949 * Inherited from caller.
950 */
b562468c 951static int mv_stop_edma_engine(void __iomem *port_mmio)
20f733e7 952{
b562468c 953 int i;
31961943 954
b562468c
ML		 955 /* Disable eDMA. The disable bit auto clears. */
956 writelfl(EDMA_DS, port_mmio + EDMA_CMD_OFS);
8b260248 957
b562468c
ML		 958 /* Wait for the chip to confirm eDMA is off. */
959 for (i = 10000; i > 0; i--) {
960 u32 reg = readl(port_mmio + EDMA_CMD_OFS);
4537deb5 961 if (!(reg & EDMA_EN))
b562468c
ML		 962 return 0;
963 udelay(10);
31961943 964 }
b562468c 965 return -EIO;
20f733e7
BR		 966}
967
e12bef50 968static int mv_stop_edma(struct ata_port *ap)
0ea9e179 969{
b562468c
ML		 970 void __iomem *port_mmio = mv_ap_base(ap);
971 struct mv_port_priv *pp = ap->private_data;
0ea9e179 972
b562468c
ML		 973 if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN))
974 return 0;
975 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
9b2c4e0b 976 mv_wait_for_edma_empty_idle(ap);
b562468c
ML		 977 if (mv_stop_edma_engine(port_mmio)) {
978 ata_port_printk(ap, KERN_ERR, "Unable to stop eDMA\n");
979 return -EIO;
980 }
981 return 0;
0ea9e179
JG		 982}
983
8a70f8dc 984#ifdef ATA_DEBUG
31961943 985static void mv_dump_mem(void __iomem *start, unsigned bytes)
20f733e7 986{
31961943
BR		 987 int b, w;
988 for (b = 0; b < bytes; ) {
989 DPRINTK("%p: ", start + b);
990 for (w = 0; b < bytes && w < 4; w++) {
2dcb407e 991 printk("%08x ", readl(start + b));
31961943
BR		 992 b += sizeof(u32);
993 }
994 printk("\n");
995 }
31961943 996}
8a70f8dc
JG		 997#endif
998
31961943
BR		 999static void mv_dump_pci_cfg(struct pci_dev *pdev, unsigned bytes)
1000{
1001#ifdef ATA_DEBUG
1002 int b, w;
1003 u32 dw;
1004 for (b = 0; b < bytes; ) {
1005 DPRINTK("%02x: ", b);
1006 for (w = 0; b < bytes && w < 4; w++) {
2dcb407e
JG		 1007 (void) pci_read_config_dword(pdev, b, &dw);
1008 printk("%08x ", dw);
31961943
BR		 1009 b += sizeof(u32);
1010 }
1011 printk("\n");
1012 }
1013#endif
1014}
1015static void mv_dump_all_regs(void __iomem *mmio_base, int port,
1016 struct pci_dev *pdev)
1017{
1018#ifdef ATA_DEBUG
8b260248 1019 void __iomem *hc_base = mv_hc_base(mmio_base,
31961943
BR		 1020 port >> MV_PORT_HC_SHIFT);
1021 void __iomem *port_base;
1022 int start_port, num_ports, p, start_hc, num_hcs, hc;
1023
1024 if (0 > port) {
1025 start_hc = start_port = 0;
1026 num_ports = 8; /* shld be benign for 4 port devs */
1027 num_hcs = 2;
1028 } else {
1029 start_hc = port >> MV_PORT_HC_SHIFT;
1030 start_port = port;
1031 num_ports = num_hcs = 1;
1032 }
8b260248 1033 DPRINTK("All registers for port(s) %u-%u:\n", start_port,
31961943
BR		 1034 num_ports > 1 ? num_ports - 1 : start_port);
1035
1036 if (NULL != pdev) {
1037 DPRINTK("PCI config space regs:\n");
1038 mv_dump_pci_cfg(pdev, 0x68);
1039 }
1040 DPRINTK("PCI regs:\n");
1041 mv_dump_mem(mmio_base+0xc00, 0x3c);
1042 mv_dump_mem(mmio_base+0xd00, 0x34);
1043 mv_dump_mem(mmio_base+0xf00, 0x4);
1044 mv_dump_mem(mmio_base+0x1d00, 0x6c);
1045 for (hc = start_hc; hc < start_hc + num_hcs; hc++) {
d220c37e 1046 hc_base = mv_hc_base(mmio_base, hc);
31961943
BR		 1047 DPRINTK("HC regs (HC %i):\n", hc);
1048 mv_dump_mem(hc_base, 0x1c);
1049 }
1050 for (p = start_port; p < start_port + num_ports; p++) {
1051 port_base = mv_port_base(mmio_base, p);
2dcb407e 1052 DPRINTK("EDMA regs (port %i):\n", p);
31961943 1053 mv_dump_mem(port_base, 0x54);
2dcb407e 1054 DPRINTK("SATA regs (port %i):\n", p);
31961943
BR		 1055 mv_dump_mem(port_base+0x300, 0x60);
1056 }
1057#endif
20f733e7
BR		 1058}
1059
1060static unsigned int mv_scr_offset(unsigned int sc_reg_in)
1061{
1062 unsigned int ofs;
1063
1064 switch (sc_reg_in) {
1065 case SCR_STATUS:
1066 case SCR_CONTROL:
1067 case SCR_ERROR:
1068 ofs = SATA_STATUS_OFS + (sc_reg_in * sizeof(u32));
1069 break;
1070 case SCR_ACTIVE:
1071 ofs = SATA_ACTIVE_OFS; /* active is not with the others */
1072 break;
1073 default:
1074 ofs = 0xffffffffU;
1075 break;
1076 }
1077 return ofs;
1078}
1079
da3dbb17 1080static int mv_scr_read(struct ata_port *ap, unsigned int sc_reg_in, u32 *val)
20f733e7
BR		 1081{
1082 unsigned int ofs = mv_scr_offset(sc_reg_in);
1083
da3dbb17
TH		 1084 if (ofs != 0xffffffffU) {
1085 *val = readl(mv_ap_base(ap) + ofs);
1086 return 0;
1087 } else
1088 return -EINVAL;
20f733e7
BR		 1089}
1090
da3dbb17 1091static int mv_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val)
20f733e7
BR		 1092{
1093 unsigned int ofs = mv_scr_offset(sc_reg_in);
1094
da3dbb17 1095 if (ofs != 0xffffffffU) {
20f733e7 1096 writelfl(val, mv_ap_base(ap) + ofs);
da3dbb17
TH		 1097 return 0;
1098 } else
1099 return -EINVAL;
20f733e7
BR		 1100}
1101
f273827e
ML		 1102static void mv6_dev_config(struct ata_device *adev)
1103{
1104 /*
e49856d8
ML		 1105 * Deal with Gen-II ("mv6") hardware quirks/restrictions:
1106 *
1107 * Gen-II does not support NCQ over a port multiplier
1108 * (no FIS-based switching).
1109 *
f273827e
ML		 1110 * We don't have hob_nsect when doing NCQ commands on Gen-II.
1111 * See mv_qc_prep() for more info.
1112 */
e49856d8 1113 if (adev->flags & ATA_DFLAG_NCQ) {
352fab70 1114 if (sata_pmp_attached(adev->link->ap)) {
e49856d8 1115 adev->flags &= ~ATA_DFLAG_NCQ;
352fab70
ML		 1116 ata_dev_printk(adev, KERN_INFO,
1117 "NCQ disabled for command-based switching\n");
1118 } else if (adev->max_sectors > GEN_II_NCQ_MAX_SECTORS) {
1119 adev->max_sectors = GEN_II_NCQ_MAX_SECTORS;
1120 ata_dev_printk(adev, KERN_INFO,
1121 "max_sectors limited to %u for NCQ\n",
1122 adev->max_sectors);
1123 }
e49856d8 1124 }
f273827e
ML		 1125}
1126
3e4a1391
ML		 1127static int mv_qc_defer(struct ata_queued_cmd *qc)
1128{
1129 struct ata_link *link = qc->dev->link;
1130 struct ata_port *ap = link->ap;
1131 struct mv_port_priv *pp = ap->private_data;
1132
29d187bb
ML		 1133 /*
1134 * Don't allow new commands if we're in a delayed EH state
1135 * for NCQ and/or FIS-based switching.
1136 */
1137 if (pp->pp_flags & MV_PP_FLAG_DELAYED_EH)
1138 return ATA_DEFER_PORT;
3e4a1391
ML		 1139 /*
1140 * If the port is completely idle, then allow the new qc.
1141 */
1142 if (ap->nr_active_links == 0)
1143 return 0;
1144
1145 if (pp->pp_flags & MV_PP_FLAG_EDMA_EN) {
1146 /*
1147 * The port is operating in host queuing mode (EDMA).
1148 * It can accomodate a new qc if the qc protocol
1149 * is compatible with the current host queue mode.
1150 */
1151 if (pp->pp_flags & MV_PP_FLAG_NCQ_EN) {
1152 /*
1153 * The host queue (EDMA) is in NCQ mode.
1154 * If the new qc is also an NCQ command,
1155 * then allow the new qc.
1156 */
1157 if (qc->tf.protocol == ATA_PROT_NCQ)
1158 return 0;
1159 } else {
1160 /*
1161 * The host queue (EDMA) is in non-NCQ, DMA mode.
1162 * If the new qc is also a non-NCQ, DMA command,
1163 * then allow the new qc.
1164 */
1165 if (qc->tf.protocol == ATA_PROT_DMA)
1166 return 0;
1167 }
1168 }
1169 return ATA_DEFER_PORT;
1170}
1171
00f42eab 1172static void mv_config_fbs(void __iomem *port_mmio, int want_ncq, int want_fbs)
e49856d8 1173{
00f42eab
ML		 1174 u32 new_fiscfg, old_fiscfg;
1175 u32 new_ltmode, old_ltmode;
1176 u32 new_haltcond, old_haltcond;
1177
1178 old_fiscfg = readl(port_mmio + FISCFG_OFS);
1179 old_ltmode = readl(port_mmio + LTMODE_OFS);
1180 old_haltcond = readl(port_mmio + EDMA_HALTCOND_OFS);
1181
1182 new_fiscfg = old_fiscfg & ~(FISCFG_SINGLE_SYNC | FISCFG_WAIT_DEV_ERR);
1183 new_ltmode = old_ltmode & ~LTMODE_BIT8;
1184 new_haltcond = old_haltcond | EDMA_ERR_DEV;
1185
1186 if (want_fbs) {
1187 new_fiscfg = old_fiscfg | FISCFG_SINGLE_SYNC;
1188 new_ltmode = old_ltmode | LTMODE_BIT8;
4c299ca3
ML		 1189 if (want_ncq)
1190 new_haltcond &= ~EDMA_ERR_DEV;
1191 else
1192 new_fiscfg |= FISCFG_WAIT_DEV_ERR;
e49856d8 1193 }
00f42eab 1194
8e7decdb
ML		 1195 if (new_fiscfg != old_fiscfg)
1196 writelfl(new_fiscfg, port_mmio + FISCFG_OFS);
e49856d8
ML		 1197 if (new_ltmode != old_ltmode)
1198 writelfl(new_ltmode, port_mmio + LTMODE_OFS);
00f42eab
ML		 1199 if (new_haltcond != old_haltcond)
1200 writelfl(new_haltcond, port_mmio + EDMA_HALTCOND_OFS);
f273827e
ML		 1201}
1202
dd2890f6
ML		 1203static void mv_60x1_errata_sata25(struct ata_port *ap, int want_ncq)
1204{
1205 struct mv_host_priv *hpriv = ap->host->private_data;
1206 u32 old, new;
1207
1208 /* workaround for 88SX60x1 FEr SATA#25 (part 1) */
1209 old = readl(hpriv->base + MV_GPIO_PORT_CTL_OFS);
1210 if (want_ncq)
1211 new = old | (1 << 22);
1212 else
1213 new = old & ~(1 << 22);
1214 if (new != old)
1215 writel(new, hpriv->base + MV_GPIO_PORT_CTL_OFS);
1216}
1217
e12bef50 1218static void mv_edma_cfg(struct ata_port *ap, int want_ncq)
e4e7b892 1219{
0c58912e 1220 u32 cfg;
e12bef50
ML		 1221 struct mv_port_priv *pp = ap->private_data;
1222 struct mv_host_priv *hpriv = ap->host->private_data;
1223 void __iomem *port_mmio = mv_ap_base(ap);
e4e7b892
JG		 1224
1225 /* set up non-NCQ EDMA configuration */
0c58912e 1226 cfg = EDMA_CFG_Q_DEPTH; /* always 0x1f for *all* chips */
00f42eab 1227 pp->pp_flags &= ~MV_PP_FLAG_FBS_EN;
e4e7b892 1228
0c58912e 1229 if (IS_GEN_I(hpriv))
e4e7b892
JG		 1230 cfg |= (1 << 8); /* enab config burst size mask */
1231
dd2890f6 1232 else if (IS_GEN_II(hpriv)) {
e4e7b892 1233 cfg |= EDMA_CFG_RD_BRST_EXT | EDMA_CFG_WR_BUFF_LEN;
dd2890f6 1234 mv_60x1_errata_sata25(ap, want_ncq);
e4e7b892 1235
dd2890f6 1236 } else if (IS_GEN_IIE(hpriv)) {
00f42eab
ML		 1237 int want_fbs = sata_pmp_attached(ap);
1238 /*
1239 * Possible future enhancement:
1240 *
1241 * The chip can use FBS with non-NCQ, if we allow it,
1242 * But first we need to have the error handling in place
1243 * for this mode (datasheet section 7.3.15.4.2.3).
1244 * So disallow non-NCQ FBS for now.
1245 */
1246 want_fbs &= want_ncq;
1247
1248 mv_config_fbs(port_mmio, want_ncq, want_fbs);
1249
1250 if (want_fbs) {
1251 pp->pp_flags |= MV_PP_FLAG_FBS_EN;
1252 cfg |= EDMA_CFG_EDMA_FBS; /* FIS-based switching */
1253 }
1254
e728eabe
JG		 1255 cfg |= (1 << 23); /* do not mask PM field in rx'd FIS */
1256 cfg |= (1 << 22); /* enab 4-entry host queue cache */
616d4a98
ML		 1257 if (HAS_PCI(ap->host))
1258 cfg |= (1 << 18); /* enab early completion */
1259 if (hpriv->hp_flags & MV_HP_CUT_THROUGH)
1260 cfg |= (1 << 17); /* enab cut-thru (dis stor&forwrd) */
e4e7b892
JG		 1261 }
1262
72109168
ML		 1263 if (want_ncq) {
1264 cfg |= EDMA_CFG_NCQ;
1265 pp->pp_flags |= MV_PP_FLAG_NCQ_EN;
1266 } else
1267 pp->pp_flags &= ~MV_PP_FLAG_NCQ_EN;
1268
e4e7b892
JG		 1269 writelfl(cfg, port_mmio + EDMA_CFG_OFS);
1270}
1271
da2fa9ba
ML		 1272static void mv_port_free_dma_mem(struct ata_port *ap)
1273{
1274 struct mv_host_priv *hpriv = ap->host->private_data;
1275 struct mv_port_priv *pp = ap->private_data;
eb73d558 1276 int tag;
da2fa9ba
ML		 1277
1278 if (pp->crqb) {
1279 dma_pool_free(hpriv->crqb_pool, pp->crqb, pp->crqb_dma);
1280 pp->crqb = NULL;
1281 }
1282 if (pp->crpb) {
1283 dma_pool_free(hpriv->crpb_pool, pp->crpb, pp->crpb_dma);
1284 pp->crpb = NULL;
1285 }
eb73d558
ML		 1286 /*
1287 * For GEN_I, there's no NCQ, so we have only a single sg_tbl.
1288 * For later hardware, we have one unique sg_tbl per NCQ tag.
1289 */
1290 for (tag = 0; tag < MV_MAX_Q_DEPTH; ++tag) {
1291 if (pp->sg_tbl[tag]) {
1292 if (tag == 0 || !IS_GEN_I(hpriv))
1293 dma_pool_free(hpriv->sg_tbl_pool,
1294 pp->sg_tbl[tag],
1295 pp->sg_tbl_dma[tag]);
1296 pp->sg_tbl[tag] = NULL;
1297 }
da2fa9ba
ML		 1298 }
1299}
1300
05b308e1
BR		 1301/**
1302 * mv_port_start - Port specific init/start routine.
1303 * @ap: ATA channel to manipulate
1304 *
1305 * Allocate and point to DMA memory, init port private memory,
1306 * zero indices.
1307 *
1308 * LOCKING:
1309 * Inherited from caller.
1310 */
31961943
BR		 1311static int mv_port_start(struct ata_port *ap)
1312{
cca3974e
JG		 1313 struct device *dev = ap->host->dev;
1314 struct mv_host_priv *hpriv = ap->host->private_data;
31961943 1315 struct mv_port_priv *pp;
dde20207 1316 int tag;
31961943 1317
24dc5f33 1318 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
6037d6bb 1319 if (!pp)
24dc5f33 1320 return -ENOMEM;
da2fa9ba 1321 ap->private_data = pp;
31961943 1322
da2fa9ba
ML		 1323 pp->crqb = dma_pool_alloc(hpriv->crqb_pool, GFP_KERNEL, &pp->crqb_dma);
1324 if (!pp->crqb)
1325 return -ENOMEM;
1326 memset(pp->crqb, 0, MV_CRQB_Q_SZ);
31961943 1327
da2fa9ba
ML		 1328 pp->crpb = dma_pool_alloc(hpriv->crpb_pool, GFP_KERNEL, &pp->crpb_dma);
1329 if (!pp->crpb)
1330 goto out_port_free_dma_mem;
1331 memset(pp->crpb, 0, MV_CRPB_Q_SZ);
31961943 1332
eb73d558
ML		 1333 /*
1334 * For GEN_I, there's no NCQ, so we only allocate a single sg_tbl.
1335 * For later hardware, we need one unique sg_tbl per NCQ tag.
1336 */
1337 for (tag = 0; tag < MV_MAX_Q_DEPTH; ++tag) {
1338 if (tag == 0 || !IS_GEN_I(hpriv)) {
1339 pp->sg_tbl[tag] = dma_pool_alloc(hpriv->sg_tbl_pool,
1340 GFP_KERNEL, &pp->sg_tbl_dma[tag]);
1341 if (!pp->sg_tbl[tag])
1342 goto out_port_free_dma_mem;
1343 } else {
1344 pp->sg_tbl[tag] = pp->sg_tbl[0];
1345 pp->sg_tbl_dma[tag] = pp->sg_tbl_dma[0];
1346 }
1347 }
31961943 1348 return 0;
da2fa9ba
ML		 1349
1350out_port_free_dma_mem:
1351 mv_port_free_dma_mem(ap);
1352 return -ENOMEM;
31961943
BR		 1353}
1354
05b308e1
BR		 1355/**
1356 * mv_port_stop - Port specific cleanup/stop routine.
1357 * @ap: ATA channel to manipulate
1358 *
1359 * Stop DMA, cleanup port memory.
1360 *
1361 * LOCKING:
cca3974e 1362 * This routine uses the host lock to protect the DMA stop.
05b308e1 1363 */
31961943
BR		 1364static void mv_port_stop(struct ata_port *ap)
1365{
e12bef50 1366 mv_stop_edma(ap);
88e675e1 1367 mv_enable_port_irqs(ap, 0);
da2fa9ba 1368 mv_port_free_dma_mem(ap);
31961943
BR		 1369}
1370
05b308e1
BR		 1371/**
1372 * mv_fill_sg - Fill out the Marvell ePRD (scatter gather) entries
1373 * @qc: queued command whose SG list to source from
1374 *
1375 * Populate the SG list and mark the last entry.
1376 *
1377 * LOCKING:
1378 * Inherited from caller.
1379 */
6c08772e 1380static void mv_fill_sg(struct ata_queued_cmd *qc)
31961943
BR		 1381{
1382 struct mv_port_priv *pp = qc->ap->private_data;
972c26bd 1383 struct scatterlist *sg;
3be6cbd7 1384 struct mv_sg *mv_sg, *last_sg = NULL;
ff2aeb1e 1385 unsigned int si;
31961943 1386
eb73d558 1387 mv_sg = pp->sg_tbl[qc->tag];
ff2aeb1e 1388 for_each_sg(qc->sg, sg, qc->n_elem, si) {
d88184fb
JG		 1389 dma_addr_t addr = sg_dma_address(sg);
1390 u32 sg_len = sg_dma_len(sg);
22374677 1391
4007b493
OJ		 1392 while (sg_len) {
1393 u32 offset = addr & 0xffff;
1394 u32 len = sg_len;
22374677 1395
4007b493
OJ		 1396 if ((offset + sg_len > 0x10000))
1397 len = 0x10000 - offset;
1398
1399 mv_sg->addr = cpu_to_le32(addr & 0xffffffff);
1400 mv_sg->addr_hi = cpu_to_le32((addr >> 16) >> 16);
6c08772e 1401 mv_sg->flags_size = cpu_to_le32(len & 0xffff);
4007b493
OJ		 1402
1403 sg_len -= len;
1404 addr += len;
1405
3be6cbd7 1406 last_sg = mv_sg;
4007b493 1407 mv_sg++;
4007b493 1408 }
31961943 1409 }
3be6cbd7
JG		 1410
1411 if (likely(last_sg))
1412 last_sg->flags_size |= cpu_to_le32(EPRD_FLAG_END_OF_TBL);
31961943
BR		 1413}
1414
5796d1c4 1415static void mv_crqb_pack_cmd(__le16 *cmdw, u8 data, u8 addr, unsigned last)
31961943 1416{
559eedad 1417 u16 tmp = data | (addr << CRQB_CMD_ADDR_SHIFT) | CRQB_CMD_CS |
31961943 1418 (last ? CRQB_CMD_LAST : 0);
559eedad 1419 *cmdw = cpu_to_le16(tmp);
31961943
BR		 1420}
1421
05b308e1
BR		 1422/**
1423 * mv_qc_prep - Host specific command preparation.
1424 * @qc: queued command to prepare
1425 *
1426 * This routine simply redirects to the general purpose routine
1427 * if command is not DMA. Else, it handles prep of the CRQB
1428 * (command request block), does some sanity checking, and calls
1429 * the SG load routine.
1430 *
1431 * LOCKING:
1432 * Inherited from caller.
1433 */
31961943
BR		 1434static void mv_qc_prep(struct ata_queued_cmd *qc)
1435{
1436 struct ata_port *ap = qc->ap;
1437 struct mv_port_priv *pp = ap->private_data;
e1469874 1438 __le16 *cw;
31961943
BR		 1439 struct ata_taskfile *tf;
1440 u16 flags = 0;
a6432436 1441 unsigned in_index;
31961943 1442
138bfdd0
ML		 1443 if ((qc->tf.protocol != ATA_PROT_DMA) &&
1444 (qc->tf.protocol != ATA_PROT_NCQ))
31961943 1445 return;
20f733e7 1446
31961943
BR		 1447 /* Fill in command request block
1448 */
e4e7b892 1449 if (!(qc->tf.flags & ATA_TFLAG_WRITE))
31961943 1450 flags |= CRQB_FLAG_READ;
beec7dbc 1451 WARN_ON(MV_MAX_Q_DEPTH <= qc->tag);
31961943 1452 flags |= qc->tag << CRQB_TAG_SHIFT;
e49856d8 1453 flags |= (qc->dev->link->pmp & 0xf) << CRQB_PMP_SHIFT;
31961943 1454
bdd4ddde 1455 /* get current queue index from software */
fcfb1f77 1456 in_index = pp->req_idx;
a6432436
ML		 1457
1458 pp->crqb[in_index].sg_addr =
eb73d558 1459 cpu_to_le32(pp->sg_tbl_dma[qc->tag] & 0xffffffff);
a6432436 1460 pp->crqb[in_index].sg_addr_hi =
eb73d558 1461 cpu_to_le32((pp->sg_tbl_dma[qc->tag] >> 16) >> 16);
a6432436 1462 pp->crqb[in_index].ctrl_flags = cpu_to_le16(flags);
31961943 1463
a6432436 1464 cw = &pp->crqb[in_index].ata_cmd[0];
31961943
BR		 1465 tf = &qc->tf;
1466
1467 /* Sadly, the CRQB cannot accomodate all registers--there are
1468 * only 11 bytes...so we must pick and choose required
1469 * registers based on the command. So, we drop feature and
1470 * hob_feature for [RW] DMA commands, but they are needed for
1471 * NCQ. NCQ will drop hob_nsect.
20f733e7 1472 */
31961943
BR		 1473 switch (tf->command) {
1474 case ATA_CMD_READ:
1475 case ATA_CMD_READ_EXT:
1476 case ATA_CMD_WRITE:
1477 case ATA_CMD_WRITE_EXT:
c15d85c8 1478 case ATA_CMD_WRITE_FUA_EXT:
31961943
BR		 1479 mv_crqb_pack_cmd(cw++, tf->hob_nsect, ATA_REG_NSECT, 0);
1480 break;
31961943
BR		 1481 case ATA_CMD_FPDMA_READ:
1482 case ATA_CMD_FPDMA_WRITE:
8b260248 1483 mv_crqb_pack_cmd(cw++, tf->hob_feature, ATA_REG_FEATURE, 0);
31961943
BR		 1484 mv_crqb_pack_cmd(cw++, tf->feature, ATA_REG_FEATURE, 0);
1485 break;
31961943
BR		 1486 default:
1487 /* The only other commands EDMA supports in non-queued and
1488 * non-NCQ mode are: [RW] STREAM DMA and W DMA FUA EXT, none
1489 * of which are defined/used by Linux. If we get here, this
1490 * driver needs work.
1491 *
1492 * FIXME: modify libata to give qc_prep a return value and
1493 * return error here.
1494 */
1495 BUG_ON(tf->command);
1496 break;
1497 }
1498 mv_crqb_pack_cmd(cw++, tf->nsect, ATA_REG_NSECT, 0);
1499 mv_crqb_pack_cmd(cw++, tf->hob_lbal, ATA_REG_LBAL, 0);
1500 mv_crqb_pack_cmd(cw++, tf->lbal, ATA_REG_LBAL, 0);
1501 mv_crqb_pack_cmd(cw++, tf->hob_lbam, ATA_REG_LBAM, 0);
1502 mv_crqb_pack_cmd(cw++, tf->lbam, ATA_REG_LBAM, 0);
1503 mv_crqb_pack_cmd(cw++, tf->hob_lbah, ATA_REG_LBAH, 0);
1504 mv_crqb_pack_cmd(cw++, tf->lbah, ATA_REG_LBAH, 0);
1505 mv_crqb_pack_cmd(cw++, tf->device, ATA_REG_DEVICE, 0);
1506 mv_crqb_pack_cmd(cw++, tf->command, ATA_REG_CMD, 1); /* last */
1507
e4e7b892
JG		 1508 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
1509 return;
1510 mv_fill_sg(qc);
1511}
1512
1513/**
1514 * mv_qc_prep_iie - Host specific command preparation.
1515 * @qc: queued command to prepare
1516 *
1517 * This routine simply redirects to the general purpose routine
1518 * if command is not DMA. Else, it handles prep of the CRQB
1519 * (command request block), does some sanity checking, and calls
1520 * the SG load routine.
1521 *
1522 * LOCKING:
1523 * Inherited from caller.
1524 */
1525static void mv_qc_prep_iie(struct ata_queued_cmd *qc)
1526{
1527 struct ata_port *ap = qc->ap;
1528 struct mv_port_priv *pp = ap->private_data;
1529 struct mv_crqb_iie *crqb;
1530 struct ata_taskfile *tf;
a6432436 1531 unsigned in_index;
e4e7b892
JG		 1532 u32 flags = 0;
1533
138bfdd0
ML		 1534 if ((qc->tf.protocol != ATA_PROT_DMA) &&
1535 (qc->tf.protocol != ATA_PROT_NCQ))
e4e7b892
JG		 1536 return;
1537
e12bef50 1538 /* Fill in Gen IIE command request block */
e4e7b892
JG		 1539 if (!(qc->tf.flags & ATA_TFLAG_WRITE))
1540 flags |= CRQB_FLAG_READ;
1541
beec7dbc 1542 WARN_ON(MV_MAX_Q_DEPTH <= qc->tag);
e4e7b892 1543 flags |= qc->tag << CRQB_TAG_SHIFT;
8c0aeb4a 1544 flags |= qc->tag << CRQB_HOSTQ_SHIFT;
e49856d8 1545 flags |= (qc->dev->link->pmp & 0xf) << CRQB_PMP_SHIFT;
e4e7b892 1546
bdd4ddde 1547 /* get current queue index from software */
fcfb1f77 1548 in_index = pp->req_idx;
a6432436
ML		 1549
1550 crqb = (struct mv_crqb_iie *) &pp->crqb[in_index];
eb73d558
ML		 1551 crqb->addr = cpu_to_le32(pp->sg_tbl_dma[qc->tag] & 0xffffffff);
1552 crqb->addr_hi = cpu_to_le32((pp->sg_tbl_dma[qc->tag] >> 16) >> 16);
e4e7b892
JG		 1553 crqb->flags = cpu_to_le32(flags);
1554
1555 tf = &qc->tf;
1556 crqb->ata_cmd[0] = cpu_to_le32(
1557 (tf->command << 16) |
1558 (tf->feature << 24)
1559 );
1560 crqb->ata_cmd[1] = cpu_to_le32(
1561 (tf->lbal << 0) |
1562 (tf->lbam << 8) |
1563 (tf->lbah << 16) |
1564 (tf->device << 24)
1565 );
1566 crqb->ata_cmd[2] = cpu_to_le32(
1567 (tf->hob_lbal << 0) |
1568 (tf->hob_lbam << 8) |
1569 (tf->hob_lbah << 16) |
1570 (tf->hob_feature << 24)
1571 );
1572 crqb->ata_cmd[3] = cpu_to_le32(
1573 (tf->nsect << 0) |
1574 (tf->hob_nsect << 8)
1575 );
1576
1577 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
31961943 1578 return;
31961943
BR		 1579 mv_fill_sg(qc);
1580}
1581
05b308e1
BR		 1582/**
1583 * mv_qc_issue - Initiate a command to the host
1584 * @qc: queued command to start
1585 *
1586 * This routine simply redirects to the general purpose routine
1587 * if command is not DMA. Else, it sanity checks our local
1588 * caches of the request producer/consumer indices then enables
1589 * DMA and bumps the request producer index.
1590 *
1591 * LOCKING:
1592 * Inherited from caller.
1593 */
9a3d9eb0 1594static unsigned int mv_qc_issue(struct ata_queued_cmd *qc)
31961943 1595{
c5d3e45a
JG		 1596 struct ata_port *ap = qc->ap;
1597 void __iomem *port_mmio = mv_ap_base(ap);
1598 struct mv_port_priv *pp = ap->private_data;
bdd4ddde 1599 u32 in_index;
31961943 1600
138bfdd0
ML		 1601 if ((qc->tf.protocol != ATA_PROT_DMA) &&
1602 (qc->tf.protocol != ATA_PROT_NCQ)) {
17c5aab5
ML		 1603 /*
1604 * We're about to send a non-EDMA capable command to the
31961943
BR		 1605 * port. Turn off EDMA so there won't be problems accessing
1606 * shadow block, etc registers.
1607 */
b562468c 1608 mv_stop_edma(ap);
88e675e1 1609 mv_enable_port_irqs(ap, ERR_IRQ);
e49856d8 1610 mv_pmp_select(ap, qc->dev->link->pmp);
9363c382 1611 return ata_sff_qc_issue(qc);
31961943
BR		 1612 }
1613
72109168 1614 mv_start_dma(ap, port_mmio, pp, qc->tf.protocol);
bdd4ddde 1615
fcfb1f77
ML		 1616 pp->req_idx = (pp->req_idx + 1) & MV_MAX_Q_DEPTH_MASK;
1617 in_index = pp->req_idx << EDMA_REQ_Q_PTR_SHIFT;
31961943
BR		 1618
1619 /* and write the request in pointer to kick the EDMA to life */
bdd4ddde
JG		 1620 writelfl((pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK) | in_index,
1621 port_mmio + EDMA_REQ_Q_IN_PTR_OFS);
31961943
BR		 1622
1623 return 0;
1624}
1625
8f767f8a
ML		 1626static struct ata_queued_cmd *mv_get_active_qc(struct ata_port *ap)
1627{
1628 struct mv_port_priv *pp = ap->private_data;
1629 struct ata_queued_cmd *qc;
1630
1631 if (pp->pp_flags & MV_PP_FLAG_NCQ_EN)
1632 return NULL;
1633 qc = ata_qc_from_tag(ap, ap->link.active_tag);
1634 if (qc && (qc->tf.flags & ATA_TFLAG_POLLING))
1635 qc = NULL;
1636 return qc;
1637}
1638
29d187bb
ML		 1639static void mv_pmp_error_handler(struct ata_port *ap)
1640{
1641 unsigned int pmp, pmp_map;
1642 struct mv_port_priv *pp = ap->private_data;
1643
1644 if (pp->pp_flags & MV_PP_FLAG_DELAYED_EH) {
1645 /*
1646 * Perform NCQ error analysis on failed PMPs
1647 * before we freeze the port entirely.
1648 *
1649 * The failed PMPs are marked earlier by mv_pmp_eh_prep().
1650 */
1651 pmp_map = pp->delayed_eh_pmp_map;
1652 pp->pp_flags &= ~MV_PP_FLAG_DELAYED_EH;
1653 for (pmp = 0; pmp_map != 0; pmp++) {
1654 unsigned int this_pmp = (1 << pmp);
1655 if (pmp_map & this_pmp) {
1656 struct ata_link *link = &ap->pmp_link[pmp];
1657 pmp_map &= ~this_pmp;
1658 ata_eh_analyze_ncq_error(link);
1659 }
1660 }
1661 ata_port_freeze(ap);
1662 }
1663 sata_pmp_error_handler(ap);
1664}
1665
4c299ca3
ML		 1666static unsigned int mv_get_err_pmp_map(struct ata_port *ap)
1667{
1668 void __iomem *port_mmio = mv_ap_base(ap);
1669
1670 return readl(port_mmio + SATA_TESTCTL_OFS) >> 16;
1671}
1672
4c299ca3
ML		 1673static void mv_pmp_eh_prep(struct ata_port *ap, unsigned int pmp_map)
1674{
1675 struct ata_eh_info *ehi;
1676 unsigned int pmp;
1677
1678 /*
1679 * Initialize EH info for PMPs which saw device errors
1680 */
1681 ehi = &ap->link.eh_info;
1682 for (pmp = 0; pmp_map != 0; pmp++) {
1683 unsigned int this_pmp = (1 << pmp);
1684 if (pmp_map & this_pmp) {
1685 struct ata_link *link = &ap->pmp_link[pmp];
1686
1687 pmp_map &= ~this_pmp;
1688 ehi = &link->eh_info;
1689 ata_ehi_clear_desc(ehi);
1690 ata_ehi_push_desc(ehi, "dev err");
1691 ehi->err_mask |= AC_ERR_DEV;
1692 ehi->action |= ATA_EH_RESET;
1693 ata_link_abort(link);
1694 }
1695 }
1696}
1697
06aaca3f
ML		 1698static int mv_req_q_empty(struct ata_port *ap)
1699{
1700 void __iomem *port_mmio = mv_ap_base(ap);
1701 u32 in_ptr, out_ptr;
1702
1703 in_ptr = (readl(port_mmio + EDMA_REQ_Q_IN_PTR_OFS)
1704 >> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK;
1705 out_ptr = (readl(port_mmio + EDMA_REQ_Q_OUT_PTR_OFS)
1706 >> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK;
1707 return (in_ptr == out_ptr); /* 1 == queue_is_empty */
1708}
1709
4c299ca3
ML		 1710static int mv_handle_fbs_ncq_dev_err(struct ata_port *ap)
1711{
1712 struct mv_port_priv *pp = ap->private_data;
1713 int failed_links;
1714 unsigned int old_map, new_map;
1715
1716 /*
1717 * Device error during FBS+NCQ operation:
1718 *
1719 * Set a port flag to prevent further I/O being enqueued.
1720 * Leave the EDMA running to drain outstanding commands from this port.
1721 * Perform the post-mortem/EH only when all responses are complete.
1722 * Follow recovery sequence from 6042/7042 datasheet (7.3.15.4.2.2).
1723 */
1724 if (!(pp->pp_flags & MV_PP_FLAG_DELAYED_EH)) {
1725 pp->pp_flags |= MV_PP_FLAG_DELAYED_EH;
1726 pp->delayed_eh_pmp_map = 0;
1727 }
1728 old_map = pp->delayed_eh_pmp_map;
1729 new_map = old_map | mv_get_err_pmp_map(ap);
1730
1731 if (old_map != new_map) {
1732 pp->delayed_eh_pmp_map = new_map;
1733 mv_pmp_eh_prep(ap, new_map & ~old_map);
1734 }
c46938cc 1735 failed_links = hweight16(new_map);
4c299ca3
ML		 1736
1737 ata_port_printk(ap, KERN_INFO, "%s: pmp_map=%04x qc_map=%04x "
1738 "failed_links=%d nr_active_links=%d\n",
1739 __func__, pp->delayed_eh_pmp_map,
1740 ap->qc_active, failed_links,
1741 ap->nr_active_links);
1742
06aaca3f 1743 if (ap->nr_active_links <= failed_links && mv_req_q_empty(ap)) {
4c299ca3
ML		 1744 mv_process_crpb_entries(ap, pp);
1745 mv_stop_edma(ap);
1746 mv_eh_freeze(ap);
1747 ata_port_printk(ap, KERN_INFO, "%s: done\n", __func__);
1748 return 1; /* handled */
1749 }
1750 ata_port_printk(ap, KERN_INFO, "%s: waiting\n", __func__);
1751 return 1; /* handled */
1752}
1753
1754static int mv_handle_fbs_non_ncq_dev_err(struct ata_port *ap)
1755{
1756 /*
1757 * Possible future enhancement:
1758 *
1759 * FBS+non-NCQ operation is not yet implemented.
1760 * See related notes in mv_edma_cfg().
1761 *
1762 * Device error during FBS+non-NCQ operation:
1763 *
1764 * We need to snapshot the shadow registers for each failed command.
1765 * Follow recovery sequence from 6042/7042 datasheet (7.3.15.4.2.3).
1766 */
1767 return 0; /* not handled */
1768}
1769
1770static int mv_handle_dev_err(struct ata_port *ap, u32 edma_err_cause)
1771{
1772 struct mv_port_priv *pp = ap->private_data;
1773
1774 if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN))
1775 return 0; /* EDMA was not active: not handled */
1776 if (!(pp->pp_flags & MV_PP_FLAG_FBS_EN))
1777 return 0; /* FBS was not active: not handled */
1778
1779 if (!(edma_err_cause & EDMA_ERR_DEV))
1780 return 0; /* non DEV error: not handled */
1781 edma_err_cause &= ~EDMA_ERR_IRQ_TRANSIENT;
1782 if (edma_err_cause & ~(EDMA_ERR_DEV | EDMA_ERR_SELF_DIS))
1783 return 0; /* other problems: not handled */
1784
1785 if (pp->pp_flags & MV_PP_FLAG_NCQ_EN) {
1786 /*
1787 * EDMA should NOT have self-disabled for this case.
1788 * If it did, then something is wrong elsewhere,
1789 * and we cannot handle it here.
1790 */
1791 if (edma_err_cause & EDMA_ERR_SELF_DIS) {
1792 ata_port_printk(ap, KERN_WARNING,
1793 "%s: err_cause=0x%x pp_flags=0x%x\n",
1794 __func__, edma_err_cause, pp->pp_flags);
1795 return 0; /* not handled */
1796 }
1797 return mv_handle_fbs_ncq_dev_err(ap);
1798 } else {
1799 /*
1800 * EDMA should have self-disabled for this case.
1801 * If it did not, then something is wrong elsewhere,
1802 * and we cannot handle it here.
1803 */
1804 if (!(edma_err_cause & EDMA_ERR_SELF_DIS)) {
1805 ata_port_printk(ap, KERN_WARNING,
1806 "%s: err_cause=0x%x pp_flags=0x%x\n",
1807 __func__, edma_err_cause, pp->pp_flags);
1808 return 0; /* not handled */
1809 }
1810 return mv_handle_fbs_non_ncq_dev_err(ap);
1811 }
1812 return 0; /* not handled */
1813}
1814
a9010329 1815static void mv_unexpected_intr(struct ata_port *ap, int edma_was_enabled)
8f767f8a 1816{
8f767f8a 1817 struct ata_eh_info *ehi = &ap->link.eh_info;
a9010329 1818 char *when = "idle";
8f767f8a 1819
8f767f8a 1820 ata_ehi_clear_desc(ehi);
a9010329
ML		 1821 if (!ap || (ap->flags & ATA_FLAG_DISABLED)) {
1822 when = "disabled";
1823 } else if (edma_was_enabled) {
1824 when = "EDMA enabled";
8f767f8a
ML		 1825 } else {
1826 struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->link.active_tag);
1827 if (qc && (qc->tf.flags & ATA_TFLAG_POLLING))
a9010329 1828 when = "polling";
8f767f8a 1829 }
a9010329 1830 ata_ehi_push_desc(ehi, "unexpected device interrupt while %s", when);
8f767f8a
ML		 1831 ehi->err_mask |= AC_ERR_OTHER;
1832 ehi->action |= ATA_EH_RESET;
1833 ata_port_freeze(ap);
1834}
1835
05b308e1
BR		 1836/**
1837 * mv_err_intr - Handle error interrupts on the port
1838 * @ap: ATA channel to manipulate
8d07379d 1839 * @qc: affected command (non-NCQ), or NULL
05b308e1 1840 *
8d07379d
ML		 1841 * Most cases require a full reset of the chip's state machine,
1842 * which also performs a COMRESET.
1843 * Also, if the port disabled DMA, update our cached copy to match.
05b308e1
BR		 1844 *
1845 * LOCKING:
1846 * Inherited from caller.
1847 */
37b9046a 1848static void mv_err_intr(struct ata_port *ap)
31961943
BR		 1849{
1850 void __iomem *port_mmio = mv_ap_base(ap);
bdd4ddde 1851 u32 edma_err_cause, eh_freeze_mask, serr = 0;
e4006077 1852 u32 fis_cause = 0;
bdd4ddde
JG		 1853 struct mv_port_priv *pp = ap->private_data;
1854 struct mv_host_priv *hpriv = ap->host->private_data;
bdd4ddde 1855 unsigned int action = 0, err_mask = 0;
9af5c9c9 1856 struct ata_eh_info *ehi = &ap->link.eh_info;
37b9046a
ML		 1857 struct ata_queued_cmd *qc;
1858 int abort = 0;
20f733e7 1859
8d07379d 1860 /*
37b9046a 1861 * Read and clear the SError and err_cause bits.
e4006077
ML		 1862 * For GenIIe, if EDMA_ERR_TRANS_IRQ_7 is set, we also must read/clear
1863 * the FIS_IRQ_CAUSE register before clearing edma_err_cause.
8d07379d 1864 */
37b9046a
ML		 1865 sata_scr_read(&ap->link, SCR_ERROR, &serr);
1866 sata_scr_write_flush(&ap->link, SCR_ERROR, serr);
1867
bdd4ddde 1868 edma_err_cause = readl(port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
e4006077
ML		 1869 if (IS_GEN_IIE(hpriv) && (edma_err_cause & EDMA_ERR_TRANS_IRQ_7)) {
1870 fis_cause = readl(port_mmio + SATA_FIS_IRQ_CAUSE_OFS);
1871 writelfl(~fis_cause, port_mmio + SATA_FIS_IRQ_CAUSE_OFS);
1872 }
8d07379d 1873 writelfl(~edma_err_cause, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
bdd4ddde 1874
4c299ca3
ML		 1875 if (edma_err_cause & EDMA_ERR_DEV) {
1876 /*
1877 * Device errors during FIS-based switching operation
1878 * require special handling.
1879 */
1880 if (mv_handle_dev_err(ap, edma_err_cause))
1881 return;
1882 }
1883
37b9046a
ML		 1884 qc = mv_get_active_qc(ap);
1885 ata_ehi_clear_desc(ehi);
1886 ata_ehi_push_desc(ehi, "edma_err_cause=%08x pp_flags=%08x",
1887 edma_err_cause, pp->pp_flags);
e4006077 1888
c443c500 1889 if (IS_GEN_IIE(hpriv) && (edma_err_cause & EDMA_ERR_TRANS_IRQ_7)) {
e4006077 1890 ata_ehi_push_desc(ehi, "fis_cause=%08x", fis_cause);
c443c500
ML		 1891 if (fis_cause & SATA_FIS_IRQ_AN) {
1892 u32 ec = edma_err_cause &
1893 ~(EDMA_ERR_TRANS_IRQ_7 | EDMA_ERR_IRQ_TRANSIENT);
1894 sata_async_notification(ap);
1895 if (!ec)
1896 return; /* Just an AN; no need for the nukes */
1897 ata_ehi_push_desc(ehi, "SDB notify");
1898 }
1899 }
bdd4ddde 1900 /*
352fab70 1901 * All generations share these EDMA error cause bits:
bdd4ddde 1902 */
37b9046a 1903 if (edma_err_cause & EDMA_ERR_DEV) {
bdd4ddde 1904 err_mask |= AC_ERR_DEV;
37b9046a
ML		 1905 action |= ATA_EH_RESET;
1906 ata_ehi_push_desc(ehi, "dev error");
1907 }
bdd4ddde 1908 if (edma_err_cause & (EDMA_ERR_D_PAR | EDMA_ERR_PRD_PAR |
6c1153e0 1909 EDMA_ERR_CRQB_PAR | EDMA_ERR_CRPB_PAR |
bdd4ddde
JG		 1910 EDMA_ERR_INTRL_PAR)) {
1911 err_mask |= AC_ERR_ATA_BUS;
cf480626 1912 action |= ATA_EH_RESET;
b64bbc39 1913 ata_ehi_push_desc(ehi, "parity error");
bdd4ddde
JG		 1914 }
1915 if (edma_err_cause & (EDMA_ERR_DEV_DCON | EDMA_ERR_DEV_CON)) {
1916 ata_ehi_hotplugged(ehi);
1917 ata_ehi_push_desc(ehi, edma_err_cause & EDMA_ERR_DEV_DCON ?
b64bbc39 1918 "dev disconnect" : "dev connect");
cf480626 1919 action |= ATA_EH_RESET;
bdd4ddde
JG		 1920 }
1921
352fab70
ML		 1922 /*
1923 * Gen-I has a different SELF_DIS bit,
1924 * different FREEZE bits, and no SERR bit:
1925 */
ee9ccdf7 1926 if (IS_GEN_I(hpriv)) {
bdd4ddde 1927 eh_freeze_mask = EDMA_EH_FREEZE_5;
bdd4ddde 1928 if (edma_err_cause & EDMA_ERR_SELF_DIS_5) {
bdd4ddde 1929 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
b64bbc39 1930 ata_ehi_push_desc(ehi, "EDMA self-disable");
bdd4ddde
JG		 1931 }
1932 } else {
1933 eh_freeze_mask = EDMA_EH_FREEZE;
bdd4ddde 1934 if (edma_err_cause & EDMA_ERR_SELF_DIS) {
bdd4ddde 1935 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
b64bbc39 1936 ata_ehi_push_desc(ehi, "EDMA self-disable");
bdd4ddde 1937 }
bdd4ddde 1938 if (edma_err_cause & EDMA_ERR_SERR) {
8d07379d
ML		 1939 ata_ehi_push_desc(ehi, "SError=%08x", serr);
1940 err_mask |= AC_ERR_ATA_BUS;
cf480626 1941 action |= ATA_EH_RESET;
bdd4ddde 1942 }
afb0edd9 1943 }
20f733e7 1944
bdd4ddde
JG		 1945 if (!err_mask) {
1946 err_mask = AC_ERR_OTHER;
cf480626 1947 action |= ATA_EH_RESET;
bdd4ddde
JG		 1948 }
1949
1950 ehi->serror |= serr;
1951 ehi->action |= action;
1952
1953 if (qc)
1954 qc->err_mask |= err_mask;
1955 else
1956 ehi->err_mask |= err_mask;
1957
37b9046a
ML		 1958 if (err_mask == AC_ERR_DEV) {
1959 /*
1960 * Cannot do ata_port_freeze() here,
1961 * because it would kill PIO access,
1962 * which is needed for further diagnosis.
1963 */
1964 mv_eh_freeze(ap);
1965 abort = 1;
1966 } else if (edma_err_cause & eh_freeze_mask) {
1967 /*
1968 * Note to self: ata_port_freeze() calls ata_port_abort()
1969 */
bdd4ddde 1970 ata_port_freeze(ap);
37b9046a
ML		 1971 } else {
1972 abort = 1;
1973 }
1974
1975 if (abort) {
1976 if (qc)
1977 ata_link_abort(qc->dev->link);
1978 else
1979 ata_port_abort(ap);
1980 }
bdd4ddde
JG		 1981}
1982
fcfb1f77
ML		 1983static void mv_process_crpb_response(struct ata_port *ap,
1984 struct mv_crpb *response, unsigned int tag, int ncq_enabled)
1985{
1986 struct ata_queued_cmd *qc = ata_qc_from_tag(ap, tag);
1987
1988 if (qc) {
1989 u8 ata_status;
1990 u16 edma_status = le16_to_cpu(response->flags);
1991 /*
1992 * edma_status from a response queue entry:
1993 * LSB is from EDMA_ERR_IRQ_CAUSE_OFS (non-NCQ only).
1994 * MSB is saved ATA status from command completion.
1995 */
1996 if (!ncq_enabled) {
1997 u8 err_cause = edma_status & 0xff & ~EDMA_ERR_DEV;
1998 if (err_cause) {
1999 /*
2000 * Error will be seen/handled by mv_err_intr().
2001 * So do nothing at all here.
2002 */
2003 return;
2004 }
2005 }
2006 ata_status = edma_status >> CRPB_FLAG_STATUS_SHIFT;
37b9046a
ML		 2007 if (!ac_err_mask(ata_status))
2008 ata_qc_complete(qc);
2009 /* else: leave it for mv_err_intr() */
fcfb1f77
ML		 2010 } else {
2011 ata_port_printk(ap, KERN_ERR, "%s: no qc for tag=%d\n",
2012 __func__, tag);
2013 }
2014}
2015
2016static void mv_process_crpb_entries(struct ata_port *ap, struct mv_port_priv *pp)
bdd4ddde
JG		 2017{
2018 void __iomem *port_mmio = mv_ap_base(ap);
2019 struct mv_host_priv *hpriv = ap->host->private_data;
fcfb1f77 2020 u32 in_index;
bdd4ddde 2021 bool work_done = false;
fcfb1f77 2022 int ncq_enabled = (pp->pp_flags & MV_PP_FLAG_NCQ_EN);
bdd4ddde 2023
fcfb1f77 2024 /* Get the hardware queue position index */
bdd4ddde
JG		 2025 in_index = (readl(port_mmio + EDMA_RSP_Q_IN_PTR_OFS)
2026 >> EDMA_RSP_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK;
2027
fcfb1f77
ML		 2028 /* Process new responses from since the last time we looked */
2029 while (in_index != pp->resp_idx) {
6c1153e0 2030 unsigned int tag;
fcfb1f77 2031 struct mv_crpb *response = &pp->crpb[pp->resp_idx];
bdd4ddde 2032
fcfb1f77 2033 pp->resp_idx = (pp->resp_idx + 1) & MV_MAX_Q_DEPTH_MASK;
bdd4ddde 2034
fcfb1f77
ML		 2035 if (IS_GEN_I(hpriv)) {
2036 /* 50xx: no NCQ, only one command active at a time */
9af5c9c9 2037 tag = ap->link.active_tag;
fcfb1f77
ML		 2038 } else {
2039 /* Gen II/IIE: get command tag from CRPB entry */
2040 tag = le16_to_cpu(response->id) & 0x1f;
bdd4ddde 2041 }
fcfb1f77 2042 mv_process_crpb_response(ap, response, tag, ncq_enabled);
bdd4ddde 2043 work_done = true;
bdd4ddde
JG		 2044 }
2045
352fab70 2046 /* Update the software queue position index in hardware */
bdd4ddde
JG		 2047 if (work_done)
2048 writelfl((pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK) |
fcfb1f77 2049 (pp->resp_idx << EDMA_RSP_Q_PTR_SHIFT),
bdd4ddde 2050 port_mmio + EDMA_RSP_Q_OUT_PTR_OFS);
20f733e7
BR		 2051}
2052
a9010329
ML		 2053static void mv_port_intr(struct ata_port *ap, u32 port_cause)
2054{
2055 struct mv_port_priv *pp;
2056 int edma_was_enabled;
2057
2058 if (!ap || (ap->flags & ATA_FLAG_DISABLED)) {
2059 mv_unexpected_intr(ap, 0);
2060 return;
2061 }
2062 /*
2063 * Grab a snapshot of the EDMA_EN flag setting,
2064 * so that we have a consistent view for this port,
2065 * even if something we call of our routines changes it.
2066 */
2067 pp = ap->private_data;
2068 edma_was_enabled = (pp->pp_flags & MV_PP_FLAG_EDMA_EN);
2069 /*
2070 * Process completed CRPB response(s) before other events.
2071 */
2072 if (edma_was_enabled && (port_cause & DONE_IRQ)) {
2073 mv_process_crpb_entries(ap, pp);
4c299ca3
ML		 2074 if (pp->pp_flags & MV_PP_FLAG_DELAYED_EH)
2075 mv_handle_fbs_ncq_dev_err(ap);
a9010329
ML		 2076 }
2077 /*
2078 * Handle chip-reported errors, or continue on to handle PIO.
2079 */
2080 if (unlikely(port_cause & ERR_IRQ)) {
2081 mv_err_intr(ap);
2082 } else if (!edma_was_enabled) {
2083 struct ata_queued_cmd *qc = mv_get_active_qc(ap);
2084 if (qc)
2085 ata_sff_host_intr(ap, qc);
2086 else
2087 mv_unexpected_intr(ap, edma_was_enabled);
2088 }
2089}
2090
05b308e1
BR		 2091/**
2092 * mv_host_intr - Handle all interrupts on the given host controller
cca3974e 2093 * @host: host specific structure
7368f919 2094 * @main_irq_cause: Main interrupt cause register for the chip.
05b308e1
BR		 2095 *
2096 * LOCKING:
2097 * Inherited from caller.
2098 */
7368f919 2099static int mv_host_intr(struct ata_host *host, u32 main_irq_cause)
20f733e7 2100{
f351b2d6 2101 struct mv_host_priv *hpriv = host->private_data;
eabd5eb1 2102 void __iomem *mmio = hpriv->base, *hc_mmio;
a3718c1f 2103 unsigned int handled = 0, port;
20f733e7 2104
a3718c1f 2105 for (port = 0; port < hpriv->n_ports; port++) {
cca3974e 2106 struct ata_port *ap = host->ports[port];
eabd5eb1
ML		 2107 unsigned int p, shift, hardport, port_cause;
2108
a3718c1f 2109 MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport);
a3718c1f 2110 /*
eabd5eb1
ML		 2111 * Each hc within the host has its own hc_irq_cause register,
2112 * where the interrupting ports bits get ack'd.
a3718c1f 2113 */
eabd5eb1
ML		 2114 if (hardport == 0) { /* first port on this hc ? */
2115 u32 hc_cause = (main_irq_cause >> shift) & HC0_IRQ_PEND;
2116 u32 port_mask, ack_irqs;
2117 /*
2118 * Skip this entire hc if nothing pending for any ports
2119 */
2120 if (!hc_cause) {
2121 port += MV_PORTS_PER_HC - 1;
2122 continue;
2123 }
2124 /*
2125 * We don't need/want to read the hc_irq_cause register,
2126 * because doing so hurts performance, and
2127 * main_irq_cause already gives us everything we need.
2128 *
2129 * But we do have to *write* to the hc_irq_cause to ack
2130 * the ports that we are handling this time through.
2131 *
2132 * This requires that we create a bitmap for those
2133 * ports which interrupted us, and use that bitmap
2134 * to ack (only) those ports via hc_irq_cause.
2135 */
2136 ack_irqs = 0;
2137 for (p = 0; p < MV_PORTS_PER_HC; ++p) {
2138 if ((port + p) >= hpriv->n_ports)
2139 break;
2140 port_mask = (DONE_IRQ | ERR_IRQ) << (p * 2);
2141 if (hc_cause & port_mask)
2142 ack_irqs |= (DMA_IRQ | DEV_IRQ) << p;
2143 }
a3718c1f 2144 hc_mmio = mv_hc_base_from_port(mmio, port);
eabd5eb1 2145 writelfl(~ack_irqs, hc_mmio + HC_IRQ_CAUSE_OFS);
a3718c1f
ML		 2146 handled = 1;
2147 }
8f767f8a 2148 /*
a9010329 2149 * Handle interrupts signalled for this port:
8f767f8a 2150 */
a9010329
ML		 2151 port_cause = (main_irq_cause >> shift) & (DONE_IRQ | ERR_IRQ);
2152 if (port_cause)
2153 mv_port_intr(ap, port_cause);
20f733e7 2154 }
a3718c1f 2155 return handled;
20f733e7
BR		 2156}
2157
a3718c1f 2158static int mv_pci_error(struct ata_host *host, void __iomem *mmio)
bdd4ddde 2159{
02a121da 2160 struct mv_host_priv *hpriv = host->private_data;
bdd4ddde
JG		 2161 struct ata_port *ap;
2162 struct ata_queued_cmd *qc;
2163 struct ata_eh_info *ehi;
2164 unsigned int i, err_mask, printed = 0;
2165 u32 err_cause;
2166
02a121da 2167 err_cause = readl(mmio + hpriv->irq_cause_ofs);
bdd4ddde
JG		 2168
2169 dev_printk(KERN_ERR, host->dev, "PCI ERROR; PCI IRQ cause=0x%08x\n",
2170 err_cause);
2171
2172 DPRINTK("All regs @ PCI error\n");
2173 mv_dump_all_regs(mmio, -1, to_pci_dev(host->dev));
2174
02a121da 2175 writelfl(0, mmio + hpriv->irq_cause_ofs);
bdd4ddde
JG		 2176
2177 for (i = 0; i < host->n_ports; i++) {
2178 ap = host->ports[i];
936fd732 2179 if (!ata_link_offline(&ap->link)) {
9af5c9c9 2180 ehi = &ap->link.eh_info;
bdd4ddde
JG		 2181 ata_ehi_clear_desc(ehi);
2182 if (!printed++)
2183 ata_ehi_push_desc(ehi,
2184 "PCI err cause 0x%08x", err_cause);
2185 err_mask = AC_ERR_HOST_BUS;
cf480626 2186 ehi->action = ATA_EH_RESET;
9af5c9c9 2187 qc = ata_qc_from_tag(ap, ap->link.active_tag);
bdd4ddde
JG		 2188 if (qc)
2189 qc->err_mask |= err_mask;
2190 else
2191 ehi->err_mask |= err_mask;
2192
2193 ata_port_freeze(ap);
2194 }
2195 }
a3718c1f 2196 return 1; /* handled */
bdd4ddde
JG		 2197}
2198
05b308e1 2199/**
c5d3e45a 2200 * mv_interrupt - Main interrupt event handler
05b308e1
BR		 2201 * @irq: unused
2202 * @dev_instance: private data; in this case the host structure
05b308e1
BR		 2203 *
2204 * Read the read only register to determine if any host
2205 * controllers have pending interrupts. If so, call lower level
2206 * routine to handle. Also check for PCI errors which are only
2207 * reported here.
2208 *
8b260248 2209 * LOCKING:
cca3974e 2210 * This routine holds the host lock while processing pending
05b308e1
BR		 2211 * interrupts.
2212 */
7d12e780 2213static irqreturn_t mv_interrupt(int irq, void *dev_instance)
20f733e7 2214{
cca3974e 2215 struct ata_host *host = dev_instance;
f351b2d6 2216 struct mv_host_priv *hpriv = host->private_data;
a3718c1f 2217 unsigned int handled = 0;
96e2c487 2218 u32 main_irq_cause, pending_irqs;
20f733e7 2219
646a4da5 2220 spin_lock(&host->lock);
7368f919 2221 main_irq_cause = readl(hpriv->main_irq_cause_addr);
96e2c487 2222 pending_irqs = main_irq_cause & hpriv->main_irq_mask;
352fab70
ML		 2223 /*
2224 * Deal with cases where we either have nothing pending, or have read
2225 * a bogus register value which can indicate HW removal or PCI fault.
20f733e7 2226 */
a44253d2
ML		 2227 if (pending_irqs && main_irq_cause != 0xffffffffU) {
2228 if (unlikely((pending_irqs & PCI_ERR) && HAS_PCI(host)))
a3718c1f
ML		 2229 handled = mv_pci_error(host, hpriv->base);
2230 else
a44253d2 2231 handled = mv_host_intr(host, pending_irqs);
bdd4ddde 2232 }
cca3974e 2233 spin_unlock(&host->lock);
20f733e7
BR		 2234 return IRQ_RETVAL(handled);
2235}
2236
c9d39130
JG		 2237static unsigned int mv5_scr_offset(unsigned int sc_reg_in)
2238{
2239 unsigned int ofs;
2240
2241 switch (sc_reg_in) {
2242 case SCR_STATUS:
2243 case SCR_ERROR:
2244 case SCR_CONTROL:
2245 ofs = sc_reg_in * sizeof(u32);
2246 break;
2247 default:
2248 ofs = 0xffffffffU;
2249 break;
2250 }
2251 return ofs;
2252}
2253
da3dbb17 2254static int mv5_scr_read(struct ata_port *ap, unsigned int sc_reg_in, u32 *val)
c9d39130 2255{
f351b2d6
SB		 2256 struct mv_host_priv *hpriv = ap->host->private_data;
2257 void __iomem *mmio = hpriv->base;
0d5ff566 2258 void __iomem *addr = mv5_phy_base(mmio, ap->port_no);
c9d39130
JG		 2259 unsigned int ofs = mv5_scr_offset(sc_reg_in);
2260
da3dbb17
TH		 2261 if (ofs != 0xffffffffU) {
2262 *val = readl(addr + ofs);
2263 return 0;
2264 } else
2265 return -EINVAL;
c9d39130
JG		 2266}
2267
da3dbb17 2268static int mv5_scr_write(struct ata_port *ap, unsigned int sc_reg_in, u32 val)
c9d39130 2269{
f351b2d6
SB		 2270 struct mv_host_priv *hpriv = ap->host->private_data;
2271 void __iomem *mmio = hpriv->base;
0d5ff566 2272 void __iomem *addr = mv5_phy_base(mmio, ap->port_no);
c9d39130
JG		 2273 unsigned int ofs = mv5_scr_offset(sc_reg_in);
2274
da3dbb17 2275 if (ofs != 0xffffffffU) {
0d5ff566 2276 writelfl(val, addr + ofs);
da3dbb17
TH		 2277 return 0;
2278 } else
2279 return -EINVAL;
c9d39130
JG		 2280}
2281
7bb3c529 2282static void mv5_reset_bus(struct ata_host *host, void __iomem *mmio)
522479fb 2283{
7bb3c529 2284 struct pci_dev *pdev = to_pci_dev(host->dev);
522479fb
JG		 2285 int early_5080;
2286
44c10138 2287 early_5080 = (pdev->device == 0x5080) && (pdev->revision == 0);
522479fb
JG		 2288
2289 if (!early_5080) {
2290 u32 tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL);
2291 tmp |= (1 << 0);
2292 writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL);
2293 }
2294
7bb3c529 2295 mv_reset_pci_bus(host, mmio);
522479fb
JG		 2296}
2297
2298static void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio)
2299{
8e7decdb 2300 writel(0x0fcfffff, mmio + MV_FLASH_CTL_OFS);
522479fb
JG		 2301}
2302
47c2b677 2303static void mv5_read_preamp(struct mv_host_priv *hpriv, int idx,
ba3fe8fb
JG		 2304 void __iomem *mmio)
2305{
c9d39130
JG		 2306 void __iomem *phy_mmio = mv5_phy_base(mmio, idx);
2307 u32 tmp;
2308
2309 tmp = readl(phy_mmio + MV5_PHY_MODE);
2310
2311 hpriv->signal[idx].pre = tmp & 0x1800; /* bits 12:11 */
2312 hpriv->signal[idx].amps = tmp & 0xe0; /* bits 7:5 */
ba3fe8fb
JG		 2313}
2314
47c2b677 2315static void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio)
ba3fe8fb 2316{
522479fb
JG		 2317 u32 tmp;
2318
8e7decdb 2319 writel(0, mmio + MV_GPIO_PORT_CTL_OFS);
522479fb
JG		 2320
2321 /* FIXME: handle MV_HP_ERRATA_50XXB2 errata */
2322
2323 tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL);
2324 tmp |= ~(1 << 0);
2325 writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL);
ba3fe8fb
JG		 2326}
2327
2a47ce06
JG		 2328static void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
2329 unsigned int port)
bca1c4eb 2330{
c9d39130
JG		 2331 void __iomem *phy_mmio = mv5_phy_base(mmio, port);
2332 const u32 mask = (1<<12) | (1<<11) | (1<<7) | (1<<6) | (1<<5);
2333 u32 tmp;
2334 int fix_apm_sq = (hpriv->hp_flags & MV_HP_ERRATA_50XXB0);
2335
2336 if (fix_apm_sq) {
8e7decdb 2337 tmp = readl(phy_mmio + MV5_LTMODE_OFS);
c9d39130 2338 tmp |= (1 << 19);
8e7decdb 2339 writel(tmp, phy_mmio + MV5_LTMODE_OFS);
c9d39130 2340
8e7decdb 2341 tmp = readl(phy_mmio + MV5_PHY_CTL_OFS);
c9d39130
JG		 2342 tmp &= ~0x3;
2343 tmp |= 0x1;
8e7decdb 2344 writel(tmp, phy_mmio + MV5_PHY_CTL_OFS);
c9d39130
JG		 2345 }
2346
2347 tmp = readl(phy_mmio + MV5_PHY_MODE);
2348 tmp &= ~mask;
2349 tmp |= hpriv->signal[port].pre;
2350 tmp |= hpriv->signal[port].amps;
2351 writel(tmp, phy_mmio + MV5_PHY_MODE);
bca1c4eb
JG		 2352}
2353
c9d39130
JG		 2354
2355#undef ZERO
2356#define ZERO(reg) writel(0, port_mmio + (reg))
2357static void mv5_reset_hc_port(struct mv_host_priv *hpriv, void __iomem *mmio,
2358 unsigned int port)
2359{
2360 void __iomem *port_mmio = mv_port_base(mmio, port);
2361
e12bef50 2362 mv_reset_channel(hpriv, mmio, port);
c9d39130
JG		 2363
2364 ZERO(0x028); /* command */
2365 writel(0x11f, port_mmio + EDMA_CFG_OFS);
2366 ZERO(0x004); /* timer */
2367 ZERO(0x008); /* irq err cause */
2368 ZERO(0x00c); /* irq err mask */
2369 ZERO(0x010); /* rq bah */
2370 ZERO(0x014); /* rq inp */
2371 ZERO(0x018); /* rq outp */
2372 ZERO(0x01c); /* respq bah */
2373 ZERO(0x024); /* respq outp */
2374 ZERO(0x020); /* respq inp */
2375 ZERO(0x02c); /* test control */
8e7decdb 2376 writel(0xbc, port_mmio + EDMA_IORDY_TMOUT_OFS);
c9d39130
JG		 2377}
2378#undef ZERO
2379
2380#define ZERO(reg) writel(0, hc_mmio + (reg))
2381static void mv5_reset_one_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
2382 unsigned int hc)
47c2b677 2383{
c9d39130
JG		 2384 void __iomem *hc_mmio = mv_hc_base(mmio, hc);
2385 u32 tmp;
2386
2387 ZERO(0x00c);
2388 ZERO(0x010);
2389 ZERO(0x014);
2390 ZERO(0x018);
2391
2392 tmp = readl(hc_mmio + 0x20);
2393 tmp &= 0x1c1c1c1c;
2394 tmp |= 0x03030303;
2395 writel(tmp, hc_mmio + 0x20);
2396}
2397#undef ZERO
2398
2399static int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
2400 unsigned int n_hc)
2401{
2402 unsigned int hc, port;
2403
2404 for (hc = 0; hc < n_hc; hc++) {
2405 for (port = 0; port < MV_PORTS_PER_HC; port++)
2406 mv5_reset_hc_port(hpriv, mmio,
2407 (hc * MV_PORTS_PER_HC) + port);
2408
2409 mv5_reset_one_hc(hpriv, mmio, hc);
2410 }
2411
2412 return 0;
47c2b677
JG		 2413}
2414
101ffae2
JG		 2415#undef ZERO
2416#define ZERO(reg) writel(0, mmio + (reg))
7bb3c529 2417static void mv_reset_pci_bus(struct ata_host *host, void __iomem *mmio)
101ffae2 2418{
02a121da 2419 struct mv_host_priv *hpriv = host->private_data;
101ffae2
JG		 2420 u32 tmp;
2421
8e7decdb 2422 tmp = readl(mmio + MV_PCI_MODE_OFS);
101ffae2 2423 tmp &= 0xff00ffff;
8e7decdb 2424 writel(tmp, mmio + MV_PCI_MODE_OFS);
101ffae2
JG		 2425
2426 ZERO(MV_PCI_DISC_TIMER);
2427 ZERO(MV_PCI_MSI_TRIGGER);
8e7decdb 2428 writel(0x000100ff, mmio + MV_PCI_XBAR_TMOUT_OFS);
101ffae2 2429 ZERO(MV_PCI_SERR_MASK);
02a121da
ML		 2430 ZERO(hpriv->irq_cause_ofs);
2431 ZERO(hpriv->irq_mask_ofs);
101ffae2
JG		 2432 ZERO(MV_PCI_ERR_LOW_ADDRESS);
2433 ZERO(MV_PCI_ERR_HIGH_ADDRESS);
2434 ZERO(MV_PCI_ERR_ATTRIBUTE);
2435 ZERO(MV_PCI_ERR_COMMAND);
2436}
2437#undef ZERO
2438
2439static void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio)
2440{
2441 u32 tmp;
2442
2443 mv5_reset_flash(hpriv, mmio);
2444
8e7decdb 2445 tmp = readl(mmio + MV_GPIO_PORT_CTL_OFS);
101ffae2
JG		 2446 tmp &= 0x3;
2447 tmp |= (1 << 5) | (1 << 6);
8e7decdb 2448 writel(tmp, mmio + MV_GPIO_PORT_CTL_OFS);
101ffae2
JG		 2449}
2450
2451/**
2452 * mv6_reset_hc - Perform the 6xxx global soft reset
2453 * @mmio: base address of the HBA
2454 *
2455 * This routine only applies to 6xxx parts.
2456 *
2457 * LOCKING:
2458 * Inherited from caller.
2459 */
c9d39130
JG		 2460static int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
2461 unsigned int n_hc)
101ffae2
JG		 2462{
2463 void __iomem *reg = mmio + PCI_MAIN_CMD_STS_OFS;
2464 int i, rc = 0;
2465 u32 t;
2466
2467 /* Following procedure defined in PCI "main command and status
2468 * register" table.
2469 */
2470 t = readl(reg);
2471 writel(t | STOP_PCI_MASTER, reg);
2472
2473 for (i = 0; i < 1000; i++) {
2474 udelay(1);
2475 t = readl(reg);
2dcb407e 2476 if (PCI_MASTER_EMPTY & t)
101ffae2 2477 break;
101ffae2
JG		 2478 }
2479 if (!(PCI_MASTER_EMPTY & t)) {
2480 printk(KERN_ERR DRV_NAME ": PCI master won't flush\n");
2481 rc = 1;
2482 goto done;
2483 }
2484
2485 /* set reset */
2486 i = 5;
2487 do {
2488 writel(t | GLOB_SFT_RST, reg);
2489 t = readl(reg);
2490 udelay(1);
2491 } while (!(GLOB_SFT_RST & t) && (i-- > 0));
2492
2493 if (!(GLOB_SFT_RST & t)) {
2494 printk(KERN_ERR DRV_NAME ": can't set global reset\n");
2495 rc = 1;
2496 goto done;
2497 }
2498
2499 /* clear reset and *reenable the PCI master* (not mentioned in spec) */
2500 i = 5;
2501 do {
2502 writel(t & ~(GLOB_SFT_RST | STOP_PCI_MASTER), reg);
2503 t = readl(reg);
2504 udelay(1);
2505 } while ((GLOB_SFT_RST & t) && (i-- > 0));
2506
2507 if (GLOB_SFT_RST & t) {
2508 printk(KERN_ERR DRV_NAME ": can't clear global reset\n");
2509 rc = 1;
2510 }
2511done:
2512 return rc;
2513}
2514
47c2b677 2515static void mv6_read_preamp(struct mv_host_priv *hpriv, int idx,
ba3fe8fb
JG		 2516 void __iomem *mmio)
2517{
2518 void __iomem *port_mmio;
2519 u32 tmp;
2520
8e7decdb 2521 tmp = readl(mmio + MV_RESET_CFG_OFS);
ba3fe8fb 2522 if ((tmp & (1 << 0)) == 0) {
47c2b677 2523 hpriv->signal[idx].amps = 0x7 << 8;
ba3fe8fb
JG		 2524 hpriv->signal[idx].pre = 0x1 << 5;
2525 return;
2526 }
2527
2528 port_mmio = mv_port_base(mmio, idx);
2529 tmp = readl(port_mmio + PHY_MODE2);
2530
2531 hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */
2532 hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */
2533}
2534
47c2b677 2535static void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio)
ba3fe8fb 2536{
8e7decdb 2537 writel(0x00000060, mmio + MV_GPIO_PORT_CTL_OFS);
ba3fe8fb
JG		 2538}
2539
c9d39130 2540static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
2a47ce06 2541 unsigned int port)
bca1c4eb 2542{
c9d39130
JG		 2543 void __iomem *port_mmio = mv_port_base(mmio, port);
2544
bca1c4eb 2545 u32 hp_flags = hpriv->hp_flags;
47c2b677
JG		 2546 int fix_phy_mode2 =
2547 hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0);
bca1c4eb 2548 int fix_phy_mode4 =
47c2b677
JG		 2549 hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0);
2550 u32 m2, tmp;
2551
2552 if (fix_phy_mode2) {
2553 m2 = readl(port_mmio + PHY_MODE2);
2554 m2 &= ~(1 << 16);
2555 m2 |= (1 << 31);
2556 writel(m2, port_mmio + PHY_MODE2);
2557
2558 udelay(200);
2559
2560 m2 = readl(port_mmio + PHY_MODE2);
2561 m2 &= ~((1 << 16) | (1 << 31));
2562 writel(m2, port_mmio + PHY_MODE2);
2563
2564 udelay(200);
2565 }
2566
2567 /* who knows what this magic does */
2568 tmp = readl(port_mmio + PHY_MODE3);
2569 tmp &= ~0x7F800000;
2570 tmp |= 0x2A800000;
2571 writel(tmp, port_mmio + PHY_MODE3);
bca1c4eb
JG		 2572
2573 if (fix_phy_mode4) {
47c2b677 2574 u32 m4;
bca1c4eb
JG		 2575
2576 m4 = readl(port_mmio + PHY_MODE4);
47c2b677
JG		 2577
2578 if (hp_flags & MV_HP_ERRATA_60X1B2)
e12bef50 2579 tmp = readl(port_mmio + PHY_MODE3);
bca1c4eb 2580
e12bef50 2581 /* workaround for errata FEr SATA#10 (part 1) */
bca1c4eb
JG		 2582 m4 = (m4 & ~(1 << 1)) | (1 << 0);
2583
2584 writel(m4, port_mmio + PHY_MODE4);
47c2b677
JG		 2585
2586 if (hp_flags & MV_HP_ERRATA_60X1B2)
e12bef50 2587 writel(tmp, port_mmio + PHY_MODE3);
bca1c4eb
JG		 2588 }
2589
2590 /* Revert values of pre-emphasis and signal amps to the saved ones */
2591 m2 = readl(port_mmio + PHY_MODE2);
2592
2593 m2 &= ~MV_M2_PREAMP_MASK;
2a47ce06
JG		 2594 m2 |= hpriv->signal[port].amps;
2595 m2 |= hpriv->signal[port].pre;
47c2b677 2596 m2 &= ~(1 << 16);
bca1c4eb 2597
e4e7b892
JG		 2598 /* according to mvSata 3.6.1, some IIE values are fixed */
2599 if (IS_GEN_IIE(hpriv)) {
2600 m2 &= ~0xC30FF01F;
2601 m2 |= 0x0000900F;
2602 }
2603
bca1c4eb
JG		 2604 writel(m2, port_mmio + PHY_MODE2);
2605}
2606
f351b2d6
SB		 2607/* TODO: use the generic LED interface to configure the SATA Presence */
2608/* & Acitivy LEDs on the board */
2609static void mv_soc_enable_leds(struct mv_host_priv *hpriv,
2610 void __iomem *mmio)
2611{
2612 return;
2613}
2614
2615static void mv_soc_read_preamp(struct mv_host_priv *hpriv, int idx,
2616 void __iomem *mmio)
2617{
2618 void __iomem *port_mmio;
2619 u32 tmp;
2620
2621 port_mmio = mv_port_base(mmio, idx);
2622 tmp = readl(port_mmio + PHY_MODE2);
2623
2624 hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */
2625 hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */
2626}
2627
2628#undef ZERO
2629#define ZERO(reg) writel(0, port_mmio + (reg))
2630static void mv_soc_reset_hc_port(struct mv_host_priv *hpriv,
2631 void __iomem *mmio, unsigned int port)
2632{
2633 void __iomem *port_mmio = mv_port_base(mmio, port);
2634
e12bef50 2635 mv_reset_channel(hpriv, mmio, port);
f351b2d6
SB		 2636
2637 ZERO(0x028); /* command */
2638 writel(0x101f, port_mmio + EDMA_CFG_OFS);
2639 ZERO(0x004); /* timer */
2640 ZERO(0x008); /* irq err cause */
2641 ZERO(0x00c); /* irq err mask */
2642 ZERO(0x010); /* rq bah */
2643 ZERO(0x014); /* rq inp */
2644 ZERO(0x018); /* rq outp */
2645 ZERO(0x01c); /* respq bah */
2646 ZERO(0x024); /* respq outp */
2647 ZERO(0x020); /* respq inp */
2648 ZERO(0x02c); /* test control */
8e7decdb 2649 writel(0xbc, port_mmio + EDMA_IORDY_TMOUT_OFS);
f351b2d6
SB		 2650}
2651
2652#undef ZERO
2653
2654#define ZERO(reg) writel(0, hc_mmio + (reg))
2655static void mv_soc_reset_one_hc(struct mv_host_priv *hpriv,
2656 void __iomem *mmio)
2657{
2658 void __iomem *hc_mmio = mv_hc_base(mmio, 0);
2659
2660 ZERO(0x00c);
2661 ZERO(0x010);
2662 ZERO(0x014);
2663
2664}
2665
2666#undef ZERO
2667
2668static int mv_soc_reset_hc(struct mv_host_priv *hpriv,
2669 void __iomem *mmio, unsigned int n_hc)
2670{
2671 unsigned int port;
2672
2673 for (port = 0; port < hpriv->n_ports; port++)
2674 mv_soc_reset_hc_port(hpriv, mmio, port);
2675
2676 mv_soc_reset_one_hc(hpriv, mmio);
2677
2678 return 0;
2679}
2680
2681static void mv_soc_reset_flash(struct mv_host_priv *hpriv,
2682 void __iomem *mmio)
2683{
2684 return;
2685}
2686
2687static void mv_soc_reset_bus(struct ata_host *host, void __iomem *mmio)
2688{
2689 return;
2690}
2691
8e7decdb 2692static void mv_setup_ifcfg(void __iomem *port_mmio, int want_gen2i)
b67a1064 2693{
8e7decdb 2694 u32 ifcfg = readl(port_mmio + SATA_INTERFACE_CFG_OFS);
b67a1064 2695
8e7decdb 2696 ifcfg = (ifcfg & 0xf7f) | 0x9b1000; /* from chip spec */
b67a1064 2697 if (want_gen2i)
8e7decdb
ML		 2698 ifcfg |= (1 << 7); /* enable gen2i speed */
2699 writelfl(ifcfg, port_mmio + SATA_INTERFACE_CFG_OFS);
b67a1064
ML		 2700}
2701
e12bef50 2702static void mv_reset_channel(struct mv_host_priv *hpriv, void __iomem *mmio,
c9d39130
JG		 2703 unsigned int port_no)
2704{
2705 void __iomem *port_mmio = mv_port_base(mmio, port_no);
2706
8e7decdb
ML		 2707 /*
2708 * The datasheet warns against setting EDMA_RESET when EDMA is active
2709 * (but doesn't say what the problem might be). So we first try
2710 * to disable the EDMA engine before doing the EDMA_RESET operation.
2711 */
0d8be5cb 2712 mv_stop_edma_engine(port_mmio);
8e7decdb 2713 writelfl(EDMA_RESET, port_mmio + EDMA_CMD_OFS);
c9d39130 2714
b67a1064 2715 if (!IS_GEN_I(hpriv)) {
8e7decdb
ML		 2716 /* Enable 3.0gb/s link speed: this survives EDMA_RESET */
2717 mv_setup_ifcfg(port_mmio, 1);
c9d39130 2718 }
b67a1064 2719 /*
8e7decdb 2720 * Strobing EDMA_RESET here causes a hard reset of the SATA transport,
b67a1064
ML		 2721 * link, and physical layers. It resets all SATA interface registers
2722 * (except for SATA_INTERFACE_CFG), and issues a COMRESET to the dev.
c9d39130 2723 */
8e7decdb 2724 writelfl(EDMA_RESET, port_mmio + EDMA_CMD_OFS);
b67a1064 2725 udelay(25); /* allow reset propagation */
c9d39130
JG		 2726 writelfl(0, port_mmio + EDMA_CMD_OFS);
2727
2728 hpriv->ops->phy_errata(hpriv, mmio, port_no);
2729
ee9ccdf7 2730 if (IS_GEN_I(hpriv))
c9d39130
JG		 2731 mdelay(1);
2732}
2733
e49856d8 2734static void mv_pmp_select(struct ata_port *ap, int pmp)
20f733e7 2735{
e49856d8
ML		 2736 if (sata_pmp_supported(ap)) {
2737 void __iomem *port_mmio = mv_ap_base(ap);
2738 u32 reg = readl(port_mmio + SATA_IFCTL_OFS);
2739 int old = reg & 0xf;
22374677 2740
e49856d8
ML		 2741 if (old != pmp) {
2742 reg = (reg & ~0xf) | pmp;
2743 writelfl(reg, port_mmio + SATA_IFCTL_OFS);
2744 }
22374677 2745 }
20f733e7
BR		 2746}
2747
e49856d8
ML		 2748static int mv_pmp_hardreset(struct ata_link *link, unsigned int *class,
2749 unsigned long deadline)
22374677 2750{
e49856d8
ML		 2751 mv_pmp_select(link->ap, sata_srst_pmp(link));
2752 return sata_std_hardreset(link, class, deadline);
2753}
bdd4ddde 2754
e49856d8
ML		 2755static int mv_softreset(struct ata_link *link, unsigned int *class,
2756 unsigned long deadline)
2757{
2758 mv_pmp_select(link->ap, sata_srst_pmp(link));
2759 return ata_sff_softreset(link, class, deadline);
22374677
JG		 2760}
2761
cc0680a5 2762static int mv_hardreset(struct ata_link *link, unsigned int *class,
bdd4ddde 2763 unsigned long deadline)
31961943 2764{
cc0680a5 2765 struct ata_port *ap = link->ap;
bdd4ddde 2766 struct mv_host_priv *hpriv = ap->host->private_data;
b562468c 2767 struct mv_port_priv *pp = ap->private_data;
f351b2d6 2768 void __iomem *mmio = hpriv->base;
0d8be5cb
ML		 2769 int rc, attempts = 0, extra = 0;
2770 u32 sstatus;
2771 bool online;
31961943 2772
e12bef50 2773 mv_reset_channel(hpriv, mmio, ap->port_no);
b562468c 2774 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
bdd4ddde 2775
0d8be5cb
ML		 2776 /* Workaround for errata FEr SATA#10 (part 2) */
2777 do {
17c5aab5
ML		 2778 const unsigned long *timing =
2779 sata_ehc_deb_timing(&link->eh_context);
bdd4ddde 2780
17c5aab5
ML		 2781 rc = sata_link_hardreset(link, timing, deadline + extra,
2782 &online, NULL);
9dcffd99 2783 rc = online ? -EAGAIN : rc;
17c5aab5 2784 if (rc)
0d8be5cb 2785 return rc;
0d8be5cb
ML		 2786 sata_scr_read(link, SCR_STATUS, &sstatus);
2787 if (!IS_GEN_I(hpriv) && ++attempts >= 5 && sstatus == 0x121) {
2788 /* Force 1.5gb/s link speed and try again */
8e7decdb 2789 mv_setup_ifcfg(mv_ap_base(ap), 0);
0d8be5cb
ML		 2790 if (time_after(jiffies + HZ, deadline))
2791 extra = HZ; /* only extend it once, max */
2792 }
2793 } while (sstatus != 0x0 && sstatus != 0x113 && sstatus != 0x123);
bdd4ddde 2794
17c5aab5 2795 return rc;
bdd4ddde
JG		 2796}
2797
bdd4ddde
JG		 2798static void mv_eh_freeze(struct ata_port *ap)
2799{
1cfd19ae 2800 mv_stop_edma(ap);
c4de573b 2801 mv_enable_port_irqs(ap, 0);
bdd4ddde
JG		 2802}
2803
2804static void mv_eh_thaw(struct ata_port *ap)
2805{
f351b2d6 2806 struct mv_host_priv *hpriv = ap->host->private_data;
c4de573b
ML		 2807 unsigned int port = ap->port_no;
2808 unsigned int hardport = mv_hardport_from_port(port);
1cfd19ae 2809 void __iomem *hc_mmio = mv_hc_base_from_port(hpriv->base, port);
bdd4ddde 2810 void __iomem *port_mmio = mv_ap_base(ap);
c4de573b 2811 u32 hc_irq_cause;
bdd4ddde 2812
bdd4ddde
JG		 2813 /* clear EDMA errors on this port */
2814 writel(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
2815
2816 /* clear pending irq events */
2817 hc_irq_cause = readl(hc_mmio + HC_IRQ_CAUSE_OFS);
1cfd19ae
ML		 2818 hc_irq_cause &= ~((DEV_IRQ | DMA_IRQ) << hardport);
2819 writelfl(hc_irq_cause, hc_mmio + HC_IRQ_CAUSE_OFS);
bdd4ddde 2820
88e675e1 2821 mv_enable_port_irqs(ap, ERR_IRQ);
31961943
BR		 2822}
2823
05b308e1
BR		 2824/**
2825 * mv_port_init - Perform some early initialization on a single port.
2826 * @port: libata data structure storing shadow register addresses
2827 * @port_mmio: base address of the port
2828 *
2829 * Initialize shadow register mmio addresses, clear outstanding
2830 * interrupts on the port, and unmask interrupts for the future
2831 * start of the port.
2832 *
2833 * LOCKING:
2834 * Inherited from caller.
2835 */
31961943 2836static void mv_port_init(struct ata_ioports *port, void __iomem *port_mmio)
20f733e7 2837{
0d5ff566 2838 void __iomem *shd_base = port_mmio + SHD_BLK_OFS;
31961943
BR		 2839 unsigned serr_ofs;
2840
8b260248 2841 /* PIO related setup
31961943
BR		 2842 */
2843 port->data_addr = shd_base + (sizeof(u32) * ATA_REG_DATA);
8b260248 2844 port->error_addr =
31961943
BR		 2845 port->feature_addr = shd_base + (sizeof(u32) * ATA_REG_ERR);
2846 port->nsect_addr = shd_base + (sizeof(u32) * ATA_REG_NSECT);
2847 port->lbal_addr = shd_base + (sizeof(u32) * ATA_REG_LBAL);
2848 port->lbam_addr = shd_base + (sizeof(u32) * ATA_REG_LBAM);
2849 port->lbah_addr = shd_base + (sizeof(u32) * ATA_REG_LBAH);
2850 port->device_addr = shd_base + (sizeof(u32) * ATA_REG_DEVICE);
8b260248 2851 port->status_addr =
31961943
BR		 2852 port->command_addr = shd_base + (sizeof(u32) * ATA_REG_STATUS);
2853 /* special case: control/altstatus doesn't have ATA_REG_ address */
2854 port->altstatus_addr = port->ctl_addr = shd_base + SHD_CTL_AST_OFS;
2855
2856 /* unused: */
8d9db2d2 2857 port->cmd_addr = port->bmdma_addr = port->scr_addr = NULL;
20f733e7 2858
31961943
BR		 2859 /* Clear any currently outstanding port interrupt conditions */
2860 serr_ofs = mv_scr_offset(SCR_ERROR);
2861 writelfl(readl(port_mmio + serr_ofs), port_mmio + serr_ofs);
2862 writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
2863
646a4da5
ML		 2864 /* unmask all non-transient EDMA error interrupts */
2865 writelfl(~EDMA_ERR_IRQ_TRANSIENT, port_mmio + EDMA_ERR_IRQ_MASK_OFS);
20f733e7 2866
8b260248 2867 VPRINTK("EDMA cfg=0x%08x EDMA IRQ err cause/mask=0x%08x/0x%08x\n",
31961943
BR		 2868 readl(port_mmio + EDMA_CFG_OFS),
2869 readl(port_mmio + EDMA_ERR_IRQ_CAUSE_OFS),
2870 readl(port_mmio + EDMA_ERR_IRQ_MASK_OFS));
20f733e7
BR		 2871}
2872
616d4a98
ML		 2873static unsigned int mv_in_pcix_mode(struct ata_host *host)
2874{
2875 struct mv_host_priv *hpriv = host->private_data;
2876 void __iomem *mmio = hpriv->base;
2877 u32 reg;
2878
2879 if (!HAS_PCI(host) || !IS_PCIE(hpriv))
2880 return 0; /* not PCI-X capable */
2881 reg = readl(mmio + MV_PCI_MODE_OFS);
2882 if ((reg & MV_PCI_MODE_MASK) == 0)
2883 return 0; /* conventional PCI mode */
2884 return 1; /* chip is in PCI-X mode */
2885}
2886
2887static int mv_pci_cut_through_okay(struct ata_host *host)
2888{
2889 struct mv_host_priv *hpriv = host->private_data;
2890 void __iomem *mmio = hpriv->base;
2891 u32 reg;
2892
2893 if (!mv_in_pcix_mode(host)) {
2894 reg = readl(mmio + PCI_COMMAND_OFS);
2895 if (reg & PCI_COMMAND_MRDTRIG)
2896 return 0; /* not okay */
2897 }
2898 return 1; /* okay */
2899}
2900
4447d351 2901static int mv_chip_id(struct ata_host *host, unsigned int board_idx)
bca1c4eb 2902{
4447d351
TH		 2903 struct pci_dev *pdev = to_pci_dev(host->dev);
2904 struct mv_host_priv *hpriv = host->private_data;
bca1c4eb
JG		 2905 u32 hp_flags = hpriv->hp_flags;
2906
5796d1c4 2907 switch (board_idx) {
47c2b677
JG		 2908 case chip_5080:
2909 hpriv->ops = &mv5xxx_ops;
ee9ccdf7 2910 hp_flags |= MV_HP_GEN_I;
47c2b677 2911
44c10138 2912 switch (pdev->revision) {
47c2b677
JG		 2913 case 0x1:
2914 hp_flags |= MV_HP_ERRATA_50XXB0;
2915 break;
2916 case 0x3:
2917 hp_flags |= MV_HP_ERRATA_50XXB2;
2918 break;
2919 default:
2920 dev_printk(KERN_WARNING, &pdev->dev,
2921 "Applying 50XXB2 workarounds to unknown rev\n");
2922 hp_flags |= MV_HP_ERRATA_50XXB2;
2923 break;
2924 }
2925 break;
2926
bca1c4eb
JG		 2927 case chip_504x:
2928 case chip_508x:
47c2b677 2929 hpriv->ops = &mv5xxx_ops;
ee9ccdf7 2930 hp_flags |= MV_HP_GEN_I;
bca1c4eb 2931
44c10138 2932 switch (pdev->revision) {
47c2b677
JG		 2933 case 0x0:
2934 hp_flags |= MV_HP_ERRATA_50XXB0;
2935 break;
2936 case 0x3:
2937 hp_flags |= MV_HP_ERRATA_50XXB2;
2938 break;
2939 default:
2940 dev_printk(KERN_WARNING, &pdev->dev,
2941 "Applying B2 workarounds to unknown rev\n");
2942 hp_flags |= MV_HP_ERRATA_50XXB2;
2943 break;
bca1c4eb
JG		 2944 }
2945 break;
2946
2947 case chip_604x:
2948 case chip_608x:
47c2b677 2949 hpriv->ops = &mv6xxx_ops;
ee9ccdf7 2950 hp_flags |= MV_HP_GEN_II;
47c2b677 2951
44c10138 2952 switch (pdev->revision) {
47c2b677
JG		 2953 case 0x7:
2954 hp_flags |= MV_HP_ERRATA_60X1B2;
2955 break;
2956 case 0x9:
2957 hp_flags |= MV_HP_ERRATA_60X1C0;
bca1c4eb
JG		 2958 break;
2959 default:
2960 dev_printk(KERN_WARNING, &pdev->dev,
47c2b677
JG		 2961 "Applying B2 workarounds to unknown rev\n");
2962 hp_flags |= MV_HP_ERRATA_60X1B2;
bca1c4eb
JG		 2963 break;
2964 }
2965 break;
2966
e4e7b892 2967 case chip_7042:
616d4a98 2968 hp_flags |= MV_HP_PCIE | MV_HP_CUT_THROUGH;
306b30f7
ML		 2969 if (pdev->vendor == PCI_VENDOR_ID_TTI &&
2970 (pdev->device == 0x2300 || pdev->device == 0x2310))
2971 {
4e520033
ML		 2972 /*
2973 * Highpoint RocketRAID PCIe 23xx series cards:
2974 *
2975 * Unconfigured drives are treated as "Legacy"
2976 * by the BIOS, and it overwrites sector 8 with
2977 * a "Lgcy" metadata block prior to Linux boot.
2978 *
2979 * Configured drives (RAID or JBOD) leave sector 8
2980 * alone, but instead overwrite a high numbered
2981 * sector for the RAID metadata. This sector can
2982 * be determined exactly, by truncating the physical
2983 * drive capacity to a nice even GB value.
2984 *
2985 * RAID metadata is at: (dev->n_sectors & ~0xfffff)
2986 *
2987 * Warn the user, lest they think we're just buggy.
2988 */
2989 printk(KERN_WARNING DRV_NAME ": Highpoint RocketRAID"
2990 " BIOS CORRUPTS DATA on all attached drives,"
2991 " regardless of if/how they are configured."
2992 " BEWARE!\n");
2993 printk(KERN_WARNING DRV_NAME ": For data safety, do not"
2994 " use sectors 8-9 on \"Legacy\" drives,"
2995 " and avoid the final two gigabytes on"
2996 " all RocketRAID BIOS initialized drives.\n");
306b30f7 2997 }
8e7decdb 2998 /* drop through */
e4e7b892
JG		 2999 case chip_6042:
3000 hpriv->ops = &mv6xxx_ops;
e4e7b892 3001 hp_flags |= MV_HP_GEN_IIE;
616d4a98
ML		 3002 if (board_idx == chip_6042 && mv_pci_cut_through_okay(host))
3003 hp_flags |= MV_HP_CUT_THROUGH;
e4e7b892 3004
44c10138 3005 switch (pdev->revision) {
e4e7b892
JG		 3006 case 0x0:
3007 hp_flags |= MV_HP_ERRATA_XX42A0;
3008 break;
3009 case 0x1:
3010 hp_flags |= MV_HP_ERRATA_60X1C0;
3011 break;
3012 default:
3013 dev_printk(KERN_WARNING, &pdev->dev,
3014 "Applying 60X1C0 workarounds to unknown rev\n");
3015 hp_flags |= MV_HP_ERRATA_60X1C0;
3016 break;
3017 }
3018 break;
f351b2d6
SB		 3019 case chip_soc:
3020 hpriv->ops = &mv_soc_ops;
3021 hp_flags |= MV_HP_ERRATA_60X1C0;
3022 break;
e4e7b892 3023
bca1c4eb 3024 default:
f351b2d6 3025 dev_printk(KERN_ERR, host->dev,
5796d1c4 3026 "BUG: invalid board index %u\n", board_idx);
bca1c4eb
JG		 3027 return 1;
3028 }
3029
3030 hpriv->hp_flags = hp_flags;
02a121da
ML		 3031 if (hp_flags & MV_HP_PCIE) {
3032 hpriv->irq_cause_ofs = PCIE_IRQ_CAUSE_OFS;
3033 hpriv->irq_mask_ofs = PCIE_IRQ_MASK_OFS;
3034 hpriv->unmask_all_irqs = PCIE_UNMASK_ALL_IRQS;
3035 } else {
3036 hpriv->irq_cause_ofs = PCI_IRQ_CAUSE_OFS;
3037 hpriv->irq_mask_ofs = PCI_IRQ_MASK_OFS;
3038 hpriv->unmask_all_irqs = PCI_UNMASK_ALL_IRQS;
3039 }
bca1c4eb
JG		 3040
3041 return 0;
3042}
3043
05b308e1 3044/**
47c2b677 3045 * mv_init_host - Perform some early initialization of the host.
4447d351
TH		 3046 * @host: ATA host to initialize
3047 * @board_idx: controller index
05b308e1
BR		 3048 *
3049 * If possible, do an early global reset of the host. Then do
3050 * our port init and clear/unmask all/relevant host interrupts.
3051 *
3052 * LOCKING:
3053 * Inherited from caller.
3054 */
4447d351 3055static int mv_init_host(struct ata_host *host, unsigned int board_idx)
20f733e7
BR		 3056{
3057 int rc = 0, n_hc, port, hc;
4447d351 3058 struct mv_host_priv *hpriv = host->private_data;
f351b2d6 3059 void __iomem *mmio = hpriv->base;
47c2b677 3060
4447d351 3061 rc = mv_chip_id(host, board_idx);
bca1c4eb 3062 if (rc)
352fab70 3063 goto done;
f351b2d6
SB		 3064
3065 if (HAS_PCI(host)) {
7368f919
ML		 3066 hpriv->main_irq_cause_addr = mmio + PCI_HC_MAIN_IRQ_CAUSE_OFS;
3067 hpriv->main_irq_mask_addr = mmio + PCI_HC_MAIN_IRQ_MASK_OFS;
f351b2d6 3068 } else {
7368f919
ML		 3069 hpriv->main_irq_cause_addr = mmio + SOC_HC_MAIN_IRQ_CAUSE_OFS;
3070 hpriv->main_irq_mask_addr = mmio + SOC_HC_MAIN_IRQ_MASK_OFS;
f351b2d6 3071 }
352fab70
ML		 3072
3073 /* global interrupt mask: 0 == mask everything */
c4de573b 3074 mv_set_main_irq_mask(host, ~0, 0);
bca1c4eb 3075
4447d351 3076 n_hc = mv_get_hc_count(host->ports[0]->flags);
bca1c4eb 3077
4447d351 3078 for (port = 0; port < host->n_ports; port++)
47c2b677 3079 hpriv->ops->read_preamp(hpriv, port, mmio);
20f733e7 3080
c9d39130 3081 rc = hpriv->ops->reset_hc(hpriv, mmio, n_hc);
47c2b677 3082 if (rc)
20f733e7 3083 goto done;
20f733e7 3084
522479fb 3085 hpriv->ops->reset_flash(hpriv, mmio);
7bb3c529 3086 hpriv->ops->reset_bus(host, mmio);
47c2b677 3087 hpriv->ops->enable_leds(hpriv, mmio);
20f733e7 3088
4447d351 3089 for (port = 0; port < host->n_ports; port++) {
cbcdd875 3090 struct ata_port *ap = host->ports[port];
2a47ce06 3091 void __iomem *port_mmio = mv_port_base(mmio, port);
cbcdd875
TH		 3092
3093 mv_port_init(&ap->ioaddr, port_mmio);
3094
7bb3c529 3095#ifdef CONFIG_PCI
f351b2d6
SB		 3096 if (HAS_PCI(host)) {
3097 unsigned int offset = port_mmio - mmio;
3098 ata_port_pbar_desc(ap, MV_PRIMARY_BAR, -1, "mmio");
3099 ata_port_pbar_desc(ap, MV_PRIMARY_BAR, offset, "port");
3100 }
7bb3c529 3101#endif
20f733e7
BR		 3102 }
3103
3104 for (hc = 0; hc < n_hc; hc++) {
31961943
BR		 3105 void __iomem *hc_mmio = mv_hc_base(mmio, hc);
3106
3107 VPRINTK("HC%i: HC config=0x%08x HC IRQ cause "
3108 "(before clear)=0x%08x\n", hc,
3109 readl(hc_mmio + HC_CFG_OFS),
3110 readl(hc_mmio + HC_IRQ_CAUSE_OFS));
3111
3112 /* Clear any currently outstanding hc interrupt conditions */
3113 writelfl(0, hc_mmio + HC_IRQ_CAUSE_OFS);
20f733e7
BR		 3114 }
3115
f351b2d6
SB		 3116 if (HAS_PCI(host)) {
3117 /* Clear any currently outstanding host interrupt conditions */
3118 writelfl(0, mmio + hpriv->irq_cause_ofs);
31961943 3119
f351b2d6
SB		 3120 /* and unmask interrupt generation for host regs */
3121 writelfl(hpriv->unmask_all_irqs, mmio + hpriv->irq_mask_ofs);
51de32d2
ML		 3122
3123 /*
3124 * enable only global host interrupts for now.
3125 * The per-port interrupts get done later as ports are set up.
3126 */
c4de573b 3127 mv_set_main_irq_mask(host, 0, PCI_ERR);
f351b2d6
SB		 3128 }
3129done:
3130 return rc;
3131}
fb621e2f 3132
fbf14e2f
BB		 3133static int mv_create_dma_pools(struct mv_host_priv *hpriv, struct device *dev)
3134{
3135 hpriv->crqb_pool = dmam_pool_create("crqb_q", dev, MV_CRQB_Q_SZ,
3136 MV_CRQB_Q_SZ, 0);
3137 if (!hpriv->crqb_pool)
3138 return -ENOMEM;
3139
3140 hpriv->crpb_pool = dmam_pool_create("crpb_q", dev, MV_CRPB_Q_SZ,
3141 MV_CRPB_Q_SZ, 0);
3142 if (!hpriv->crpb_pool)
3143 return -ENOMEM;
3144
3145 hpriv->sg_tbl_pool = dmam_pool_create("sg_tbl", dev, MV_SG_TBL_SZ,
3146 MV_SG_TBL_SZ, 0);
3147 if (!hpriv->sg_tbl_pool)
3148 return -ENOMEM;
3149
3150 return 0;
3151}
3152
15a32632
LB		 3153static void mv_conf_mbus_windows(struct mv_host_priv *hpriv,
3154 struct mbus_dram_target_info *dram)
3155{
3156 int i;
3157
3158 for (i = 0; i < 4; i++) {
3159 writel(0, hpriv->base + WINDOW_CTRL(i));
3160 writel(0, hpriv->base + WINDOW_BASE(i));
3161 }
3162
3163 for (i = 0; i < dram->num_cs; i++) {
3164 struct mbus_dram_window *cs = dram->cs + i;
3165
3166 writel(((cs->size - 1) & 0xffff0000) |
3167 (cs->mbus_attr << 8) |
3168 (dram->mbus_dram_target_id << 4) | 1,
3169 hpriv->base + WINDOW_CTRL(i));
3170 writel(cs->base, hpriv->base + WINDOW_BASE(i));
3171 }
3172}
3173
f351b2d6
SB		 3174/**
3175 * mv_platform_probe - handle a positive probe of an soc Marvell
3176 * host
3177 * @pdev: platform device found
3178 *
3179 * LOCKING:
3180 * Inherited from caller.
3181 */
3182static int mv_platform_probe(struct platform_device *pdev)
3183{
3184 static int printed_version;
3185 const struct mv_sata_platform_data *mv_platform_data;
3186 const struct ata_port_info *ppi[] =
3187 { &mv_port_info[chip_soc], NULL };
3188 struct ata_host *host;
3189 struct mv_host_priv *hpriv;
3190 struct resource *res;
3191 int n_ports, rc;
20f733e7 3192
f351b2d6
SB		 3193 if (!printed_version++)
3194 dev_printk(KERN_INFO, &pdev->dev, "version " DRV_VERSION "\n");
bca1c4eb 3195
f351b2d6
SB		 3196 /*
3197 * Simple resource validation ..
3198 */
3199 if (unlikely(pdev->num_resources != 2)) {
3200 dev_err(&pdev->dev, "invalid number of resources\n");
3201 return -EINVAL;
3202 }
3203
3204 /*
3205 * Get the register base first
3206 */
3207 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3208 if (res == NULL)
3209 return -EINVAL;
3210
3211 /* allocate host */
3212 mv_platform_data = pdev->dev.platform_data;
3213 n_ports = mv_platform_data->n_ports;
3214
3215 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
3216 hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL);
3217
3218 if (!host || !hpriv)
3219 return -ENOMEM;
3220 host->private_data = hpriv;
3221 hpriv->n_ports = n_ports;
3222
3223 host->iomap = NULL;
f1cb0ea1
SB		 3224 hpriv->base = devm_ioremap(&pdev->dev, res->start,
3225 res->end - res->start + 1);
f351b2d6
SB		 3226 hpriv->base -= MV_SATAHC0_REG_BASE;
3227
15a32632
LB		 3228 /*
3229 * (Re-)program MBUS remapping windows if we are asked to.
3230 */
3231 if (mv_platform_data->dram != NULL)
3232 mv_conf_mbus_windows(hpriv, mv_platform_data->dram);
3233
fbf14e2f
BB		 3234 rc = mv_create_dma_pools(hpriv, &pdev->dev);
3235 if (rc)
3236 return rc;
3237
f351b2d6
SB		 3238 /* initialize adapter */
3239 rc = mv_init_host(host, chip_soc);
3240 if (rc)
3241 return rc;
3242
3243 dev_printk(KERN_INFO, &pdev->dev,
3244 "slots %u ports %d\n", (unsigned)MV_MAX_Q_DEPTH,
3245 host->n_ports);
3246
3247 return ata_host_activate(host, platform_get_irq(pdev, 0), mv_interrupt,
3248 IRQF_SHARED, &mv6_sht);
3249}
3250
3251/*
3252 *
3253 * mv_platform_remove - unplug a platform interface
3254 * @pdev: platform device
3255 *
3256 * A platform bus SATA device has been unplugged. Perform the needed
3257 * cleanup. Also called on module unload for any active devices.
3258 */
3259static int __devexit mv_platform_remove(struct platform_device *pdev)
3260{
3261 struct device *dev = &pdev->dev;
3262 struct ata_host *host = dev_get_drvdata(dev);
f351b2d6
SB		 3263
3264 ata_host_detach(host);
f351b2d6 3265 return 0;
20f733e7
BR		 3266}
3267
f351b2d6
SB		 3268static struct platform_driver mv_platform_driver = {
3269 .probe = mv_platform_probe,
3270 .remove = __devexit_p(mv_platform_remove),
3271 .driver = {
3272 .name = DRV_NAME,
3273 .owner = THIS_MODULE,
3274 },
3275};
3276
3277
7bb3c529 3278#ifdef CONFIG_PCI
f351b2d6
SB		 3279static int mv_pci_init_one(struct pci_dev *pdev,
3280 const struct pci_device_id *ent);
3281
7bb3c529
SB		 3282
3283static struct pci_driver mv_pci_driver = {
3284 .name = DRV_NAME,
3285 .id_table = mv_pci_tbl,
f351b2d6 3286 .probe = mv_pci_init_one,
7bb3c529
SB		 3287 .remove = ata_pci_remove_one,
3288};
3289
3290/*
3291 * module options
3292 */
3293static int msi; /* Use PCI msi; either zero (off, default) or non-zero */
3294
3295
3296/* move to PCI layer or libata core? */
3297static int pci_go_64(struct pci_dev *pdev)
3298{
3299 int rc;
3300
3301 if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
3302 rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
3303 if (rc) {
3304 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
3305 if (rc) {
3306 dev_printk(KERN_ERR, &pdev->dev,
3307 "64-bit DMA enable failed\n");
3308 return rc;
3309 }
3310 }
3311 } else {
3312 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
3313 if (rc) {
3314 dev_printk(KERN_ERR, &pdev->dev,
3315 "32-bit DMA enable failed\n");
3316 return rc;
3317 }
3318 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
3319 if (rc) {
3320 dev_printk(KERN_ERR, &pdev->dev,
3321 "32-bit consistent DMA enable failed\n");
3322 return rc;
3323 }
3324 }
3325
3326 return rc;
3327}
3328
05b308e1
BR		 3329/**
3330 * mv_print_info - Dump key info to kernel log for perusal.
4447d351 3331 * @host: ATA host to print info about
05b308e1
BR		 3332 *
3333 * FIXME: complete this.
3334 *
3335 * LOCKING:
3336 * Inherited from caller.
3337 */
4447d351 3338static void mv_print_info(struct ata_host *host)
31961943 3339{
4447d351
TH		 3340 struct pci_dev *pdev = to_pci_dev(host->dev);
3341 struct mv_host_priv *hpriv = host->private_data;
44c10138 3342 u8 scc;
c1e4fe71 3343 const char *scc_s, *gen;
31961943
BR		 3344
3345 /* Use this to determine the HW stepping of the chip so we know
3346 * what errata to workaround
3347 */
31961943
BR		 3348 pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &scc);
3349 if (scc == 0)
3350 scc_s = "SCSI";
3351 else if (scc == 0x01)
3352 scc_s = "RAID";
3353 else
c1e4fe71
JG		 3354 scc_s = "?";
3355
3356 if (IS_GEN_I(hpriv))
3357 gen = "I";
3358 else if (IS_GEN_II(hpriv))
3359 gen = "II";
3360 else if (IS_GEN_IIE(hpriv))
3361 gen = "IIE";
3362 else
3363 gen = "?";
31961943 3364
a9524a76 3365 dev_printk(KERN_INFO, &pdev->dev,
c1e4fe71
JG		 3366 "Gen-%s %u slots %u ports %s mode IRQ via %s\n",
3367 gen, (unsigned)MV_MAX_Q_DEPTH, host->n_ports,
31961943
BR		 3368 scc_s, (MV_HP_FLAG_MSI & hpriv->hp_flags) ? "MSI" : "INTx");
3369}
3370
05b308e1 3371/**
f351b2d6 3372 * mv_pci_init_one - handle a positive probe of a PCI Marvell host
05b308e1
BR		 3373 * @pdev: PCI device found
3374 * @ent: PCI device ID entry for the matched host
3375 *
3376 * LOCKING:
3377 * Inherited from caller.
3378 */
f351b2d6
SB		 3379static int mv_pci_init_one(struct pci_dev *pdev,
3380 const struct pci_device_id *ent)
20f733e7 3381{
2dcb407e 3382 static int printed_version;
20f733e7 3383 unsigned int board_idx = (unsigned int)ent->driver_data;
4447d351
TH		 3384 const struct ata_port_info *ppi[] = { &mv_port_info[board_idx], NULL };
3385 struct ata_host *host;
3386 struct mv_host_priv *hpriv;
3387 int n_ports, rc;
20f733e7 3388
a9524a76
JG		 3389 if (!printed_version++)
3390 dev_printk(KERN_INFO, &pdev->dev, "version " DRV_VERSION "\n");
20f733e7 3391
4447d351
TH		 3392 /* allocate host */
3393 n_ports = mv_get_hc_count(ppi[0]->flags) * MV_PORTS_PER_HC;
3394
3395 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
3396 hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL);
3397 if (!host || !hpriv)
3398 return -ENOMEM;
3399 host->private_data = hpriv;
f351b2d6 3400 hpriv->n_ports = n_ports;
4447d351
TH		 3401
3402 /* acquire resources */
24dc5f33
TH		 3403 rc = pcim_enable_device(pdev);
3404 if (rc)
20f733e7 3405 return rc;
20f733e7 3406
0d5ff566
TH		 3407 rc = pcim_iomap_regions(pdev, 1 << MV_PRIMARY_BAR, DRV_NAME);
3408 if (rc == -EBUSY)
24dc5f33 3409 pcim_pin_device(pdev);
0d5ff566 3410 if (rc)
24dc5f33 3411 return rc;
4447d351 3412 host->iomap = pcim_iomap_table(pdev);
f351b2d6 3413 hpriv->base = host->iomap[MV_PRIMARY_BAR];
20f733e7 3414
d88184fb
JG		 3415 rc = pci_go_64(pdev);
3416 if (rc)
3417 return rc;
3418
da2fa9ba
ML		 3419 rc = mv_create_dma_pools(hpriv, &pdev->dev);
3420 if (rc)
3421 return rc;
3422
20f733e7 3423 /* initialize adapter */
4447d351 3424 rc = mv_init_host(host, board_idx);
24dc5f33
TH		 3425 if (rc)
3426 return rc;
20f733e7 3427
31961943 3428 /* Enable interrupts */
6a59dcf8 3429 if (msi && pci_enable_msi(pdev))
31961943 3430 pci_intx(pdev, 1);
20f733e7 3431
31961943 3432 mv_dump_pci_cfg(pdev, 0x68);
4447d351 3433 mv_print_info(host);
20f733e7 3434
4447d351 3435 pci_set_master(pdev);
ea8b4db9 3436 pci_try_set_mwi(pdev);
4447d351 3437 return ata_host_activate(host, pdev->irq, mv_interrupt, IRQF_SHARED,
c5d3e45a 3438 IS_GEN_I(hpriv) ? &mv5_sht : &mv6_sht);
20f733e7 3439}
7bb3c529 3440#endif
20f733e7 3441
f351b2d6
SB		 3442static int mv_platform_probe(struct platform_device *pdev);
3443static int __devexit mv_platform_remove(struct platform_device *pdev);
3444
20f733e7
BR		 3445static int __init mv_init(void)
3446{
7bb3c529
SB		 3447 int rc = -ENODEV;
3448#ifdef CONFIG_PCI
3449 rc = pci_register_driver(&mv_pci_driver);
f351b2d6
SB		 3450 if (rc < 0)
3451 return rc;
3452#endif
3453 rc = platform_driver_register(&mv_platform_driver);
3454
3455#ifdef CONFIG_PCI
3456 if (rc < 0)
3457 pci_unregister_driver(&mv_pci_driver);
7bb3c529
SB		 3458#endif
3459 return rc;
20f733e7
BR		 3460}
3461
3462static void __exit mv_exit(void)
3463{
7bb3c529 3464#ifdef CONFIG_PCI
20f733e7 3465 pci_unregister_driver(&mv_pci_driver);
7bb3c529 3466#endif
f351b2d6 3467 platform_driver_unregister(&mv_platform_driver);
20f733e7
BR		 3468}
3469
3470MODULE_AUTHOR("Brett Russ");
3471MODULE_DESCRIPTION("SCSI low-level driver for Marvell SATA controllers");
3472MODULE_LICENSE("GPL");
3473MODULE_DEVICE_TABLE(pci, mv_pci_tbl);
3474MODULE_VERSION(DRV_VERSION);
17c5aab5 3475MODULE_ALIAS("platform:" DRV_NAME);
20f733e7 3476
7bb3c529 3477#ifdef CONFIG_PCI
ddef9bb3
JG		 3478module_param(msi, int, 0444);
3479MODULE_PARM_DESC(msi, "Enable use of PCI MSI (0=off, 1=on)");
7bb3c529 3480#endif
ddef9bb3 3481
20f733e7
BR		 3482module_init(mv_init);
3483module_exit(mv_exit);
Linux 6.x block layer and io_uring tree(s)