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[libata] Export ata_pio_queue_task() so that it can be used from sata_mv.
[linux-2.6-block.git] / drivers / ata / sata_mv.c
CommitLineData
20f733e7
BR		 1/*
2 * sata_mv.c - Marvell SATA support
3 *
e12bef50 4 * Copyright 2008: Marvell Corporation, all rights reserved.
8b260248 5 * Copyright 2005: EMC Corporation, all rights reserved.
e2b1be56 6 * Copyright 2005 Red Hat, Inc. All rights reserved.
20f733e7
BR		 7 *
8 * Please ALWAYS copy linux-ide@vger.kernel.org on emails.
9 *
10 * This program is free software; you can redistribute it and/or modify
11 * it under the terms of the GNU General Public License as published by
12 * the Free Software Foundation; version 2 of the License.
13 *
14 * This program is distributed in the hope that it will be useful,
15 * but WITHOUT ANY WARRANTY; without even the implied warranty of
16 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
17 * GNU General Public License for more details.
18 *
19 * You should have received a copy of the GNU General Public License
20 * along with this program; if not, write to the Free Software
21 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
22 *
23 */
24
4a05e209 25/*
85afb934
ML		 26 * sata_mv TODO list:
27 *
28 * --> Errata workaround for NCQ device errors.
29 *
30 * --> More errata workarounds for PCI-X.
31 *
32 * --> Complete a full errata audit for all chipsets to identify others.
33 *
85afb934
ML		 34 * --> Develop a low-power-consumption strategy, and implement it.
35 *
36 * --> [Experiment, low priority] Investigate interrupt coalescing.
37 * Quite often, especially with PCI Message Signalled Interrupts (MSI),
38 * the overhead reduced by interrupt mitigation is quite often not
39 * worth the latency cost.
40 *
41 * --> [Experiment, Marvell value added] Is it possible to use target
42 * mode to cross-connect two Linux boxes with Marvell cards? If so,
43 * creating LibATA target mode support would be very interesting.
44 *
45 * Target mode, for those without docs, is the ability to directly
46 * connect two SATA ports.
47 */
4a05e209 48
20f733e7
BR		 49#include <linux/kernel.h>
50#include <linux/module.h>
51#include <linux/pci.h>
52#include <linux/init.h>
53#include <linux/blkdev.h>
54#include <linux/delay.h>
55#include <linux/interrupt.h>
8d8b6004 56#include <linux/dmapool.h>
20f733e7 57#include <linux/dma-mapping.h>
a9524a76 58#include <linux/device.h>
f351b2d6
SB		 59#include <linux/platform_device.h>
60#include <linux/ata_platform.h>
15a32632 61#include <linux/mbus.h>
c46938cc 62#include <linux/bitops.h>
20f733e7 63#include <scsi/scsi_host.h>
193515d5 64#include <scsi/scsi_cmnd.h>
6c08772e 65#include <scsi/scsi_device.h>
20f733e7 66#include <linux/libata.h>
20f733e7
BR		 67
68#define DRV_NAME "sata_mv"
da14265e 69#define DRV_VERSION "1.26"
20f733e7
BR		 70
71enum {
72 /* BAR's are enumerated in terms of pci_resource_start() terms */
73 MV_PRIMARY_BAR = 0, /* offset 0x10: memory space */
74 MV_IO_BAR = 2, /* offset 0x18: IO space */
75 MV_MISC_BAR = 3, /* offset 0x1c: FLASH, NVRAM, SRAM */
76
77 MV_MAJOR_REG_AREA_SZ = 0x10000, /* 64KB */
78 MV_MINOR_REG_AREA_SZ = 0x2000, /* 8KB */
79
80 MV_PCI_REG_BASE = 0,
81 MV_IRQ_COAL_REG_BASE = 0x18000, /* 6xxx part only */
615ab953
ML		 82 MV_IRQ_COAL_CAUSE = (MV_IRQ_COAL_REG_BASE + 0x08),
83 MV_IRQ_COAL_CAUSE_LO = (MV_IRQ_COAL_REG_BASE + 0x88),
84 MV_IRQ_COAL_CAUSE_HI = (MV_IRQ_COAL_REG_BASE + 0x8c),
85 MV_IRQ_COAL_THRESHOLD = (MV_IRQ_COAL_REG_BASE + 0xcc),
86 MV_IRQ_COAL_TIME_THRESHOLD = (MV_IRQ_COAL_REG_BASE + 0xd0),
87
20f733e7 88 MV_SATAHC0_REG_BASE = 0x20000,
8e7decdb
ML		 89 MV_FLASH_CTL_OFS = 0x1046c,
90 MV_GPIO_PORT_CTL_OFS = 0x104f0,
91 MV_RESET_CFG_OFS = 0x180d8,
20f733e7
BR		 92
93 MV_PCI_REG_SZ = MV_MAJOR_REG_AREA_SZ,
94 MV_SATAHC_REG_SZ = MV_MAJOR_REG_AREA_SZ,
95 MV_SATAHC_ARBTR_REG_SZ = MV_MINOR_REG_AREA_SZ, /* arbiter */
96 MV_PORT_REG_SZ = MV_MINOR_REG_AREA_SZ,
97
31961943
BR		 98 MV_MAX_Q_DEPTH = 32,
99 MV_MAX_Q_DEPTH_MASK = MV_MAX_Q_DEPTH - 1,
100
101 /* CRQB needs alignment on a 1KB boundary. Size == 1KB
102 * CRPB needs alignment on a 256B boundary. Size == 256B
31961943
BR		 103 * ePRD (SG) entries need alignment on a 16B boundary. Size == 16B
104 */
105 MV_CRQB_Q_SZ = (32 * MV_MAX_Q_DEPTH),
106 MV_CRPB_Q_SZ = (8 * MV_MAX_Q_DEPTH),
da2fa9ba 107 MV_MAX_SG_CT = 256,
31961943 108 MV_SG_TBL_SZ = (16 * MV_MAX_SG_CT),
31961943 109
352fab70 110 /* Determine hc from 0-7 port: hc = port >> MV_PORT_HC_SHIFT */
20f733e7 111 MV_PORT_HC_SHIFT = 2,
352fab70
ML		 112 MV_PORTS_PER_HC = (1 << MV_PORT_HC_SHIFT), /* 4 */
113 /* Determine hc port from 0-7 port: hardport = port & MV_PORT_MASK */
114 MV_PORT_MASK = (MV_PORTS_PER_HC - 1), /* 3 */
20f733e7
BR		 115
116 /* Host Flags */
117 MV_FLAG_DUAL_HC = (1 << 30), /* two SATA Host Controllers */
118 MV_FLAG_IRQ_COALESCE = (1 << 29), /* IRQ coalescing capability */
7bb3c529 119
c5d3e45a 120 MV_COMMON_FLAGS = ATA_FLAG_SATA | ATA_FLAG_NO_LEGACY |
91b1a84c 121 ATA_FLAG_MMIO | ATA_FLAG_PIO_POLLING,
ad3aef51 122
91b1a84c 123 MV_GEN_I_FLAGS = MV_COMMON_FLAGS | ATA_FLAG_NO_ATAPI,
20f733e7 124
91b1a84c 125 MV_GEN_II_FLAGS = MV_COMMON_FLAGS | MV_FLAG_IRQ_COALESCE |
ad3aef51 126 ATA_FLAG_PMP | ATA_FLAG_ACPI_SATA |
da14265e 127 ATA_FLAG_NCQ,
91b1a84c
ML		 128
129 MV_GEN_IIE_FLAGS = MV_GEN_II_FLAGS | ATA_FLAG_AN,
ad3aef51 130
31961943
BR		 131 CRQB_FLAG_READ = (1 << 0),
132 CRQB_TAG_SHIFT = 1,
c5d3e45a 133 CRQB_IOID_SHIFT = 6, /* CRQB Gen-II/IIE IO Id shift */
e12bef50 134 CRQB_PMP_SHIFT = 12, /* CRQB Gen-II/IIE PMP shift */
c5d3e45a 135 CRQB_HOSTQ_SHIFT = 17, /* CRQB Gen-II/IIE HostQueTag shift */
31961943
BR		 136 CRQB_CMD_ADDR_SHIFT = 8,
137 CRQB_CMD_CS = (0x2 << 11),
138 CRQB_CMD_LAST = (1 << 15),
139
140 CRPB_FLAG_STATUS_SHIFT = 8,
c5d3e45a
JG		 141 CRPB_IOID_SHIFT_6 = 5, /* CRPB Gen-II IO Id shift */
142 CRPB_IOID_SHIFT_7 = 7, /* CRPB Gen-IIE IO Id shift */
31961943
BR		 143
144 EPRD_FLAG_END_OF_TBL = (1 << 31),
145
20f733e7
BR		 146 /* PCI interface registers */
147
31961943 148 PCI_COMMAND_OFS = 0xc00,
8e7decdb 149 PCI_COMMAND_MRDTRIG = (1 << 7), /* PCI Master Read Trigger */
31961943 150
20f733e7
BR		 151 PCI_MAIN_CMD_STS_OFS = 0xd30,
152 STOP_PCI_MASTER = (1 << 2),
153 PCI_MASTER_EMPTY = (1 << 3),
154 GLOB_SFT_RST = (1 << 4),
155
8e7decdb
ML		 156 MV_PCI_MODE_OFS = 0xd00,
157 MV_PCI_MODE_MASK = 0x30,
158
522479fb
JG		 159 MV_PCI_EXP_ROM_BAR_CTL = 0xd2c,
160 MV_PCI_DISC_TIMER = 0xd04,
161 MV_PCI_MSI_TRIGGER = 0xc38,
162 MV_PCI_SERR_MASK = 0xc28,
8e7decdb 163 MV_PCI_XBAR_TMOUT_OFS = 0x1d04,
522479fb
JG		 164 MV_PCI_ERR_LOW_ADDRESS = 0x1d40,
165 MV_PCI_ERR_HIGH_ADDRESS = 0x1d44,
166 MV_PCI_ERR_ATTRIBUTE = 0x1d48,
167 MV_PCI_ERR_COMMAND = 0x1d50,
168
02a121da
ML		 169 PCI_IRQ_CAUSE_OFS = 0x1d58,
170 PCI_IRQ_MASK_OFS = 0x1d5c,
20f733e7
BR		 171 PCI_UNMASK_ALL_IRQS = 0x7fffff, /* bits 22-0 */
172
02a121da
ML		 173 PCIE_IRQ_CAUSE_OFS = 0x1900,
174 PCIE_IRQ_MASK_OFS = 0x1910,
646a4da5 175 PCIE_UNMASK_ALL_IRQS = 0x40a, /* assorted bits */
02a121da 176
7368f919
ML		 177 /* Host Controller Main Interrupt Cause/Mask registers (1 per-chip) */
178 PCI_HC_MAIN_IRQ_CAUSE_OFS = 0x1d60,
179 PCI_HC_MAIN_IRQ_MASK_OFS = 0x1d64,
180 SOC_HC_MAIN_IRQ_CAUSE_OFS = 0x20020,
181 SOC_HC_MAIN_IRQ_MASK_OFS = 0x20024,
352fab70
ML		 182 ERR_IRQ = (1 << 0), /* shift by port # */
183 DONE_IRQ = (1 << 1), /* shift by port # */
20f733e7
BR		 184 HC0_IRQ_PEND = 0x1ff, /* bits 0-8 = HC0's ports */
185 HC_SHIFT = 9, /* bits 9-17 = HC1's ports */
186 PCI_ERR = (1 << 18),
187 TRAN_LO_DONE = (1 << 19), /* 6xxx: IRQ coalescing */
188 TRAN_HI_DONE = (1 << 20), /* 6xxx: IRQ coalescing */
fb621e2f
JG		 189 PORTS_0_3_COAL_DONE = (1 << 8),
190 PORTS_4_7_COAL_DONE = (1 << 17),
20f733e7
BR		 191 PORTS_0_7_COAL_DONE = (1 << 21), /* 6xxx: IRQ coalescing */
192 GPIO_INT = (1 << 22),
193 SELF_INT = (1 << 23),
194 TWSI_INT = (1 << 24),
195 HC_MAIN_RSVD = (0x7f << 25), /* bits 31-25 */
fb621e2f 196 HC_MAIN_RSVD_5 = (0x1fff << 19), /* bits 31-19 */
e12bef50 197 HC_MAIN_RSVD_SOC = (0x3fffffb << 6), /* bits 31-9, 7-6 */
20f733e7
BR		 198
199 /* SATAHC registers */
200 HC_CFG_OFS = 0,
201
202 HC_IRQ_CAUSE_OFS = 0x14,
352fab70
ML		 203 DMA_IRQ = (1 << 0), /* shift by port # */
204 HC_COAL_IRQ = (1 << 4), /* IRQ coalescing */
20f733e7
BR		 205 DEV_IRQ = (1 << 8), /* shift by port # */
206
207 /* Shadow block registers */
31961943
BR		 208 SHD_BLK_OFS = 0x100,
209 SHD_CTL_AST_OFS = 0x20, /* ofs from SHD_BLK_OFS */
20f733e7
BR		 210
211 /* SATA registers */
212 SATA_STATUS_OFS = 0x300, /* ctrl, err regs follow status */
213 SATA_ACTIVE_OFS = 0x350,
0c58912e 214 SATA_FIS_IRQ_CAUSE_OFS = 0x364,
c443c500 215 SATA_FIS_IRQ_AN = (1 << 9), /* async notification */
17c5aab5 216
e12bef50 217 LTMODE_OFS = 0x30c,
17c5aab5
ML		 218 LTMODE_BIT8 = (1 << 8), /* unknown, but necessary */
219
47c2b677 220 PHY_MODE3 = 0x310,
bca1c4eb 221 PHY_MODE4 = 0x314,
ba069e37
ML		 222 PHY_MODE4_CFG_MASK = 0x00000003, /* phy internal config field */
223 PHY_MODE4_CFG_VALUE = 0x00000001, /* phy internal config field */
224 PHY_MODE4_RSVD_ZEROS = 0x5de3fffa, /* Gen2e always write zeros */
225 PHY_MODE4_RSVD_ONES = 0x00000005, /* Gen2e always write ones */
226
bca1c4eb 227 PHY_MODE2 = 0x330,
e12bef50 228 SATA_IFCTL_OFS = 0x344,
8e7decdb 229 SATA_TESTCTL_OFS = 0x348,
e12bef50
ML		 230 SATA_IFSTAT_OFS = 0x34c,
231 VENDOR_UNIQUE_FIS_OFS = 0x35c,
17c5aab5 232
8e7decdb
ML		 233 FISCFG_OFS = 0x360,
234 FISCFG_WAIT_DEV_ERR = (1 << 8), /* wait for host on DevErr */
235 FISCFG_SINGLE_SYNC = (1 << 16), /* SYNC on DMA activation */
17c5aab5 236
c9d39130 237 MV5_PHY_MODE = 0x74,
8e7decdb
ML		 238 MV5_LTMODE_OFS = 0x30,
239 MV5_PHY_CTL_OFS = 0x0C,
240 SATA_INTERFACE_CFG_OFS = 0x050,
bca1c4eb
JG		 241
242 MV_M2_PREAMP_MASK = 0x7e0,
20f733e7
BR		 243
244 /* Port registers */
245 EDMA_CFG_OFS = 0,
0c58912e
ML		 246 EDMA_CFG_Q_DEPTH = 0x1f, /* max device queue depth */
247 EDMA_CFG_NCQ = (1 << 5), /* for R/W FPDMA queued */
248 EDMA_CFG_NCQ_GO_ON_ERR = (1 << 14), /* continue on error */
249 EDMA_CFG_RD_BRST_EXT = (1 << 11), /* read burst 512B */
250 EDMA_CFG_WR_BUFF_LEN = (1 << 13), /* write buffer 512B */
e12bef50
ML		 251 EDMA_CFG_EDMA_FBS = (1 << 16), /* EDMA FIS-Based Switching */
252 EDMA_CFG_FBS = (1 << 26), /* FIS-Based Switching */
20f733e7
BR		 253
254 EDMA_ERR_IRQ_CAUSE_OFS = 0x8,
255 EDMA_ERR_IRQ_MASK_OFS = 0xc,
6c1153e0
JG		 256 EDMA_ERR_D_PAR = (1 << 0), /* UDMA data parity err */
257 EDMA_ERR_PRD_PAR = (1 << 1), /* UDMA PRD parity err */
258 EDMA_ERR_DEV = (1 << 2), /* device error */
259 EDMA_ERR_DEV_DCON = (1 << 3), /* device disconnect */
260 EDMA_ERR_DEV_CON = (1 << 4), /* device connected */
261 EDMA_ERR_SERR = (1 << 5), /* SError bits [WBDST] raised */
c5d3e45a
JG		 262 EDMA_ERR_SELF_DIS = (1 << 7), /* Gen II/IIE self-disable */
263 EDMA_ERR_SELF_DIS_5 = (1 << 8), /* Gen I self-disable */
6c1153e0 264 EDMA_ERR_BIST_ASYNC = (1 << 8), /* BIST FIS or Async Notify */
c5d3e45a 265 EDMA_ERR_TRANS_IRQ_7 = (1 << 8), /* Gen IIE transprt layer irq */
6c1153e0
JG		 266 EDMA_ERR_CRQB_PAR = (1 << 9), /* CRQB parity error */
267 EDMA_ERR_CRPB_PAR = (1 << 10), /* CRPB parity error */
268 EDMA_ERR_INTRL_PAR = (1 << 11), /* internal parity error */
269 EDMA_ERR_IORDY = (1 << 12), /* IORdy timeout */
646a4da5 270
6c1153e0 271 EDMA_ERR_LNK_CTRL_RX = (0xf << 13), /* link ctrl rx error */
646a4da5
ML		 272 EDMA_ERR_LNK_CTRL_RX_0 = (1 << 13), /* transient: CRC err */
273 EDMA_ERR_LNK_CTRL_RX_1 = (1 << 14), /* transient: FIFO err */
274 EDMA_ERR_LNK_CTRL_RX_2 = (1 << 15), /* fatal: caught SYNC */
275 EDMA_ERR_LNK_CTRL_RX_3 = (1 << 16), /* transient: FIS rx err */
276
6c1153e0 277 EDMA_ERR_LNK_DATA_RX = (0xf << 17), /* link data rx error */
646a4da5 278
6c1153e0 279 EDMA_ERR_LNK_CTRL_TX = (0x1f << 21), /* link ctrl tx error */
646a4da5
ML		 280 EDMA_ERR_LNK_CTRL_TX_0 = (1 << 21), /* transient: CRC err */
281 EDMA_ERR_LNK_CTRL_TX_1 = (1 << 22), /* transient: FIFO err */
282 EDMA_ERR_LNK_CTRL_TX_2 = (1 << 23), /* transient: caught SYNC */
283 EDMA_ERR_LNK_CTRL_TX_3 = (1 << 24), /* transient: caught DMAT */
284 EDMA_ERR_LNK_CTRL_TX_4 = (1 << 25), /* transient: FIS collision */
285
6c1153e0 286 EDMA_ERR_LNK_DATA_TX = (0x1f << 26), /* link data tx error */
646a4da5 287
6c1153e0 288 EDMA_ERR_TRANS_PROTO = (1 << 31), /* transport protocol error */
c5d3e45a
JG		 289 EDMA_ERR_OVERRUN_5 = (1 << 5),
290 EDMA_ERR_UNDERRUN_5 = (1 << 6),
646a4da5
ML		 291
292 EDMA_ERR_IRQ_TRANSIENT = EDMA_ERR_LNK_CTRL_RX_0 |
293 EDMA_ERR_LNK_CTRL_RX_1 |
294 EDMA_ERR_LNK_CTRL_RX_3 |
85afb934 295 EDMA_ERR_LNK_CTRL_TX,
646a4da5 296
bdd4ddde
JG		 297 EDMA_EH_FREEZE = EDMA_ERR_D_PAR |
298 EDMA_ERR_PRD_PAR |
299 EDMA_ERR_DEV_DCON |
300 EDMA_ERR_DEV_CON |
301 EDMA_ERR_SERR |
302 EDMA_ERR_SELF_DIS |
6c1153e0 303 EDMA_ERR_CRQB_PAR |
bdd4ddde
JG		 304 EDMA_ERR_CRPB_PAR |
305 EDMA_ERR_INTRL_PAR |
306 EDMA_ERR_IORDY |
307 EDMA_ERR_LNK_CTRL_RX_2 |
308 EDMA_ERR_LNK_DATA_RX |
309 EDMA_ERR_LNK_DATA_TX |
310 EDMA_ERR_TRANS_PROTO,
e12bef50 311
bdd4ddde
JG		 312 EDMA_EH_FREEZE_5 = EDMA_ERR_D_PAR |
313 EDMA_ERR_PRD_PAR |
314 EDMA_ERR_DEV_DCON |
315 EDMA_ERR_DEV_CON |
316 EDMA_ERR_OVERRUN_5 |
317 EDMA_ERR_UNDERRUN_5 |
318 EDMA_ERR_SELF_DIS_5 |
6c1153e0 319 EDMA_ERR_CRQB_PAR |
bdd4ddde
JG		 320 EDMA_ERR_CRPB_PAR |
321 EDMA_ERR_INTRL_PAR |
322 EDMA_ERR_IORDY,
20f733e7 323
31961943
BR		 324 EDMA_REQ_Q_BASE_HI_OFS = 0x10,
325 EDMA_REQ_Q_IN_PTR_OFS = 0x14, /* also contains BASE_LO */
31961943
BR		 326
327 EDMA_REQ_Q_OUT_PTR_OFS = 0x18,
328 EDMA_REQ_Q_PTR_SHIFT = 5,
329
330 EDMA_RSP_Q_BASE_HI_OFS = 0x1c,
331 EDMA_RSP_Q_IN_PTR_OFS = 0x20,
332 EDMA_RSP_Q_OUT_PTR_OFS = 0x24, /* also contains BASE_LO */
31961943
BR		 333 EDMA_RSP_Q_PTR_SHIFT = 3,
334
0ea9e179
JG		 335 EDMA_CMD_OFS = 0x28, /* EDMA command register */
336 EDMA_EN = (1 << 0), /* enable EDMA */
337 EDMA_DS = (1 << 1), /* disable EDMA; self-negated */
8e7decdb
ML		 338 EDMA_RESET = (1 << 2), /* reset eng/trans/link/phy */
339
340 EDMA_STATUS_OFS = 0x30, /* EDMA engine status */
341 EDMA_STATUS_CACHE_EMPTY = (1 << 6), /* GenIIe command cache empty */
342 EDMA_STATUS_IDLE = (1 << 7), /* GenIIe EDMA enabled/idle */
20f733e7 343
8e7decdb
ML		 344 EDMA_IORDY_TMOUT_OFS = 0x34,
345 EDMA_ARB_CFG_OFS = 0x38,
346
347 EDMA_HALTCOND_OFS = 0x60, /* GenIIe halt conditions */
c01e8a23 348 EDMA_UNKNOWN_RSVD_OFS = 0x6C, /* GenIIe unknown/reserved */
da14265e
ML		 349
350 BMDMA_CMD_OFS = 0x224, /* bmdma command register */
351 BMDMA_STATUS_OFS = 0x228, /* bmdma status register */
352 BMDMA_PRD_LOW_OFS = 0x22c, /* bmdma PRD addr 31:0 */
353 BMDMA_PRD_HIGH_OFS = 0x230, /* bmdma PRD addr 63:32 */
354
31961943
BR		 355 /* Host private flags (hp_flags) */
356 MV_HP_FLAG_MSI = (1 << 0),
47c2b677
JG		 357 MV_HP_ERRATA_50XXB0 = (1 << 1),
358 MV_HP_ERRATA_50XXB2 = (1 << 2),
359 MV_HP_ERRATA_60X1B2 = (1 << 3),
360 MV_HP_ERRATA_60X1C0 = (1 << 4),
0ea9e179
JG		 361 MV_HP_GEN_I = (1 << 6), /* Generation I: 50xx */
362 MV_HP_GEN_II = (1 << 7), /* Generation II: 60xx */
363 MV_HP_GEN_IIE = (1 << 8), /* Generation IIE: 6042/7042 */
02a121da 364 MV_HP_PCIE = (1 << 9), /* PCIe bus/regs: 7042 */
616d4a98 365 MV_HP_CUT_THROUGH = (1 << 10), /* can use EDMA cut-through */
1f398472 366 MV_HP_FLAG_SOC = (1 << 11), /* SystemOnChip, no PCI */
20f733e7 367
31961943 368 /* Port private flags (pp_flags) */
0ea9e179 369 MV_PP_FLAG_EDMA_EN = (1 << 0), /* is EDMA engine enabled? */
72109168 370 MV_PP_FLAG_NCQ_EN = (1 << 1), /* is EDMA set up for NCQ? */
00f42eab 371 MV_PP_FLAG_FBS_EN = (1 << 2), /* is EDMA set up for FBS? */
29d187bb 372 MV_PP_FLAG_DELAYED_EH = (1 << 3), /* delayed dev err handling */
d16ab3f6 373 MV_PP_FLAG_FAKE_ATA_BUSY = (1 << 4), /* ignore initial ATA_DRDY */
20f733e7
BR		 374};
375
ee9ccdf7
JG		 376#define IS_GEN_I(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_I)
377#define IS_GEN_II(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_II)
e4e7b892 378#define IS_GEN_IIE(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_IIE)
8e7decdb 379#define IS_PCIE(hpriv) ((hpriv)->hp_flags & MV_HP_PCIE)
1f398472 380#define IS_SOC(hpriv) ((hpriv)->hp_flags & MV_HP_FLAG_SOC)
bca1c4eb 381
15a32632
LB		 382#define WINDOW_CTRL(i) (0x20030 + ((i) << 4))
383#define WINDOW_BASE(i) (0x20034 + ((i) << 4))
384
095fec88 385enum {
baf14aa1
JG		 386 /* DMA boundary 0xffff is required by the s/g splitting
387 * we need on /length/ in mv_fill-sg().
388 */
389 MV_DMA_BOUNDARY = 0xffffU,
095fec88 390
0ea9e179
JG		 391 /* mask of register bits containing lower 32 bits
392 * of EDMA request queue DMA address
393 */
095fec88
JG		 394 EDMA_REQ_Q_BASE_LO_MASK = 0xfffffc00U,
395
0ea9e179 396 /* ditto, for response queue */
095fec88
JG		 397 EDMA_RSP_Q_BASE_LO_MASK = 0xffffff00U,
398};
399
522479fb
JG		 400enum chip_type {
401 chip_504x,
402 chip_508x,
403 chip_5080,
404 chip_604x,
405 chip_608x,
e4e7b892
JG		 406 chip_6042,
407 chip_7042,
f351b2d6 408 chip_soc,
522479fb
JG		 409};
410
31961943
BR		 411/* Command ReQuest Block: 32B */
412struct mv_crqb {
e1469874
ML		 413 __le32 sg_addr;
414 __le32 sg_addr_hi;
415 __le16 ctrl_flags;
416 __le16 ata_cmd[11];
31961943 417};
20f733e7 418
e4e7b892 419struct mv_crqb_iie {
e1469874
ML		 420 __le32 addr;
421 __le32 addr_hi;
422 __le32 flags;
423 __le32 len;
424 __le32 ata_cmd[4];
e4e7b892
JG		 425};
426
31961943
BR		 427/* Command ResPonse Block: 8B */
428struct mv_crpb {
e1469874
ML		 429 __le16 id;
430 __le16 flags;
431 __le32 tmstmp;
20f733e7
BR		 432};
433
31961943
BR		 434/* EDMA Physical Region Descriptor (ePRD); A.K.A. SG */
435struct mv_sg {
e1469874
ML		 436 __le32 addr;
437 __le32 flags_size;
438 __le32 addr_hi;
439 __le32 reserved;
31961943 440};
20f733e7 441
08da1759
ML		 442/*
443 * We keep a local cache of a few frequently accessed port
444 * registers here, to avoid having to read them (very slow)
445 * when switching between EDMA and non-EDMA modes.
446 */
447struct mv_cached_regs {
448 u32 fiscfg;
449 u32 ltmode;
450 u32 haltcond;
c01e8a23 451 u32 unknown_rsvd;
08da1759
ML		 452};
453
31961943
BR		 454struct mv_port_priv {
455 struct mv_crqb *crqb;
456 dma_addr_t crqb_dma;
457 struct mv_crpb *crpb;
458 dma_addr_t crpb_dma;
eb73d558
ML		 459 struct mv_sg *sg_tbl[MV_MAX_Q_DEPTH];
460 dma_addr_t sg_tbl_dma[MV_MAX_Q_DEPTH];
bdd4ddde
JG		 461
462 unsigned int req_idx;
463 unsigned int resp_idx;
464
31961943 465 u32 pp_flags;
08da1759 466 struct mv_cached_regs cached;
29d187bb 467 unsigned int delayed_eh_pmp_map;
31961943
BR		 468};
469
bca1c4eb
JG		 470struct mv_port_signal {
471 u32 amps;
472 u32 pre;
473};
474
02a121da
ML		 475struct mv_host_priv {
476 u32 hp_flags;
96e2c487 477 u32 main_irq_mask;
02a121da
ML		 478 struct mv_port_signal signal[8];
479 const struct mv_hw_ops *ops;
f351b2d6
SB		 480 int n_ports;
481 void __iomem *base;
7368f919
ML		 482 void __iomem *main_irq_cause_addr;
483 void __iomem *main_irq_mask_addr;
02a121da
ML		 484 u32 irq_cause_ofs;
485 u32 irq_mask_ofs;
486 u32 unmask_all_irqs;
da2fa9ba
ML		 487 /*
488 * These consistent DMA memory pools give us guaranteed
489 * alignment for hardware-accessed data structures,
490 * and less memory waste in accomplishing the alignment.
491 */
492 struct dma_pool *crqb_pool;
493 struct dma_pool *crpb_pool;
494 struct dma_pool *sg_tbl_pool;
02a121da
ML		 495};
496
47c2b677 497struct mv_hw_ops {
2a47ce06
JG		 498 void (*phy_errata)(struct mv_host_priv *hpriv, void __iomem *mmio,
499 unsigned int port);
47c2b677
JG		 500 void (*enable_leds)(struct mv_host_priv *hpriv, void __iomem *mmio);
501 void (*read_preamp)(struct mv_host_priv *hpriv, int idx,
502 void __iomem *mmio);
c9d39130
JG		 503 int (*reset_hc)(struct mv_host_priv *hpriv, void __iomem *mmio,
504 unsigned int n_hc);
522479fb 505 void (*reset_flash)(struct mv_host_priv *hpriv, void __iomem *mmio);
7bb3c529 506 void (*reset_bus)(struct ata_host *host, void __iomem *mmio);
47c2b677
JG		 507};
508
82ef04fb
TH		 509static int mv_scr_read(struct ata_link *link, unsigned int sc_reg_in, u32 *val);
510static int mv_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val);
511static int mv5_scr_read(struct ata_link *link, unsigned int sc_reg_in, u32 *val);
512static int mv5_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val);
31961943
BR		 513static int mv_port_start(struct ata_port *ap);
514static void mv_port_stop(struct ata_port *ap);
3e4a1391 515static int mv_qc_defer(struct ata_queued_cmd *qc);
31961943 516static void mv_qc_prep(struct ata_queued_cmd *qc);
e4e7b892 517static void mv_qc_prep_iie(struct ata_queued_cmd *qc);
9a3d9eb0 518static unsigned int mv_qc_issue(struct ata_queued_cmd *qc);
a1efdaba
TH		 519static int mv_hardreset(struct ata_link *link, unsigned int *class,
520 unsigned long deadline);
bdd4ddde
JG		 521static void mv_eh_freeze(struct ata_port *ap);
522static void mv_eh_thaw(struct ata_port *ap);
f273827e 523static void mv6_dev_config(struct ata_device *dev);
20f733e7 524
2a47ce06
JG		 525static void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
526 unsigned int port);
47c2b677
JG		 527static void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio);
528static void mv5_read_preamp(struct mv_host_priv *hpriv, int idx,
529 void __iomem *mmio);
c9d39130
JG		 530static int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
531 unsigned int n_hc);
522479fb 532static void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio);
7bb3c529 533static void mv5_reset_bus(struct ata_host *host, void __iomem *mmio);
47c2b677 534
2a47ce06
JG		 535static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
536 unsigned int port);
47c2b677
JG		 537static void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio);
538static void mv6_read_preamp(struct mv_host_priv *hpriv, int idx,
539 void __iomem *mmio);
c9d39130
JG		 540static int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
541 unsigned int n_hc);
522479fb 542static void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio);
f351b2d6
SB		 543static void mv_soc_enable_leds(struct mv_host_priv *hpriv,
544 void __iomem *mmio);
545static void mv_soc_read_preamp(struct mv_host_priv *hpriv, int idx,
546 void __iomem *mmio);
547static int mv_soc_reset_hc(struct mv_host_priv *hpriv,
548 void __iomem *mmio, unsigned int n_hc);
549static void mv_soc_reset_flash(struct mv_host_priv *hpriv,
550 void __iomem *mmio);
551static void mv_soc_reset_bus(struct ata_host *host, void __iomem *mmio);
7bb3c529 552static void mv_reset_pci_bus(struct ata_host *host, void __iomem *mmio);
e12bef50 553static void mv_reset_channel(struct mv_host_priv *hpriv, void __iomem *mmio,
c9d39130 554 unsigned int port_no);
e12bef50 555static int mv_stop_edma(struct ata_port *ap);
b562468c 556static int mv_stop_edma_engine(void __iomem *port_mmio);
00b81235 557static void mv_edma_cfg(struct ata_port *ap, int want_ncq, int want_edma);
47c2b677 558
e49856d8
ML		 559static void mv_pmp_select(struct ata_port *ap, int pmp);
560static int mv_pmp_hardreset(struct ata_link *link, unsigned int *class,
561 unsigned long deadline);
562static int mv_softreset(struct ata_link *link, unsigned int *class,
563 unsigned long deadline);
29d187bb 564static void mv_pmp_error_handler(struct ata_port *ap);
4c299ca3
ML		 565static void mv_process_crpb_entries(struct ata_port *ap,
566 struct mv_port_priv *pp);
47c2b677 567
da14265e
ML		 568static void mv_sff_irq_clear(struct ata_port *ap);
569static int mv_check_atapi_dma(struct ata_queued_cmd *qc);
570static void mv_bmdma_setup(struct ata_queued_cmd *qc);
571static void mv_bmdma_start(struct ata_queued_cmd *qc);
572static void mv_bmdma_stop(struct ata_queued_cmd *qc);
573static u8 mv_bmdma_status(struct ata_port *ap);
d16ab3f6 574static u8 mv_sff_check_status(struct ata_port *ap);
da14265e 575
eb73d558
ML		 576/* .sg_tablesize is (MV_MAX_SG_CT / 2) in the structures below
577 * because we have to allow room for worst case splitting of
578 * PRDs for 64K boundaries in mv_fill_sg().
579 */
c5d3e45a 580static struct scsi_host_template mv5_sht = {
68d1d07b 581 ATA_BASE_SHT(DRV_NAME),
baf14aa1 582 .sg_tablesize = MV_MAX_SG_CT / 2,
c5d3e45a 583 .dma_boundary = MV_DMA_BOUNDARY,
c5d3e45a
JG		 584};
585
586static struct scsi_host_template mv6_sht = {
68d1d07b 587 ATA_NCQ_SHT(DRV_NAME),
138bfdd0 588 .can_queue = MV_MAX_Q_DEPTH - 1,
baf14aa1 589 .sg_tablesize = MV_MAX_SG_CT / 2,
20f733e7 590 .dma_boundary = MV_DMA_BOUNDARY,
20f733e7
BR		 591};
592
029cfd6b
TH		 593static struct ata_port_operations mv5_ops = {
594 .inherits = &ata_sff_port_ops,
c9d39130 595
3e4a1391 596 .qc_defer = mv_qc_defer,
c9d39130
JG		 597 .qc_prep = mv_qc_prep,
598 .qc_issue = mv_qc_issue,
c9d39130 599
bdd4ddde
JG		 600 .freeze = mv_eh_freeze,
601 .thaw = mv_eh_thaw,
a1efdaba 602 .hardreset = mv_hardreset,
a1efdaba 603 .error_handler = ata_std_error_handler, /* avoid SFF EH */
029cfd6b 604 .post_internal_cmd = ATA_OP_NULL,
bdd4ddde 605
c9d39130
JG		 606 .scr_read = mv5_scr_read,
607 .scr_write = mv5_scr_write,
608
609 .port_start = mv_port_start,
610 .port_stop = mv_port_stop,
c9d39130
JG		 611};
612
029cfd6b
TH		 613static struct ata_port_operations mv6_ops = {
614 .inherits = &mv5_ops,
f273827e 615 .dev_config = mv6_dev_config,
20f733e7
BR		 616 .scr_read = mv_scr_read,
617 .scr_write = mv_scr_write,
618
e49856d8
ML		 619 .pmp_hardreset = mv_pmp_hardreset,
620 .pmp_softreset = mv_softreset,
621 .softreset = mv_softreset,
29d187bb 622 .error_handler = mv_pmp_error_handler,
da14265e 623
d16ab3f6 624 .sff_check_status = mv_sff_check_status,
da14265e
ML		 625 .sff_irq_clear = mv_sff_irq_clear,
626 .check_atapi_dma = mv_check_atapi_dma,
627 .bmdma_setup = mv_bmdma_setup,
628 .bmdma_start = mv_bmdma_start,
629 .bmdma_stop = mv_bmdma_stop,
630 .bmdma_status = mv_bmdma_status,
20f733e7
BR		 631};
632
029cfd6b
TH		 633static struct ata_port_operations mv_iie_ops = {
634 .inherits = &mv6_ops,
635 .dev_config = ATA_OP_NULL,
e4e7b892 636 .qc_prep = mv_qc_prep_iie,
e4e7b892
JG		 637};
638
98ac62de 639static const struct ata_port_info mv_port_info[] = {
20f733e7 640 { /* chip_504x */
91b1a84c 641 .flags = MV_GEN_I_FLAGS,
31961943 642 .pio_mask = 0x1f, /* pio0-4 */
bf6263a8 643 .udma_mask = ATA_UDMA6,
c9d39130 644 .port_ops = &mv5_ops,
20f733e7
BR		 645 },
646 { /* chip_508x */
91b1a84c 647 .flags = MV_GEN_I_FLAGS | MV_FLAG_DUAL_HC,
31961943 648 .pio_mask = 0x1f, /* pio0-4 */
bf6263a8 649 .udma_mask = ATA_UDMA6,
c9d39130 650 .port_ops = &mv5_ops,
20f733e7 651 },
47c2b677 652 { /* chip_5080 */
91b1a84c 653 .flags = MV_GEN_I_FLAGS | MV_FLAG_DUAL_HC,
47c2b677 654 .pio_mask = 0x1f, /* pio0-4 */
bf6263a8 655 .udma_mask = ATA_UDMA6,
c9d39130 656 .port_ops = &mv5_ops,
47c2b677 657 },
20f733e7 658 { /* chip_604x */
91b1a84c 659 .flags = MV_GEN_II_FLAGS,
31961943 660 .pio_mask = 0x1f, /* pio0-4 */
bf6263a8 661 .udma_mask = ATA_UDMA6,
c9d39130 662 .port_ops = &mv6_ops,
20f733e7
BR		 663 },
664 { /* chip_608x */
91b1a84c 665 .flags = MV_GEN_II_FLAGS | MV_FLAG_DUAL_HC,
31961943 666 .pio_mask = 0x1f, /* pio0-4 */
bf6263a8 667 .udma_mask = ATA_UDMA6,
c9d39130 668 .port_ops = &mv6_ops,
20f733e7 669 },
e4e7b892 670 { /* chip_6042 */
91b1a84c 671 .flags = MV_GEN_IIE_FLAGS,
e4e7b892 672 .pio_mask = 0x1f, /* pio0-4 */
bf6263a8 673 .udma_mask = ATA_UDMA6,
e4e7b892
JG		 674 .port_ops = &mv_iie_ops,
675 },
676 { /* chip_7042 */
91b1a84c 677 .flags = MV_GEN_IIE_FLAGS,
e4e7b892 678 .pio_mask = 0x1f, /* pio0-4 */
bf6263a8 679 .udma_mask = ATA_UDMA6,
e4e7b892
JG		 680 .port_ops = &mv_iie_ops,
681 },
f351b2d6 682 { /* chip_soc */
91b1a84c 683 .flags = MV_GEN_IIE_FLAGS,
17c5aab5
ML		 684 .pio_mask = 0x1f, /* pio0-4 */
685 .udma_mask = ATA_UDMA6,
686 .port_ops = &mv_iie_ops,
f351b2d6 687 },
20f733e7
BR		 688};
689
3b7d697d 690static const struct pci_device_id mv_pci_tbl[] = {
2d2744fc
JG		 691 { PCI_VDEVICE(MARVELL, 0x5040), chip_504x },
692 { PCI_VDEVICE(MARVELL, 0x5041), chip_504x },
693 { PCI_VDEVICE(MARVELL, 0x5080), chip_5080 },
694 { PCI_VDEVICE(MARVELL, 0x5081), chip_508x },
46c5784c
ML		 695 /* RocketRAID 1720/174x have different identifiers */
696 { PCI_VDEVICE(TTI, 0x1720), chip_6042 },
4462254a
ML		 697 { PCI_VDEVICE(TTI, 0x1740), chip_6042 },
698 { PCI_VDEVICE(TTI, 0x1742), chip_6042 },
2d2744fc
JG		 699
700 { PCI_VDEVICE(MARVELL, 0x6040), chip_604x },
701 { PCI_VDEVICE(MARVELL, 0x6041), chip_604x },
702 { PCI_VDEVICE(MARVELL, 0x6042), chip_6042 },
703 { PCI_VDEVICE(MARVELL, 0x6080), chip_608x },
704 { PCI_VDEVICE(MARVELL, 0x6081), chip_608x },
705
706 { PCI_VDEVICE(ADAPTEC2, 0x0241), chip_604x },
707
d9f9c6bc
FA		 708 /* Adaptec 1430SA */
709 { PCI_VDEVICE(ADAPTEC2, 0x0243), chip_7042 },
710
02a121da 711 /* Marvell 7042 support */
6a3d586d
MT		 712 { PCI_VDEVICE(MARVELL, 0x7042), chip_7042 },
713
02a121da
ML		 714 /* Highpoint RocketRAID PCIe series */
715 { PCI_VDEVICE(TTI, 0x2300), chip_7042 },
716 { PCI_VDEVICE(TTI, 0x2310), chip_7042 },
717
2d2744fc 718 { } /* terminate list */
20f733e7
BR		 719};
720
47c2b677
JG		 721static const struct mv_hw_ops mv5xxx_ops = {
722 .phy_errata = mv5_phy_errata,
723 .enable_leds = mv5_enable_leds,
724 .read_preamp = mv5_read_preamp,
725 .reset_hc = mv5_reset_hc,
522479fb
JG		 726 .reset_flash = mv5_reset_flash,
727 .reset_bus = mv5_reset_bus,
47c2b677
JG		 728};
729
730static const struct mv_hw_ops mv6xxx_ops = {
731 .phy_errata = mv6_phy_errata,
732 .enable_leds = mv6_enable_leds,
733 .read_preamp = mv6_read_preamp,
734 .reset_hc = mv6_reset_hc,
522479fb
JG		 735 .reset_flash = mv6_reset_flash,
736 .reset_bus = mv_reset_pci_bus,
47c2b677
JG		 737};
738
f351b2d6
SB		 739static const struct mv_hw_ops mv_soc_ops = {
740 .phy_errata = mv6_phy_errata,
741 .enable_leds = mv_soc_enable_leds,
742 .read_preamp = mv_soc_read_preamp,
743 .reset_hc = mv_soc_reset_hc,
744 .reset_flash = mv_soc_reset_flash,
745 .reset_bus = mv_soc_reset_bus,
746};
747
20f733e7
BR		 748/*
749 * Functions
750 */
751
752static inline void writelfl(unsigned long data, void __iomem *addr)
753{
754 writel(data, addr);
755 (void) readl(addr); /* flush to avoid PCI posted write */
756}
757
c9d39130
JG		 758static inline unsigned int mv_hc_from_port(unsigned int port)
759{
760 return port >> MV_PORT_HC_SHIFT;
761}
762
763static inline unsigned int mv_hardport_from_port(unsigned int port)
764{
765 return port & MV_PORT_MASK;
766}
767
1cfd19ae
ML		 768/*
769 * Consolidate some rather tricky bit shift calculations.
770 * This is hot-path stuff, so not a function.
771 * Simple code, with two return values, so macro rather than inline.
772 *
773 * port is the sole input, in range 0..7.
7368f919
ML		 774 * shift is one output, for use with main_irq_cause / main_irq_mask registers.
775 * hardport is the other output, in range 0..3.
1cfd19ae
ML		 776 *
777 * Note that port and hardport may be the same variable in some cases.
778 */
779#define MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport) \
780{ \
781 shift = mv_hc_from_port(port) * HC_SHIFT; \
782 hardport = mv_hardport_from_port(port); \
783 shift += hardport * 2; \
784}
785
352fab70
ML		 786static inline void __iomem *mv_hc_base(void __iomem *base, unsigned int hc)
787{
788 return (base + MV_SATAHC0_REG_BASE + (hc * MV_SATAHC_REG_SZ));
789}
790
c9d39130
JG		 791static inline void __iomem *mv_hc_base_from_port(void __iomem *base,
792 unsigned int port)
793{
794 return mv_hc_base(base, mv_hc_from_port(port));
795}
796
20f733e7
BR		 797static inline void __iomem *mv_port_base(void __iomem *base, unsigned int port)
798{
c9d39130 799 return mv_hc_base_from_port(base, port) +
8b260248 800 MV_SATAHC_ARBTR_REG_SZ +
c9d39130 801 (mv_hardport_from_port(port) * MV_PORT_REG_SZ);
20f733e7
BR		 802}
803
e12bef50
ML		 804static void __iomem *mv5_phy_base(void __iomem *mmio, unsigned int port)
805{
806 void __iomem *hc_mmio = mv_hc_base_from_port(mmio, port);
807 unsigned long ofs = (mv_hardport_from_port(port) + 1) * 0x100UL;
808
809 return hc_mmio + ofs;
810}
811
f351b2d6
SB		 812static inline void __iomem *mv_host_base(struct ata_host *host)
813{
814 struct mv_host_priv *hpriv = host->private_data;
815 return hpriv->base;
816}
817
20f733e7
BR		 818static inline void __iomem *mv_ap_base(struct ata_port *ap)
819{
f351b2d6 820 return mv_port_base(mv_host_base(ap->host), ap->port_no);
20f733e7
BR		 821}
822
cca3974e 823static inline int mv_get_hc_count(unsigned long port_flags)
31961943 824{
cca3974e 825 return ((port_flags & MV_FLAG_DUAL_HC) ? 2 : 1);
31961943
BR		 826}
827
08da1759
ML		 828/**
829 * mv_save_cached_regs - (re-)initialize cached port registers
830 * @ap: the port whose registers we are caching
831 *
832 * Initialize the local cache of port registers,
833 * so that reading them over and over again can
834 * be avoided on the hotter paths of this driver.
835 * This saves a few microseconds each time we switch
836 * to/from EDMA mode to perform (eg.) a drive cache flush.
837 */
838static void mv_save_cached_regs(struct ata_port *ap)
839{
840 void __iomem *port_mmio = mv_ap_base(ap);
841 struct mv_port_priv *pp = ap->private_data;
842
843 pp->cached.fiscfg = readl(port_mmio + FISCFG_OFS);
844 pp->cached.ltmode = readl(port_mmio + LTMODE_OFS);
845 pp->cached.haltcond = readl(port_mmio + EDMA_HALTCOND_OFS);
c01e8a23 846 pp->cached.unknown_rsvd = readl(port_mmio + EDMA_UNKNOWN_RSVD_OFS);
08da1759
ML		 847}
848
849/**
850 * mv_write_cached_reg - write to a cached port register
851 * @addr: hardware address of the register
852 * @old: pointer to cached value of the register
853 * @new: new value for the register
854 *
855 * Write a new value to a cached register,
856 * but only if the value is different from before.
857 */
858static inline void mv_write_cached_reg(void __iomem *addr, u32 *old, u32 new)
859{
860 if (new != *old) {
861 *old = new;
862 writel(new, addr);
863 }
864}
865
c5d3e45a
JG		 866static void mv_set_edma_ptrs(void __iomem *port_mmio,
867 struct mv_host_priv *hpriv,
868 struct mv_port_priv *pp)
869{
bdd4ddde
JG		 870 u32 index;
871
c5d3e45a
JG		 872 /*
873 * initialize request queue
874 */
fcfb1f77
ML		 875 pp->req_idx &= MV_MAX_Q_DEPTH_MASK; /* paranoia */
876 index = pp->req_idx << EDMA_REQ_Q_PTR_SHIFT;
bdd4ddde 877
c5d3e45a
JG		 878 WARN_ON(pp->crqb_dma & 0x3ff);
879 writel((pp->crqb_dma >> 16) >> 16, port_mmio + EDMA_REQ_Q_BASE_HI_OFS);
bdd4ddde 880 writelfl((pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK) | index,
c5d3e45a 881 port_mmio + EDMA_REQ_Q_IN_PTR_OFS);
5cf73bfb 882 writelfl(index, port_mmio + EDMA_REQ_Q_OUT_PTR_OFS);
c5d3e45a
JG		 883
884 /*
885 * initialize response queue
886 */
fcfb1f77
ML		 887 pp->resp_idx &= MV_MAX_Q_DEPTH_MASK; /* paranoia */
888 index = pp->resp_idx << EDMA_RSP_Q_PTR_SHIFT;
bdd4ddde 889
c5d3e45a
JG		 890 WARN_ON(pp->crpb_dma & 0xff);
891 writel((pp->crpb_dma >> 16) >> 16, port_mmio + EDMA_RSP_Q_BASE_HI_OFS);
5cf73bfb 892 writelfl(index, port_mmio + EDMA_RSP_Q_IN_PTR_OFS);
bdd4ddde 893 writelfl((pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK) | index,
c5d3e45a 894 port_mmio + EDMA_RSP_Q_OUT_PTR_OFS);
c5d3e45a
JG		 895}
896
c4de573b
ML		 897static void mv_set_main_irq_mask(struct ata_host *host,
898 u32 disable_bits, u32 enable_bits)
899{
900 struct mv_host_priv *hpriv = host->private_data;
901 u32 old_mask, new_mask;
902
96e2c487 903 old_mask = hpriv->main_irq_mask;
c4de573b 904 new_mask = (old_mask & ~disable_bits) | enable_bits;
96e2c487
ML		 905 if (new_mask != old_mask) {
906 hpriv->main_irq_mask = new_mask;
c4de573b 907 writelfl(new_mask, hpriv->main_irq_mask_addr);
96e2c487 908 }
c4de573b
ML		 909}
910
911static void mv_enable_port_irqs(struct ata_port *ap,
912 unsigned int port_bits)
913{
914 unsigned int shift, hardport, port = ap->port_no;
915 u32 disable_bits, enable_bits;
916
917 MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport);
918
919 disable_bits = (DONE_IRQ | ERR_IRQ) << shift;
920 enable_bits = port_bits << shift;
921 mv_set_main_irq_mask(ap->host, disable_bits, enable_bits);
922}
923
00b81235
ML		 924static void mv_clear_and_enable_port_irqs(struct ata_port *ap,
925 void __iomem *port_mmio,
926 unsigned int port_irqs)
927{
928 struct mv_host_priv *hpriv = ap->host->private_data;
929 int hardport = mv_hardport_from_port(ap->port_no);
930 void __iomem *hc_mmio = mv_hc_base_from_port(
931 mv_host_base(ap->host), ap->port_no);
932 u32 hc_irq_cause;
933
934 /* clear EDMA event indicators, if any */
935 writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
936
937 /* clear pending irq events */
938 hc_irq_cause = ~((DEV_IRQ | DMA_IRQ) << hardport);
939 writelfl(hc_irq_cause, hc_mmio + HC_IRQ_CAUSE_OFS);
940
941 /* clear FIS IRQ Cause */
942 if (IS_GEN_IIE(hpriv))
943 writelfl(0, port_mmio + SATA_FIS_IRQ_CAUSE_OFS);
944
945 mv_enable_port_irqs(ap, port_irqs);
946}
947
05b308e1 948/**
00b81235 949 * mv_start_edma - Enable eDMA engine
05b308e1
BR		 950 * @base: port base address
951 * @pp: port private data
952 *
beec7dbc
TH		 953 * Verify the local cache of the eDMA state is accurate with a
954 * WARN_ON.
05b308e1
BR		 955 *
956 * LOCKING:
957 * Inherited from caller.
958 */
00b81235 959static void mv_start_edma(struct ata_port *ap, void __iomem *port_mmio,
72109168 960 struct mv_port_priv *pp, u8 protocol)
20f733e7 961{
72109168
ML		 962 int want_ncq = (protocol == ATA_PROT_NCQ);
963
964 if (pp->pp_flags & MV_PP_FLAG_EDMA_EN) {
965 int using_ncq = ((pp->pp_flags & MV_PP_FLAG_NCQ_EN) != 0);
966 if (want_ncq != using_ncq)
b562468c 967 mv_stop_edma(ap);
72109168 968 }
c5d3e45a 969 if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN)) {
0c58912e 970 struct mv_host_priv *hpriv = ap->host->private_data;
0c58912e 971
00b81235 972 mv_edma_cfg(ap, want_ncq, 1);
0c58912e 973
f630d562 974 mv_set_edma_ptrs(port_mmio, hpriv, pp);
00b81235 975 mv_clear_and_enable_port_irqs(ap, port_mmio, DONE_IRQ|ERR_IRQ);
bdd4ddde 976
f630d562 977 writelfl(EDMA_EN, port_mmio + EDMA_CMD_OFS);
afb0edd9
BR		 978 pp->pp_flags |= MV_PP_FLAG_EDMA_EN;
979 }
20f733e7
BR		 980}
981
9b2c4e0b
ML		 982static void mv_wait_for_edma_empty_idle(struct ata_port *ap)
983{
984 void __iomem *port_mmio = mv_ap_base(ap);
985 const u32 empty_idle = (EDMA_STATUS_CACHE_EMPTY | EDMA_STATUS_IDLE);
986 const int per_loop = 5, timeout = (15 * 1000 / per_loop);
987 int i;
988
989 /*
990 * Wait for the EDMA engine to finish transactions in progress.
c46938cc
ML		 991 * No idea what a good "timeout" value might be, but measurements
992 * indicate that it often requires hundreds of microseconds
993 * with two drives in-use. So we use the 15msec value above
994 * as a rough guess at what even more drives might require.
9b2c4e0b
ML		 995 */
996 for (i = 0; i < timeout; ++i) {
997 u32 edma_stat = readl(port_mmio + EDMA_STATUS_OFS);
998 if ((edma_stat & empty_idle) == empty_idle)
999 break;
1000 udelay(per_loop);
1001 }
1002 /* ata_port_printk(ap, KERN_INFO, "%s: %u+ usecs\n", __func__, i); */
1003}
1004
05b308e1 1005/**
e12bef50 1006 * mv_stop_edma_engine - Disable eDMA engine
b562468c 1007 * @port_mmio: io base address
05b308e1
BR		 1008 *
1009 * LOCKING:
1010 * Inherited from caller.
1011 */
b562468c 1012static int mv_stop_edma_engine(void __iomem *port_mmio)
20f733e7 1013{
b562468c 1014 int i;
31961943 1015
b562468c
ML		 1016 /* Disable eDMA. The disable bit auto clears. */
1017 writelfl(EDMA_DS, port_mmio + EDMA_CMD_OFS);
8b260248 1018
b562468c
ML		 1019 /* Wait for the chip to confirm eDMA is off. */
1020 for (i = 10000; i > 0; i--) {
1021 u32 reg = readl(port_mmio + EDMA_CMD_OFS);
4537deb5 1022 if (!(reg & EDMA_EN))
b562468c
ML		 1023 return 0;
1024 udelay(10);
31961943 1025 }
b562468c 1026 return -EIO;
20f733e7
BR		 1027}
1028
e12bef50 1029static int mv_stop_edma(struct ata_port *ap)
0ea9e179 1030{
b562468c
ML		 1031 void __iomem *port_mmio = mv_ap_base(ap);
1032 struct mv_port_priv *pp = ap->private_data;
66e57a2c 1033 int err = 0;
0ea9e179 1034
b562468c
ML		 1035 if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN))
1036 return 0;
1037 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
9b2c4e0b 1038 mv_wait_for_edma_empty_idle(ap);
b562468c
ML		 1039 if (mv_stop_edma_engine(port_mmio)) {
1040 ata_port_printk(ap, KERN_ERR, "Unable to stop eDMA\n");
66e57a2c 1041 err = -EIO;
b562468c 1042 }
66e57a2c
ML		 1043 mv_edma_cfg(ap, 0, 0);
1044 return err;
0ea9e179
JG		 1045}
1046
8a70f8dc 1047#ifdef ATA_DEBUG
31961943 1048static void mv_dump_mem(void __iomem *start, unsigned bytes)
20f733e7 1049{
31961943
BR		 1050 int b, w;
1051 for (b = 0; b < bytes; ) {
1052 DPRINTK("%p: ", start + b);
1053 for (w = 0; b < bytes && w < 4; w++) {
2dcb407e 1054 printk("%08x ", readl(start + b));
31961943
BR		 1055 b += sizeof(u32);
1056 }
1057 printk("\n");
1058 }
31961943 1059}
8a70f8dc
JG		 1060#endif
1061
31961943
BR		 1062static void mv_dump_pci_cfg(struct pci_dev *pdev, unsigned bytes)
1063{
1064#ifdef ATA_DEBUG
1065 int b, w;
1066 u32 dw;
1067 for (b = 0; b < bytes; ) {
1068 DPRINTK("%02x: ", b);
1069 for (w = 0; b < bytes && w < 4; w++) {
2dcb407e
JG		 1070 (void) pci_read_config_dword(pdev, b, &dw);
1071 printk("%08x ", dw);
31961943
BR		 1072 b += sizeof(u32);
1073 }
1074 printk("\n");
1075 }
1076#endif
1077}
1078static void mv_dump_all_regs(void __iomem *mmio_base, int port,
1079 struct pci_dev *pdev)
1080{
1081#ifdef ATA_DEBUG
8b260248 1082 void __iomem *hc_base = mv_hc_base(mmio_base,
31961943
BR		 1083 port >> MV_PORT_HC_SHIFT);
1084 void __iomem *port_base;
1085 int start_port, num_ports, p, start_hc, num_hcs, hc;
1086
1087 if (0 > port) {
1088 start_hc = start_port = 0;
1089 num_ports = 8; /* shld be benign for 4 port devs */
1090 num_hcs = 2;
1091 } else {
1092 start_hc = port >> MV_PORT_HC_SHIFT;
1093 start_port = port;
1094 num_ports = num_hcs = 1;
1095 }
8b260248 1096 DPRINTK("All registers for port(s) %u-%u:\n", start_port,
31961943
BR		 1097 num_ports > 1 ? num_ports - 1 : start_port);
1098
1099 if (NULL != pdev) {
1100 DPRINTK("PCI config space regs:\n");
1101 mv_dump_pci_cfg(pdev, 0x68);
1102 }
1103 DPRINTK("PCI regs:\n");
1104 mv_dump_mem(mmio_base+0xc00, 0x3c);
1105 mv_dump_mem(mmio_base+0xd00, 0x34);
1106 mv_dump_mem(mmio_base+0xf00, 0x4);
1107 mv_dump_mem(mmio_base+0x1d00, 0x6c);
1108 for (hc = start_hc; hc < start_hc + num_hcs; hc++) {
d220c37e 1109 hc_base = mv_hc_base(mmio_base, hc);
31961943
BR		 1110 DPRINTK("HC regs (HC %i):\n", hc);
1111 mv_dump_mem(hc_base, 0x1c);
1112 }
1113 for (p = start_port; p < start_port + num_ports; p++) {
1114 port_base = mv_port_base(mmio_base, p);
2dcb407e 1115 DPRINTK("EDMA regs (port %i):\n", p);
31961943 1116 mv_dump_mem(port_base, 0x54);
2dcb407e 1117 DPRINTK("SATA regs (port %i):\n", p);
31961943
BR		 1118 mv_dump_mem(port_base+0x300, 0x60);
1119 }
1120#endif
20f733e7
BR		 1121}
1122
1123static unsigned int mv_scr_offset(unsigned int sc_reg_in)
1124{
1125 unsigned int ofs;
1126
1127 switch (sc_reg_in) {
1128 case SCR_STATUS:
1129 case SCR_CONTROL:
1130 case SCR_ERROR:
1131 ofs = SATA_STATUS_OFS + (sc_reg_in * sizeof(u32));
1132 break;
1133 case SCR_ACTIVE:
1134 ofs = SATA_ACTIVE_OFS; /* active is not with the others */
1135 break;
1136 default:
1137 ofs = 0xffffffffU;
1138 break;
1139 }
1140 return ofs;
1141}
1142
82ef04fb 1143static int mv_scr_read(struct ata_link *link, unsigned int sc_reg_in, u32 *val)
20f733e7
BR		 1144{
1145 unsigned int ofs = mv_scr_offset(sc_reg_in);
1146
da3dbb17 1147 if (ofs != 0xffffffffU) {
82ef04fb 1148 *val = readl(mv_ap_base(link->ap) + ofs);
da3dbb17
TH		 1149 return 0;
1150 } else
1151 return -EINVAL;
20f733e7
BR		 1152}
1153
82ef04fb 1154static int mv_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val)
20f733e7
BR		 1155{
1156 unsigned int ofs = mv_scr_offset(sc_reg_in);
1157
da3dbb17 1158 if (ofs != 0xffffffffU) {
82ef04fb 1159 writelfl(val, mv_ap_base(link->ap) + ofs);
da3dbb17
TH		 1160 return 0;
1161 } else
1162 return -EINVAL;
20f733e7
BR		 1163}
1164
f273827e
ML		 1165static void mv6_dev_config(struct ata_device *adev)
1166{
1167 /*
e49856d8
ML		 1168 * Deal with Gen-II ("mv6") hardware quirks/restrictions:
1169 *
1170 * Gen-II does not support NCQ over a port multiplier
1171 * (no FIS-based switching).
f273827e 1172 */
e49856d8 1173 if (adev->flags & ATA_DFLAG_NCQ) {
352fab70 1174 if (sata_pmp_attached(adev->link->ap)) {
e49856d8 1175 adev->flags &= ~ATA_DFLAG_NCQ;
352fab70
ML		 1176 ata_dev_printk(adev, KERN_INFO,
1177 "NCQ disabled for command-based switching\n");
352fab70 1178 }
e49856d8 1179 }
f273827e
ML		 1180}
1181
3e4a1391
ML		 1182static int mv_qc_defer(struct ata_queued_cmd *qc)
1183{
1184 struct ata_link *link = qc->dev->link;
1185 struct ata_port *ap = link->ap;
1186 struct mv_port_priv *pp = ap->private_data;
1187
29d187bb
ML		 1188 /*
1189 * Don't allow new commands if we're in a delayed EH state
1190 * for NCQ and/or FIS-based switching.
1191 */
1192 if (pp->pp_flags & MV_PP_FLAG_DELAYED_EH)
1193 return ATA_DEFER_PORT;
3e4a1391
ML		 1194 /*
1195 * If the port is completely idle, then allow the new qc.
1196 */
1197 if (ap->nr_active_links == 0)
1198 return 0;
1199
4bdee6c5
TH		 1200 /*
1201 * The port is operating in host queuing mode (EDMA) with NCQ
1202 * enabled, allow multiple NCQ commands. EDMA also allows
1203 * queueing multiple DMA commands but libata core currently
1204 * doesn't allow it.
1205 */
1206 if ((pp->pp_flags & MV_PP_FLAG_EDMA_EN) &&
1207 (pp->pp_flags & MV_PP_FLAG_NCQ_EN) && ata_is_ncq(qc->tf.protocol))
1208 return 0;
1209
3e4a1391
ML		 1210 return ATA_DEFER_PORT;
1211}
1212
08da1759 1213static void mv_config_fbs(struct ata_port *ap, int want_ncq, int want_fbs)
e49856d8 1214{
08da1759
ML		 1215 struct mv_port_priv *pp = ap->private_data;
1216 void __iomem *port_mmio;
00f42eab 1217
08da1759
ML		 1218 u32 fiscfg, *old_fiscfg = &pp->cached.fiscfg;
1219 u32 ltmode, *old_ltmode = &pp->cached.ltmode;
1220 u32 haltcond, *old_haltcond = &pp->cached.haltcond;
00f42eab 1221
08da1759
ML		 1222 ltmode = *old_ltmode & ~LTMODE_BIT8;
1223 haltcond = *old_haltcond | EDMA_ERR_DEV;
00f42eab
ML		 1224
1225 if (want_fbs) {
08da1759
ML		 1226 fiscfg = *old_fiscfg | FISCFG_SINGLE_SYNC;
1227 ltmode = *old_ltmode | LTMODE_BIT8;
4c299ca3 1228 if (want_ncq)
08da1759 1229 haltcond &= ~EDMA_ERR_DEV;
4c299ca3 1230 else
08da1759
ML		 1231 fiscfg |= FISCFG_WAIT_DEV_ERR;
1232 } else {
1233 fiscfg = *old_fiscfg & ~(FISCFG_SINGLE_SYNC | FISCFG_WAIT_DEV_ERR);
e49856d8 1234 }
00f42eab 1235
08da1759
ML		 1236 port_mmio = mv_ap_base(ap);
1237 mv_write_cached_reg(port_mmio + FISCFG_OFS, old_fiscfg, fiscfg);
1238 mv_write_cached_reg(port_mmio + LTMODE_OFS, old_ltmode, ltmode);
1239 mv_write_cached_reg(port_mmio + EDMA_HALTCOND_OFS, old_haltcond, haltcond);
f273827e
ML		 1240}
1241
dd2890f6
ML		 1242static void mv_60x1_errata_sata25(struct ata_port *ap, int want_ncq)
1243{
1244 struct mv_host_priv *hpriv = ap->host->private_data;
1245 u32 old, new;
1246
1247 /* workaround for 88SX60x1 FEr SATA#25 (part 1) */
1248 old = readl(hpriv->base + MV_GPIO_PORT_CTL_OFS);
1249 if (want_ncq)
1250 new = old | (1 << 22);
1251 else
1252 new = old & ~(1 << 22);
1253 if (new != old)
1254 writel(new, hpriv->base + MV_GPIO_PORT_CTL_OFS);
1255}
1256
c01e8a23
ML		 1257/**
1258 * mv_bmdma_enable - set a magic bit on GEN_IIE to allow bmdma
1259 * @ap: Port being initialized
1260 *
1261 * There are two DMA modes on these chips: basic DMA, and EDMA.
1262 *
1263 * Bit-0 of the "EDMA RESERVED" register enables/disables use
1264 * of basic DMA on the GEN_IIE versions of the chips.
1265 *
1266 * This bit survives EDMA resets, and must be set for basic DMA
1267 * to function, and should be cleared when EDMA is active.
1268 */
1269static void mv_bmdma_enable_iie(struct ata_port *ap, int enable_bmdma)
1270{
1271 struct mv_port_priv *pp = ap->private_data;
1272 u32 new, *old = &pp->cached.unknown_rsvd;
1273
1274 if (enable_bmdma)
1275 new = *old | 1;
1276 else
1277 new = *old & ~1;
1278 mv_write_cached_reg(mv_ap_base(ap) + EDMA_UNKNOWN_RSVD_OFS, old, new);
1279}
1280
00b81235 1281static void mv_edma_cfg(struct ata_port *ap, int want_ncq, int want_edma)
e4e7b892 1282{
0c58912e 1283 u32 cfg;
e12bef50
ML		 1284 struct mv_port_priv *pp = ap->private_data;
1285 struct mv_host_priv *hpriv = ap->host->private_data;
1286 void __iomem *port_mmio = mv_ap_base(ap);
e4e7b892
JG		 1287
1288 /* set up non-NCQ EDMA configuration */
0c58912e 1289 cfg = EDMA_CFG_Q_DEPTH; /* always 0x1f for *all* chips */
d16ab3f6
ML		 1290 pp->pp_flags &=
1291 ~(MV_PP_FLAG_FBS_EN | MV_PP_FLAG_NCQ_EN | MV_PP_FLAG_FAKE_ATA_BUSY);
e4e7b892 1292
0c58912e 1293 if (IS_GEN_I(hpriv))
e4e7b892
JG		 1294 cfg |= (1 << 8); /* enab config burst size mask */
1295
dd2890f6 1296 else if (IS_GEN_II(hpriv)) {
e4e7b892 1297 cfg |= EDMA_CFG_RD_BRST_EXT | EDMA_CFG_WR_BUFF_LEN;
dd2890f6 1298 mv_60x1_errata_sata25(ap, want_ncq);
e4e7b892 1299
dd2890f6 1300 } else if (IS_GEN_IIE(hpriv)) {
00f42eab
ML		 1301 int want_fbs = sata_pmp_attached(ap);
1302 /*
1303 * Possible future enhancement:
1304 *
1305 * The chip can use FBS with non-NCQ, if we allow it,
1306 * But first we need to have the error handling in place
1307 * for this mode (datasheet section 7.3.15.4.2.3).
1308 * So disallow non-NCQ FBS for now.
1309 */
1310 want_fbs &= want_ncq;
1311
08da1759 1312 mv_config_fbs(ap, want_ncq, want_fbs);
00f42eab
ML		 1313
1314 if (want_fbs) {
1315 pp->pp_flags |= MV_PP_FLAG_FBS_EN;
1316 cfg |= EDMA_CFG_EDMA_FBS; /* FIS-based switching */
1317 }
1318
e728eabe 1319 cfg |= (1 << 23); /* do not mask PM field in rx'd FIS */
00b81235
ML		 1320 if (want_edma) {
1321 cfg |= (1 << 22); /* enab 4-entry host queue cache */
1322 if (!IS_SOC(hpriv))
1323 cfg |= (1 << 18); /* enab early completion */
1324 }
616d4a98
ML		 1325 if (hpriv->hp_flags & MV_HP_CUT_THROUGH)
1326 cfg |= (1 << 17); /* enab cut-thru (dis stor&forwrd) */
c01e8a23 1327 mv_bmdma_enable_iie(ap, !want_edma);
e4e7b892
JG		 1328 }
1329
72109168
ML		 1330 if (want_ncq) {
1331 cfg |= EDMA_CFG_NCQ;
1332 pp->pp_flags |= MV_PP_FLAG_NCQ_EN;
00b81235 1333 }
72109168 1334
e4e7b892
JG		 1335 writelfl(cfg, port_mmio + EDMA_CFG_OFS);
1336}
1337
da2fa9ba
ML		 1338static void mv_port_free_dma_mem(struct ata_port *ap)
1339{
1340 struct mv_host_priv *hpriv = ap->host->private_data;
1341 struct mv_port_priv *pp = ap->private_data;
eb73d558 1342 int tag;
da2fa9ba
ML		 1343
1344 if (pp->crqb) {
1345 dma_pool_free(hpriv->crqb_pool, pp->crqb, pp->crqb_dma);
1346 pp->crqb = NULL;
1347 }
1348 if (pp->crpb) {
1349 dma_pool_free(hpriv->crpb_pool, pp->crpb, pp->crpb_dma);
1350 pp->crpb = NULL;
1351 }
eb73d558
ML		 1352 /*
1353 * For GEN_I, there's no NCQ, so we have only a single sg_tbl.
1354 * For later hardware, we have one unique sg_tbl per NCQ tag.
1355 */
1356 for (tag = 0; tag < MV_MAX_Q_DEPTH; ++tag) {
1357 if (pp->sg_tbl[tag]) {
1358 if (tag == 0 || !IS_GEN_I(hpriv))
1359 dma_pool_free(hpriv->sg_tbl_pool,
1360 pp->sg_tbl[tag],
1361 pp->sg_tbl_dma[tag]);
1362 pp->sg_tbl[tag] = NULL;
1363 }
da2fa9ba
ML		 1364 }
1365}
1366
05b308e1
BR		 1367/**
1368 * mv_port_start - Port specific init/start routine.
1369 * @ap: ATA channel to manipulate
1370 *
1371 * Allocate and point to DMA memory, init port private memory,
1372 * zero indices.
1373 *
1374 * LOCKING:
1375 * Inherited from caller.
1376 */
31961943
BR		 1377static int mv_port_start(struct ata_port *ap)
1378{
cca3974e
JG		 1379 struct device *dev = ap->host->dev;
1380 struct mv_host_priv *hpriv = ap->host->private_data;
31961943 1381 struct mv_port_priv *pp;
dde20207 1382 int tag;
31961943 1383
24dc5f33 1384 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
6037d6bb 1385 if (!pp)
24dc5f33 1386 return -ENOMEM;
da2fa9ba 1387 ap->private_data = pp;
31961943 1388
da2fa9ba
ML		 1389 pp->crqb = dma_pool_alloc(hpriv->crqb_pool, GFP_KERNEL, &pp->crqb_dma);
1390 if (!pp->crqb)
1391 return -ENOMEM;
1392 memset(pp->crqb, 0, MV_CRQB_Q_SZ);
31961943 1393
da2fa9ba
ML		 1394 pp->crpb = dma_pool_alloc(hpriv->crpb_pool, GFP_KERNEL, &pp->crpb_dma);
1395 if (!pp->crpb)
1396 goto out_port_free_dma_mem;
1397 memset(pp->crpb, 0, MV_CRPB_Q_SZ);
31961943 1398
3bd0a70e
ML		 1399 /* 6041/6081 Rev. "C0" (and newer) are okay with async notify */
1400 if (hpriv->hp_flags & MV_HP_ERRATA_60X1C0)
1401 ap->flags |= ATA_FLAG_AN;
eb73d558
ML		 1402 /*
1403 * For GEN_I, there's no NCQ, so we only allocate a single sg_tbl.
1404 * For later hardware, we need one unique sg_tbl per NCQ tag.
1405 */
1406 for (tag = 0; tag < MV_MAX_Q_DEPTH; ++tag) {
1407 if (tag == 0 || !IS_GEN_I(hpriv)) {
1408 pp->sg_tbl[tag] = dma_pool_alloc(hpriv->sg_tbl_pool,
1409 GFP_KERNEL, &pp->sg_tbl_dma[tag]);
1410 if (!pp->sg_tbl[tag])
1411 goto out_port_free_dma_mem;
1412 } else {
1413 pp->sg_tbl[tag] = pp->sg_tbl[0];
1414 pp->sg_tbl_dma[tag] = pp->sg_tbl_dma[0];
1415 }
1416 }
08da1759 1417 mv_save_cached_regs(ap);
66e57a2c 1418 mv_edma_cfg(ap, 0, 0);
31961943 1419 return 0;
da2fa9ba
ML		 1420
1421out_port_free_dma_mem:
1422 mv_port_free_dma_mem(ap);
1423 return -ENOMEM;
31961943
BR		 1424}
1425
05b308e1
BR		 1426/**
1427 * mv_port_stop - Port specific cleanup/stop routine.
1428 * @ap: ATA channel to manipulate
1429 *
1430 * Stop DMA, cleanup port memory.
1431 *
1432 * LOCKING:
cca3974e 1433 * This routine uses the host lock to protect the DMA stop.
05b308e1 1434 */
31961943
BR		 1435static void mv_port_stop(struct ata_port *ap)
1436{
e12bef50 1437 mv_stop_edma(ap);
88e675e1 1438 mv_enable_port_irqs(ap, 0);
da2fa9ba 1439 mv_port_free_dma_mem(ap);
31961943
BR		 1440}
1441
05b308e1
BR		 1442/**
1443 * mv_fill_sg - Fill out the Marvell ePRD (scatter gather) entries
1444 * @qc: queued command whose SG list to source from
1445 *
1446 * Populate the SG list and mark the last entry.
1447 *
1448 * LOCKING:
1449 * Inherited from caller.
1450 */
6c08772e 1451static void mv_fill_sg(struct ata_queued_cmd *qc)
31961943
BR		 1452{
1453 struct mv_port_priv *pp = qc->ap->private_data;
972c26bd 1454 struct scatterlist *sg;
3be6cbd7 1455 struct mv_sg *mv_sg, *last_sg = NULL;
ff2aeb1e 1456 unsigned int si;
31961943 1457
eb73d558 1458 mv_sg = pp->sg_tbl[qc->tag];
ff2aeb1e 1459 for_each_sg(qc->sg, sg, qc->n_elem, si) {
d88184fb
JG		 1460 dma_addr_t addr = sg_dma_address(sg);
1461 u32 sg_len = sg_dma_len(sg);
22374677 1462
4007b493
OJ		 1463 while (sg_len) {
1464 u32 offset = addr & 0xffff;
1465 u32 len = sg_len;
22374677 1466
32cd11a6 1467 if (offset + len > 0x10000)
4007b493
OJ		 1468 len = 0x10000 - offset;
1469
1470 mv_sg->addr = cpu_to_le32(addr & 0xffffffff);
1471 mv_sg->addr_hi = cpu_to_le32((addr >> 16) >> 16);
6c08772e 1472 mv_sg->flags_size = cpu_to_le32(len & 0xffff);
32cd11a6 1473 mv_sg->reserved = 0;
4007b493
OJ		 1474
1475 sg_len -= len;
1476 addr += len;
1477
3be6cbd7 1478 last_sg = mv_sg;
4007b493 1479 mv_sg++;
4007b493 1480 }
31961943 1481 }
3be6cbd7
JG		 1482
1483 if (likely(last_sg))
1484 last_sg->flags_size |= cpu_to_le32(EPRD_FLAG_END_OF_TBL);
32cd11a6 1485 mb(); /* ensure data structure is visible to the chipset */
31961943
BR		 1486}
1487
5796d1c4 1488static void mv_crqb_pack_cmd(__le16 *cmdw, u8 data, u8 addr, unsigned last)
31961943 1489{
559eedad 1490 u16 tmp = data | (addr << CRQB_CMD_ADDR_SHIFT) | CRQB_CMD_CS |
31961943 1491 (last ? CRQB_CMD_LAST : 0);
559eedad 1492 *cmdw = cpu_to_le16(tmp);
31961943
BR		 1493}
1494
da14265e
ML		 1495/**
1496 * mv_sff_irq_clear - Clear hardware interrupt after DMA.
1497 * @ap: Port associated with this ATA transaction.
1498 *
1499 * We need this only for ATAPI bmdma transactions,
1500 * as otherwise we experience spurious interrupts
1501 * after libata-sff handles the bmdma interrupts.
1502 */
1503static void mv_sff_irq_clear(struct ata_port *ap)
1504{
1505 mv_clear_and_enable_port_irqs(ap, mv_ap_base(ap), ERR_IRQ);
1506}
1507
1508/**
1509 * mv_check_atapi_dma - Filter ATAPI cmds which are unsuitable for DMA.
1510 * @qc: queued command to check for chipset/DMA compatibility.
1511 *
1512 * The bmdma engines cannot handle speculative data sizes
1513 * (bytecount under/over flow). So only allow DMA for
1514 * data transfer commands with known data sizes.
1515 *
1516 * LOCKING:
1517 * Inherited from caller.
1518 */
1519static int mv_check_atapi_dma(struct ata_queued_cmd *qc)
1520{
1521 struct scsi_cmnd *scmd = qc->scsicmd;
1522
1523 if (scmd) {
1524 switch (scmd->cmnd[0]) {
1525 case READ_6:
1526 case READ_10:
1527 case READ_12:
1528 case WRITE_6:
1529 case WRITE_10:
1530 case WRITE_12:
1531 case GPCMD_READ_CD:
1532 case GPCMD_SEND_DVD_STRUCTURE:
1533 case GPCMD_SEND_CUE_SHEET:
1534 return 0; /* DMA is safe */
1535 }
1536 }
1537 return -EOPNOTSUPP; /* use PIO instead */
1538}
1539
1540/**
1541 * mv_bmdma_setup - Set up BMDMA transaction
1542 * @qc: queued command to prepare DMA for.
1543 *
1544 * LOCKING:
1545 * Inherited from caller.
1546 */
1547static void mv_bmdma_setup(struct ata_queued_cmd *qc)
1548{
1549 struct ata_port *ap = qc->ap;
1550 void __iomem *port_mmio = mv_ap_base(ap);
1551 struct mv_port_priv *pp = ap->private_data;
1552
1553 mv_fill_sg(qc);
1554
1555 /* clear all DMA cmd bits */
1556 writel(0, port_mmio + BMDMA_CMD_OFS);
1557
1558 /* load PRD table addr. */
1559 writel((pp->sg_tbl_dma[qc->tag] >> 16) >> 16,
1560 port_mmio + BMDMA_PRD_HIGH_OFS);
1561 writelfl(pp->sg_tbl_dma[qc->tag],
1562 port_mmio + BMDMA_PRD_LOW_OFS);
1563
1564 /* issue r/w command */
1565 ap->ops->sff_exec_command(ap, &qc->tf);
1566}
1567
1568/**
1569 * mv_bmdma_start - Start a BMDMA transaction
1570 * @qc: queued command to start DMA on.
1571 *
1572 * LOCKING:
1573 * Inherited from caller.
1574 */
1575static void mv_bmdma_start(struct ata_queued_cmd *qc)
1576{
1577 struct ata_port *ap = qc->ap;
1578 void __iomem *port_mmio = mv_ap_base(ap);
1579 unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE);
1580 u32 cmd = (rw ? 0 : ATA_DMA_WR) | ATA_DMA_START;
1581
1582 /* start host DMA transaction */
1583 writelfl(cmd, port_mmio + BMDMA_CMD_OFS);
1584}
1585
1586/**
1587 * mv_bmdma_stop - Stop BMDMA transfer
1588 * @qc: queued command to stop DMA on.
1589 *
1590 * Clears the ATA_DMA_START flag in the bmdma control register
1591 *
1592 * LOCKING:
1593 * Inherited from caller.
1594 */
1595static void mv_bmdma_stop(struct ata_queued_cmd *qc)
1596{
1597 struct ata_port *ap = qc->ap;
1598 void __iomem *port_mmio = mv_ap_base(ap);
1599 u32 cmd;
1600
1601 /* clear start/stop bit */
1602 cmd = readl(port_mmio + BMDMA_CMD_OFS);
1603 cmd &= ~ATA_DMA_START;
1604 writelfl(cmd, port_mmio + BMDMA_CMD_OFS);
1605
1606 /* one-PIO-cycle guaranteed wait, per spec, for HDMA1:0 transition */
1607 ata_sff_dma_pause(ap);
1608}
1609
1610/**
1611 * mv_bmdma_status - Read BMDMA status
1612 * @ap: port for which to retrieve DMA status.
1613 *
1614 * Read and return equivalent of the sff BMDMA status register.
1615 *
1616 * LOCKING:
1617 * Inherited from caller.
1618 */
1619static u8 mv_bmdma_status(struct ata_port *ap)
1620{
1621 void __iomem *port_mmio = mv_ap_base(ap);
1622 u32 reg, status;
1623
1624 /*
1625 * Other bits are valid only if ATA_DMA_ACTIVE==0,
1626 * and the ATA_DMA_INTR bit doesn't exist.
1627 */
1628 reg = readl(port_mmio + BMDMA_STATUS_OFS);
1629 if (reg & ATA_DMA_ACTIVE)
1630 status = ATA_DMA_ACTIVE;
1631 else
1632 status = (reg & ATA_DMA_ERR) | ATA_DMA_INTR;
1633 return status;
1634}
1635
05b308e1
BR		 1636/**
1637 * mv_qc_prep - Host specific command preparation.
1638 * @qc: queued command to prepare
1639 *
1640 * This routine simply redirects to the general purpose routine
1641 * if command is not DMA. Else, it handles prep of the CRQB
1642 * (command request block), does some sanity checking, and calls
1643 * the SG load routine.
1644 *
1645 * LOCKING:
1646 * Inherited from caller.
1647 */
31961943
BR		 1648static void mv_qc_prep(struct ata_queued_cmd *qc)
1649{
1650 struct ata_port *ap = qc->ap;
1651 struct mv_port_priv *pp = ap->private_data;
e1469874 1652 __le16 *cw;
31961943
BR		 1653 struct ata_taskfile *tf;
1654 u16 flags = 0;
a6432436 1655 unsigned in_index;
31961943 1656
138bfdd0
ML		 1657 if ((qc->tf.protocol != ATA_PROT_DMA) &&
1658 (qc->tf.protocol != ATA_PROT_NCQ))
31961943 1659 return;
20f733e7 1660
31961943
BR		 1661 /* Fill in command request block
1662 */
e4e7b892 1663 if (!(qc->tf.flags & ATA_TFLAG_WRITE))
31961943 1664 flags |= CRQB_FLAG_READ;
beec7dbc 1665 WARN_ON(MV_MAX_Q_DEPTH <= qc->tag);
31961943 1666 flags |= qc->tag << CRQB_TAG_SHIFT;
e49856d8 1667 flags |= (qc->dev->link->pmp & 0xf) << CRQB_PMP_SHIFT;
31961943 1668
bdd4ddde 1669 /* get current queue index from software */
fcfb1f77 1670 in_index = pp->req_idx;
a6432436
ML		 1671
1672 pp->crqb[in_index].sg_addr =
eb73d558 1673 cpu_to_le32(pp->sg_tbl_dma[qc->tag] & 0xffffffff);
a6432436 1674 pp->crqb[in_index].sg_addr_hi =
eb73d558 1675 cpu_to_le32((pp->sg_tbl_dma[qc->tag] >> 16) >> 16);
a6432436 1676 pp->crqb[in_index].ctrl_flags = cpu_to_le16(flags);
31961943 1677
a6432436 1678 cw = &pp->crqb[in_index].ata_cmd[0];
31961943
BR		 1679 tf = &qc->tf;
1680
1681 /* Sadly, the CRQB cannot accomodate all registers--there are
1682 * only 11 bytes...so we must pick and choose required
1683 * registers based on the command. So, we drop feature and
1684 * hob_feature for [RW] DMA commands, but they are needed for
cd12e1f7
ML		 1685 * NCQ. NCQ will drop hob_nsect, which is not needed there
1686 * (nsect is used only for the tag; feat/hob_feat hold true nsect).
20f733e7 1687 */
31961943
BR		 1688 switch (tf->command) {
1689 case ATA_CMD_READ:
1690 case ATA_CMD_READ_EXT:
1691 case ATA_CMD_WRITE:
1692 case ATA_CMD_WRITE_EXT:
c15d85c8 1693 case ATA_CMD_WRITE_FUA_EXT:
31961943
BR		 1694 mv_crqb_pack_cmd(cw++, tf->hob_nsect, ATA_REG_NSECT, 0);
1695 break;
31961943
BR		 1696 case ATA_CMD_FPDMA_READ:
1697 case ATA_CMD_FPDMA_WRITE:
8b260248 1698 mv_crqb_pack_cmd(cw++, tf->hob_feature, ATA_REG_FEATURE, 0);
31961943
BR		 1699 mv_crqb_pack_cmd(cw++, tf->feature, ATA_REG_FEATURE, 0);
1700 break;
31961943
BR		 1701 default:
1702 /* The only other commands EDMA supports in non-queued and
1703 * non-NCQ mode are: [RW] STREAM DMA and W DMA FUA EXT, none
1704 * of which are defined/used by Linux. If we get here, this
1705 * driver needs work.
1706 *
1707 * FIXME: modify libata to give qc_prep a return value and
1708 * return error here.
1709 */
1710 BUG_ON(tf->command);
1711 break;
1712 }
1713 mv_crqb_pack_cmd(cw++, tf->nsect, ATA_REG_NSECT, 0);
1714 mv_crqb_pack_cmd(cw++, tf->hob_lbal, ATA_REG_LBAL, 0);
1715 mv_crqb_pack_cmd(cw++, tf->lbal, ATA_REG_LBAL, 0);
1716 mv_crqb_pack_cmd(cw++, tf->hob_lbam, ATA_REG_LBAM, 0);
1717 mv_crqb_pack_cmd(cw++, tf->lbam, ATA_REG_LBAM, 0);
1718 mv_crqb_pack_cmd(cw++, tf->hob_lbah, ATA_REG_LBAH, 0);
1719 mv_crqb_pack_cmd(cw++, tf->lbah, ATA_REG_LBAH, 0);
1720 mv_crqb_pack_cmd(cw++, tf->device, ATA_REG_DEVICE, 0);
1721 mv_crqb_pack_cmd(cw++, tf->command, ATA_REG_CMD, 1); /* last */
1722
e4e7b892
JG		 1723 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
1724 return;
1725 mv_fill_sg(qc);
1726}
1727
1728/**
1729 * mv_qc_prep_iie - Host specific command preparation.
1730 * @qc: queued command to prepare
1731 *
1732 * This routine simply redirects to the general purpose routine
1733 * if command is not DMA. Else, it handles prep of the CRQB
1734 * (command request block), does some sanity checking, and calls
1735 * the SG load routine.
1736 *
1737 * LOCKING:
1738 * Inherited from caller.
1739 */
1740static void mv_qc_prep_iie(struct ata_queued_cmd *qc)
1741{
1742 struct ata_port *ap = qc->ap;
1743 struct mv_port_priv *pp = ap->private_data;
1744 struct mv_crqb_iie *crqb;
1745 struct ata_taskfile *tf;
a6432436 1746 unsigned in_index;
e4e7b892
JG		 1747 u32 flags = 0;
1748
138bfdd0
ML		 1749 if ((qc->tf.protocol != ATA_PROT_DMA) &&
1750 (qc->tf.protocol != ATA_PROT_NCQ))
e4e7b892
JG		 1751 return;
1752
e12bef50 1753 /* Fill in Gen IIE command request block */
e4e7b892
JG		 1754 if (!(qc->tf.flags & ATA_TFLAG_WRITE))
1755 flags |= CRQB_FLAG_READ;
1756
beec7dbc 1757 WARN_ON(MV_MAX_Q_DEPTH <= qc->tag);
e4e7b892 1758 flags |= qc->tag << CRQB_TAG_SHIFT;
8c0aeb4a 1759 flags |= qc->tag << CRQB_HOSTQ_SHIFT;
e49856d8 1760 flags |= (qc->dev->link->pmp & 0xf) << CRQB_PMP_SHIFT;
e4e7b892 1761
bdd4ddde 1762 /* get current queue index from software */
fcfb1f77 1763 in_index = pp->req_idx;
a6432436
ML		 1764
1765 crqb = (struct mv_crqb_iie *) &pp->crqb[in_index];
eb73d558
ML		 1766 crqb->addr = cpu_to_le32(pp->sg_tbl_dma[qc->tag] & 0xffffffff);
1767 crqb->addr_hi = cpu_to_le32((pp->sg_tbl_dma[qc->tag] >> 16) >> 16);
e4e7b892
JG		 1768 crqb->flags = cpu_to_le32(flags);
1769
1770 tf = &qc->tf;
1771 crqb->ata_cmd[0] = cpu_to_le32(
1772 (tf->command << 16) |
1773 (tf->feature << 24)
1774 );
1775 crqb->ata_cmd[1] = cpu_to_le32(
1776 (tf->lbal << 0) |
1777 (tf->lbam << 8) |
1778 (tf->lbah << 16) |
1779 (tf->device << 24)
1780 );
1781 crqb->ata_cmd[2] = cpu_to_le32(
1782 (tf->hob_lbal << 0) |
1783 (tf->hob_lbam << 8) |
1784 (tf->hob_lbah << 16) |
1785 (tf->hob_feature << 24)
1786 );
1787 crqb->ata_cmd[3] = cpu_to_le32(
1788 (tf->nsect << 0) |
1789 (tf->hob_nsect << 8)
1790 );
1791
1792 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
31961943 1793 return;
31961943
BR		 1794 mv_fill_sg(qc);
1795}
1796
d16ab3f6
ML		 1797/**
1798 * mv_sff_check_status - fetch device status, if valid
1799 * @ap: ATA port to fetch status from
1800 *
1801 * When using command issue via mv_qc_issue_fis(),
1802 * the initial ATA_BUSY state does not show up in the
1803 * ATA status (shadow) register. This can confuse libata!
1804 *
1805 * So we have a hook here to fake ATA_BUSY for that situation,
1806 * until the first time a BUSY, DRQ, or ERR bit is seen.
1807 *
1808 * The rest of the time, it simply returns the ATA status register.
1809 */
1810static u8 mv_sff_check_status(struct ata_port *ap)
1811{
1812 u8 stat = ioread8(ap->ioaddr.status_addr);
1813 struct mv_port_priv *pp = ap->private_data;
1814
1815 if (pp->pp_flags & MV_PP_FLAG_FAKE_ATA_BUSY) {
1816 if (stat & (ATA_BUSY | ATA_DRQ | ATA_ERR))
1817 pp->pp_flags &= ~MV_PP_FLAG_FAKE_ATA_BUSY;
1818 else
1819 stat = ATA_BUSY;
1820 }
1821 return stat;
1822}
1823
05b308e1
BR		 1824/**
1825 * mv_qc_issue - Initiate a command to the host
1826 * @qc: queued command to start
1827 *
1828 * This routine simply redirects to the general purpose routine
1829 * if command is not DMA. Else, it sanity checks our local
1830 * caches of the request producer/consumer indices then enables
1831 * DMA and bumps the request producer index.
1832 *
1833 * LOCKING:
1834 * Inherited from caller.
1835 */
9a3d9eb0 1836static unsigned int mv_qc_issue(struct ata_queued_cmd *qc)
31961943 1837{
f48765cc 1838 static int limit_warnings = 10;
c5d3e45a
JG		 1839 struct ata_port *ap = qc->ap;
1840 void __iomem *port_mmio = mv_ap_base(ap);
1841 struct mv_port_priv *pp = ap->private_data;
bdd4ddde 1842 u32 in_index;
42ed893d 1843 unsigned int port_irqs;
f48765cc 1844
d16ab3f6
ML		 1845 pp->pp_flags &= ~MV_PP_FLAG_FAKE_ATA_BUSY; /* paranoia */
1846
f48765cc
ML		 1847 switch (qc->tf.protocol) {
1848 case ATA_PROT_DMA:
1849 case ATA_PROT_NCQ:
1850 mv_start_edma(ap, port_mmio, pp, qc->tf.protocol);
1851 pp->req_idx = (pp->req_idx + 1) & MV_MAX_Q_DEPTH_MASK;
1852 in_index = pp->req_idx << EDMA_REQ_Q_PTR_SHIFT;
1853
1854 /* Write the request in pointer to kick the EDMA to life */
1855 writelfl((pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK) | in_index,
1856 port_mmio + EDMA_REQ_Q_IN_PTR_OFS);
1857 return 0;
31961943 1858
f48765cc 1859 case ATA_PROT_PIO:
c6112bd8
ML		 1860 /*
1861 * Errata SATA#16, SATA#24: warn if multiple DRQs expected.
1862 *
1863 * Someday, we might implement special polling workarounds
1864 * for these, but it all seems rather unnecessary since we
1865 * normally use only DMA for commands which transfer more
1866 * than a single block of data.
1867 *
1868 * Much of the time, this could just work regardless.
1869 * So for now, just log the incident, and allow the attempt.
1870 */
c7843e8f 1871 if (limit_warnings > 0 && (qc->nbytes / qc->sect_size) > 1) {
c6112bd8
ML		 1872 --limit_warnings;
1873 ata_link_printk(qc->dev->link, KERN_WARNING, DRV_NAME
1874 ": attempting PIO w/multiple DRQ: "
1875 "this may fail due to h/w errata\n");
1876 }
f48765cc 1877 /* drop through */
42ed893d 1878 case ATA_PROT_NODATA:
f48765cc 1879 case ATAPI_PROT_PIO:
42ed893d
ML		 1880 case ATAPI_PROT_NODATA:
1881 if (ap->flags & ATA_FLAG_PIO_POLLING)
1882 qc->tf.flags |= ATA_TFLAG_POLLING;
1883 break;
31961943 1884 }
42ed893d
ML		 1885
1886 if (qc->tf.flags & ATA_TFLAG_POLLING)
1887 port_irqs = ERR_IRQ; /* mask device interrupt when polling */
1888 else
1889 port_irqs = ERR_IRQ | DONE_IRQ; /* unmask all interrupts */
1890
1891 /*
1892 * We're about to send a non-EDMA capable command to the
1893 * port. Turn off EDMA so there won't be problems accessing
1894 * shadow block, etc registers.
1895 */
1896 mv_stop_edma(ap);
1897 mv_clear_and_enable_port_irqs(ap, mv_ap_base(ap), port_irqs);
1898 mv_pmp_select(ap, qc->dev->link->pmp);
1899 return ata_sff_qc_issue(qc);
31961943
BR		 1900}
1901
8f767f8a
ML		 1902static struct ata_queued_cmd *mv_get_active_qc(struct ata_port *ap)
1903{
1904 struct mv_port_priv *pp = ap->private_data;
1905 struct ata_queued_cmd *qc;
1906
1907 if (pp->pp_flags & MV_PP_FLAG_NCQ_EN)
1908 return NULL;
1909 qc = ata_qc_from_tag(ap, ap->link.active_tag);
95db5051
ML		 1910 if (qc) {
1911 if (qc->tf.flags & ATA_TFLAG_POLLING)
1912 qc = NULL;
1913 else if (!(qc->flags & ATA_QCFLAG_ACTIVE))
1914 qc = NULL;
1915 }
8f767f8a
ML		 1916 return qc;
1917}
1918
29d187bb
ML		 1919static void mv_pmp_error_handler(struct ata_port *ap)
1920{
1921 unsigned int pmp, pmp_map;
1922 struct mv_port_priv *pp = ap->private_data;
1923
1924 if (pp->pp_flags & MV_PP_FLAG_DELAYED_EH) {
1925 /*
1926 * Perform NCQ error analysis on failed PMPs
1927 * before we freeze the port entirely.
1928 *
1929 * The failed PMPs are marked earlier by mv_pmp_eh_prep().
1930 */
1931 pmp_map = pp->delayed_eh_pmp_map;
1932 pp->pp_flags &= ~MV_PP_FLAG_DELAYED_EH;
1933 for (pmp = 0; pmp_map != 0; pmp++) {
1934 unsigned int this_pmp = (1 << pmp);
1935 if (pmp_map & this_pmp) {
1936 struct ata_link *link = &ap->pmp_link[pmp];
1937 pmp_map &= ~this_pmp;
1938 ata_eh_analyze_ncq_error(link);
1939 }
1940 }
1941 ata_port_freeze(ap);
1942 }
1943 sata_pmp_error_handler(ap);
1944}
1945
4c299ca3
ML		 1946static unsigned int mv_get_err_pmp_map(struct ata_port *ap)
1947{
1948 void __iomem *port_mmio = mv_ap_base(ap);
1949
1950 return readl(port_mmio + SATA_TESTCTL_OFS) >> 16;
1951}
1952
4c299ca3
ML		 1953static void mv_pmp_eh_prep(struct ata_port *ap, unsigned int pmp_map)
1954{
1955 struct ata_eh_info *ehi;
1956 unsigned int pmp;
1957
1958 /*
1959 * Initialize EH info for PMPs which saw device errors
1960 */
1961 ehi = &ap->link.eh_info;
1962 for (pmp = 0; pmp_map != 0; pmp++) {
1963 unsigned int this_pmp = (1 << pmp);
1964 if (pmp_map & this_pmp) {
1965 struct ata_link *link = &ap->pmp_link[pmp];
1966
1967 pmp_map &= ~this_pmp;
1968 ehi = &link->eh_info;
1969 ata_ehi_clear_desc(ehi);
1970 ata_ehi_push_desc(ehi, "dev err");
1971 ehi->err_mask |= AC_ERR_DEV;
1972 ehi->action |= ATA_EH_RESET;
1973 ata_link_abort(link);
1974 }
1975 }
1976}
1977
06aaca3f
ML		 1978static int mv_req_q_empty(struct ata_port *ap)
1979{
1980 void __iomem *port_mmio = mv_ap_base(ap);
1981 u32 in_ptr, out_ptr;
1982
1983 in_ptr = (readl(port_mmio + EDMA_REQ_Q_IN_PTR_OFS)
1984 >> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK;
1985 out_ptr = (readl(port_mmio + EDMA_REQ_Q_OUT_PTR_OFS)
1986 >> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK;
1987 return (in_ptr == out_ptr); /* 1 == queue_is_empty */
1988}
1989
4c299ca3
ML		 1990static int mv_handle_fbs_ncq_dev_err(struct ata_port *ap)
1991{
1992 struct mv_port_priv *pp = ap->private_data;
1993 int failed_links;
1994 unsigned int old_map, new_map;
1995
1996 /*
1997 * Device error during FBS+NCQ operation:
1998 *
1999 * Set a port flag to prevent further I/O being enqueued.
2000 * Leave the EDMA running to drain outstanding commands from this port.
2001 * Perform the post-mortem/EH only when all responses are complete.
2002 * Follow recovery sequence from 6042/7042 datasheet (7.3.15.4.2.2).
2003 */
2004 if (!(pp->pp_flags & MV_PP_FLAG_DELAYED_EH)) {
2005 pp->pp_flags |= MV_PP_FLAG_DELAYED_EH;
2006 pp->delayed_eh_pmp_map = 0;
2007 }
2008 old_map = pp->delayed_eh_pmp_map;
2009 new_map = old_map | mv_get_err_pmp_map(ap);
2010
2011 if (old_map != new_map) {
2012 pp->delayed_eh_pmp_map = new_map;
2013 mv_pmp_eh_prep(ap, new_map & ~old_map);
2014 }
c46938cc 2015 failed_links = hweight16(new_map);
4c299ca3
ML		 2016
2017 ata_port_printk(ap, KERN_INFO, "%s: pmp_map=%04x qc_map=%04x "
2018 "failed_links=%d nr_active_links=%d\n",
2019 __func__, pp->delayed_eh_pmp_map,
2020 ap->qc_active, failed_links,
2021 ap->nr_active_links);
2022
06aaca3f 2023 if (ap->nr_active_links <= failed_links && mv_req_q_empty(ap)) {
4c299ca3
ML		 2024 mv_process_crpb_entries(ap, pp);
2025 mv_stop_edma(ap);
2026 mv_eh_freeze(ap);
2027 ata_port_printk(ap, KERN_INFO, "%s: done\n", __func__);
2028 return 1; /* handled */
2029 }
2030 ata_port_printk(ap, KERN_INFO, "%s: waiting\n", __func__);
2031 return 1; /* handled */
2032}
2033
2034static int mv_handle_fbs_non_ncq_dev_err(struct ata_port *ap)
2035{
2036 /*
2037 * Possible future enhancement:
2038 *
2039 * FBS+non-NCQ operation is not yet implemented.
2040 * See related notes in mv_edma_cfg().
2041 *
2042 * Device error during FBS+non-NCQ operation:
2043 *
2044 * We need to snapshot the shadow registers for each failed command.
2045 * Follow recovery sequence from 6042/7042 datasheet (7.3.15.4.2.3).
2046 */
2047 return 0; /* not handled */
2048}
2049
2050static int mv_handle_dev_err(struct ata_port *ap, u32 edma_err_cause)
2051{
2052 struct mv_port_priv *pp = ap->private_data;
2053
2054 if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN))
2055 return 0; /* EDMA was not active: not handled */
2056 if (!(pp->pp_flags & MV_PP_FLAG_FBS_EN))
2057 return 0; /* FBS was not active: not handled */
2058
2059 if (!(edma_err_cause & EDMA_ERR_DEV))
2060 return 0; /* non DEV error: not handled */
2061 edma_err_cause &= ~EDMA_ERR_IRQ_TRANSIENT;
2062 if (edma_err_cause & ~(EDMA_ERR_DEV | EDMA_ERR_SELF_DIS))
2063 return 0; /* other problems: not handled */
2064
2065 if (pp->pp_flags & MV_PP_FLAG_NCQ_EN) {
2066 /*
2067 * EDMA should NOT have self-disabled for this case.
2068 * If it did, then something is wrong elsewhere,
2069 * and we cannot handle it here.
2070 */
2071 if (edma_err_cause & EDMA_ERR_SELF_DIS) {
2072 ata_port_printk(ap, KERN_WARNING,
2073 "%s: err_cause=0x%x pp_flags=0x%x\n",
2074 __func__, edma_err_cause, pp->pp_flags);
2075 return 0; /* not handled */
2076 }
2077 return mv_handle_fbs_ncq_dev_err(ap);
2078 } else {
2079 /*
2080 * EDMA should have self-disabled for this case.
2081 * If it did not, then something is wrong elsewhere,
2082 * and we cannot handle it here.
2083 */
2084 if (!(edma_err_cause & EDMA_ERR_SELF_DIS)) {
2085 ata_port_printk(ap, KERN_WARNING,
2086 "%s: err_cause=0x%x pp_flags=0x%x\n",
2087 __func__, edma_err_cause, pp->pp_flags);
2088 return 0; /* not handled */
2089 }
2090 return mv_handle_fbs_non_ncq_dev_err(ap);
2091 }
2092 return 0; /* not handled */
2093}
2094
a9010329 2095static void mv_unexpected_intr(struct ata_port *ap, int edma_was_enabled)
8f767f8a 2096{
8f767f8a 2097 struct ata_eh_info *ehi = &ap->link.eh_info;
a9010329 2098 char *when = "idle";
8f767f8a 2099
8f767f8a 2100 ata_ehi_clear_desc(ehi);
a9010329
ML		 2101 if (!ap || (ap->flags & ATA_FLAG_DISABLED)) {
2102 when = "disabled";
2103 } else if (edma_was_enabled) {
2104 when = "EDMA enabled";
8f767f8a
ML		 2105 } else {
2106 struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->link.active_tag);
2107 if (qc && (qc->tf.flags & ATA_TFLAG_POLLING))
a9010329 2108 when = "polling";
8f767f8a 2109 }
a9010329 2110 ata_ehi_push_desc(ehi, "unexpected device interrupt while %s", when);
8f767f8a
ML		 2111 ehi->err_mask |= AC_ERR_OTHER;
2112 ehi->action |= ATA_EH_RESET;
2113 ata_port_freeze(ap);
2114}
2115
05b308e1
BR		 2116/**
2117 * mv_err_intr - Handle error interrupts on the port
2118 * @ap: ATA channel to manipulate
2119 *
8d07379d
ML		 2120 * Most cases require a full reset of the chip's state machine,
2121 * which also performs a COMRESET.
2122 * Also, if the port disabled DMA, update our cached copy to match.
05b308e1
BR		 2123 *
2124 * LOCKING:
2125 * Inherited from caller.
2126 */
37b9046a 2127static void mv_err_intr(struct ata_port *ap)
31961943
BR		 2128{
2129 void __iomem *port_mmio = mv_ap_base(ap);
bdd4ddde 2130 u32 edma_err_cause, eh_freeze_mask, serr = 0;
e4006077 2131 u32 fis_cause = 0;
bdd4ddde
JG		 2132 struct mv_port_priv *pp = ap->private_data;
2133 struct mv_host_priv *hpriv = ap->host->private_data;
bdd4ddde 2134 unsigned int action = 0, err_mask = 0;
9af5c9c9 2135 struct ata_eh_info *ehi = &ap->link.eh_info;
37b9046a
ML		 2136 struct ata_queued_cmd *qc;
2137 int abort = 0;
20f733e7 2138
8d07379d 2139 /*
37b9046a 2140 * Read and clear the SError and err_cause bits.
e4006077
ML		 2141 * For GenIIe, if EDMA_ERR_TRANS_IRQ_7 is set, we also must read/clear
2142 * the FIS_IRQ_CAUSE register before clearing edma_err_cause.
8d07379d 2143 */
37b9046a
ML		 2144 sata_scr_read(&ap->link, SCR_ERROR, &serr);
2145 sata_scr_write_flush(&ap->link, SCR_ERROR, serr);
2146
bdd4ddde 2147 edma_err_cause = readl(port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
e4006077
ML		 2148 if (IS_GEN_IIE(hpriv) && (edma_err_cause & EDMA_ERR_TRANS_IRQ_7)) {
2149 fis_cause = readl(port_mmio + SATA_FIS_IRQ_CAUSE_OFS);
2150 writelfl(~fis_cause, port_mmio + SATA_FIS_IRQ_CAUSE_OFS);
2151 }
8d07379d 2152 writelfl(~edma_err_cause, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
bdd4ddde 2153
4c299ca3
ML		 2154 if (edma_err_cause & EDMA_ERR_DEV) {
2155 /*
2156 * Device errors during FIS-based switching operation
2157 * require special handling.
2158 */
2159 if (mv_handle_dev_err(ap, edma_err_cause))
2160 return;
2161 }
2162
37b9046a
ML		 2163 qc = mv_get_active_qc(ap);
2164 ata_ehi_clear_desc(ehi);
2165 ata_ehi_push_desc(ehi, "edma_err_cause=%08x pp_flags=%08x",
2166 edma_err_cause, pp->pp_flags);
e4006077 2167
c443c500 2168 if (IS_GEN_IIE(hpriv) && (edma_err_cause & EDMA_ERR_TRANS_IRQ_7)) {
e4006077 2169 ata_ehi_push_desc(ehi, "fis_cause=%08x", fis_cause);
c443c500
ML		 2170 if (fis_cause & SATA_FIS_IRQ_AN) {
2171 u32 ec = edma_err_cause &
2172 ~(EDMA_ERR_TRANS_IRQ_7 | EDMA_ERR_IRQ_TRANSIENT);
2173 sata_async_notification(ap);
2174 if (!ec)
2175 return; /* Just an AN; no need for the nukes */
2176 ata_ehi_push_desc(ehi, "SDB notify");
2177 }
2178 }
bdd4ddde 2179 /*
352fab70 2180 * All generations share these EDMA error cause bits:
bdd4ddde 2181 */
37b9046a 2182 if (edma_err_cause & EDMA_ERR_DEV) {
bdd4ddde 2183 err_mask |= AC_ERR_DEV;
37b9046a
ML		 2184 action |= ATA_EH_RESET;
2185 ata_ehi_push_desc(ehi, "dev error");
2186 }
bdd4ddde 2187 if (edma_err_cause & (EDMA_ERR_D_PAR | EDMA_ERR_PRD_PAR |
6c1153e0 2188 EDMA_ERR_CRQB_PAR | EDMA_ERR_CRPB_PAR |
bdd4ddde
JG		 2189 EDMA_ERR_INTRL_PAR)) {
2190 err_mask |= AC_ERR_ATA_BUS;
cf480626 2191 action |= ATA_EH_RESET;
b64bbc39 2192 ata_ehi_push_desc(ehi, "parity error");
bdd4ddde
JG		 2193 }
2194 if (edma_err_cause & (EDMA_ERR_DEV_DCON | EDMA_ERR_DEV_CON)) {
2195 ata_ehi_hotplugged(ehi);
2196 ata_ehi_push_desc(ehi, edma_err_cause & EDMA_ERR_DEV_DCON ?
b64bbc39 2197 "dev disconnect" : "dev connect");
cf480626 2198 action |= ATA_EH_RESET;
bdd4ddde
JG		 2199 }
2200
352fab70
ML		 2201 /*
2202 * Gen-I has a different SELF_DIS bit,
2203 * different FREEZE bits, and no SERR bit:
2204 */
ee9ccdf7 2205 if (IS_GEN_I(hpriv)) {
bdd4ddde 2206 eh_freeze_mask = EDMA_EH_FREEZE_5;
bdd4ddde 2207 if (edma_err_cause & EDMA_ERR_SELF_DIS_5) {
bdd4ddde 2208 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
b64bbc39 2209 ata_ehi_push_desc(ehi, "EDMA self-disable");
bdd4ddde
JG		 2210 }
2211 } else {
2212 eh_freeze_mask = EDMA_EH_FREEZE;
bdd4ddde 2213 if (edma_err_cause & EDMA_ERR_SELF_DIS) {
bdd4ddde 2214 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
b64bbc39 2215 ata_ehi_push_desc(ehi, "EDMA self-disable");
bdd4ddde 2216 }
bdd4ddde 2217 if (edma_err_cause & EDMA_ERR_SERR) {
8d07379d
ML		 2218 ata_ehi_push_desc(ehi, "SError=%08x", serr);
2219 err_mask |= AC_ERR_ATA_BUS;
cf480626 2220 action |= ATA_EH_RESET;
bdd4ddde 2221 }
afb0edd9 2222 }
20f733e7 2223
bdd4ddde
JG		 2224 if (!err_mask) {
2225 err_mask = AC_ERR_OTHER;
cf480626 2226 action |= ATA_EH_RESET;
bdd4ddde
JG		 2227 }
2228
2229 ehi->serror |= serr;
2230 ehi->action |= action;
2231
2232 if (qc)
2233 qc->err_mask |= err_mask;
2234 else
2235 ehi->err_mask |= err_mask;
2236
37b9046a
ML		 2237 if (err_mask == AC_ERR_DEV) {
2238 /*
2239 * Cannot do ata_port_freeze() here,
2240 * because it would kill PIO access,
2241 * which is needed for further diagnosis.
2242 */
2243 mv_eh_freeze(ap);
2244 abort = 1;
2245 } else if (edma_err_cause & eh_freeze_mask) {
2246 /*
2247 * Note to self: ata_port_freeze() calls ata_port_abort()
2248 */
bdd4ddde 2249 ata_port_freeze(ap);
37b9046a
ML		 2250 } else {
2251 abort = 1;
2252 }
2253
2254 if (abort) {
2255 if (qc)
2256 ata_link_abort(qc->dev->link);
2257 else
2258 ata_port_abort(ap);
2259 }
bdd4ddde
JG		 2260}
2261
fcfb1f77
ML		 2262static void mv_process_crpb_response(struct ata_port *ap,
2263 struct mv_crpb *response, unsigned int tag, int ncq_enabled)
2264{
2265 struct ata_queued_cmd *qc = ata_qc_from_tag(ap, tag);
2266
2267 if (qc) {
2268 u8 ata_status;
2269 u16 edma_status = le16_to_cpu(response->flags);
2270 /*
2271 * edma_status from a response queue entry:
2272 * LSB is from EDMA_ERR_IRQ_CAUSE_OFS (non-NCQ only).
2273 * MSB is saved ATA status from command completion.
2274 */
2275 if (!ncq_enabled) {
2276 u8 err_cause = edma_status & 0xff & ~EDMA_ERR_DEV;
2277 if (err_cause) {
2278 /*
2279 * Error will be seen/handled by mv_err_intr().
2280 * So do nothing at all here.
2281 */
2282 return;
2283 }
2284 }
2285 ata_status = edma_status >> CRPB_FLAG_STATUS_SHIFT;
37b9046a
ML		 2286 if (!ac_err_mask(ata_status))
2287 ata_qc_complete(qc);
2288 /* else: leave it for mv_err_intr() */
fcfb1f77
ML		 2289 } else {
2290 ata_port_printk(ap, KERN_ERR, "%s: no qc for tag=%d\n",
2291 __func__, tag);
2292 }
2293}
2294
2295static void mv_process_crpb_entries(struct ata_port *ap, struct mv_port_priv *pp)
bdd4ddde
JG		 2296{
2297 void __iomem *port_mmio = mv_ap_base(ap);
2298 struct mv_host_priv *hpriv = ap->host->private_data;
fcfb1f77 2299 u32 in_index;
bdd4ddde 2300 bool work_done = false;
fcfb1f77 2301 int ncq_enabled = (pp->pp_flags & MV_PP_FLAG_NCQ_EN);
bdd4ddde 2302
fcfb1f77 2303 /* Get the hardware queue position index */
bdd4ddde
JG		 2304 in_index = (readl(port_mmio + EDMA_RSP_Q_IN_PTR_OFS)
2305 >> EDMA_RSP_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK;
2306
fcfb1f77
ML		 2307 /* Process new responses from since the last time we looked */
2308 while (in_index != pp->resp_idx) {
6c1153e0 2309 unsigned int tag;
fcfb1f77 2310 struct mv_crpb *response = &pp->crpb[pp->resp_idx];
bdd4ddde 2311
fcfb1f77 2312 pp->resp_idx = (pp->resp_idx + 1) & MV_MAX_Q_DEPTH_MASK;
bdd4ddde 2313
fcfb1f77
ML		 2314 if (IS_GEN_I(hpriv)) {
2315 /* 50xx: no NCQ, only one command active at a time */
9af5c9c9 2316 tag = ap->link.active_tag;
fcfb1f77
ML		 2317 } else {
2318 /* Gen II/IIE: get command tag from CRPB entry */
2319 tag = le16_to_cpu(response->id) & 0x1f;
bdd4ddde 2320 }
fcfb1f77 2321 mv_process_crpb_response(ap, response, tag, ncq_enabled);
bdd4ddde 2322 work_done = true;
bdd4ddde
JG		 2323 }
2324
352fab70 2325 /* Update the software queue position index in hardware */
bdd4ddde
JG		 2326 if (work_done)
2327 writelfl((pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK) |
fcfb1f77 2328 (pp->resp_idx << EDMA_RSP_Q_PTR_SHIFT),
bdd4ddde 2329 port_mmio + EDMA_RSP_Q_OUT_PTR_OFS);
20f733e7
BR		 2330}
2331
a9010329
ML		 2332static void mv_port_intr(struct ata_port *ap, u32 port_cause)
2333{
2334 struct mv_port_priv *pp;
2335 int edma_was_enabled;
2336
2337 if (!ap || (ap->flags & ATA_FLAG_DISABLED)) {
2338 mv_unexpected_intr(ap, 0);
2339 return;
2340 }
2341 /*
2342 * Grab a snapshot of the EDMA_EN flag setting,
2343 * so that we have a consistent view for this port,
2344 * even if something we call of our routines changes it.
2345 */
2346 pp = ap->private_data;
2347 edma_was_enabled = (pp->pp_flags & MV_PP_FLAG_EDMA_EN);
2348 /*
2349 * Process completed CRPB response(s) before other events.
2350 */
2351 if (edma_was_enabled && (port_cause & DONE_IRQ)) {
2352 mv_process_crpb_entries(ap, pp);
4c299ca3
ML		 2353 if (pp->pp_flags & MV_PP_FLAG_DELAYED_EH)
2354 mv_handle_fbs_ncq_dev_err(ap);
a9010329
ML		 2355 }
2356 /*
2357 * Handle chip-reported errors, or continue on to handle PIO.
2358 */
2359 if (unlikely(port_cause & ERR_IRQ)) {
2360 mv_err_intr(ap);
2361 } else if (!edma_was_enabled) {
2362 struct ata_queued_cmd *qc = mv_get_active_qc(ap);
2363 if (qc)
2364 ata_sff_host_intr(ap, qc);
2365 else
2366 mv_unexpected_intr(ap, edma_was_enabled);
2367 }
2368}
2369
05b308e1
BR		 2370/**
2371 * mv_host_intr - Handle all interrupts on the given host controller
cca3974e 2372 * @host: host specific structure
7368f919 2373 * @main_irq_cause: Main interrupt cause register for the chip.
05b308e1
BR		 2374 *
2375 * LOCKING:
2376 * Inherited from caller.
2377 */
7368f919 2378static int mv_host_intr(struct ata_host *host, u32 main_irq_cause)
20f733e7 2379{
f351b2d6 2380 struct mv_host_priv *hpriv = host->private_data;
eabd5eb1 2381 void __iomem *mmio = hpriv->base, *hc_mmio;
a3718c1f 2382 unsigned int handled = 0, port;
20f733e7 2383
a3718c1f 2384 for (port = 0; port < hpriv->n_ports; port++) {
cca3974e 2385 struct ata_port *ap = host->ports[port];
eabd5eb1
ML		 2386 unsigned int p, shift, hardport, port_cause;
2387
a3718c1f 2388 MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport);
a3718c1f 2389 /*
eabd5eb1
ML		 2390 * Each hc within the host has its own hc_irq_cause register,
2391 * where the interrupting ports bits get ack'd.
a3718c1f 2392 */
eabd5eb1
ML		 2393 if (hardport == 0) { /* first port on this hc ? */
2394 u32 hc_cause = (main_irq_cause >> shift) & HC0_IRQ_PEND;
2395 u32 port_mask, ack_irqs;
2396 /*
2397 * Skip this entire hc if nothing pending for any ports
2398 */
2399 if (!hc_cause) {
2400 port += MV_PORTS_PER_HC - 1;
2401 continue;
2402 }
2403 /*
2404 * We don't need/want to read the hc_irq_cause register,
2405 * because doing so hurts performance, and
2406 * main_irq_cause already gives us everything we need.
2407 *
2408 * But we do have to *write* to the hc_irq_cause to ack
2409 * the ports that we are handling this time through.
2410 *
2411 * This requires that we create a bitmap for those
2412 * ports which interrupted us, and use that bitmap
2413 * to ack (only) those ports via hc_irq_cause.
2414 */
2415 ack_irqs = 0;
2416 for (p = 0; p < MV_PORTS_PER_HC; ++p) {
2417 if ((port + p) >= hpriv->n_ports)
2418 break;
2419 port_mask = (DONE_IRQ | ERR_IRQ) << (p * 2);
2420 if (hc_cause & port_mask)
2421 ack_irqs |= (DMA_IRQ | DEV_IRQ) << p;
2422 }
a3718c1f 2423 hc_mmio = mv_hc_base_from_port(mmio, port);
eabd5eb1 2424 writelfl(~ack_irqs, hc_mmio + HC_IRQ_CAUSE_OFS);
a3718c1f
ML		 2425 handled = 1;
2426 }
8f767f8a 2427 /*
a9010329 2428 * Handle interrupts signalled for this port:
8f767f8a 2429 */
a9010329
ML		 2430 port_cause = (main_irq_cause >> shift) & (DONE_IRQ | ERR_IRQ);
2431 if (port_cause)
2432 mv_port_intr(ap, port_cause);
20f733e7 2433 }
a3718c1f 2434 return handled;
20f733e7
BR		 2435}
2436
a3718c1f 2437static int mv_pci_error(struct ata_host *host, void __iomem *mmio)
bdd4ddde 2438{
02a121da 2439 struct mv_host_priv *hpriv = host->private_data;
bdd4ddde
JG		 2440 struct ata_port *ap;
2441 struct ata_queued_cmd *qc;
2442 struct ata_eh_info *ehi;
2443 unsigned int i, err_mask, printed = 0;
2444 u32 err_cause;
2445
02a121da 2446 err_cause = readl(mmio + hpriv->irq_cause_ofs);
bdd4ddde
JG		 2447
2448 dev_printk(KERN_ERR, host->dev, "PCI ERROR; PCI IRQ cause=0x%08x\n",
2449 err_cause);
2450
2451 DPRINTK("All regs @ PCI error\n");
2452 mv_dump_all_regs(mmio, -1, to_pci_dev(host->dev));
2453
02a121da 2454 writelfl(0, mmio + hpriv->irq_cause_ofs);
bdd4ddde
JG		 2455
2456 for (i = 0; i < host->n_ports; i++) {
2457 ap = host->ports[i];
936fd732 2458 if (!ata_link_offline(&ap->link)) {
9af5c9c9 2459 ehi = &ap->link.eh_info;
bdd4ddde
JG		 2460 ata_ehi_clear_desc(ehi);
2461 if (!printed++)
2462 ata_ehi_push_desc(ehi,
2463 "PCI err cause 0x%08x", err_cause);
2464 err_mask = AC_ERR_HOST_BUS;
cf480626 2465 ehi->action = ATA_EH_RESET;
9af5c9c9 2466 qc = ata_qc_from_tag(ap, ap->link.active_tag);
bdd4ddde
JG		 2467 if (qc)
2468 qc->err_mask |= err_mask;
2469 else
2470 ehi->err_mask |= err_mask;
2471
2472 ata_port_freeze(ap);
2473 }
2474 }
a3718c1f 2475 return 1; /* handled */
bdd4ddde
JG		 2476}
2477
05b308e1 2478/**
c5d3e45a 2479 * mv_interrupt - Main interrupt event handler
05b308e1
BR		 2480 * @irq: unused
2481 * @dev_instance: private data; in this case the host structure
05b308e1
BR		 2482 *
2483 * Read the read only register to determine if any host
2484 * controllers have pending interrupts. If so, call lower level
2485 * routine to handle. Also check for PCI errors which are only
2486 * reported here.
2487 *
8b260248 2488 * LOCKING:
cca3974e 2489 * This routine holds the host lock while processing pending
05b308e1
BR		 2490 * interrupts.
2491 */
7d12e780 2492static irqreturn_t mv_interrupt(int irq, void *dev_instance)
20f733e7 2493{
cca3974e 2494 struct ata_host *host = dev_instance;
f351b2d6 2495 struct mv_host_priv *hpriv = host->private_data;
a3718c1f 2496 unsigned int handled = 0;
6d3c30ef 2497 int using_msi = hpriv->hp_flags & MV_HP_FLAG_MSI;
96e2c487 2498 u32 main_irq_cause, pending_irqs;
20f733e7 2499
646a4da5 2500 spin_lock(&host->lock);
6d3c30ef
ML		 2501
2502 /* for MSI: block new interrupts while in here */
2503 if (using_msi)
2504 writel(0, hpriv->main_irq_mask_addr);
2505
7368f919 2506 main_irq_cause = readl(hpriv->main_irq_cause_addr);
96e2c487 2507 pending_irqs = main_irq_cause & hpriv->main_irq_mask;
352fab70
ML		 2508 /*
2509 * Deal with cases where we either have nothing pending, or have read
2510 * a bogus register value which can indicate HW removal or PCI fault.
20f733e7 2511 */
a44253d2 2512 if (pending_irqs && main_irq_cause != 0xffffffffU) {
1f398472 2513 if (unlikely((pending_irqs & PCI_ERR) && !IS_SOC(hpriv)))
a3718c1f
ML		 2514 handled = mv_pci_error(host, hpriv->base);
2515 else
a44253d2 2516 handled = mv_host_intr(host, pending_irqs);
bdd4ddde 2517 }
6d3c30ef
ML		 2518
2519 /* for MSI: unmask; interrupt cause bits will retrigger now */
2520 if (using_msi)
2521 writel(hpriv->main_irq_mask, hpriv->main_irq_mask_addr);
2522
9d51af7b
ML		 2523 spin_unlock(&host->lock);
2524
20f733e7
BR		 2525 return IRQ_RETVAL(handled);
2526}
2527
c9d39130
JG		 2528static unsigned int mv5_scr_offset(unsigned int sc_reg_in)
2529{
2530 unsigned int ofs;
2531
2532 switch (sc_reg_in) {
2533 case SCR_STATUS:
2534 case SCR_ERROR:
2535 case SCR_CONTROL:
2536 ofs = sc_reg_in * sizeof(u32);
2537 break;
2538 default:
2539 ofs = 0xffffffffU;
2540 break;
2541 }
2542 return ofs;
2543}
2544
82ef04fb 2545static int mv5_scr_read(struct ata_link *link, unsigned int sc_reg_in, u32 *val)
c9d39130 2546{
82ef04fb 2547 struct mv_host_priv *hpriv = link->ap->host->private_data;
f351b2d6 2548 void __iomem *mmio = hpriv->base;
82ef04fb 2549 void __iomem *addr = mv5_phy_base(mmio, link->ap->port_no);
c9d39130
JG		 2550 unsigned int ofs = mv5_scr_offset(sc_reg_in);
2551
da3dbb17
TH		 2552 if (ofs != 0xffffffffU) {
2553 *val = readl(addr + ofs);
2554 return 0;
2555 } else
2556 return -EINVAL;
c9d39130
JG		 2557}
2558
82ef04fb 2559static int mv5_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val)
c9d39130 2560{
82ef04fb 2561 struct mv_host_priv *hpriv = link->ap->host->private_data;
f351b2d6 2562 void __iomem *mmio = hpriv->base;
82ef04fb 2563 void __iomem *addr = mv5_phy_base(mmio, link->ap->port_no);
c9d39130
JG		 2564 unsigned int ofs = mv5_scr_offset(sc_reg_in);
2565
da3dbb17 2566 if (ofs != 0xffffffffU) {
0d5ff566 2567 writelfl(val, addr + ofs);
da3dbb17
TH		 2568 return 0;
2569 } else
2570 return -EINVAL;
c9d39130
JG		 2571}
2572
7bb3c529 2573static void mv5_reset_bus(struct ata_host *host, void __iomem *mmio)
522479fb 2574{
7bb3c529 2575 struct pci_dev *pdev = to_pci_dev(host->dev);
522479fb
JG		 2576 int early_5080;
2577
44c10138 2578 early_5080 = (pdev->device == 0x5080) && (pdev->revision == 0);
522479fb
JG		 2579
2580 if (!early_5080) {
2581 u32 tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL);
2582 tmp |= (1 << 0);
2583 writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL);
2584 }
2585
7bb3c529 2586 mv_reset_pci_bus(host, mmio);
522479fb
JG		 2587}
2588
2589static void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio)
2590{
8e7decdb 2591 writel(0x0fcfffff, mmio + MV_FLASH_CTL_OFS);
522479fb
JG		 2592}
2593
47c2b677 2594static void mv5_read_preamp(struct mv_host_priv *hpriv, int idx,
ba3fe8fb
JG		 2595 void __iomem *mmio)
2596{
c9d39130
JG		 2597 void __iomem *phy_mmio = mv5_phy_base(mmio, idx);
2598 u32 tmp;
2599
2600 tmp = readl(phy_mmio + MV5_PHY_MODE);
2601
2602 hpriv->signal[idx].pre = tmp & 0x1800; /* bits 12:11 */
2603 hpriv->signal[idx].amps = tmp & 0xe0; /* bits 7:5 */
ba3fe8fb
JG		 2604}
2605
47c2b677 2606static void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio)
ba3fe8fb 2607{
522479fb
JG		 2608 u32 tmp;
2609
8e7decdb 2610 writel(0, mmio + MV_GPIO_PORT_CTL_OFS);
522479fb
JG		 2611
2612 /* FIXME: handle MV_HP_ERRATA_50XXB2 errata */
2613
2614 tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL);
2615 tmp |= ~(1 << 0);
2616 writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL);
ba3fe8fb
JG		 2617}
2618
2a47ce06
JG		 2619static void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
2620 unsigned int port)
bca1c4eb 2621{
c9d39130
JG		 2622 void __iomem *phy_mmio = mv5_phy_base(mmio, port);
2623 const u32 mask = (1<<12) | (1<<11) | (1<<7) | (1<<6) | (1<<5);
2624 u32 tmp;
2625 int fix_apm_sq = (hpriv->hp_flags & MV_HP_ERRATA_50XXB0);
2626
2627 if (fix_apm_sq) {
8e7decdb 2628 tmp = readl(phy_mmio + MV5_LTMODE_OFS);
c9d39130 2629 tmp |= (1 << 19);
8e7decdb 2630 writel(tmp, phy_mmio + MV5_LTMODE_OFS);
c9d39130 2631
8e7decdb 2632 tmp = readl(phy_mmio + MV5_PHY_CTL_OFS);
c9d39130
JG		 2633 tmp &= ~0x3;
2634 tmp |= 0x1;
8e7decdb 2635 writel(tmp, phy_mmio + MV5_PHY_CTL_OFS);
c9d39130
JG		 2636 }
2637
2638 tmp = readl(phy_mmio + MV5_PHY_MODE);
2639 tmp &= ~mask;
2640 tmp |= hpriv->signal[port].pre;
2641 tmp |= hpriv->signal[port].amps;
2642 writel(tmp, phy_mmio + MV5_PHY_MODE);
bca1c4eb
JG		 2643}
2644
c9d39130
JG		 2645
2646#undef ZERO
2647#define ZERO(reg) writel(0, port_mmio + (reg))
2648static void mv5_reset_hc_port(struct mv_host_priv *hpriv, void __iomem *mmio,
2649 unsigned int port)
2650{
2651 void __iomem *port_mmio = mv_port_base(mmio, port);
2652
e12bef50 2653 mv_reset_channel(hpriv, mmio, port);
c9d39130
JG		 2654
2655 ZERO(0x028); /* command */
2656 writel(0x11f, port_mmio + EDMA_CFG_OFS);
2657 ZERO(0x004); /* timer */
2658 ZERO(0x008); /* irq err cause */
2659 ZERO(0x00c); /* irq err mask */
2660 ZERO(0x010); /* rq bah */
2661 ZERO(0x014); /* rq inp */
2662 ZERO(0x018); /* rq outp */
2663 ZERO(0x01c); /* respq bah */
2664 ZERO(0x024); /* respq outp */
2665 ZERO(0x020); /* respq inp */
2666 ZERO(0x02c); /* test control */
8e7decdb 2667 writel(0xbc, port_mmio + EDMA_IORDY_TMOUT_OFS);
c9d39130
JG		 2668}
2669#undef ZERO
2670
2671#define ZERO(reg) writel(0, hc_mmio + (reg))
2672static void mv5_reset_one_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
2673 unsigned int hc)
47c2b677 2674{
c9d39130
JG		 2675 void __iomem *hc_mmio = mv_hc_base(mmio, hc);
2676 u32 tmp;
2677
2678 ZERO(0x00c);
2679 ZERO(0x010);
2680 ZERO(0x014);
2681 ZERO(0x018);
2682
2683 tmp = readl(hc_mmio + 0x20);
2684 tmp &= 0x1c1c1c1c;
2685 tmp |= 0x03030303;
2686 writel(tmp, hc_mmio + 0x20);
2687}
2688#undef ZERO
2689
2690static int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
2691 unsigned int n_hc)
2692{
2693 unsigned int hc, port;
2694
2695 for (hc = 0; hc < n_hc; hc++) {
2696 for (port = 0; port < MV_PORTS_PER_HC; port++)
2697 mv5_reset_hc_port(hpriv, mmio,
2698 (hc * MV_PORTS_PER_HC) + port);
2699
2700 mv5_reset_one_hc(hpriv, mmio, hc);
2701 }
2702
2703 return 0;
47c2b677
JG		 2704}
2705
101ffae2
JG		 2706#undef ZERO
2707#define ZERO(reg) writel(0, mmio + (reg))
7bb3c529 2708static void mv_reset_pci_bus(struct ata_host *host, void __iomem *mmio)
101ffae2 2709{
02a121da 2710 struct mv_host_priv *hpriv = host->private_data;
101ffae2
JG		 2711 u32 tmp;
2712
8e7decdb 2713 tmp = readl(mmio + MV_PCI_MODE_OFS);
101ffae2 2714 tmp &= 0xff00ffff;
8e7decdb 2715 writel(tmp, mmio + MV_PCI_MODE_OFS);
101ffae2
JG		 2716
2717 ZERO(MV_PCI_DISC_TIMER);
2718 ZERO(MV_PCI_MSI_TRIGGER);
8e7decdb 2719 writel(0x000100ff, mmio + MV_PCI_XBAR_TMOUT_OFS);
101ffae2 2720 ZERO(MV_PCI_SERR_MASK);
02a121da
ML		 2721 ZERO(hpriv->irq_cause_ofs);
2722 ZERO(hpriv->irq_mask_ofs);
101ffae2
JG		 2723 ZERO(MV_PCI_ERR_LOW_ADDRESS);
2724 ZERO(MV_PCI_ERR_HIGH_ADDRESS);
2725 ZERO(MV_PCI_ERR_ATTRIBUTE);
2726 ZERO(MV_PCI_ERR_COMMAND);
2727}
2728#undef ZERO
2729
2730static void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio)
2731{
2732 u32 tmp;
2733
2734 mv5_reset_flash(hpriv, mmio);
2735
8e7decdb 2736 tmp = readl(mmio + MV_GPIO_PORT_CTL_OFS);
101ffae2
JG		 2737 tmp &= 0x3;
2738 tmp |= (1 << 5) | (1 << 6);
8e7decdb 2739 writel(tmp, mmio + MV_GPIO_PORT_CTL_OFS);
101ffae2
JG		 2740}
2741
2742/**
2743 * mv6_reset_hc - Perform the 6xxx global soft reset
2744 * @mmio: base address of the HBA
2745 *
2746 * This routine only applies to 6xxx parts.
2747 *
2748 * LOCKING:
2749 * Inherited from caller.
2750 */
c9d39130
JG		 2751static int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
2752 unsigned int n_hc)
101ffae2
JG		 2753{
2754 void __iomem *reg = mmio + PCI_MAIN_CMD_STS_OFS;
2755 int i, rc = 0;
2756 u32 t;
2757
2758 /* Following procedure defined in PCI "main command and status
2759 * register" table.
2760 */
2761 t = readl(reg);
2762 writel(t | STOP_PCI_MASTER, reg);
2763
2764 for (i = 0; i < 1000; i++) {
2765 udelay(1);
2766 t = readl(reg);
2dcb407e 2767 if (PCI_MASTER_EMPTY & t)
101ffae2 2768 break;
101ffae2
JG		 2769 }
2770 if (!(PCI_MASTER_EMPTY & t)) {
2771 printk(KERN_ERR DRV_NAME ": PCI master won't flush\n");
2772 rc = 1;
2773 goto done;
2774 }
2775
2776 /* set reset */
2777 i = 5;
2778 do {
2779 writel(t | GLOB_SFT_RST, reg);
2780 t = readl(reg);
2781 udelay(1);
2782 } while (!(GLOB_SFT_RST & t) && (i-- > 0));
2783
2784 if (!(GLOB_SFT_RST & t)) {
2785 printk(KERN_ERR DRV_NAME ": can't set global reset\n");
2786 rc = 1;
2787 goto done;
2788 }
2789
2790 /* clear reset and *reenable the PCI master* (not mentioned in spec) */
2791 i = 5;
2792 do {
2793 writel(t & ~(GLOB_SFT_RST | STOP_PCI_MASTER), reg);
2794 t = readl(reg);
2795 udelay(1);
2796 } while ((GLOB_SFT_RST & t) && (i-- > 0));
2797
2798 if (GLOB_SFT_RST & t) {
2799 printk(KERN_ERR DRV_NAME ": can't clear global reset\n");
2800 rc = 1;
2801 }
2802done:
2803 return rc;
2804}
2805
47c2b677 2806static void mv6_read_preamp(struct mv_host_priv *hpriv, int idx,
ba3fe8fb
JG		 2807 void __iomem *mmio)
2808{
2809 void __iomem *port_mmio;
2810 u32 tmp;
2811
8e7decdb 2812 tmp = readl(mmio + MV_RESET_CFG_OFS);
ba3fe8fb 2813 if ((tmp & (1 << 0)) == 0) {
47c2b677 2814 hpriv->signal[idx].amps = 0x7 << 8;
ba3fe8fb
JG		 2815 hpriv->signal[idx].pre = 0x1 << 5;
2816 return;
2817 }
2818
2819 port_mmio = mv_port_base(mmio, idx);
2820 tmp = readl(port_mmio + PHY_MODE2);
2821
2822 hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */
2823 hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */
2824}
2825
47c2b677 2826static void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio)
ba3fe8fb 2827{
8e7decdb 2828 writel(0x00000060, mmio + MV_GPIO_PORT_CTL_OFS);
ba3fe8fb
JG		 2829}
2830
c9d39130 2831static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
2a47ce06 2832 unsigned int port)
bca1c4eb 2833{
c9d39130
JG		 2834 void __iomem *port_mmio = mv_port_base(mmio, port);
2835
bca1c4eb 2836 u32 hp_flags = hpriv->hp_flags;
47c2b677
JG		 2837 int fix_phy_mode2 =
2838 hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0);
bca1c4eb 2839 int fix_phy_mode4 =
47c2b677 2840 hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0);
8c30a8b9 2841 u32 m2, m3;
47c2b677
JG		 2842
2843 if (fix_phy_mode2) {
2844 m2 = readl(port_mmio + PHY_MODE2);
2845 m2 &= ~(1 << 16);
2846 m2 |= (1 << 31);
2847 writel(m2, port_mmio + PHY_MODE2);
2848
2849 udelay(200);
2850
2851 m2 = readl(port_mmio + PHY_MODE2);
2852 m2 &= ~((1 << 16) | (1 << 31));
2853 writel(m2, port_mmio + PHY_MODE2);
2854
2855 udelay(200);
2856 }
2857
8c30a8b9
ML		 2858 /*
2859 * Gen-II/IIe PHY_MODE3 errata RM#2:
2860 * Achieves better receiver noise performance than the h/w default:
2861 */
2862 m3 = readl(port_mmio + PHY_MODE3);
2863 m3 = (m3 & 0x1f) | (0x5555601 << 5);
bca1c4eb 2864
0388a8c0
ML		 2865 /* Guideline 88F5182 (GL# SATA-S11) */
2866 if (IS_SOC(hpriv))
2867 m3 &= ~0x1c;
2868
bca1c4eb 2869 if (fix_phy_mode4) {
ba069e37
ML		 2870 u32 m4 = readl(port_mmio + PHY_MODE4);
2871 /*
2872 * Enforce reserved-bit restrictions on GenIIe devices only.
2873 * For earlier chipsets, force only the internal config field
2874 * (workaround for errata FEr SATA#10 part 1).
2875 */
8c30a8b9 2876 if (IS_GEN_IIE(hpriv))
ba069e37
ML		 2877 m4 = (m4 & ~PHY_MODE4_RSVD_ZEROS) | PHY_MODE4_RSVD_ONES;
2878 else
2879 m4 = (m4 & ~PHY_MODE4_CFG_MASK) | PHY_MODE4_CFG_VALUE;
8c30a8b9 2880 writel(m4, port_mmio + PHY_MODE4);
bca1c4eb 2881 }
b406c7a6
ML		 2882 /*
2883 * Workaround for 60x1-B2 errata SATA#13:
2884 * Any write to PHY_MODE4 (above) may corrupt PHY_MODE3,
2885 * so we must always rewrite PHY_MODE3 after PHY_MODE4.
2886 */
2887 writel(m3, port_mmio + PHY_MODE3);
bca1c4eb
JG		 2888
2889 /* Revert values of pre-emphasis and signal amps to the saved ones */
2890 m2 = readl(port_mmio + PHY_MODE2);
2891
2892 m2 &= ~MV_M2_PREAMP_MASK;
2a47ce06
JG		 2893 m2 |= hpriv->signal[port].amps;
2894 m2 |= hpriv->signal[port].pre;
47c2b677 2895 m2 &= ~(1 << 16);
bca1c4eb 2896
e4e7b892
JG		 2897 /* according to mvSata 3.6.1, some IIE values are fixed */
2898 if (IS_GEN_IIE(hpriv)) {
2899 m2 &= ~0xC30FF01F;
2900 m2 |= 0x0000900F;
2901 }
2902
bca1c4eb
JG		 2903 writel(m2, port_mmio + PHY_MODE2);
2904}
2905
f351b2d6
SB		 2906/* TODO: use the generic LED interface to configure the SATA Presence */
2907/* & Acitivy LEDs on the board */
2908static void mv_soc_enable_leds(struct mv_host_priv *hpriv,
2909 void __iomem *mmio)
2910{
2911 return;
2912}
2913
2914static void mv_soc_read_preamp(struct mv_host_priv *hpriv, int idx,
2915 void __iomem *mmio)
2916{
2917 void __iomem *port_mmio;
2918 u32 tmp;
2919
2920 port_mmio = mv_port_base(mmio, idx);
2921 tmp = readl(port_mmio + PHY_MODE2);
2922
2923 hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */
2924 hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */
2925}
2926
2927#undef ZERO
2928#define ZERO(reg) writel(0, port_mmio + (reg))
2929static void mv_soc_reset_hc_port(struct mv_host_priv *hpriv,
2930 void __iomem *mmio, unsigned int port)
2931{
2932 void __iomem *port_mmio = mv_port_base(mmio, port);
2933
e12bef50 2934 mv_reset_channel(hpriv, mmio, port);
f351b2d6
SB		 2935
2936 ZERO(0x028); /* command */
2937 writel(0x101f, port_mmio + EDMA_CFG_OFS);
2938 ZERO(0x004); /* timer */
2939 ZERO(0x008); /* irq err cause */
2940 ZERO(0x00c); /* irq err mask */
2941 ZERO(0x010); /* rq bah */
2942 ZERO(0x014); /* rq inp */
2943 ZERO(0x018); /* rq outp */
2944 ZERO(0x01c); /* respq bah */
2945 ZERO(0x024); /* respq outp */
2946 ZERO(0x020); /* respq inp */
2947 ZERO(0x02c); /* test control */
8e7decdb 2948 writel(0xbc, port_mmio + EDMA_IORDY_TMOUT_OFS);
f351b2d6
SB		 2949}
2950
2951#undef ZERO
2952
2953#define ZERO(reg) writel(0, hc_mmio + (reg))
2954static void mv_soc_reset_one_hc(struct mv_host_priv *hpriv,
2955 void __iomem *mmio)
2956{
2957 void __iomem *hc_mmio = mv_hc_base(mmio, 0);
2958
2959 ZERO(0x00c);
2960 ZERO(0x010);
2961 ZERO(0x014);
2962
2963}
2964
2965#undef ZERO
2966
2967static int mv_soc_reset_hc(struct mv_host_priv *hpriv,
2968 void __iomem *mmio, unsigned int n_hc)
2969{
2970 unsigned int port;
2971
2972 for (port = 0; port < hpriv->n_ports; port++)
2973 mv_soc_reset_hc_port(hpriv, mmio, port);
2974
2975 mv_soc_reset_one_hc(hpriv, mmio);
2976
2977 return 0;
2978}
2979
2980static void mv_soc_reset_flash(struct mv_host_priv *hpriv,
2981 void __iomem *mmio)
2982{
2983 return;
2984}
2985
2986static void mv_soc_reset_bus(struct ata_host *host, void __iomem *mmio)
2987{
2988 return;
2989}
2990
8e7decdb 2991static void mv_setup_ifcfg(void __iomem *port_mmio, int want_gen2i)
b67a1064 2992{
8e7decdb 2993 u32 ifcfg = readl(port_mmio + SATA_INTERFACE_CFG_OFS);
b67a1064 2994
8e7decdb 2995 ifcfg = (ifcfg & 0xf7f) | 0x9b1000; /* from chip spec */
b67a1064 2996 if (want_gen2i)
8e7decdb
ML		 2997 ifcfg |= (1 << 7); /* enable gen2i speed */
2998 writelfl(ifcfg, port_mmio + SATA_INTERFACE_CFG_OFS);
b67a1064
ML		 2999}
3000
e12bef50 3001static void mv_reset_channel(struct mv_host_priv *hpriv, void __iomem *mmio,
c9d39130
JG		 3002 unsigned int port_no)
3003{
3004 void __iomem *port_mmio = mv_port_base(mmio, port_no);
3005
8e7decdb
ML		 3006 /*
3007 * The datasheet warns against setting EDMA_RESET when EDMA is active
3008 * (but doesn't say what the problem might be). So we first try
3009 * to disable the EDMA engine before doing the EDMA_RESET operation.
3010 */
0d8be5cb 3011 mv_stop_edma_engine(port_mmio);
8e7decdb 3012 writelfl(EDMA_RESET, port_mmio + EDMA_CMD_OFS);
c9d39130 3013
b67a1064 3014 if (!IS_GEN_I(hpriv)) {
8e7decdb
ML		 3015 /* Enable 3.0gb/s link speed: this survives EDMA_RESET */
3016 mv_setup_ifcfg(port_mmio, 1);
c9d39130 3017 }
b67a1064 3018 /*
8e7decdb 3019 * Strobing EDMA_RESET here causes a hard reset of the SATA transport,
b67a1064
ML		 3020 * link, and physical layers. It resets all SATA interface registers
3021 * (except for SATA_INTERFACE_CFG), and issues a COMRESET to the dev.
c9d39130 3022 */
8e7decdb 3023 writelfl(EDMA_RESET, port_mmio + EDMA_CMD_OFS);
b67a1064 3024 udelay(25); /* allow reset propagation */
c9d39130
JG		 3025 writelfl(0, port_mmio + EDMA_CMD_OFS);
3026
3027 hpriv->ops->phy_errata(hpriv, mmio, port_no);
3028
ee9ccdf7 3029 if (IS_GEN_I(hpriv))
c9d39130
JG		 3030 mdelay(1);
3031}
3032
e49856d8 3033static void mv_pmp_select(struct ata_port *ap, int pmp)
20f733e7 3034{
e49856d8
ML		 3035 if (sata_pmp_supported(ap)) {
3036 void __iomem *port_mmio = mv_ap_base(ap);
3037 u32 reg = readl(port_mmio + SATA_IFCTL_OFS);
3038 int old = reg & 0xf;
22374677 3039
e49856d8
ML		 3040 if (old != pmp) {
3041 reg = (reg & ~0xf) | pmp;
3042 writelfl(reg, port_mmio + SATA_IFCTL_OFS);
3043 }
22374677 3044 }
20f733e7
BR		 3045}
3046
e49856d8
ML		 3047static int mv_pmp_hardreset(struct ata_link *link, unsigned int *class,
3048 unsigned long deadline)
22374677 3049{
e49856d8
ML		 3050 mv_pmp_select(link->ap, sata_srst_pmp(link));
3051 return sata_std_hardreset(link, class, deadline);
3052}
bdd4ddde 3053
e49856d8
ML		 3054static int mv_softreset(struct ata_link *link, unsigned int *class,
3055 unsigned long deadline)
3056{
3057 mv_pmp_select(link->ap, sata_srst_pmp(link));
3058 return ata_sff_softreset(link, class, deadline);
22374677
JG		 3059}
3060
cc0680a5 3061static int mv_hardreset(struct ata_link *link, unsigned int *class,
bdd4ddde 3062 unsigned long deadline)
31961943 3063{
cc0680a5 3064 struct ata_port *ap = link->ap;
bdd4ddde 3065 struct mv_host_priv *hpriv = ap->host->private_data;
b562468c 3066 struct mv_port_priv *pp = ap->private_data;
f351b2d6 3067 void __iomem *mmio = hpriv->base;
0d8be5cb
ML		 3068 int rc, attempts = 0, extra = 0;
3069 u32 sstatus;
3070 bool online;
31961943 3071
e12bef50 3072 mv_reset_channel(hpriv, mmio, ap->port_no);
b562468c 3073 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
d16ab3f6
ML		 3074 pp->pp_flags &=
3075 ~(MV_PP_FLAG_FBS_EN | MV_PP_FLAG_NCQ_EN | MV_PP_FLAG_FAKE_ATA_BUSY);
bdd4ddde 3076
0d8be5cb
ML		 3077 /* Workaround for errata FEr SATA#10 (part 2) */
3078 do {
17c5aab5
ML		 3079 const unsigned long *timing =
3080 sata_ehc_deb_timing(&link->eh_context);
bdd4ddde 3081
17c5aab5
ML		 3082 rc = sata_link_hardreset(link, timing, deadline + extra,
3083 &online, NULL);
9dcffd99 3084 rc = online ? -EAGAIN : rc;
17c5aab5 3085 if (rc)
0d8be5cb 3086 return rc;
0d8be5cb
ML		 3087 sata_scr_read(link, SCR_STATUS, &sstatus);
3088 if (!IS_GEN_I(hpriv) && ++attempts >= 5 && sstatus == 0x121) {
3089 /* Force 1.5gb/s link speed and try again */
8e7decdb 3090 mv_setup_ifcfg(mv_ap_base(ap), 0);
0d8be5cb
ML		 3091 if (time_after(jiffies + HZ, deadline))
3092 extra = HZ; /* only extend it once, max */
3093 }
3094 } while (sstatus != 0x0 && sstatus != 0x113 && sstatus != 0x123);
08da1759 3095 mv_save_cached_regs(ap);
66e57a2c 3096 mv_edma_cfg(ap, 0, 0);
bdd4ddde 3097
17c5aab5 3098 return rc;
bdd4ddde
JG		 3099}
3100
bdd4ddde
JG		 3101static void mv_eh_freeze(struct ata_port *ap)
3102{
1cfd19ae 3103 mv_stop_edma(ap);
c4de573b 3104 mv_enable_port_irqs(ap, 0);
bdd4ddde
JG		 3105}
3106
3107static void mv_eh_thaw(struct ata_port *ap)
3108{
f351b2d6 3109 struct mv_host_priv *hpriv = ap->host->private_data;
c4de573b
ML		 3110 unsigned int port = ap->port_no;
3111 unsigned int hardport = mv_hardport_from_port(port);
1cfd19ae 3112 void __iomem *hc_mmio = mv_hc_base_from_port(hpriv->base, port);
bdd4ddde 3113 void __iomem *port_mmio = mv_ap_base(ap);
c4de573b 3114 u32 hc_irq_cause;
bdd4ddde 3115
bdd4ddde
JG		 3116 /* clear EDMA errors on this port */
3117 writel(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
3118
3119 /* clear pending irq events */
cae6edc3 3120 hc_irq_cause = ~((DEV_IRQ | DMA_IRQ) << hardport);
1cfd19ae 3121 writelfl(hc_irq_cause, hc_mmio + HC_IRQ_CAUSE_OFS);
bdd4ddde 3122
88e675e1 3123 mv_enable_port_irqs(ap, ERR_IRQ);
31961943
BR		 3124}
3125
05b308e1
BR		 3126/**
3127 * mv_port_init - Perform some early initialization on a single port.
3128 * @port: libata data structure storing shadow register addresses
3129 * @port_mmio: base address of the port
3130 *
3131 * Initialize shadow register mmio addresses, clear outstanding
3132 * interrupts on the port, and unmask interrupts for the future
3133 * start of the port.
3134 *
3135 * LOCKING:
3136 * Inherited from caller.
3137 */
31961943 3138static void mv_port_init(struct ata_ioports *port, void __iomem *port_mmio)
20f733e7 3139{
0d5ff566 3140 void __iomem *shd_base = port_mmio + SHD_BLK_OFS;
31961943
BR		 3141 unsigned serr_ofs;
3142
8b260248 3143 /* PIO related setup
31961943
BR		 3144 */
3145 port->data_addr = shd_base + (sizeof(u32) * ATA_REG_DATA);
8b260248 3146 port->error_addr =
31961943
BR		 3147 port->feature_addr = shd_base + (sizeof(u32) * ATA_REG_ERR);
3148 port->nsect_addr = shd_base + (sizeof(u32) * ATA_REG_NSECT);
3149 port->lbal_addr = shd_base + (sizeof(u32) * ATA_REG_LBAL);
3150 port->lbam_addr = shd_base + (sizeof(u32) * ATA_REG_LBAM);
3151 port->lbah_addr = shd_base + (sizeof(u32) * ATA_REG_LBAH);
3152 port->device_addr = shd_base + (sizeof(u32) * ATA_REG_DEVICE);
8b260248 3153 port->status_addr =
31961943
BR		 3154 port->command_addr = shd_base + (sizeof(u32) * ATA_REG_STATUS);
3155 /* special case: control/altstatus doesn't have ATA_REG_ address */
3156 port->altstatus_addr = port->ctl_addr = shd_base + SHD_CTL_AST_OFS;
3157
3158 /* unused: */
8d9db2d2 3159 port->cmd_addr = port->bmdma_addr = port->scr_addr = NULL;
20f733e7 3160
31961943
BR		 3161 /* Clear any currently outstanding port interrupt conditions */
3162 serr_ofs = mv_scr_offset(SCR_ERROR);
3163 writelfl(readl(port_mmio + serr_ofs), port_mmio + serr_ofs);
3164 writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE_OFS);
3165
646a4da5
ML		 3166 /* unmask all non-transient EDMA error interrupts */
3167 writelfl(~EDMA_ERR_IRQ_TRANSIENT, port_mmio + EDMA_ERR_IRQ_MASK_OFS);
20f733e7 3168
8b260248 3169 VPRINTK("EDMA cfg=0x%08x EDMA IRQ err cause/mask=0x%08x/0x%08x\n",
31961943
BR		 3170 readl(port_mmio + EDMA_CFG_OFS),
3171 readl(port_mmio + EDMA_ERR_IRQ_CAUSE_OFS),
3172 readl(port_mmio + EDMA_ERR_IRQ_MASK_OFS));
20f733e7
BR		 3173}
3174
616d4a98
ML		 3175static unsigned int mv_in_pcix_mode(struct ata_host *host)
3176{
3177 struct mv_host_priv *hpriv = host->private_data;
3178 void __iomem *mmio = hpriv->base;
3179 u32 reg;
3180
1f398472 3181 if (IS_SOC(hpriv) || !IS_PCIE(hpriv))
616d4a98
ML		 3182 return 0; /* not PCI-X capable */
3183 reg = readl(mmio + MV_PCI_MODE_OFS);
3184 if ((reg & MV_PCI_MODE_MASK) == 0)
3185 return 0; /* conventional PCI mode */
3186 return 1; /* chip is in PCI-X mode */
3187}
3188
3189static int mv_pci_cut_through_okay(struct ata_host *host)
3190{
3191 struct mv_host_priv *hpriv = host->private_data;
3192 void __iomem *mmio = hpriv->base;
3193 u32 reg;
3194
3195 if (!mv_in_pcix_mode(host)) {
3196 reg = readl(mmio + PCI_COMMAND_OFS);
3197 if (reg & PCI_COMMAND_MRDTRIG)
3198 return 0; /* not okay */
3199 }
3200 return 1; /* okay */
3201}
3202
4447d351 3203static int mv_chip_id(struct ata_host *host, unsigned int board_idx)
bca1c4eb 3204{
4447d351
TH		 3205 struct pci_dev *pdev = to_pci_dev(host->dev);
3206 struct mv_host_priv *hpriv = host->private_data;
bca1c4eb
JG		 3207 u32 hp_flags = hpriv->hp_flags;
3208
5796d1c4 3209 switch (board_idx) {
47c2b677
JG		 3210 case chip_5080:
3211 hpriv->ops = &mv5xxx_ops;
ee9ccdf7 3212 hp_flags |= MV_HP_GEN_I;
47c2b677 3213
44c10138 3214 switch (pdev->revision) {
47c2b677
JG		 3215 case 0x1:
3216 hp_flags |= MV_HP_ERRATA_50XXB0;
3217 break;
3218 case 0x3:
3219 hp_flags |= MV_HP_ERRATA_50XXB2;
3220 break;
3221 default:
3222 dev_printk(KERN_WARNING, &pdev->dev,
3223 "Applying 50XXB2 workarounds to unknown rev\n");
3224 hp_flags |= MV_HP_ERRATA_50XXB2;
3225 break;
3226 }
3227 break;
3228
bca1c4eb
JG		 3229 case chip_504x:
3230 case chip_508x:
47c2b677 3231 hpriv->ops = &mv5xxx_ops;
ee9ccdf7 3232 hp_flags |= MV_HP_GEN_I;
bca1c4eb 3233
44c10138 3234 switch (pdev->revision) {
47c2b677
JG		 3235 case 0x0:
3236 hp_flags |= MV_HP_ERRATA_50XXB0;
3237 break;
3238 case 0x3:
3239 hp_flags |= MV_HP_ERRATA_50XXB2;
3240 break;
3241 default:
3242 dev_printk(KERN_WARNING, &pdev->dev,
3243 "Applying B2 workarounds to unknown rev\n");
3244 hp_flags |= MV_HP_ERRATA_50XXB2;
3245 break;
bca1c4eb
JG		 3246 }
3247 break;
3248
3249 case chip_604x:
3250 case chip_608x:
47c2b677 3251 hpriv->ops = &mv6xxx_ops;
ee9ccdf7 3252 hp_flags |= MV_HP_GEN_II;
47c2b677 3253
44c10138 3254 switch (pdev->revision) {
47c2b677
JG		 3255 case 0x7:
3256 hp_flags |= MV_HP_ERRATA_60X1B2;
3257 break;
3258 case 0x9:
3259 hp_flags |= MV_HP_ERRATA_60X1C0;
bca1c4eb
JG		 3260 break;
3261 default:
3262 dev_printk(KERN_WARNING, &pdev->dev,
47c2b677
JG		 3263 "Applying B2 workarounds to unknown rev\n");
3264 hp_flags |= MV_HP_ERRATA_60X1B2;
bca1c4eb
JG		 3265 break;
3266 }
3267 break;
3268
e4e7b892 3269 case chip_7042:
616d4a98 3270 hp_flags |= MV_HP_PCIE | MV_HP_CUT_THROUGH;
306b30f7
ML		 3271 if (pdev->vendor == PCI_VENDOR_ID_TTI &&
3272 (pdev->device == 0x2300 || pdev->device == 0x2310))
3273 {
4e520033
ML		 3274 /*
3275 * Highpoint RocketRAID PCIe 23xx series cards:
3276 *
3277 * Unconfigured drives are treated as "Legacy"
3278 * by the BIOS, and it overwrites sector 8 with
3279 * a "Lgcy" metadata block prior to Linux boot.
3280 *
3281 * Configured drives (RAID or JBOD) leave sector 8
3282 * alone, but instead overwrite a high numbered
3283 * sector for the RAID metadata. This sector can
3284 * be determined exactly, by truncating the physical
3285 * drive capacity to a nice even GB value.
3286 *
3287 * RAID metadata is at: (dev->n_sectors & ~0xfffff)
3288 *
3289 * Warn the user, lest they think we're just buggy.
3290 */
3291 printk(KERN_WARNING DRV_NAME ": Highpoint RocketRAID"
3292 " BIOS CORRUPTS DATA on all attached drives,"
3293 " regardless of if/how they are configured."
3294 " BEWARE!\n");
3295 printk(KERN_WARNING DRV_NAME ": For data safety, do not"
3296 " use sectors 8-9 on \"Legacy\" drives,"
3297 " and avoid the final two gigabytes on"
3298 " all RocketRAID BIOS initialized drives.\n");
306b30f7 3299 }
8e7decdb 3300 /* drop through */
e4e7b892
JG		 3301 case chip_6042:
3302 hpriv->ops = &mv6xxx_ops;
e4e7b892 3303 hp_flags |= MV_HP_GEN_IIE;
616d4a98
ML		 3304 if (board_idx == chip_6042 && mv_pci_cut_through_okay(host))
3305 hp_flags |= MV_HP_CUT_THROUGH;
e4e7b892 3306
44c10138 3307 switch (pdev->revision) {
5cf73bfb 3308 case 0x2: /* Rev.B0: the first/only public release */
e4e7b892
JG		 3309 hp_flags |= MV_HP_ERRATA_60X1C0;
3310 break;
3311 default:
3312 dev_printk(KERN_WARNING, &pdev->dev,
3313 "Applying 60X1C0 workarounds to unknown rev\n");
3314 hp_flags |= MV_HP_ERRATA_60X1C0;
3315 break;
3316 }
3317 break;
f351b2d6
SB		 3318 case chip_soc:
3319 hpriv->ops = &mv_soc_ops;
eb3a55a9
SB		 3320 hp_flags |= MV_HP_FLAG_SOC | MV_HP_GEN_IIE |
3321 MV_HP_ERRATA_60X1C0;
f351b2d6 3322 break;
e4e7b892 3323
bca1c4eb 3324 default:
f351b2d6 3325 dev_printk(KERN_ERR, host->dev,
5796d1c4 3326 "BUG: invalid board index %u\n", board_idx);
bca1c4eb
JG		 3327 return 1;
3328 }
3329
3330 hpriv->hp_flags = hp_flags;
02a121da
ML		 3331 if (hp_flags & MV_HP_PCIE) {
3332 hpriv->irq_cause_ofs = PCIE_IRQ_CAUSE_OFS;
3333 hpriv->irq_mask_ofs = PCIE_IRQ_MASK_OFS;
3334 hpriv->unmask_all_irqs = PCIE_UNMASK_ALL_IRQS;
3335 } else {
3336 hpriv->irq_cause_ofs = PCI_IRQ_CAUSE_OFS;
3337 hpriv->irq_mask_ofs = PCI_IRQ_MASK_OFS;
3338 hpriv->unmask_all_irqs = PCI_UNMASK_ALL_IRQS;
3339 }
bca1c4eb
JG		 3340
3341 return 0;
3342}
3343
05b308e1 3344/**
47c2b677 3345 * mv_init_host - Perform some early initialization of the host.
4447d351
TH		 3346 * @host: ATA host to initialize
3347 * @board_idx: controller index
05b308e1
BR		 3348 *
3349 * If possible, do an early global reset of the host. Then do
3350 * our port init and clear/unmask all/relevant host interrupts.
3351 *
3352 * LOCKING:
3353 * Inherited from caller.
3354 */
4447d351 3355static int mv_init_host(struct ata_host *host, unsigned int board_idx)
20f733e7
BR		 3356{
3357 int rc = 0, n_hc, port, hc;
4447d351 3358 struct mv_host_priv *hpriv = host->private_data;
f351b2d6 3359 void __iomem *mmio = hpriv->base;
47c2b677 3360
4447d351 3361 rc = mv_chip_id(host, board_idx);
bca1c4eb 3362 if (rc)
352fab70 3363 goto done;
f351b2d6 3364
1f398472 3365 if (IS_SOC(hpriv)) {
7368f919
ML		 3366 hpriv->main_irq_cause_addr = mmio + SOC_HC_MAIN_IRQ_CAUSE_OFS;
3367 hpriv->main_irq_mask_addr = mmio + SOC_HC_MAIN_IRQ_MASK_OFS;
1f398472
ML		 3368 } else {
3369 hpriv->main_irq_cause_addr = mmio + PCI_HC_MAIN_IRQ_CAUSE_OFS;
3370 hpriv->main_irq_mask_addr = mmio + PCI_HC_MAIN_IRQ_MASK_OFS;
f351b2d6 3371 }
352fab70 3372
5d0fb2e7
TR		 3373 /* initialize shadow irq mask with register's value */
3374 hpriv->main_irq_mask = readl(hpriv->main_irq_mask_addr);
3375
352fab70 3376 /* global interrupt mask: 0 == mask everything */
c4de573b 3377 mv_set_main_irq_mask(host, ~0, 0);
bca1c4eb 3378
4447d351 3379 n_hc = mv_get_hc_count(host->ports[0]->flags);
bca1c4eb 3380
4447d351 3381 for (port = 0; port < host->n_ports; port++)
47c2b677 3382 hpriv->ops->read_preamp(hpriv, port, mmio);
20f733e7 3383
c9d39130 3384 rc = hpriv->ops->reset_hc(hpriv, mmio, n_hc);
47c2b677 3385 if (rc)
20f733e7 3386 goto done;
20f733e7 3387
522479fb 3388 hpriv->ops->reset_flash(hpriv, mmio);
7bb3c529 3389 hpriv->ops->reset_bus(host, mmio);
47c2b677 3390 hpriv->ops->enable_leds(hpriv, mmio);
20f733e7 3391
4447d351 3392 for (port = 0; port < host->n_ports; port++) {
cbcdd875 3393 struct ata_port *ap = host->ports[port];
2a47ce06 3394 void __iomem *port_mmio = mv_port_base(mmio, port);
cbcdd875
TH		 3395
3396 mv_port_init(&ap->ioaddr, port_mmio);
3397
7bb3c529 3398#ifdef CONFIG_PCI
1f398472 3399 if (!IS_SOC(hpriv)) {
f351b2d6
SB		 3400 unsigned int offset = port_mmio - mmio;
3401 ata_port_pbar_desc(ap, MV_PRIMARY_BAR, -1, "mmio");
3402 ata_port_pbar_desc(ap, MV_PRIMARY_BAR, offset, "port");
3403 }
7bb3c529 3404#endif
20f733e7
BR		 3405 }
3406
3407 for (hc = 0; hc < n_hc; hc++) {
31961943
BR		 3408 void __iomem *hc_mmio = mv_hc_base(mmio, hc);
3409
3410 VPRINTK("HC%i: HC config=0x%08x HC IRQ cause "
3411 "(before clear)=0x%08x\n", hc,
3412 readl(hc_mmio + HC_CFG_OFS),
3413 readl(hc_mmio + HC_IRQ_CAUSE_OFS));
3414
3415 /* Clear any currently outstanding hc interrupt conditions */
3416 writelfl(0, hc_mmio + HC_IRQ_CAUSE_OFS);
20f733e7
BR		 3417 }
3418
6be96ac1
ML		 3419 /* Clear any currently outstanding host interrupt conditions */
3420 writelfl(0, mmio + hpriv->irq_cause_ofs);
31961943 3421
6be96ac1
ML		 3422 /* and unmask interrupt generation for host regs */
3423 writelfl(hpriv->unmask_all_irqs, mmio + hpriv->irq_mask_ofs);
51de32d2 3424
6be96ac1
ML		 3425 /*
3426 * enable only global host interrupts for now.
3427 * The per-port interrupts get done later as ports are set up.
3428 */
3429 mv_set_main_irq_mask(host, 0, PCI_ERR);
f351b2d6
SB		 3430done:
3431 return rc;
3432}
fb621e2f 3433
fbf14e2f
BB		 3434static int mv_create_dma_pools(struct mv_host_priv *hpriv, struct device *dev)
3435{
3436 hpriv->crqb_pool = dmam_pool_create("crqb_q", dev, MV_CRQB_Q_SZ,
3437 MV_CRQB_Q_SZ, 0);
3438 if (!hpriv->crqb_pool)
3439 return -ENOMEM;
3440
3441 hpriv->crpb_pool = dmam_pool_create("crpb_q", dev, MV_CRPB_Q_SZ,
3442 MV_CRPB_Q_SZ, 0);
3443 if (!hpriv->crpb_pool)
3444 return -ENOMEM;
3445
3446 hpriv->sg_tbl_pool = dmam_pool_create("sg_tbl", dev, MV_SG_TBL_SZ,
3447 MV_SG_TBL_SZ, 0);
3448 if (!hpriv->sg_tbl_pool)
3449 return -ENOMEM;
3450
3451 return 0;
3452}
3453
15a32632
LB		 3454static void mv_conf_mbus_windows(struct mv_host_priv *hpriv,
3455 struct mbus_dram_target_info *dram)
3456{
3457 int i;
3458
3459 for (i = 0; i < 4; i++) {
3460 writel(0, hpriv->base + WINDOW_CTRL(i));
3461 writel(0, hpriv->base + WINDOW_BASE(i));
3462 }
3463
3464 for (i = 0; i < dram->num_cs; i++) {
3465 struct mbus_dram_window *cs = dram->cs + i;
3466
3467 writel(((cs->size - 1) & 0xffff0000) |
3468 (cs->mbus_attr << 8) |
3469 (dram->mbus_dram_target_id << 4) | 1,
3470 hpriv->base + WINDOW_CTRL(i));
3471 writel(cs->base, hpriv->base + WINDOW_BASE(i));
3472 }
3473}
3474
f351b2d6
SB		 3475/**
3476 * mv_platform_probe - handle a positive probe of an soc Marvell
3477 * host
3478 * @pdev: platform device found
3479 *
3480 * LOCKING:
3481 * Inherited from caller.
3482 */
3483static int mv_platform_probe(struct platform_device *pdev)
3484{
3485 static int printed_version;
3486 const struct mv_sata_platform_data *mv_platform_data;
3487 const struct ata_port_info *ppi[] =
3488 { &mv_port_info[chip_soc], NULL };
3489 struct ata_host *host;
3490 struct mv_host_priv *hpriv;
3491 struct resource *res;
3492 int n_ports, rc;
20f733e7 3493
f351b2d6
SB		 3494 if (!printed_version++)
3495 dev_printk(KERN_INFO, &pdev->dev, "version " DRV_VERSION "\n");
bca1c4eb 3496
f351b2d6
SB		 3497 /*
3498 * Simple resource validation ..
3499 */
3500 if (unlikely(pdev->num_resources != 2)) {
3501 dev_err(&pdev->dev, "invalid number of resources\n");
3502 return -EINVAL;
3503 }
3504
3505 /*
3506 * Get the register base first
3507 */
3508 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
3509 if (res == NULL)
3510 return -EINVAL;
3511
3512 /* allocate host */
3513 mv_platform_data = pdev->dev.platform_data;
3514 n_ports = mv_platform_data->n_ports;
3515
3516 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
3517 hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL);
3518
3519 if (!host || !hpriv)
3520 return -ENOMEM;
3521 host->private_data = hpriv;
3522 hpriv->n_ports = n_ports;
3523
3524 host->iomap = NULL;
f1cb0ea1
SB		 3525 hpriv->base = devm_ioremap(&pdev->dev, res->start,
3526 res->end - res->start + 1);
f351b2d6
SB		 3527 hpriv->base -= MV_SATAHC0_REG_BASE;
3528
15a32632
LB		 3529 /*
3530 * (Re-)program MBUS remapping windows if we are asked to.
3531 */
3532 if (mv_platform_data->dram != NULL)
3533 mv_conf_mbus_windows(hpriv, mv_platform_data->dram);
3534
fbf14e2f
BB		 3535 rc = mv_create_dma_pools(hpriv, &pdev->dev);
3536 if (rc)
3537 return rc;
3538
f351b2d6
SB		 3539 /* initialize adapter */
3540 rc = mv_init_host(host, chip_soc);
3541 if (rc)
3542 return rc;
3543
3544 dev_printk(KERN_INFO, &pdev->dev,
3545 "slots %u ports %d\n", (unsigned)MV_MAX_Q_DEPTH,
3546 host->n_ports);
3547
3548 return ata_host_activate(host, platform_get_irq(pdev, 0), mv_interrupt,
3549 IRQF_SHARED, &mv6_sht);
3550}
3551
3552/*
3553 *
3554 * mv_platform_remove - unplug a platform interface
3555 * @pdev: platform device
3556 *
3557 * A platform bus SATA device has been unplugged. Perform the needed
3558 * cleanup. Also called on module unload for any active devices.
3559 */
3560static int __devexit mv_platform_remove(struct platform_device *pdev)
3561{
3562 struct device *dev = &pdev->dev;
3563 struct ata_host *host = dev_get_drvdata(dev);
f351b2d6
SB		 3564
3565 ata_host_detach(host);
f351b2d6 3566 return 0;
20f733e7
BR		 3567}
3568
f351b2d6
SB		 3569static struct platform_driver mv_platform_driver = {
3570 .probe = mv_platform_probe,
3571 .remove = __devexit_p(mv_platform_remove),
3572 .driver = {
3573 .name = DRV_NAME,
3574 .owner = THIS_MODULE,
3575 },
3576};
3577
3578
7bb3c529 3579#ifdef CONFIG_PCI
f351b2d6
SB		 3580static int mv_pci_init_one(struct pci_dev *pdev,
3581 const struct pci_device_id *ent);
3582
7bb3c529
SB		 3583
3584static struct pci_driver mv_pci_driver = {
3585 .name = DRV_NAME,
3586 .id_table = mv_pci_tbl,
f351b2d6 3587 .probe = mv_pci_init_one,
7bb3c529
SB		 3588 .remove = ata_pci_remove_one,
3589};
3590
3591/*
3592 * module options
3593 */
3594static int msi; /* Use PCI msi; either zero (off, default) or non-zero */
3595
3596
3597/* move to PCI layer or libata core? */
3598static int pci_go_64(struct pci_dev *pdev)
3599{
3600 int rc;
3601
3602 if (!pci_set_dma_mask(pdev, DMA_64BIT_MASK)) {
3603 rc = pci_set_consistent_dma_mask(pdev, DMA_64BIT_MASK);
3604 if (rc) {
3605 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
3606 if (rc) {
3607 dev_printk(KERN_ERR, &pdev->dev,
3608 "64-bit DMA enable failed\n");
3609 return rc;
3610 }
3611 }
3612 } else {
3613 rc = pci_set_dma_mask(pdev, DMA_32BIT_MASK);
3614 if (rc) {
3615 dev_printk(KERN_ERR, &pdev->dev,
3616 "32-bit DMA enable failed\n");
3617 return rc;
3618 }
3619 rc = pci_set_consistent_dma_mask(pdev, DMA_32BIT_MASK);
3620 if (rc) {
3621 dev_printk(KERN_ERR, &pdev->dev,
3622 "32-bit consistent DMA enable failed\n");
3623 return rc;
3624 }
3625 }
3626
3627 return rc;
3628}
3629
05b308e1
BR		 3630/**
3631 * mv_print_info - Dump key info to kernel log for perusal.
4447d351 3632 * @host: ATA host to print info about
05b308e1
BR		 3633 *
3634 * FIXME: complete this.
3635 *
3636 * LOCKING:
3637 * Inherited from caller.
3638 */
4447d351 3639static void mv_print_info(struct ata_host *host)
31961943 3640{
4447d351
TH		 3641 struct pci_dev *pdev = to_pci_dev(host->dev);
3642 struct mv_host_priv *hpriv = host->private_data;
44c10138 3643 u8 scc;
c1e4fe71 3644 const char *scc_s, *gen;
31961943
BR		 3645
3646 /* Use this to determine the HW stepping of the chip so we know
3647 * what errata to workaround
3648 */
31961943
BR		 3649 pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &scc);
3650 if (scc == 0)
3651 scc_s = "SCSI";
3652 else if (scc == 0x01)
3653 scc_s = "RAID";
3654 else
c1e4fe71
JG		 3655 scc_s = "?";
3656
3657 if (IS_GEN_I(hpriv))
3658 gen = "I";
3659 else if (IS_GEN_II(hpriv))
3660 gen = "II";
3661 else if (IS_GEN_IIE(hpriv))
3662 gen = "IIE";
3663 else
3664 gen = "?";
31961943 3665
a9524a76 3666 dev_printk(KERN_INFO, &pdev->dev,
c1e4fe71
JG		 3667 "Gen-%s %u slots %u ports %s mode IRQ via %s\n",
3668 gen, (unsigned)MV_MAX_Q_DEPTH, host->n_ports,
31961943
BR		 3669 scc_s, (MV_HP_FLAG_MSI & hpriv->hp_flags) ? "MSI" : "INTx");
3670}
3671
05b308e1 3672/**
f351b2d6 3673 * mv_pci_init_one - handle a positive probe of a PCI Marvell host
05b308e1
BR		 3674 * @pdev: PCI device found
3675 * @ent: PCI device ID entry for the matched host
3676 *
3677 * LOCKING:
3678 * Inherited from caller.
3679 */
f351b2d6
SB		 3680static int mv_pci_init_one(struct pci_dev *pdev,
3681 const struct pci_device_id *ent)
20f733e7 3682{
2dcb407e 3683 static int printed_version;
20f733e7 3684 unsigned int board_idx = (unsigned int)ent->driver_data;
4447d351
TH		 3685 const struct ata_port_info *ppi[] = { &mv_port_info[board_idx], NULL };
3686 struct ata_host *host;
3687 struct mv_host_priv *hpriv;
3688 int n_ports, rc;
20f733e7 3689
a9524a76
JG		 3690 if (!printed_version++)
3691 dev_printk(KERN_INFO, &pdev->dev, "version " DRV_VERSION "\n");
20f733e7 3692
4447d351
TH		 3693 /* allocate host */
3694 n_ports = mv_get_hc_count(ppi[0]->flags) * MV_PORTS_PER_HC;
3695
3696 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
3697 hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL);
3698 if (!host || !hpriv)
3699 return -ENOMEM;
3700 host->private_data = hpriv;
f351b2d6 3701 hpriv->n_ports = n_ports;
4447d351
TH		 3702
3703 /* acquire resources */
24dc5f33
TH		 3704 rc = pcim_enable_device(pdev);
3705 if (rc)
20f733e7 3706 return rc;
20f733e7 3707
0d5ff566
TH		 3708 rc = pcim_iomap_regions(pdev, 1 << MV_PRIMARY_BAR, DRV_NAME);
3709 if (rc == -EBUSY)
24dc5f33 3710 pcim_pin_device(pdev);
0d5ff566 3711 if (rc)
24dc5f33 3712 return rc;
4447d351 3713 host->iomap = pcim_iomap_table(pdev);
f351b2d6 3714 hpriv->base = host->iomap[MV_PRIMARY_BAR];
20f733e7 3715
d88184fb
JG		 3716 rc = pci_go_64(pdev);
3717 if (rc)
3718 return rc;
3719
da2fa9ba
ML		 3720 rc = mv_create_dma_pools(hpriv, &pdev->dev);
3721 if (rc)
3722 return rc;
3723
20f733e7 3724 /* initialize adapter */
4447d351 3725 rc = mv_init_host(host, board_idx);
24dc5f33
TH		 3726 if (rc)
3727 return rc;
20f733e7 3728
6d3c30ef
ML		 3729 /* Enable message-switched interrupts, if requested */
3730 if (msi && pci_enable_msi(pdev) == 0)
3731 hpriv->hp_flags |= MV_HP_FLAG_MSI;
20f733e7 3732
31961943 3733 mv_dump_pci_cfg(pdev, 0x68);
4447d351 3734 mv_print_info(host);
20f733e7 3735
4447d351 3736 pci_set_master(pdev);
ea8b4db9 3737 pci_try_set_mwi(pdev);
4447d351 3738 return ata_host_activate(host, pdev->irq, mv_interrupt, IRQF_SHARED,
c5d3e45a 3739 IS_GEN_I(hpriv) ? &mv5_sht : &mv6_sht);
20f733e7 3740}
7bb3c529 3741#endif
20f733e7 3742
f351b2d6
SB		 3743static int mv_platform_probe(struct platform_device *pdev);
3744static int __devexit mv_platform_remove(struct platform_device *pdev);
3745
20f733e7
BR		 3746static int __init mv_init(void)
3747{
7bb3c529
SB		 3748 int rc = -ENODEV;
3749#ifdef CONFIG_PCI
3750 rc = pci_register_driver(&mv_pci_driver);
f351b2d6
SB		 3751 if (rc < 0)
3752 return rc;
3753#endif
3754 rc = platform_driver_register(&mv_platform_driver);
3755
3756#ifdef CONFIG_PCI
3757 if (rc < 0)
3758 pci_unregister_driver(&mv_pci_driver);
7bb3c529
SB		 3759#endif
3760 return rc;
20f733e7
BR		 3761}
3762
3763static void __exit mv_exit(void)
3764{
7bb3c529 3765#ifdef CONFIG_PCI
20f733e7 3766 pci_unregister_driver(&mv_pci_driver);
7bb3c529 3767#endif
f351b2d6 3768 platform_driver_unregister(&mv_platform_driver);
20f733e7
BR		 3769}
3770
3771MODULE_AUTHOR("Brett Russ");
3772MODULE_DESCRIPTION("SCSI low-level driver for Marvell SATA controllers");
3773MODULE_LICENSE("GPL");
3774MODULE_DEVICE_TABLE(pci, mv_pci_tbl);
3775MODULE_VERSION(DRV_VERSION);
17c5aab5 3776MODULE_ALIAS("platform:" DRV_NAME);
20f733e7 3777
7bb3c529 3778#ifdef CONFIG_PCI
ddef9bb3
JG		 3779module_param(msi, int, 0444);
3780MODULE_PARM_DESC(msi, "Enable use of PCI MSI (0=off, 1=on)");
7bb3c529 3781#endif
ddef9bb3 3782
20f733e7
BR		 3783module_init(mv_init);
3784module_exit(mv_exit);
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