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873e65bc | 1 | // SPDX-License-Identifier: GPL-2.0-only |
20f733e7 BR |
2 | /* |
3 | * sata_mv.c - Marvell SATA support | |
4 | * | |
40f21b11 | 5 | * Copyright 2008-2009: Marvell Corporation, all rights reserved. |
8b260248 | 6 | * Copyright 2005: EMC Corporation, all rights reserved. |
e2b1be56 | 7 | * Copyright 2005 Red Hat, Inc. All rights reserved. |
20f733e7 | 8 | * |
40f21b11 ML |
9 | * Originally written by Brett Russ. |
10 | * Extensive overhaul and enhancement by Mark Lord <mlord@pobox.com>. | |
11 | * | |
20f733e7 | 12 | * Please ALWAYS copy linux-ide@vger.kernel.org on emails. |
20f733e7 BR |
13 | */ |
14 | ||
4a05e209 | 15 | /* |
85afb934 ML |
16 | * sata_mv TODO list: |
17 | * | |
85afb934 ML |
18 | * --> Develop a low-power-consumption strategy, and implement it. |
19 | * | |
2b748a0a | 20 | * --> Add sysfs attributes for per-chip / per-HC IRQ coalescing thresholds. |
85afb934 ML |
21 | * |
22 | * --> [Experiment, Marvell value added] Is it possible to use target | |
23 | * mode to cross-connect two Linux boxes with Marvell cards? If so, | |
24 | * creating LibATA target mode support would be very interesting. | |
25 | * | |
26 | * Target mode, for those without docs, is the ability to directly | |
27 | * connect two SATA ports. | |
28 | */ | |
4a05e209 | 29 | |
65ad7fef ML |
30 | /* |
31 | * 80x1-B2 errata PCI#11: | |
32 | * | |
33 | * Users of the 6041/6081 Rev.B2 chips (current is C0) | |
34 | * should be careful to insert those cards only onto PCI-X bus #0, | |
35 | * and only in device slots 0..7, not higher. The chips may not | |
36 | * work correctly otherwise (note: this is a pretty rare condition). | |
37 | */ | |
38 | ||
20f733e7 BR |
39 | #include <linux/kernel.h> |
40 | #include <linux/module.h> | |
41 | #include <linux/pci.h> | |
42 | #include <linux/init.h> | |
43 | #include <linux/blkdev.h> | |
44 | #include <linux/delay.h> | |
45 | #include <linux/interrupt.h> | |
8d8b6004 | 46 | #include <linux/dmapool.h> |
20f733e7 | 47 | #include <linux/dma-mapping.h> |
a9524a76 | 48 | #include <linux/device.h> |
c77a2f4e | 49 | #include <linux/clk.h> |
b7db4f2e | 50 | #include <linux/phy/phy.h> |
f351b2d6 SB |
51 | #include <linux/platform_device.h> |
52 | #include <linux/ata_platform.h> | |
15a32632 | 53 | #include <linux/mbus.h> |
c46938cc | 54 | #include <linux/bitops.h> |
5a0e3ad6 | 55 | #include <linux/gfp.h> |
97b414e1 AL |
56 | #include <linux/of.h> |
57 | #include <linux/of_irq.h> | |
20f733e7 | 58 | #include <scsi/scsi_host.h> |
193515d5 | 59 | #include <scsi/scsi_cmnd.h> |
6c08772e | 60 | #include <scsi/scsi_device.h> |
20f733e7 | 61 | #include <linux/libata.h> |
20f733e7 BR |
62 | |
63 | #define DRV_NAME "sata_mv" | |
cae5a29d | 64 | #define DRV_VERSION "1.28" |
20f733e7 | 65 | |
40f21b11 ML |
66 | /* |
67 | * module options | |
68 | */ | |
69 | ||
40f21b11 | 70 | #ifdef CONFIG_PCI |
13b74085 | 71 | static int msi; |
40f21b11 ML |
72 | module_param(msi, int, S_IRUGO); |
73 | MODULE_PARM_DESC(msi, "Enable use of PCI MSI (0=off, 1=on)"); | |
74 | #endif | |
75 | ||
2b748a0a ML |
76 | static int irq_coalescing_io_count; |
77 | module_param(irq_coalescing_io_count, int, S_IRUGO); | |
78 | MODULE_PARM_DESC(irq_coalescing_io_count, | |
79 | "IRQ coalescing I/O count threshold (0..255)"); | |
80 | ||
81 | static int irq_coalescing_usecs; | |
82 | module_param(irq_coalescing_usecs, int, S_IRUGO); | |
83 | MODULE_PARM_DESC(irq_coalescing_usecs, | |
84 | "IRQ coalescing time threshold in usecs"); | |
85 | ||
20f733e7 BR |
86 | enum { |
87 | /* BAR's are enumerated in terms of pci_resource_start() terms */ | |
88 | MV_PRIMARY_BAR = 0, /* offset 0x10: memory space */ | |
89 | MV_IO_BAR = 2, /* offset 0x18: IO space */ | |
90 | MV_MISC_BAR = 3, /* offset 0x1c: FLASH, NVRAM, SRAM */ | |
91 | ||
92 | MV_MAJOR_REG_AREA_SZ = 0x10000, /* 64KB */ | |
93 | MV_MINOR_REG_AREA_SZ = 0x2000, /* 8KB */ | |
94 | ||
2b748a0a ML |
95 | /* For use with both IRQ coalescing methods ("all ports" or "per-HC" */ |
96 | COAL_CLOCKS_PER_USEC = 150, /* for calculating COAL_TIMEs */ | |
97 | MAX_COAL_TIME_THRESHOLD = ((1 << 24) - 1), /* internal clocks count */ | |
98 | MAX_COAL_IO_COUNT = 255, /* completed I/O count */ | |
99 | ||
20f733e7 | 100 | MV_PCI_REG_BASE = 0, |
615ab953 | 101 | |
2b748a0a ML |
102 | /* |
103 | * Per-chip ("all ports") interrupt coalescing feature. | |
104 | * This is only for GEN_II / GEN_IIE hardware. | |
105 | * | |
106 | * Coalescing defers the interrupt until either the IO_THRESHOLD | |
107 | * (count of completed I/Os) is met, or the TIME_THRESHOLD is met. | |
108 | */ | |
cae5a29d ML |
109 | COAL_REG_BASE = 0x18000, |
110 | IRQ_COAL_CAUSE = (COAL_REG_BASE + 0x08), | |
2b748a0a ML |
111 | ALL_PORTS_COAL_IRQ = (1 << 4), /* all ports irq event */ |
112 | ||
cae5a29d ML |
113 | IRQ_COAL_IO_THRESHOLD = (COAL_REG_BASE + 0xcc), |
114 | IRQ_COAL_TIME_THRESHOLD = (COAL_REG_BASE + 0xd0), | |
2b748a0a ML |
115 | |
116 | /* | |
117 | * Registers for the (unused here) transaction coalescing feature: | |
118 | */ | |
cae5a29d ML |
119 | TRAN_COAL_CAUSE_LO = (COAL_REG_BASE + 0x88), |
120 | TRAN_COAL_CAUSE_HI = (COAL_REG_BASE + 0x8c), | |
2b748a0a | 121 | |
cae5a29d ML |
122 | SATAHC0_REG_BASE = 0x20000, |
123 | FLASH_CTL = 0x1046c, | |
124 | GPIO_PORT_CTL = 0x104f0, | |
125 | RESET_CFG = 0x180d8, | |
20f733e7 BR |
126 | |
127 | MV_PCI_REG_SZ = MV_MAJOR_REG_AREA_SZ, | |
128 | MV_SATAHC_REG_SZ = MV_MAJOR_REG_AREA_SZ, | |
129 | MV_SATAHC_ARBTR_REG_SZ = MV_MINOR_REG_AREA_SZ, /* arbiter */ | |
130 | MV_PORT_REG_SZ = MV_MINOR_REG_AREA_SZ, | |
131 | ||
31961943 BR |
132 | MV_MAX_Q_DEPTH = 32, |
133 | MV_MAX_Q_DEPTH_MASK = MV_MAX_Q_DEPTH - 1, | |
134 | ||
135 | /* CRQB needs alignment on a 1KB boundary. Size == 1KB | |
136 | * CRPB needs alignment on a 256B boundary. Size == 256B | |
31961943 BR |
137 | * ePRD (SG) entries need alignment on a 16B boundary. Size == 16B |
138 | */ | |
139 | MV_CRQB_Q_SZ = (32 * MV_MAX_Q_DEPTH), | |
140 | MV_CRPB_Q_SZ = (8 * MV_MAX_Q_DEPTH), | |
da2fa9ba | 141 | MV_MAX_SG_CT = 256, |
31961943 | 142 | MV_SG_TBL_SZ = (16 * MV_MAX_SG_CT), |
31961943 | 143 | |
352fab70 | 144 | /* Determine hc from 0-7 port: hc = port >> MV_PORT_HC_SHIFT */ |
20f733e7 | 145 | MV_PORT_HC_SHIFT = 2, |
352fab70 ML |
146 | MV_PORTS_PER_HC = (1 << MV_PORT_HC_SHIFT), /* 4 */ |
147 | /* Determine hc port from 0-7 port: hardport = port & MV_PORT_MASK */ | |
148 | MV_PORT_MASK = (MV_PORTS_PER_HC - 1), /* 3 */ | |
20f733e7 BR |
149 | |
150 | /* Host Flags */ | |
151 | MV_FLAG_DUAL_HC = (1 << 30), /* two SATA Host Controllers */ | |
7bb3c529 | 152 | |
9cbe056f | 153 | MV_COMMON_FLAGS = ATA_FLAG_SATA | ATA_FLAG_PIO_POLLING, |
ad3aef51 | 154 | |
91b1a84c | 155 | MV_GEN_I_FLAGS = MV_COMMON_FLAGS | ATA_FLAG_NO_ATAPI, |
20f733e7 | 156 | |
40f21b11 ML |
157 | MV_GEN_II_FLAGS = MV_COMMON_FLAGS | ATA_FLAG_NCQ | |
158 | ATA_FLAG_PMP | ATA_FLAG_ACPI_SATA, | |
91b1a84c ML |
159 | |
160 | MV_GEN_IIE_FLAGS = MV_GEN_II_FLAGS | ATA_FLAG_AN, | |
ad3aef51 | 161 | |
31961943 BR |
162 | CRQB_FLAG_READ = (1 << 0), |
163 | CRQB_TAG_SHIFT = 1, | |
c5d3e45a | 164 | CRQB_IOID_SHIFT = 6, /* CRQB Gen-II/IIE IO Id shift */ |
e12bef50 | 165 | CRQB_PMP_SHIFT = 12, /* CRQB Gen-II/IIE PMP shift */ |
c5d3e45a | 166 | CRQB_HOSTQ_SHIFT = 17, /* CRQB Gen-II/IIE HostQueTag shift */ |
31961943 BR |
167 | CRQB_CMD_ADDR_SHIFT = 8, |
168 | CRQB_CMD_CS = (0x2 << 11), | |
169 | CRQB_CMD_LAST = (1 << 15), | |
170 | ||
171 | CRPB_FLAG_STATUS_SHIFT = 8, | |
c5d3e45a JG |
172 | CRPB_IOID_SHIFT_6 = 5, /* CRPB Gen-II IO Id shift */ |
173 | CRPB_IOID_SHIFT_7 = 7, /* CRPB Gen-IIE IO Id shift */ | |
31961943 BR |
174 | |
175 | EPRD_FLAG_END_OF_TBL = (1 << 31), | |
176 | ||
20f733e7 BR |
177 | /* PCI interface registers */ |
178 | ||
cae5a29d ML |
179 | MV_PCI_COMMAND = 0xc00, |
180 | MV_PCI_COMMAND_MWRCOM = (1 << 4), /* PCI Master Write Combining */ | |
181 | MV_PCI_COMMAND_MRDTRIG = (1 << 7), /* PCI Master Read Trigger */ | |
31961943 | 182 | |
cae5a29d | 183 | PCI_MAIN_CMD_STS = 0xd30, |
20f733e7 BR |
184 | STOP_PCI_MASTER = (1 << 2), |
185 | PCI_MASTER_EMPTY = (1 << 3), | |
186 | GLOB_SFT_RST = (1 << 4), | |
187 | ||
cae5a29d | 188 | MV_PCI_MODE = 0xd00, |
8e7decdb ML |
189 | MV_PCI_MODE_MASK = 0x30, |
190 | ||
522479fb JG |
191 | MV_PCI_EXP_ROM_BAR_CTL = 0xd2c, |
192 | MV_PCI_DISC_TIMER = 0xd04, | |
193 | MV_PCI_MSI_TRIGGER = 0xc38, | |
194 | MV_PCI_SERR_MASK = 0xc28, | |
cae5a29d | 195 | MV_PCI_XBAR_TMOUT = 0x1d04, |
522479fb JG |
196 | MV_PCI_ERR_LOW_ADDRESS = 0x1d40, |
197 | MV_PCI_ERR_HIGH_ADDRESS = 0x1d44, | |
198 | MV_PCI_ERR_ATTRIBUTE = 0x1d48, | |
199 | MV_PCI_ERR_COMMAND = 0x1d50, | |
200 | ||
cae5a29d ML |
201 | PCI_IRQ_CAUSE = 0x1d58, |
202 | PCI_IRQ_MASK = 0x1d5c, | |
20f733e7 BR |
203 | PCI_UNMASK_ALL_IRQS = 0x7fffff, /* bits 22-0 */ |
204 | ||
cae5a29d ML |
205 | PCIE_IRQ_CAUSE = 0x1900, |
206 | PCIE_IRQ_MASK = 0x1910, | |
646a4da5 | 207 | PCIE_UNMASK_ALL_IRQS = 0x40a, /* assorted bits */ |
02a121da | 208 | |
7368f919 | 209 | /* Host Controller Main Interrupt Cause/Mask registers (1 per-chip) */ |
cae5a29d ML |
210 | PCI_HC_MAIN_IRQ_CAUSE = 0x1d60, |
211 | PCI_HC_MAIN_IRQ_MASK = 0x1d64, | |
212 | SOC_HC_MAIN_IRQ_CAUSE = 0x20020, | |
213 | SOC_HC_MAIN_IRQ_MASK = 0x20024, | |
40f21b11 ML |
214 | ERR_IRQ = (1 << 0), /* shift by (2 * port #) */ |
215 | DONE_IRQ = (1 << 1), /* shift by (2 * port #) */ | |
20f733e7 BR |
216 | HC0_IRQ_PEND = 0x1ff, /* bits 0-8 = HC0's ports */ |
217 | HC_SHIFT = 9, /* bits 9-17 = HC1's ports */ | |
2b748a0a ML |
218 | DONE_IRQ_0_3 = 0x000000aa, /* DONE_IRQ ports 0,1,2,3 */ |
219 | DONE_IRQ_4_7 = (DONE_IRQ_0_3 << HC_SHIFT), /* 4,5,6,7 */ | |
20f733e7 | 220 | PCI_ERR = (1 << 18), |
40f21b11 ML |
221 | TRAN_COAL_LO_DONE = (1 << 19), /* transaction coalescing */ |
222 | TRAN_COAL_HI_DONE = (1 << 20), /* transaction coalescing */ | |
223 | PORTS_0_3_COAL_DONE = (1 << 8), /* HC0 IRQ coalescing */ | |
224 | PORTS_4_7_COAL_DONE = (1 << 17), /* HC1 IRQ coalescing */ | |
225 | ALL_PORTS_COAL_DONE = (1 << 21), /* GEN_II(E) IRQ coalescing */ | |
20f733e7 BR |
226 | GPIO_INT = (1 << 22), |
227 | SELF_INT = (1 << 23), | |
228 | TWSI_INT = (1 << 24), | |
229 | HC_MAIN_RSVD = (0x7f << 25), /* bits 31-25 */ | |
fb621e2f | 230 | HC_MAIN_RSVD_5 = (0x1fff << 19), /* bits 31-19 */ |
e12bef50 | 231 | HC_MAIN_RSVD_SOC = (0x3fffffb << 6), /* bits 31-9, 7-6 */ |
20f733e7 BR |
232 | |
233 | /* SATAHC registers */ | |
cae5a29d | 234 | HC_CFG = 0x00, |
20f733e7 | 235 | |
cae5a29d | 236 | HC_IRQ_CAUSE = 0x14, |
352fab70 ML |
237 | DMA_IRQ = (1 << 0), /* shift by port # */ |
238 | HC_COAL_IRQ = (1 << 4), /* IRQ coalescing */ | |
20f733e7 BR |
239 | DEV_IRQ = (1 << 8), /* shift by port # */ |
240 | ||
2b748a0a ML |
241 | /* |
242 | * Per-HC (Host-Controller) interrupt coalescing feature. | |
243 | * This is present on all chip generations. | |
244 | * | |
245 | * Coalescing defers the interrupt until either the IO_THRESHOLD | |
246 | * (count of completed I/Os) is met, or the TIME_THRESHOLD is met. | |
247 | */ | |
cae5a29d ML |
248 | HC_IRQ_COAL_IO_THRESHOLD = 0x000c, |
249 | HC_IRQ_COAL_TIME_THRESHOLD = 0x0010, | |
2b748a0a | 250 | |
cae5a29d | 251 | SOC_LED_CTRL = 0x2c, |
000b344f ML |
252 | SOC_LED_CTRL_BLINK = (1 << 0), /* Active LED blink */ |
253 | SOC_LED_CTRL_ACT_PRESENCE = (1 << 2), /* Multiplex dev presence */ | |
254 | /* with dev activity LED */ | |
255 | ||
20f733e7 | 256 | /* Shadow block registers */ |
cae5a29d ML |
257 | SHD_BLK = 0x100, |
258 | SHD_CTL_AST = 0x20, /* ofs from SHD_BLK */ | |
20f733e7 BR |
259 | |
260 | /* SATA registers */ | |
cae5a29d ML |
261 | SATA_STATUS = 0x300, /* ctrl, err regs follow status */ |
262 | SATA_ACTIVE = 0x350, | |
263 | FIS_IRQ_CAUSE = 0x364, | |
264 | FIS_IRQ_CAUSE_AN = (1 << 9), /* async notification */ | |
17c5aab5 | 265 | |
cae5a29d | 266 | LTMODE = 0x30c, /* requires read-after-write */ |
17c5aab5 ML |
267 | LTMODE_BIT8 = (1 << 8), /* unknown, but necessary */ |
268 | ||
cae5a29d | 269 | PHY_MODE2 = 0x330, |
47c2b677 | 270 | PHY_MODE3 = 0x310, |
cae5a29d ML |
271 | |
272 | PHY_MODE4 = 0x314, /* requires read-after-write */ | |
ba069e37 ML |
273 | PHY_MODE4_CFG_MASK = 0x00000003, /* phy internal config field */ |
274 | PHY_MODE4_CFG_VALUE = 0x00000001, /* phy internal config field */ | |
275 | PHY_MODE4_RSVD_ZEROS = 0x5de3fffa, /* Gen2e always write zeros */ | |
276 | PHY_MODE4_RSVD_ONES = 0x00000005, /* Gen2e always write ones */ | |
277 | ||
cae5a29d ML |
278 | SATA_IFCTL = 0x344, |
279 | SATA_TESTCTL = 0x348, | |
280 | SATA_IFSTAT = 0x34c, | |
281 | VENDOR_UNIQUE_FIS = 0x35c, | |
17c5aab5 | 282 | |
cae5a29d | 283 | FISCFG = 0x360, |
8e7decdb ML |
284 | FISCFG_WAIT_DEV_ERR = (1 << 8), /* wait for host on DevErr */ |
285 | FISCFG_SINGLE_SYNC = (1 << 16), /* SYNC on DMA activation */ | |
17c5aab5 | 286 | |
29b7e43c MM |
287 | PHY_MODE9_GEN2 = 0x398, |
288 | PHY_MODE9_GEN1 = 0x39c, | |
289 | PHYCFG_OFS = 0x3a0, /* only in 65n devices */ | |
290 | ||
c9d39130 | 291 | MV5_PHY_MODE = 0x74, |
cae5a29d ML |
292 | MV5_LTMODE = 0x30, |
293 | MV5_PHY_CTL = 0x0C, | |
294 | SATA_IFCFG = 0x050, | |
9013d64e | 295 | LP_PHY_CTL = 0x058, |
3661aa99 TP |
296 | LP_PHY_CTL_PIN_PU_PLL = (1 << 0), |
297 | LP_PHY_CTL_PIN_PU_RX = (1 << 1), | |
298 | LP_PHY_CTL_PIN_PU_TX = (1 << 2), | |
299 | LP_PHY_CTL_GEN_TX_3G = (1 << 5), | |
300 | LP_PHY_CTL_GEN_RX_3G = (1 << 9), | |
bca1c4eb JG |
301 | |
302 | MV_M2_PREAMP_MASK = 0x7e0, | |
20f733e7 BR |
303 | |
304 | /* Port registers */ | |
cae5a29d | 305 | EDMA_CFG = 0, |
0c58912e ML |
306 | EDMA_CFG_Q_DEPTH = 0x1f, /* max device queue depth */ |
307 | EDMA_CFG_NCQ = (1 << 5), /* for R/W FPDMA queued */ | |
308 | EDMA_CFG_NCQ_GO_ON_ERR = (1 << 14), /* continue on error */ | |
309 | EDMA_CFG_RD_BRST_EXT = (1 << 11), /* read burst 512B */ | |
310 | EDMA_CFG_WR_BUFF_LEN = (1 << 13), /* write buffer 512B */ | |
e12bef50 ML |
311 | EDMA_CFG_EDMA_FBS = (1 << 16), /* EDMA FIS-Based Switching */ |
312 | EDMA_CFG_FBS = (1 << 26), /* FIS-Based Switching */ | |
20f733e7 | 313 | |
cae5a29d ML |
314 | EDMA_ERR_IRQ_CAUSE = 0x8, |
315 | EDMA_ERR_IRQ_MASK = 0xc, | |
6c1153e0 JG |
316 | EDMA_ERR_D_PAR = (1 << 0), /* UDMA data parity err */ |
317 | EDMA_ERR_PRD_PAR = (1 << 1), /* UDMA PRD parity err */ | |
318 | EDMA_ERR_DEV = (1 << 2), /* device error */ | |
319 | EDMA_ERR_DEV_DCON = (1 << 3), /* device disconnect */ | |
320 | EDMA_ERR_DEV_CON = (1 << 4), /* device connected */ | |
321 | EDMA_ERR_SERR = (1 << 5), /* SError bits [WBDST] raised */ | |
c5d3e45a JG |
322 | EDMA_ERR_SELF_DIS = (1 << 7), /* Gen II/IIE self-disable */ |
323 | EDMA_ERR_SELF_DIS_5 = (1 << 8), /* Gen I self-disable */ | |
6c1153e0 | 324 | EDMA_ERR_BIST_ASYNC = (1 << 8), /* BIST FIS or Async Notify */ |
c5d3e45a | 325 | EDMA_ERR_TRANS_IRQ_7 = (1 << 8), /* Gen IIE transprt layer irq */ |
6c1153e0 JG |
326 | EDMA_ERR_CRQB_PAR = (1 << 9), /* CRQB parity error */ |
327 | EDMA_ERR_CRPB_PAR = (1 << 10), /* CRPB parity error */ | |
328 | EDMA_ERR_INTRL_PAR = (1 << 11), /* internal parity error */ | |
329 | EDMA_ERR_IORDY = (1 << 12), /* IORdy timeout */ | |
646a4da5 | 330 | |
6c1153e0 | 331 | EDMA_ERR_LNK_CTRL_RX = (0xf << 13), /* link ctrl rx error */ |
646a4da5 ML |
332 | EDMA_ERR_LNK_CTRL_RX_0 = (1 << 13), /* transient: CRC err */ |
333 | EDMA_ERR_LNK_CTRL_RX_1 = (1 << 14), /* transient: FIFO err */ | |
334 | EDMA_ERR_LNK_CTRL_RX_2 = (1 << 15), /* fatal: caught SYNC */ | |
335 | EDMA_ERR_LNK_CTRL_RX_3 = (1 << 16), /* transient: FIS rx err */ | |
336 | ||
6c1153e0 | 337 | EDMA_ERR_LNK_DATA_RX = (0xf << 17), /* link data rx error */ |
646a4da5 | 338 | |
6c1153e0 | 339 | EDMA_ERR_LNK_CTRL_TX = (0x1f << 21), /* link ctrl tx error */ |
646a4da5 ML |
340 | EDMA_ERR_LNK_CTRL_TX_0 = (1 << 21), /* transient: CRC err */ |
341 | EDMA_ERR_LNK_CTRL_TX_1 = (1 << 22), /* transient: FIFO err */ | |
342 | EDMA_ERR_LNK_CTRL_TX_2 = (1 << 23), /* transient: caught SYNC */ | |
343 | EDMA_ERR_LNK_CTRL_TX_3 = (1 << 24), /* transient: caught DMAT */ | |
344 | EDMA_ERR_LNK_CTRL_TX_4 = (1 << 25), /* transient: FIS collision */ | |
345 | ||
6c1153e0 | 346 | EDMA_ERR_LNK_DATA_TX = (0x1f << 26), /* link data tx error */ |
646a4da5 | 347 | |
6c1153e0 | 348 | EDMA_ERR_TRANS_PROTO = (1 << 31), /* transport protocol error */ |
c5d3e45a JG |
349 | EDMA_ERR_OVERRUN_5 = (1 << 5), |
350 | EDMA_ERR_UNDERRUN_5 = (1 << 6), | |
646a4da5 ML |
351 | |
352 | EDMA_ERR_IRQ_TRANSIENT = EDMA_ERR_LNK_CTRL_RX_0 | | |
353 | EDMA_ERR_LNK_CTRL_RX_1 | | |
354 | EDMA_ERR_LNK_CTRL_RX_3 | | |
85afb934 | 355 | EDMA_ERR_LNK_CTRL_TX, |
646a4da5 | 356 | |
bdd4ddde JG |
357 | EDMA_EH_FREEZE = EDMA_ERR_D_PAR | |
358 | EDMA_ERR_PRD_PAR | | |
359 | EDMA_ERR_DEV_DCON | | |
360 | EDMA_ERR_DEV_CON | | |
361 | EDMA_ERR_SERR | | |
362 | EDMA_ERR_SELF_DIS | | |
6c1153e0 | 363 | EDMA_ERR_CRQB_PAR | |
bdd4ddde JG |
364 | EDMA_ERR_CRPB_PAR | |
365 | EDMA_ERR_INTRL_PAR | | |
366 | EDMA_ERR_IORDY | | |
367 | EDMA_ERR_LNK_CTRL_RX_2 | | |
368 | EDMA_ERR_LNK_DATA_RX | | |
369 | EDMA_ERR_LNK_DATA_TX | | |
370 | EDMA_ERR_TRANS_PROTO, | |
e12bef50 | 371 | |
bdd4ddde JG |
372 | EDMA_EH_FREEZE_5 = EDMA_ERR_D_PAR | |
373 | EDMA_ERR_PRD_PAR | | |
374 | EDMA_ERR_DEV_DCON | | |
375 | EDMA_ERR_DEV_CON | | |
376 | EDMA_ERR_OVERRUN_5 | | |
377 | EDMA_ERR_UNDERRUN_5 | | |
378 | EDMA_ERR_SELF_DIS_5 | | |
6c1153e0 | 379 | EDMA_ERR_CRQB_PAR | |
bdd4ddde JG |
380 | EDMA_ERR_CRPB_PAR | |
381 | EDMA_ERR_INTRL_PAR | | |
382 | EDMA_ERR_IORDY, | |
20f733e7 | 383 | |
cae5a29d ML |
384 | EDMA_REQ_Q_BASE_HI = 0x10, |
385 | EDMA_REQ_Q_IN_PTR = 0x14, /* also contains BASE_LO */ | |
31961943 | 386 | |
cae5a29d | 387 | EDMA_REQ_Q_OUT_PTR = 0x18, |
31961943 BR |
388 | EDMA_REQ_Q_PTR_SHIFT = 5, |
389 | ||
cae5a29d ML |
390 | EDMA_RSP_Q_BASE_HI = 0x1c, |
391 | EDMA_RSP_Q_IN_PTR = 0x20, | |
392 | EDMA_RSP_Q_OUT_PTR = 0x24, /* also contains BASE_LO */ | |
31961943 BR |
393 | EDMA_RSP_Q_PTR_SHIFT = 3, |
394 | ||
cae5a29d | 395 | EDMA_CMD = 0x28, /* EDMA command register */ |
0ea9e179 JG |
396 | EDMA_EN = (1 << 0), /* enable EDMA */ |
397 | EDMA_DS = (1 << 1), /* disable EDMA; self-negated */ | |
8e7decdb ML |
398 | EDMA_RESET = (1 << 2), /* reset eng/trans/link/phy */ |
399 | ||
cae5a29d | 400 | EDMA_STATUS = 0x30, /* EDMA engine status */ |
8e7decdb ML |
401 | EDMA_STATUS_CACHE_EMPTY = (1 << 6), /* GenIIe command cache empty */ |
402 | EDMA_STATUS_IDLE = (1 << 7), /* GenIIe EDMA enabled/idle */ | |
20f733e7 | 403 | |
cae5a29d ML |
404 | EDMA_IORDY_TMOUT = 0x34, |
405 | EDMA_ARB_CFG = 0x38, | |
8e7decdb | 406 | |
cae5a29d ML |
407 | EDMA_HALTCOND = 0x60, /* GenIIe halt conditions */ |
408 | EDMA_UNKNOWN_RSVD = 0x6C, /* GenIIe unknown/reserved */ | |
da14265e | 409 | |
cae5a29d ML |
410 | BMDMA_CMD = 0x224, /* bmdma command register */ |
411 | BMDMA_STATUS = 0x228, /* bmdma status register */ | |
412 | BMDMA_PRD_LOW = 0x22c, /* bmdma PRD addr 31:0 */ | |
413 | BMDMA_PRD_HIGH = 0x230, /* bmdma PRD addr 63:32 */ | |
da14265e | 414 | |
31961943 BR |
415 | /* Host private flags (hp_flags) */ |
416 | MV_HP_FLAG_MSI = (1 << 0), | |
47c2b677 JG |
417 | MV_HP_ERRATA_50XXB0 = (1 << 1), |
418 | MV_HP_ERRATA_50XXB2 = (1 << 2), | |
419 | MV_HP_ERRATA_60X1B2 = (1 << 3), | |
420 | MV_HP_ERRATA_60X1C0 = (1 << 4), | |
0ea9e179 JG |
421 | MV_HP_GEN_I = (1 << 6), /* Generation I: 50xx */ |
422 | MV_HP_GEN_II = (1 << 7), /* Generation II: 60xx */ | |
423 | MV_HP_GEN_IIE = (1 << 8), /* Generation IIE: 6042/7042 */ | |
02a121da | 424 | MV_HP_PCIE = (1 << 9), /* PCIe bus/regs: 7042 */ |
616d4a98 | 425 | MV_HP_CUT_THROUGH = (1 << 10), /* can use EDMA cut-through */ |
1f398472 | 426 | MV_HP_FLAG_SOC = (1 << 11), /* SystemOnChip, no PCI */ |
000b344f | 427 | MV_HP_QUIRK_LED_BLINK_EN = (1 << 12), /* is led blinking enabled? */ |
9013d64e | 428 | MV_HP_FIX_LP_PHY_CTL = (1 << 13), /* fix speed in LP_PHY_CTL ? */ |
20f733e7 | 429 | |
31961943 | 430 | /* Port private flags (pp_flags) */ |
0ea9e179 | 431 | MV_PP_FLAG_EDMA_EN = (1 << 0), /* is EDMA engine enabled? */ |
72109168 | 432 | MV_PP_FLAG_NCQ_EN = (1 << 1), /* is EDMA set up for NCQ? */ |
00f42eab | 433 | MV_PP_FLAG_FBS_EN = (1 << 2), /* is EDMA set up for FBS? */ |
29d187bb | 434 | MV_PP_FLAG_DELAYED_EH = (1 << 3), /* delayed dev err handling */ |
d16ab3f6 | 435 | MV_PP_FLAG_FAKE_ATA_BUSY = (1 << 4), /* ignore initial ATA_DRDY */ |
20f733e7 BR |
436 | }; |
437 | ||
ee9ccdf7 JG |
438 | #define IS_GEN_I(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_I) |
439 | #define IS_GEN_II(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_II) | |
e4e7b892 | 440 | #define IS_GEN_IIE(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_IIE) |
8e7decdb | 441 | #define IS_PCIE(hpriv) ((hpriv)->hp_flags & MV_HP_PCIE) |
1f398472 | 442 | #define IS_SOC(hpriv) ((hpriv)->hp_flags & MV_HP_FLAG_SOC) |
bca1c4eb | 443 | |
15a32632 LB |
444 | #define WINDOW_CTRL(i) (0x20030 + ((i) << 4)) |
445 | #define WINDOW_BASE(i) (0x20034 + ((i) << 4)) | |
446 | ||
095fec88 | 447 | enum { |
baf14aa1 JG |
448 | /* DMA boundary 0xffff is required by the s/g splitting |
449 | * we need on /length/ in mv_fill-sg(). | |
450 | */ | |
451 | MV_DMA_BOUNDARY = 0xffffU, | |
095fec88 | 452 | |
0ea9e179 JG |
453 | /* mask of register bits containing lower 32 bits |
454 | * of EDMA request queue DMA address | |
455 | */ | |
095fec88 JG |
456 | EDMA_REQ_Q_BASE_LO_MASK = 0xfffffc00U, |
457 | ||
0ea9e179 | 458 | /* ditto, for response queue */ |
095fec88 JG |
459 | EDMA_RSP_Q_BASE_LO_MASK = 0xffffff00U, |
460 | }; | |
461 | ||
522479fb JG |
462 | enum chip_type { |
463 | chip_504x, | |
464 | chip_508x, | |
465 | chip_5080, | |
466 | chip_604x, | |
467 | chip_608x, | |
e4e7b892 JG |
468 | chip_6042, |
469 | chip_7042, | |
f351b2d6 | 470 | chip_soc, |
522479fb JG |
471 | }; |
472 | ||
31961943 BR |
473 | /* Command ReQuest Block: 32B */ |
474 | struct mv_crqb { | |
e1469874 ML |
475 | __le32 sg_addr; |
476 | __le32 sg_addr_hi; | |
477 | __le16 ctrl_flags; | |
478 | __le16 ata_cmd[11]; | |
31961943 | 479 | }; |
20f733e7 | 480 | |
e4e7b892 | 481 | struct mv_crqb_iie { |
e1469874 ML |
482 | __le32 addr; |
483 | __le32 addr_hi; | |
484 | __le32 flags; | |
485 | __le32 len; | |
486 | __le32 ata_cmd[4]; | |
e4e7b892 JG |
487 | }; |
488 | ||
31961943 BR |
489 | /* Command ResPonse Block: 8B */ |
490 | struct mv_crpb { | |
e1469874 ML |
491 | __le16 id; |
492 | __le16 flags; | |
493 | __le32 tmstmp; | |
20f733e7 BR |
494 | }; |
495 | ||
31961943 BR |
496 | /* EDMA Physical Region Descriptor (ePRD); A.K.A. SG */ |
497 | struct mv_sg { | |
e1469874 ML |
498 | __le32 addr; |
499 | __le32 flags_size; | |
500 | __le32 addr_hi; | |
501 | __le32 reserved; | |
31961943 | 502 | }; |
20f733e7 | 503 | |
08da1759 ML |
504 | /* |
505 | * We keep a local cache of a few frequently accessed port | |
506 | * registers here, to avoid having to read them (very slow) | |
507 | * when switching between EDMA and non-EDMA modes. | |
508 | */ | |
509 | struct mv_cached_regs { | |
510 | u32 fiscfg; | |
511 | u32 ltmode; | |
512 | u32 haltcond; | |
c01e8a23 | 513 | u32 unknown_rsvd; |
08da1759 ML |
514 | }; |
515 | ||
31961943 BR |
516 | struct mv_port_priv { |
517 | struct mv_crqb *crqb; | |
518 | dma_addr_t crqb_dma; | |
519 | struct mv_crpb *crpb; | |
520 | dma_addr_t crpb_dma; | |
eb73d558 ML |
521 | struct mv_sg *sg_tbl[MV_MAX_Q_DEPTH]; |
522 | dma_addr_t sg_tbl_dma[MV_MAX_Q_DEPTH]; | |
bdd4ddde JG |
523 | |
524 | unsigned int req_idx; | |
525 | unsigned int resp_idx; | |
526 | ||
31961943 | 527 | u32 pp_flags; |
08da1759 | 528 | struct mv_cached_regs cached; |
29d187bb | 529 | unsigned int delayed_eh_pmp_map; |
31961943 BR |
530 | }; |
531 | ||
bca1c4eb JG |
532 | struct mv_port_signal { |
533 | u32 amps; | |
534 | u32 pre; | |
535 | }; | |
536 | ||
02a121da ML |
537 | struct mv_host_priv { |
538 | u32 hp_flags; | |
1bfeff03 | 539 | unsigned int board_idx; |
96e2c487 | 540 | u32 main_irq_mask; |
02a121da ML |
541 | struct mv_port_signal signal[8]; |
542 | const struct mv_hw_ops *ops; | |
f351b2d6 SB |
543 | int n_ports; |
544 | void __iomem *base; | |
7368f919 ML |
545 | void __iomem *main_irq_cause_addr; |
546 | void __iomem *main_irq_mask_addr; | |
cae5a29d ML |
547 | u32 irq_cause_offset; |
548 | u32 irq_mask_offset; | |
02a121da | 549 | u32 unmask_all_irqs; |
c77a2f4e | 550 | |
e0067f0b EG |
551 | /* |
552 | * Needed on some devices that require their clocks to be enabled. | |
553 | * These are optional: if the platform device does not have any | |
554 | * clocks, they won't be used. Also, if the underlying hardware | |
555 | * does not support the common clock framework (CONFIG_HAVE_CLK=n), | |
556 | * all the clock operations become no-ops (see clk.h). | |
557 | */ | |
c77a2f4e | 558 | struct clk *clk; |
eee98990 | 559 | struct clk **port_clks; |
b7db4f2e AL |
560 | /* |
561 | * Some devices have a SATA PHY which can be enabled/disabled | |
562 | * in order to save power. These are optional: if the platform | |
563 | * devices does not have any phy, they won't be used. | |
564 | */ | |
565 | struct phy **port_phys; | |
da2fa9ba ML |
566 | /* |
567 | * These consistent DMA memory pools give us guaranteed | |
568 | * alignment for hardware-accessed data structures, | |
569 | * and less memory waste in accomplishing the alignment. | |
570 | */ | |
571 | struct dma_pool *crqb_pool; | |
572 | struct dma_pool *crpb_pool; | |
573 | struct dma_pool *sg_tbl_pool; | |
02a121da ML |
574 | }; |
575 | ||
47c2b677 | 576 | struct mv_hw_ops { |
2a47ce06 JG |
577 | void (*phy_errata)(struct mv_host_priv *hpriv, void __iomem *mmio, |
578 | unsigned int port); | |
47c2b677 JG |
579 | void (*enable_leds)(struct mv_host_priv *hpriv, void __iomem *mmio); |
580 | void (*read_preamp)(struct mv_host_priv *hpriv, int idx, | |
581 | void __iomem *mmio); | |
f76ba003 | 582 | int (*reset_hc)(struct ata_host *host, void __iomem *mmio, |
c9d39130 | 583 | unsigned int n_hc); |
522479fb | 584 | void (*reset_flash)(struct mv_host_priv *hpriv, void __iomem *mmio); |
7bb3c529 | 585 | void (*reset_bus)(struct ata_host *host, void __iomem *mmio); |
47c2b677 JG |
586 | }; |
587 | ||
82ef04fb TH |
588 | static int mv_scr_read(struct ata_link *link, unsigned int sc_reg_in, u32 *val); |
589 | static int mv_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val); | |
590 | static int mv5_scr_read(struct ata_link *link, unsigned int sc_reg_in, u32 *val); | |
591 | static int mv5_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val); | |
31961943 BR |
592 | static int mv_port_start(struct ata_port *ap); |
593 | static void mv_port_stop(struct ata_port *ap); | |
3e4a1391 | 594 | static int mv_qc_defer(struct ata_queued_cmd *qc); |
95364f36 JS |
595 | static enum ata_completion_errors mv_qc_prep(struct ata_queued_cmd *qc); |
596 | static enum ata_completion_errors mv_qc_prep_iie(struct ata_queued_cmd *qc); | |
9a3d9eb0 | 597 | static unsigned int mv_qc_issue(struct ata_queued_cmd *qc); |
a1efdaba TH |
598 | static int mv_hardreset(struct ata_link *link, unsigned int *class, |
599 | unsigned long deadline); | |
bdd4ddde JG |
600 | static void mv_eh_freeze(struct ata_port *ap); |
601 | static void mv_eh_thaw(struct ata_port *ap); | |
f273827e | 602 | static void mv6_dev_config(struct ata_device *dev); |
20f733e7 | 603 | |
2a47ce06 JG |
604 | static void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio, |
605 | unsigned int port); | |
47c2b677 JG |
606 | static void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio); |
607 | static void mv5_read_preamp(struct mv_host_priv *hpriv, int idx, | |
608 | void __iomem *mmio); | |
f76ba003 | 609 | static int mv5_reset_hc(struct ata_host *host, void __iomem *mmio, |
c9d39130 | 610 | unsigned int n_hc); |
522479fb | 611 | static void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio); |
7bb3c529 | 612 | static void mv5_reset_bus(struct ata_host *host, void __iomem *mmio); |
47c2b677 | 613 | |
2a47ce06 JG |
614 | static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio, |
615 | unsigned int port); | |
47c2b677 JG |
616 | static void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio); |
617 | static void mv6_read_preamp(struct mv_host_priv *hpriv, int idx, | |
618 | void __iomem *mmio); | |
f76ba003 | 619 | static int mv6_reset_hc(struct ata_host *host, void __iomem *mmio, |
c9d39130 | 620 | unsigned int n_hc); |
522479fb | 621 | static void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio); |
f351b2d6 SB |
622 | static void mv_soc_enable_leds(struct mv_host_priv *hpriv, |
623 | void __iomem *mmio); | |
624 | static void mv_soc_read_preamp(struct mv_host_priv *hpriv, int idx, | |
625 | void __iomem *mmio); | |
f76ba003 | 626 | static int mv_soc_reset_hc(struct ata_host *host, |
f351b2d6 SB |
627 | void __iomem *mmio, unsigned int n_hc); |
628 | static void mv_soc_reset_flash(struct mv_host_priv *hpriv, | |
629 | void __iomem *mmio); | |
630 | static void mv_soc_reset_bus(struct ata_host *host, void __iomem *mmio); | |
29b7e43c MM |
631 | static void mv_soc_65n_phy_errata(struct mv_host_priv *hpriv, |
632 | void __iomem *mmio, unsigned int port); | |
7bb3c529 | 633 | static void mv_reset_pci_bus(struct ata_host *host, void __iomem *mmio); |
e12bef50 | 634 | static void mv_reset_channel(struct mv_host_priv *hpriv, void __iomem *mmio, |
c9d39130 | 635 | unsigned int port_no); |
e12bef50 | 636 | static int mv_stop_edma(struct ata_port *ap); |
b562468c | 637 | static int mv_stop_edma_engine(void __iomem *port_mmio); |
00b81235 | 638 | static void mv_edma_cfg(struct ata_port *ap, int want_ncq, int want_edma); |
47c2b677 | 639 | |
e49856d8 ML |
640 | static void mv_pmp_select(struct ata_port *ap, int pmp); |
641 | static int mv_pmp_hardreset(struct ata_link *link, unsigned int *class, | |
642 | unsigned long deadline); | |
643 | static int mv_softreset(struct ata_link *link, unsigned int *class, | |
644 | unsigned long deadline); | |
29d187bb | 645 | static void mv_pmp_error_handler(struct ata_port *ap); |
4c299ca3 ML |
646 | static void mv_process_crpb_entries(struct ata_port *ap, |
647 | struct mv_port_priv *pp); | |
47c2b677 | 648 | |
da14265e ML |
649 | static void mv_sff_irq_clear(struct ata_port *ap); |
650 | static int mv_check_atapi_dma(struct ata_queued_cmd *qc); | |
651 | static void mv_bmdma_setup(struct ata_queued_cmd *qc); | |
652 | static void mv_bmdma_start(struct ata_queued_cmd *qc); | |
653 | static void mv_bmdma_stop(struct ata_queued_cmd *qc); | |
654 | static u8 mv_bmdma_status(struct ata_port *ap); | |
d16ab3f6 | 655 | static u8 mv_sff_check_status(struct ata_port *ap); |
da14265e | 656 | |
eb73d558 ML |
657 | /* .sg_tablesize is (MV_MAX_SG_CT / 2) in the structures below |
658 | * because we have to allow room for worst case splitting of | |
659 | * PRDs for 64K boundaries in mv_fill_sg(). | |
660 | */ | |
13b74085 | 661 | #ifdef CONFIG_PCI |
25df73d9 | 662 | static const struct scsi_host_template mv5_sht = { |
68d1d07b | 663 | ATA_BASE_SHT(DRV_NAME), |
baf14aa1 | 664 | .sg_tablesize = MV_MAX_SG_CT / 2, |
c5d3e45a | 665 | .dma_boundary = MV_DMA_BOUNDARY, |
c5d3e45a | 666 | }; |
13b74085 | 667 | #endif |
25df73d9 | 668 | static const struct scsi_host_template mv6_sht = { |
e75f41a9 | 669 | __ATA_BASE_SHT(DRV_NAME), |
138bfdd0 | 670 | .can_queue = MV_MAX_Q_DEPTH - 1, |
baf14aa1 | 671 | .sg_tablesize = MV_MAX_SG_CT / 2, |
20f733e7 | 672 | .dma_boundary = MV_DMA_BOUNDARY, |
c3f69c7f | 673 | .sdev_groups = ata_ncq_sdev_groups, |
e75f41a9 LJ |
674 | .change_queue_depth = ata_scsi_change_queue_depth, |
675 | .tag_alloc_policy = BLK_TAG_ALLOC_RR, | |
676 | .slave_configure = ata_scsi_slave_config | |
20f733e7 BR |
677 | }; |
678 | ||
029cfd6b TH |
679 | static struct ata_port_operations mv5_ops = { |
680 | .inherits = &ata_sff_port_ops, | |
c9d39130 | 681 | |
c96f1732 AC |
682 | .lost_interrupt = ATA_OP_NULL, |
683 | ||
3e4a1391 | 684 | .qc_defer = mv_qc_defer, |
c9d39130 JG |
685 | .qc_prep = mv_qc_prep, |
686 | .qc_issue = mv_qc_issue, | |
c9d39130 | 687 | |
bdd4ddde JG |
688 | .freeze = mv_eh_freeze, |
689 | .thaw = mv_eh_thaw, | |
a1efdaba | 690 | .hardreset = mv_hardreset, |
bdd4ddde | 691 | |
c9d39130 JG |
692 | .scr_read = mv5_scr_read, |
693 | .scr_write = mv5_scr_write, | |
694 | ||
695 | .port_start = mv_port_start, | |
696 | .port_stop = mv_port_stop, | |
c9d39130 JG |
697 | }; |
698 | ||
029cfd6b | 699 | static struct ata_port_operations mv6_ops = { |
8930ff25 TH |
700 | .inherits = &ata_bmdma_port_ops, |
701 | ||
702 | .lost_interrupt = ATA_OP_NULL, | |
703 | ||
704 | .qc_defer = mv_qc_defer, | |
705 | .qc_prep = mv_qc_prep, | |
706 | .qc_issue = mv_qc_issue, | |
707 | ||
f273827e | 708 | .dev_config = mv6_dev_config, |
20f733e7 | 709 | |
8930ff25 TH |
710 | .freeze = mv_eh_freeze, |
711 | .thaw = mv_eh_thaw, | |
712 | .hardreset = mv_hardreset, | |
713 | .softreset = mv_softreset, | |
e49856d8 ML |
714 | .pmp_hardreset = mv_pmp_hardreset, |
715 | .pmp_softreset = mv_softreset, | |
29d187bb | 716 | .error_handler = mv_pmp_error_handler, |
da14265e | 717 | |
8930ff25 TH |
718 | .scr_read = mv_scr_read, |
719 | .scr_write = mv_scr_write, | |
720 | ||
40f21b11 | 721 | .sff_check_status = mv_sff_check_status, |
da14265e ML |
722 | .sff_irq_clear = mv_sff_irq_clear, |
723 | .check_atapi_dma = mv_check_atapi_dma, | |
724 | .bmdma_setup = mv_bmdma_setup, | |
725 | .bmdma_start = mv_bmdma_start, | |
726 | .bmdma_stop = mv_bmdma_stop, | |
727 | .bmdma_status = mv_bmdma_status, | |
8930ff25 TH |
728 | |
729 | .port_start = mv_port_start, | |
730 | .port_stop = mv_port_stop, | |
20f733e7 BR |
731 | }; |
732 | ||
029cfd6b TH |
733 | static struct ata_port_operations mv_iie_ops = { |
734 | .inherits = &mv6_ops, | |
735 | .dev_config = ATA_OP_NULL, | |
e4e7b892 | 736 | .qc_prep = mv_qc_prep_iie, |
e4e7b892 JG |
737 | }; |
738 | ||
98ac62de | 739 | static const struct ata_port_info mv_port_info[] = { |
20f733e7 | 740 | { /* chip_504x */ |
91b1a84c | 741 | .flags = MV_GEN_I_FLAGS, |
c361acbc | 742 | .pio_mask = ATA_PIO4, |
bf6263a8 | 743 | .udma_mask = ATA_UDMA6, |
c9d39130 | 744 | .port_ops = &mv5_ops, |
20f733e7 BR |
745 | }, |
746 | { /* chip_508x */ | |
91b1a84c | 747 | .flags = MV_GEN_I_FLAGS | MV_FLAG_DUAL_HC, |
c361acbc | 748 | .pio_mask = ATA_PIO4, |
bf6263a8 | 749 | .udma_mask = ATA_UDMA6, |
c9d39130 | 750 | .port_ops = &mv5_ops, |
20f733e7 | 751 | }, |
47c2b677 | 752 | { /* chip_5080 */ |
91b1a84c | 753 | .flags = MV_GEN_I_FLAGS | MV_FLAG_DUAL_HC, |
c361acbc | 754 | .pio_mask = ATA_PIO4, |
bf6263a8 | 755 | .udma_mask = ATA_UDMA6, |
c9d39130 | 756 | .port_ops = &mv5_ops, |
47c2b677 | 757 | }, |
20f733e7 | 758 | { /* chip_604x */ |
91b1a84c | 759 | .flags = MV_GEN_II_FLAGS, |
c361acbc | 760 | .pio_mask = ATA_PIO4, |
bf6263a8 | 761 | .udma_mask = ATA_UDMA6, |
c9d39130 | 762 | .port_ops = &mv6_ops, |
20f733e7 BR |
763 | }, |
764 | { /* chip_608x */ | |
91b1a84c | 765 | .flags = MV_GEN_II_FLAGS | MV_FLAG_DUAL_HC, |
c361acbc | 766 | .pio_mask = ATA_PIO4, |
bf6263a8 | 767 | .udma_mask = ATA_UDMA6, |
c9d39130 | 768 | .port_ops = &mv6_ops, |
20f733e7 | 769 | }, |
e4e7b892 | 770 | { /* chip_6042 */ |
91b1a84c | 771 | .flags = MV_GEN_IIE_FLAGS, |
c361acbc | 772 | .pio_mask = ATA_PIO4, |
bf6263a8 | 773 | .udma_mask = ATA_UDMA6, |
e4e7b892 JG |
774 | .port_ops = &mv_iie_ops, |
775 | }, | |
776 | { /* chip_7042 */ | |
91b1a84c | 777 | .flags = MV_GEN_IIE_FLAGS, |
c361acbc | 778 | .pio_mask = ATA_PIO4, |
bf6263a8 | 779 | .udma_mask = ATA_UDMA6, |
e4e7b892 JG |
780 | .port_ops = &mv_iie_ops, |
781 | }, | |
f351b2d6 | 782 | { /* chip_soc */ |
91b1a84c | 783 | .flags = MV_GEN_IIE_FLAGS, |
c361acbc | 784 | .pio_mask = ATA_PIO4, |
17c5aab5 ML |
785 | .udma_mask = ATA_UDMA6, |
786 | .port_ops = &mv_iie_ops, | |
f351b2d6 | 787 | }, |
20f733e7 BR |
788 | }; |
789 | ||
3b7d697d | 790 | static const struct pci_device_id mv_pci_tbl[] = { |
2d2744fc JG |
791 | { PCI_VDEVICE(MARVELL, 0x5040), chip_504x }, |
792 | { PCI_VDEVICE(MARVELL, 0x5041), chip_504x }, | |
793 | { PCI_VDEVICE(MARVELL, 0x5080), chip_5080 }, | |
794 | { PCI_VDEVICE(MARVELL, 0x5081), chip_508x }, | |
46c5784c ML |
795 | /* RocketRAID 1720/174x have different identifiers */ |
796 | { PCI_VDEVICE(TTI, 0x1720), chip_6042 }, | |
4462254a ML |
797 | { PCI_VDEVICE(TTI, 0x1740), chip_6042 }, |
798 | { PCI_VDEVICE(TTI, 0x1742), chip_6042 }, | |
2d2744fc JG |
799 | |
800 | { PCI_VDEVICE(MARVELL, 0x6040), chip_604x }, | |
801 | { PCI_VDEVICE(MARVELL, 0x6041), chip_604x }, | |
802 | { PCI_VDEVICE(MARVELL, 0x6042), chip_6042 }, | |
803 | { PCI_VDEVICE(MARVELL, 0x6080), chip_608x }, | |
804 | { PCI_VDEVICE(MARVELL, 0x6081), chip_608x }, | |
805 | ||
806 | { PCI_VDEVICE(ADAPTEC2, 0x0241), chip_604x }, | |
807 | ||
d9f9c6bc FA |
808 | /* Adaptec 1430SA */ |
809 | { PCI_VDEVICE(ADAPTEC2, 0x0243), chip_7042 }, | |
810 | ||
02a121da | 811 | /* Marvell 7042 support */ |
6a3d586d MT |
812 | { PCI_VDEVICE(MARVELL, 0x7042), chip_7042 }, |
813 | ||
02a121da ML |
814 | /* Highpoint RocketRAID PCIe series */ |
815 | { PCI_VDEVICE(TTI, 0x2300), chip_7042 }, | |
816 | { PCI_VDEVICE(TTI, 0x2310), chip_7042 }, | |
817 | ||
2d2744fc | 818 | { } /* terminate list */ |
20f733e7 BR |
819 | }; |
820 | ||
47c2b677 JG |
821 | static const struct mv_hw_ops mv5xxx_ops = { |
822 | .phy_errata = mv5_phy_errata, | |
823 | .enable_leds = mv5_enable_leds, | |
824 | .read_preamp = mv5_read_preamp, | |
825 | .reset_hc = mv5_reset_hc, | |
522479fb JG |
826 | .reset_flash = mv5_reset_flash, |
827 | .reset_bus = mv5_reset_bus, | |
47c2b677 JG |
828 | }; |
829 | ||
830 | static const struct mv_hw_ops mv6xxx_ops = { | |
831 | .phy_errata = mv6_phy_errata, | |
832 | .enable_leds = mv6_enable_leds, | |
833 | .read_preamp = mv6_read_preamp, | |
834 | .reset_hc = mv6_reset_hc, | |
522479fb JG |
835 | .reset_flash = mv6_reset_flash, |
836 | .reset_bus = mv_reset_pci_bus, | |
47c2b677 JG |
837 | }; |
838 | ||
f351b2d6 SB |
839 | static const struct mv_hw_ops mv_soc_ops = { |
840 | .phy_errata = mv6_phy_errata, | |
841 | .enable_leds = mv_soc_enable_leds, | |
842 | .read_preamp = mv_soc_read_preamp, | |
843 | .reset_hc = mv_soc_reset_hc, | |
844 | .reset_flash = mv_soc_reset_flash, | |
845 | .reset_bus = mv_soc_reset_bus, | |
846 | }; | |
847 | ||
29b7e43c MM |
848 | static const struct mv_hw_ops mv_soc_65n_ops = { |
849 | .phy_errata = mv_soc_65n_phy_errata, | |
850 | .enable_leds = mv_soc_enable_leds, | |
851 | .reset_hc = mv_soc_reset_hc, | |
852 | .reset_flash = mv_soc_reset_flash, | |
853 | .reset_bus = mv_soc_reset_bus, | |
854 | }; | |
855 | ||
20f733e7 BR |
856 | /* |
857 | * Functions | |
858 | */ | |
859 | ||
860 | static inline void writelfl(unsigned long data, void __iomem *addr) | |
861 | { | |
862 | writel(data, addr); | |
863 | (void) readl(addr); /* flush to avoid PCI posted write */ | |
864 | } | |
865 | ||
c9d39130 JG |
866 | static inline unsigned int mv_hc_from_port(unsigned int port) |
867 | { | |
868 | return port >> MV_PORT_HC_SHIFT; | |
869 | } | |
870 | ||
871 | static inline unsigned int mv_hardport_from_port(unsigned int port) | |
872 | { | |
873 | return port & MV_PORT_MASK; | |
874 | } | |
875 | ||
1cfd19ae ML |
876 | /* |
877 | * Consolidate some rather tricky bit shift calculations. | |
878 | * This is hot-path stuff, so not a function. | |
879 | * Simple code, with two return values, so macro rather than inline. | |
880 | * | |
881 | * port is the sole input, in range 0..7. | |
7368f919 ML |
882 | * shift is one output, for use with main_irq_cause / main_irq_mask registers. |
883 | * hardport is the other output, in range 0..3. | |
1cfd19ae ML |
884 | * |
885 | * Note that port and hardport may be the same variable in some cases. | |
886 | */ | |
887 | #define MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport) \ | |
888 | { \ | |
889 | shift = mv_hc_from_port(port) * HC_SHIFT; \ | |
890 | hardport = mv_hardport_from_port(port); \ | |
891 | shift += hardport * 2; \ | |
892 | } | |
893 | ||
352fab70 ML |
894 | static inline void __iomem *mv_hc_base(void __iomem *base, unsigned int hc) |
895 | { | |
cae5a29d | 896 | return (base + SATAHC0_REG_BASE + (hc * MV_SATAHC_REG_SZ)); |
352fab70 ML |
897 | } |
898 | ||
c9d39130 JG |
899 | static inline void __iomem *mv_hc_base_from_port(void __iomem *base, |
900 | unsigned int port) | |
901 | { | |
902 | return mv_hc_base(base, mv_hc_from_port(port)); | |
903 | } | |
904 | ||
20f733e7 BR |
905 | static inline void __iomem *mv_port_base(void __iomem *base, unsigned int port) |
906 | { | |
c9d39130 | 907 | return mv_hc_base_from_port(base, port) + |
8b260248 | 908 | MV_SATAHC_ARBTR_REG_SZ + |
c9d39130 | 909 | (mv_hardport_from_port(port) * MV_PORT_REG_SZ); |
20f733e7 BR |
910 | } |
911 | ||
e12bef50 ML |
912 | static void __iomem *mv5_phy_base(void __iomem *mmio, unsigned int port) |
913 | { | |
914 | void __iomem *hc_mmio = mv_hc_base_from_port(mmio, port); | |
915 | unsigned long ofs = (mv_hardport_from_port(port) + 1) * 0x100UL; | |
916 | ||
917 | return hc_mmio + ofs; | |
918 | } | |
919 | ||
f351b2d6 SB |
920 | static inline void __iomem *mv_host_base(struct ata_host *host) |
921 | { | |
922 | struct mv_host_priv *hpriv = host->private_data; | |
923 | return hpriv->base; | |
924 | } | |
925 | ||
20f733e7 BR |
926 | static inline void __iomem *mv_ap_base(struct ata_port *ap) |
927 | { | |
f351b2d6 | 928 | return mv_port_base(mv_host_base(ap->host), ap->port_no); |
20f733e7 BR |
929 | } |
930 | ||
cca3974e | 931 | static inline int mv_get_hc_count(unsigned long port_flags) |
31961943 | 932 | { |
cca3974e | 933 | return ((port_flags & MV_FLAG_DUAL_HC) ? 2 : 1); |
31961943 BR |
934 | } |
935 | ||
08da1759 ML |
936 | /** |
937 | * mv_save_cached_regs - (re-)initialize cached port registers | |
938 | * @ap: the port whose registers we are caching | |
939 | * | |
940 | * Initialize the local cache of port registers, | |
941 | * so that reading them over and over again can | |
942 | * be avoided on the hotter paths of this driver. | |
943 | * This saves a few microseconds each time we switch | |
944 | * to/from EDMA mode to perform (eg.) a drive cache flush. | |
945 | */ | |
946 | static void mv_save_cached_regs(struct ata_port *ap) | |
947 | { | |
948 | void __iomem *port_mmio = mv_ap_base(ap); | |
949 | struct mv_port_priv *pp = ap->private_data; | |
950 | ||
cae5a29d ML |
951 | pp->cached.fiscfg = readl(port_mmio + FISCFG); |
952 | pp->cached.ltmode = readl(port_mmio + LTMODE); | |
953 | pp->cached.haltcond = readl(port_mmio + EDMA_HALTCOND); | |
954 | pp->cached.unknown_rsvd = readl(port_mmio + EDMA_UNKNOWN_RSVD); | |
08da1759 ML |
955 | } |
956 | ||
957 | /** | |
958 | * mv_write_cached_reg - write to a cached port register | |
959 | * @addr: hardware address of the register | |
960 | * @old: pointer to cached value of the register | |
961 | * @new: new value for the register | |
962 | * | |
963 | * Write a new value to a cached register, | |
964 | * but only if the value is different from before. | |
965 | */ | |
966 | static inline void mv_write_cached_reg(void __iomem *addr, u32 *old, u32 new) | |
967 | { | |
968 | if (new != *old) { | |
12f3b6d7 | 969 | unsigned long laddr; |
08da1759 | 970 | *old = new; |
12f3b6d7 ML |
971 | /* |
972 | * Workaround for 88SX60x1-B2 FEr SATA#13: | |
973 | * Read-after-write is needed to prevent generating 64-bit | |
974 | * write cycles on the PCI bus for SATA interface registers | |
975 | * at offsets ending in 0x4 or 0xc. | |
976 | * | |
977 | * Looks like a lot of fuss, but it avoids an unnecessary | |
978 | * +1 usec read-after-write delay for unaffected registers. | |
979 | */ | |
76bf3441 | 980 | laddr = (unsigned long)addr & 0xffff; |
12f3b6d7 ML |
981 | if (laddr >= 0x300 && laddr <= 0x33c) { |
982 | laddr &= 0x000f; | |
983 | if (laddr == 0x4 || laddr == 0xc) { | |
984 | writelfl(new, addr); /* read after write */ | |
985 | return; | |
986 | } | |
987 | } | |
988 | writel(new, addr); /* unaffected by the errata */ | |
08da1759 ML |
989 | } |
990 | } | |
991 | ||
c5d3e45a JG |
992 | static void mv_set_edma_ptrs(void __iomem *port_mmio, |
993 | struct mv_host_priv *hpriv, | |
994 | struct mv_port_priv *pp) | |
995 | { | |
bdd4ddde JG |
996 | u32 index; |
997 | ||
c5d3e45a JG |
998 | /* |
999 | * initialize request queue | |
1000 | */ | |
fcfb1f77 ML |
1001 | pp->req_idx &= MV_MAX_Q_DEPTH_MASK; /* paranoia */ |
1002 | index = pp->req_idx << EDMA_REQ_Q_PTR_SHIFT; | |
bdd4ddde | 1003 | |
c5d3e45a | 1004 | WARN_ON(pp->crqb_dma & 0x3ff); |
cae5a29d | 1005 | writel((pp->crqb_dma >> 16) >> 16, port_mmio + EDMA_REQ_Q_BASE_HI); |
bdd4ddde | 1006 | writelfl((pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK) | index, |
cae5a29d ML |
1007 | port_mmio + EDMA_REQ_Q_IN_PTR); |
1008 | writelfl(index, port_mmio + EDMA_REQ_Q_OUT_PTR); | |
c5d3e45a JG |
1009 | |
1010 | /* | |
1011 | * initialize response queue | |
1012 | */ | |
fcfb1f77 ML |
1013 | pp->resp_idx &= MV_MAX_Q_DEPTH_MASK; /* paranoia */ |
1014 | index = pp->resp_idx << EDMA_RSP_Q_PTR_SHIFT; | |
bdd4ddde | 1015 | |
c5d3e45a | 1016 | WARN_ON(pp->crpb_dma & 0xff); |
cae5a29d ML |
1017 | writel((pp->crpb_dma >> 16) >> 16, port_mmio + EDMA_RSP_Q_BASE_HI); |
1018 | writelfl(index, port_mmio + EDMA_RSP_Q_IN_PTR); | |
bdd4ddde | 1019 | writelfl((pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK) | index, |
cae5a29d | 1020 | port_mmio + EDMA_RSP_Q_OUT_PTR); |
c5d3e45a JG |
1021 | } |
1022 | ||
2b748a0a ML |
1023 | static void mv_write_main_irq_mask(u32 mask, struct mv_host_priv *hpriv) |
1024 | { | |
1025 | /* | |
1026 | * When writing to the main_irq_mask in hardware, | |
1027 | * we must ensure exclusivity between the interrupt coalescing bits | |
1028 | * and the corresponding individual port DONE_IRQ bits. | |
1029 | * | |
1030 | * Note that this register is really an "IRQ enable" register, | |
1031 | * not an "IRQ mask" register as Marvell's naming might suggest. | |
1032 | */ | |
1033 | if (mask & (ALL_PORTS_COAL_DONE | PORTS_0_3_COAL_DONE)) | |
1034 | mask &= ~DONE_IRQ_0_3; | |
1035 | if (mask & (ALL_PORTS_COAL_DONE | PORTS_4_7_COAL_DONE)) | |
1036 | mask &= ~DONE_IRQ_4_7; | |
1037 | writelfl(mask, hpriv->main_irq_mask_addr); | |
1038 | } | |
1039 | ||
c4de573b ML |
1040 | static void mv_set_main_irq_mask(struct ata_host *host, |
1041 | u32 disable_bits, u32 enable_bits) | |
1042 | { | |
1043 | struct mv_host_priv *hpriv = host->private_data; | |
1044 | u32 old_mask, new_mask; | |
1045 | ||
96e2c487 | 1046 | old_mask = hpriv->main_irq_mask; |
c4de573b | 1047 | new_mask = (old_mask & ~disable_bits) | enable_bits; |
96e2c487 ML |
1048 | if (new_mask != old_mask) { |
1049 | hpriv->main_irq_mask = new_mask; | |
2b748a0a | 1050 | mv_write_main_irq_mask(new_mask, hpriv); |
96e2c487 | 1051 | } |
c4de573b ML |
1052 | } |
1053 | ||
1054 | static void mv_enable_port_irqs(struct ata_port *ap, | |
1055 | unsigned int port_bits) | |
1056 | { | |
1057 | unsigned int shift, hardport, port = ap->port_no; | |
1058 | u32 disable_bits, enable_bits; | |
1059 | ||
1060 | MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport); | |
1061 | ||
1062 | disable_bits = (DONE_IRQ | ERR_IRQ) << shift; | |
1063 | enable_bits = port_bits << shift; | |
1064 | mv_set_main_irq_mask(ap->host, disable_bits, enable_bits); | |
1065 | } | |
1066 | ||
00b81235 ML |
1067 | static void mv_clear_and_enable_port_irqs(struct ata_port *ap, |
1068 | void __iomem *port_mmio, | |
1069 | unsigned int port_irqs) | |
1070 | { | |
1071 | struct mv_host_priv *hpriv = ap->host->private_data; | |
1072 | int hardport = mv_hardport_from_port(ap->port_no); | |
1073 | void __iomem *hc_mmio = mv_hc_base_from_port( | |
1074 | mv_host_base(ap->host), ap->port_no); | |
1075 | u32 hc_irq_cause; | |
1076 | ||
1077 | /* clear EDMA event indicators, if any */ | |
cae5a29d | 1078 | writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE); |
00b81235 ML |
1079 | |
1080 | /* clear pending irq events */ | |
1081 | hc_irq_cause = ~((DEV_IRQ | DMA_IRQ) << hardport); | |
cae5a29d | 1082 | writelfl(hc_irq_cause, hc_mmio + HC_IRQ_CAUSE); |
00b81235 ML |
1083 | |
1084 | /* clear FIS IRQ Cause */ | |
1085 | if (IS_GEN_IIE(hpriv)) | |
cae5a29d | 1086 | writelfl(0, port_mmio + FIS_IRQ_CAUSE); |
00b81235 ML |
1087 | |
1088 | mv_enable_port_irqs(ap, port_irqs); | |
1089 | } | |
1090 | ||
2b748a0a ML |
1091 | static void mv_set_irq_coalescing(struct ata_host *host, |
1092 | unsigned int count, unsigned int usecs) | |
1093 | { | |
1094 | struct mv_host_priv *hpriv = host->private_data; | |
1095 | void __iomem *mmio = hpriv->base, *hc_mmio; | |
1096 | u32 coal_enable = 0; | |
1097 | unsigned long flags; | |
6abf4678 | 1098 | unsigned int clks, is_dual_hc = hpriv->n_ports > MV_PORTS_PER_HC; |
2b748a0a ML |
1099 | const u32 coal_disable = PORTS_0_3_COAL_DONE | PORTS_4_7_COAL_DONE | |
1100 | ALL_PORTS_COAL_DONE; | |
1101 | ||
1102 | /* Disable IRQ coalescing if either threshold is zero */ | |
1103 | if (!usecs || !count) { | |
1104 | clks = count = 0; | |
1105 | } else { | |
1106 | /* Respect maximum limits of the hardware */ | |
1107 | clks = usecs * COAL_CLOCKS_PER_USEC; | |
1108 | if (clks > MAX_COAL_TIME_THRESHOLD) | |
1109 | clks = MAX_COAL_TIME_THRESHOLD; | |
1110 | if (count > MAX_COAL_IO_COUNT) | |
1111 | count = MAX_COAL_IO_COUNT; | |
1112 | } | |
1113 | ||
1114 | spin_lock_irqsave(&host->lock, flags); | |
6abf4678 | 1115 | mv_set_main_irq_mask(host, coal_disable, 0); |
2b748a0a | 1116 | |
6abf4678 | 1117 | if (is_dual_hc && !IS_GEN_I(hpriv)) { |
2b748a0a | 1118 | /* |
6abf4678 ML |
1119 | * GEN_II/GEN_IIE with dual host controllers: |
1120 | * one set of global thresholds for the entire chip. | |
2b748a0a | 1121 | */ |
cae5a29d ML |
1122 | writel(clks, mmio + IRQ_COAL_TIME_THRESHOLD); |
1123 | writel(count, mmio + IRQ_COAL_IO_THRESHOLD); | |
2b748a0a | 1124 | /* clear leftover coal IRQ bit */ |
cae5a29d | 1125 | writel(~ALL_PORTS_COAL_IRQ, mmio + IRQ_COAL_CAUSE); |
6abf4678 ML |
1126 | if (count) |
1127 | coal_enable = ALL_PORTS_COAL_DONE; | |
1128 | clks = count = 0; /* force clearing of regular regs below */ | |
2b748a0a | 1129 | } |
6abf4678 | 1130 | |
2b748a0a ML |
1131 | /* |
1132 | * All chips: independent thresholds for each HC on the chip. | |
1133 | */ | |
1134 | hc_mmio = mv_hc_base_from_port(mmio, 0); | |
cae5a29d ML |
1135 | writel(clks, hc_mmio + HC_IRQ_COAL_TIME_THRESHOLD); |
1136 | writel(count, hc_mmio + HC_IRQ_COAL_IO_THRESHOLD); | |
1137 | writel(~HC_COAL_IRQ, hc_mmio + HC_IRQ_CAUSE); | |
6abf4678 ML |
1138 | if (count) |
1139 | coal_enable |= PORTS_0_3_COAL_DONE; | |
1140 | if (is_dual_hc) { | |
2b748a0a | 1141 | hc_mmio = mv_hc_base_from_port(mmio, MV_PORTS_PER_HC); |
cae5a29d ML |
1142 | writel(clks, hc_mmio + HC_IRQ_COAL_TIME_THRESHOLD); |
1143 | writel(count, hc_mmio + HC_IRQ_COAL_IO_THRESHOLD); | |
1144 | writel(~HC_COAL_IRQ, hc_mmio + HC_IRQ_CAUSE); | |
6abf4678 ML |
1145 | if (count) |
1146 | coal_enable |= PORTS_4_7_COAL_DONE; | |
2b748a0a | 1147 | } |
2b748a0a | 1148 | |
6abf4678 | 1149 | mv_set_main_irq_mask(host, 0, coal_enable); |
2b748a0a ML |
1150 | spin_unlock_irqrestore(&host->lock, flags); |
1151 | } | |
1152 | ||
f3a23c2c | 1153 | /* |
00b81235 | 1154 | * mv_start_edma - Enable eDMA engine |
05b308e1 BR |
1155 | * @pp: port private data |
1156 | * | |
beec7dbc TH |
1157 | * Verify the local cache of the eDMA state is accurate with a |
1158 | * WARN_ON. | |
05b308e1 BR |
1159 | * |
1160 | * LOCKING: | |
1161 | * Inherited from caller. | |
1162 | */ | |
00b81235 | 1163 | static void mv_start_edma(struct ata_port *ap, void __iomem *port_mmio, |
72109168 | 1164 | struct mv_port_priv *pp, u8 protocol) |
20f733e7 | 1165 | { |
72109168 ML |
1166 | int want_ncq = (protocol == ATA_PROT_NCQ); |
1167 | ||
1168 | if (pp->pp_flags & MV_PP_FLAG_EDMA_EN) { | |
1169 | int using_ncq = ((pp->pp_flags & MV_PP_FLAG_NCQ_EN) != 0); | |
1170 | if (want_ncq != using_ncq) | |
b562468c | 1171 | mv_stop_edma(ap); |
72109168 | 1172 | } |
c5d3e45a | 1173 | if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN)) { |
0c58912e | 1174 | struct mv_host_priv *hpriv = ap->host->private_data; |
0c58912e | 1175 | |
00b81235 | 1176 | mv_edma_cfg(ap, want_ncq, 1); |
0c58912e | 1177 | |
f630d562 | 1178 | mv_set_edma_ptrs(port_mmio, hpriv, pp); |
00b81235 | 1179 | mv_clear_and_enable_port_irqs(ap, port_mmio, DONE_IRQ|ERR_IRQ); |
bdd4ddde | 1180 | |
cae5a29d | 1181 | writelfl(EDMA_EN, port_mmio + EDMA_CMD); |
afb0edd9 BR |
1182 | pp->pp_flags |= MV_PP_FLAG_EDMA_EN; |
1183 | } | |
20f733e7 BR |
1184 | } |
1185 | ||
9b2c4e0b ML |
1186 | static void mv_wait_for_edma_empty_idle(struct ata_port *ap) |
1187 | { | |
1188 | void __iomem *port_mmio = mv_ap_base(ap); | |
1189 | const u32 empty_idle = (EDMA_STATUS_CACHE_EMPTY | EDMA_STATUS_IDLE); | |
1190 | const int per_loop = 5, timeout = (15 * 1000 / per_loop); | |
1191 | int i; | |
1192 | ||
1193 | /* | |
1194 | * Wait for the EDMA engine to finish transactions in progress. | |
c46938cc ML |
1195 | * No idea what a good "timeout" value might be, but measurements |
1196 | * indicate that it often requires hundreds of microseconds | |
1197 | * with two drives in-use. So we use the 15msec value above | |
1198 | * as a rough guess at what even more drives might require. | |
9b2c4e0b ML |
1199 | */ |
1200 | for (i = 0; i < timeout; ++i) { | |
cae5a29d | 1201 | u32 edma_stat = readl(port_mmio + EDMA_STATUS); |
9b2c4e0b ML |
1202 | if ((edma_stat & empty_idle) == empty_idle) |
1203 | break; | |
1204 | udelay(per_loop); | |
1205 | } | |
a9a79dfe | 1206 | /* ata_port_info(ap, "%s: %u+ usecs\n", __func__, i); */ |
9b2c4e0b ML |
1207 | } |
1208 | ||
05b308e1 | 1209 | /** |
e12bef50 | 1210 | * mv_stop_edma_engine - Disable eDMA engine |
b562468c | 1211 | * @port_mmio: io base address |
05b308e1 BR |
1212 | * |
1213 | * LOCKING: | |
1214 | * Inherited from caller. | |
1215 | */ | |
b562468c | 1216 | static int mv_stop_edma_engine(void __iomem *port_mmio) |
20f733e7 | 1217 | { |
b562468c | 1218 | int i; |
31961943 | 1219 | |
b562468c | 1220 | /* Disable eDMA. The disable bit auto clears. */ |
cae5a29d | 1221 | writelfl(EDMA_DS, port_mmio + EDMA_CMD); |
8b260248 | 1222 | |
b562468c ML |
1223 | /* Wait for the chip to confirm eDMA is off. */ |
1224 | for (i = 10000; i > 0; i--) { | |
cae5a29d | 1225 | u32 reg = readl(port_mmio + EDMA_CMD); |
4537deb5 | 1226 | if (!(reg & EDMA_EN)) |
b562468c ML |
1227 | return 0; |
1228 | udelay(10); | |
31961943 | 1229 | } |
b562468c | 1230 | return -EIO; |
20f733e7 BR |
1231 | } |
1232 | ||
e12bef50 | 1233 | static int mv_stop_edma(struct ata_port *ap) |
0ea9e179 | 1234 | { |
b562468c ML |
1235 | void __iomem *port_mmio = mv_ap_base(ap); |
1236 | struct mv_port_priv *pp = ap->private_data; | |
66e57a2c | 1237 | int err = 0; |
0ea9e179 | 1238 | |
b562468c ML |
1239 | if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN)) |
1240 | return 0; | |
1241 | pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN; | |
9b2c4e0b | 1242 | mv_wait_for_edma_empty_idle(ap); |
b562468c | 1243 | if (mv_stop_edma_engine(port_mmio)) { |
a9a79dfe | 1244 | ata_port_err(ap, "Unable to stop eDMA\n"); |
66e57a2c | 1245 | err = -EIO; |
b562468c | 1246 | } |
66e57a2c ML |
1247 | mv_edma_cfg(ap, 0, 0); |
1248 | return err; | |
0ea9e179 JG |
1249 | } |
1250 | ||
a2715a42 | 1251 | static void mv_dump_mem(struct device *dev, void __iomem *start, unsigned bytes) |
20f733e7 | 1252 | { |
a2715a42 HR |
1253 | int b, w, o; |
1254 | unsigned char linebuf[38]; | |
1255 | ||
31961943 | 1256 | for (b = 0; b < bytes; ) { |
a2715a42 HR |
1257 | for (w = 0, o = 0; b < bytes && w < 4; w++) { |
1258 | o += snprintf(linebuf + o, sizeof(linebuf) - o, | |
1259 | "%08x ", readl(start + b)); | |
31961943 BR |
1260 | b += sizeof(u32); |
1261 | } | |
a2715a42 HR |
1262 | dev_dbg(dev, "%s: %p: %s\n", |
1263 | __func__, start + b, linebuf); | |
31961943 | 1264 | } |
31961943 | 1265 | } |
a2715a42 | 1266 | |
31961943 BR |
1267 | static void mv_dump_pci_cfg(struct pci_dev *pdev, unsigned bytes) |
1268 | { | |
a2715a42 HR |
1269 | int b, w, o; |
1270 | u32 dw = 0; | |
1271 | unsigned char linebuf[38]; | |
1272 | ||
31961943 | 1273 | for (b = 0; b < bytes; ) { |
a2715a42 | 1274 | for (w = 0, o = 0; b < bytes && w < 4; w++) { |
2dcb407e | 1275 | (void) pci_read_config_dword(pdev, b, &dw); |
a2715a42 HR |
1276 | o += snprintf(linebuf + o, sizeof(linebuf) - o, |
1277 | "%08x ", dw); | |
31961943 BR |
1278 | b += sizeof(u32); |
1279 | } | |
a2715a42 HR |
1280 | dev_dbg(&pdev->dev, "%s: %02x: %s\n", |
1281 | __func__, b, linebuf); | |
31961943 | 1282 | } |
31961943 | 1283 | } |
a2715a42 | 1284 | |
37fcfade | 1285 | static void mv_dump_all_regs(void __iomem *mmio_base, |
31961943 BR |
1286 | struct pci_dev *pdev) |
1287 | { | |
37fcfade | 1288 | void __iomem *hc_base; |
31961943 BR |
1289 | void __iomem *port_base; |
1290 | int start_port, num_ports, p, start_hc, num_hcs, hc; | |
1291 | ||
37fcfade HR |
1292 | start_hc = start_port = 0; |
1293 | num_ports = 8; /* should be benign for 4 port devs */ | |
1294 | num_hcs = 2; | |
a2715a42 HR |
1295 | dev_dbg(&pdev->dev, |
1296 | "%s: All registers for port(s) %u-%u:\n", __func__, | |
1297 | start_port, num_ports > 1 ? num_ports - 1 : start_port); | |
1298 | ||
1299 | dev_dbg(&pdev->dev, "%s: PCI config space regs:\n", __func__); | |
1300 | mv_dump_pci_cfg(pdev, 0x68); | |
1301 | ||
1302 | dev_dbg(&pdev->dev, "%s: PCI regs:\n", __func__); | |
1303 | mv_dump_mem(&pdev->dev, mmio_base+0xc00, 0x3c); | |
1304 | mv_dump_mem(&pdev->dev, mmio_base+0xd00, 0x34); | |
1305 | mv_dump_mem(&pdev->dev, mmio_base+0xf00, 0x4); | |
1306 | mv_dump_mem(&pdev->dev, mmio_base+0x1d00, 0x6c); | |
31961943 | 1307 | for (hc = start_hc; hc < start_hc + num_hcs; hc++) { |
d220c37e | 1308 | hc_base = mv_hc_base(mmio_base, hc); |
a2715a42 HR |
1309 | dev_dbg(&pdev->dev, "%s: HC regs (HC %i):\n", __func__, hc); |
1310 | mv_dump_mem(&pdev->dev, hc_base, 0x1c); | |
31961943 BR |
1311 | } |
1312 | for (p = start_port; p < start_port + num_ports; p++) { | |
1313 | port_base = mv_port_base(mmio_base, p); | |
a2715a42 HR |
1314 | dev_dbg(&pdev->dev, "%s: EDMA regs (port %i):\n", __func__, p); |
1315 | mv_dump_mem(&pdev->dev, port_base, 0x54); | |
1316 | dev_dbg(&pdev->dev, "%s: SATA regs (port %i):\n", __func__, p); | |
1317 | mv_dump_mem(&pdev->dev, port_base+0x300, 0x60); | |
31961943 | 1318 | } |
20f733e7 BR |
1319 | } |
1320 | ||
1321 | static unsigned int mv_scr_offset(unsigned int sc_reg_in) | |
1322 | { | |
1323 | unsigned int ofs; | |
1324 | ||
1325 | switch (sc_reg_in) { | |
1326 | case SCR_STATUS: | |
1327 | case SCR_CONTROL: | |
1328 | case SCR_ERROR: | |
cae5a29d | 1329 | ofs = SATA_STATUS + (sc_reg_in * sizeof(u32)); |
20f733e7 BR |
1330 | break; |
1331 | case SCR_ACTIVE: | |
cae5a29d | 1332 | ofs = SATA_ACTIVE; /* active is not with the others */ |
20f733e7 BR |
1333 | break; |
1334 | default: | |
1335 | ofs = 0xffffffffU; | |
1336 | break; | |
1337 | } | |
1338 | return ofs; | |
1339 | } | |
1340 | ||
82ef04fb | 1341 | static int mv_scr_read(struct ata_link *link, unsigned int sc_reg_in, u32 *val) |
20f733e7 BR |
1342 | { |
1343 | unsigned int ofs = mv_scr_offset(sc_reg_in); | |
1344 | ||
da3dbb17 | 1345 | if (ofs != 0xffffffffU) { |
82ef04fb | 1346 | *val = readl(mv_ap_base(link->ap) + ofs); |
da3dbb17 TH |
1347 | return 0; |
1348 | } else | |
1349 | return -EINVAL; | |
20f733e7 BR |
1350 | } |
1351 | ||
82ef04fb | 1352 | static int mv_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val) |
20f733e7 BR |
1353 | { |
1354 | unsigned int ofs = mv_scr_offset(sc_reg_in); | |
1355 | ||
da3dbb17 | 1356 | if (ofs != 0xffffffffU) { |
20091773 | 1357 | void __iomem *addr = mv_ap_base(link->ap) + ofs; |
9013d64e | 1358 | struct mv_host_priv *hpriv = link->ap->host->private_data; |
20091773 ML |
1359 | if (sc_reg_in == SCR_CONTROL) { |
1360 | /* | |
1361 | * Workaround for 88SX60x1 FEr SATA#26: | |
1362 | * | |
25985edc | 1363 | * COMRESETs have to take care not to accidentally |
20091773 ML |
1364 | * put the drive to sleep when writing SCR_CONTROL. |
1365 | * Setting bits 12..15 prevents this problem. | |
1366 | * | |
1367 | * So if we see an outbound COMMRESET, set those bits. | |
1368 | * Ditto for the followup write that clears the reset. | |
1369 | * | |
1370 | * The proprietary driver does this for | |
1371 | * all chip versions, and so do we. | |
1372 | */ | |
1373 | if ((val & 0xf) == 1 || (readl(addr) & 0xf) == 1) | |
1374 | val |= 0xf000; | |
9013d64e LA |
1375 | |
1376 | if (hpriv->hp_flags & MV_HP_FIX_LP_PHY_CTL) { | |
1377 | void __iomem *lp_phy_addr = | |
1378 | mv_ap_base(link->ap) + LP_PHY_CTL; | |
1379 | /* | |
1380 | * Set PHY speed according to SControl speed. | |
1381 | */ | |
3661aa99 TP |
1382 | u32 lp_phy_val = |
1383 | LP_PHY_CTL_PIN_PU_PLL | | |
1384 | LP_PHY_CTL_PIN_PU_RX | | |
1385 | LP_PHY_CTL_PIN_PU_TX; | |
1386 | ||
1387 | if ((val & 0xf0) != 0x10) | |
1388 | lp_phy_val |= | |
1389 | LP_PHY_CTL_GEN_TX_3G | | |
1390 | LP_PHY_CTL_GEN_RX_3G; | |
1391 | ||
1392 | writelfl(lp_phy_val, lp_phy_addr); | |
9013d64e | 1393 | } |
20091773 ML |
1394 | } |
1395 | writelfl(val, addr); | |
da3dbb17 TH |
1396 | return 0; |
1397 | } else | |
1398 | return -EINVAL; | |
20f733e7 BR |
1399 | } |
1400 | ||
f273827e ML |
1401 | static void mv6_dev_config(struct ata_device *adev) |
1402 | { | |
1403 | /* | |
e49856d8 ML |
1404 | * Deal with Gen-II ("mv6") hardware quirks/restrictions: |
1405 | * | |
1406 | * Gen-II does not support NCQ over a port multiplier | |
1407 | * (no FIS-based switching). | |
f273827e | 1408 | */ |
e49856d8 | 1409 | if (adev->flags & ATA_DFLAG_NCQ) { |
352fab70 | 1410 | if (sata_pmp_attached(adev->link->ap)) { |
e49856d8 | 1411 | adev->flags &= ~ATA_DFLAG_NCQ; |
a9a79dfe | 1412 | ata_dev_info(adev, |
352fab70 | 1413 | "NCQ disabled for command-based switching\n"); |
352fab70 | 1414 | } |
e49856d8 | 1415 | } |
f273827e ML |
1416 | } |
1417 | ||
3e4a1391 ML |
1418 | static int mv_qc_defer(struct ata_queued_cmd *qc) |
1419 | { | |
1420 | struct ata_link *link = qc->dev->link; | |
1421 | struct ata_port *ap = link->ap; | |
1422 | struct mv_port_priv *pp = ap->private_data; | |
1423 | ||
29d187bb ML |
1424 | /* |
1425 | * Don't allow new commands if we're in a delayed EH state | |
1426 | * for NCQ and/or FIS-based switching. | |
1427 | */ | |
1428 | if (pp->pp_flags & MV_PP_FLAG_DELAYED_EH) | |
1429 | return ATA_DEFER_PORT; | |
159a7ff7 GG |
1430 | |
1431 | /* PIO commands need exclusive link: no other commands [DMA or PIO] | |
1432 | * can run concurrently. | |
1433 | * set excl_link when we want to send a PIO command in DMA mode | |
1434 | * or a non-NCQ command in NCQ mode. | |
1435 | * When we receive a command from that link, and there are no | |
1436 | * outstanding commands, mark a flag to clear excl_link and let | |
1437 | * the command go through. | |
1438 | */ | |
1439 | if (unlikely(ap->excl_link)) { | |
1440 | if (link == ap->excl_link) { | |
1441 | if (ap->nr_active_links) | |
1442 | return ATA_DEFER_PORT; | |
1443 | qc->flags |= ATA_QCFLAG_CLEAR_EXCL; | |
1444 | return 0; | |
1445 | } else | |
1446 | return ATA_DEFER_PORT; | |
1447 | } | |
1448 | ||
3e4a1391 ML |
1449 | /* |
1450 | * If the port is completely idle, then allow the new qc. | |
1451 | */ | |
1452 | if (ap->nr_active_links == 0) | |
1453 | return 0; | |
1454 | ||
4bdee6c5 TH |
1455 | /* |
1456 | * The port is operating in host queuing mode (EDMA) with NCQ | |
1457 | * enabled, allow multiple NCQ commands. EDMA also allows | |
1458 | * queueing multiple DMA commands but libata core currently | |
1459 | * doesn't allow it. | |
1460 | */ | |
1461 | if ((pp->pp_flags & MV_PP_FLAG_EDMA_EN) && | |
159a7ff7 GG |
1462 | (pp->pp_flags & MV_PP_FLAG_NCQ_EN)) { |
1463 | if (ata_is_ncq(qc->tf.protocol)) | |
1464 | return 0; | |
1465 | else { | |
1466 | ap->excl_link = link; | |
1467 | return ATA_DEFER_PORT; | |
1468 | } | |
1469 | } | |
4bdee6c5 | 1470 | |
3e4a1391 ML |
1471 | return ATA_DEFER_PORT; |
1472 | } | |
1473 | ||
08da1759 | 1474 | static void mv_config_fbs(struct ata_port *ap, int want_ncq, int want_fbs) |
e49856d8 | 1475 | { |
08da1759 ML |
1476 | struct mv_port_priv *pp = ap->private_data; |
1477 | void __iomem *port_mmio; | |
00f42eab | 1478 | |
08da1759 ML |
1479 | u32 fiscfg, *old_fiscfg = &pp->cached.fiscfg; |
1480 | u32 ltmode, *old_ltmode = &pp->cached.ltmode; | |
1481 | u32 haltcond, *old_haltcond = &pp->cached.haltcond; | |
00f42eab | 1482 | |
08da1759 ML |
1483 | ltmode = *old_ltmode & ~LTMODE_BIT8; |
1484 | haltcond = *old_haltcond | EDMA_ERR_DEV; | |
00f42eab ML |
1485 | |
1486 | if (want_fbs) { | |
08da1759 ML |
1487 | fiscfg = *old_fiscfg | FISCFG_SINGLE_SYNC; |
1488 | ltmode = *old_ltmode | LTMODE_BIT8; | |
4c299ca3 | 1489 | if (want_ncq) |
08da1759 | 1490 | haltcond &= ~EDMA_ERR_DEV; |
4c299ca3 | 1491 | else |
08da1759 ML |
1492 | fiscfg |= FISCFG_WAIT_DEV_ERR; |
1493 | } else { | |
1494 | fiscfg = *old_fiscfg & ~(FISCFG_SINGLE_SYNC | FISCFG_WAIT_DEV_ERR); | |
e49856d8 | 1495 | } |
00f42eab | 1496 | |
08da1759 | 1497 | port_mmio = mv_ap_base(ap); |
cae5a29d ML |
1498 | mv_write_cached_reg(port_mmio + FISCFG, old_fiscfg, fiscfg); |
1499 | mv_write_cached_reg(port_mmio + LTMODE, old_ltmode, ltmode); | |
1500 | mv_write_cached_reg(port_mmio + EDMA_HALTCOND, old_haltcond, haltcond); | |
f273827e ML |
1501 | } |
1502 | ||
dd2890f6 ML |
1503 | static void mv_60x1_errata_sata25(struct ata_port *ap, int want_ncq) |
1504 | { | |
1505 | struct mv_host_priv *hpriv = ap->host->private_data; | |
1506 | u32 old, new; | |
1507 | ||
1508 | /* workaround for 88SX60x1 FEr SATA#25 (part 1) */ | |
cae5a29d | 1509 | old = readl(hpriv->base + GPIO_PORT_CTL); |
dd2890f6 ML |
1510 | if (want_ncq) |
1511 | new = old | (1 << 22); | |
1512 | else | |
1513 | new = old & ~(1 << 22); | |
1514 | if (new != old) | |
cae5a29d | 1515 | writel(new, hpriv->base + GPIO_PORT_CTL); |
dd2890f6 ML |
1516 | } |
1517 | ||
f3a23c2c | 1518 | /* |
40f21b11 ML |
1519 | * mv_bmdma_enable - set a magic bit on GEN_IIE to allow bmdma |
1520 | * @ap: Port being initialized | |
c01e8a23 ML |
1521 | * |
1522 | * There are two DMA modes on these chips: basic DMA, and EDMA. | |
1523 | * | |
1524 | * Bit-0 of the "EDMA RESERVED" register enables/disables use | |
1525 | * of basic DMA on the GEN_IIE versions of the chips. | |
1526 | * | |
1527 | * This bit survives EDMA resets, and must be set for basic DMA | |
1528 | * to function, and should be cleared when EDMA is active. | |
1529 | */ | |
1530 | static void mv_bmdma_enable_iie(struct ata_port *ap, int enable_bmdma) | |
1531 | { | |
1532 | struct mv_port_priv *pp = ap->private_data; | |
1533 | u32 new, *old = &pp->cached.unknown_rsvd; | |
1534 | ||
1535 | if (enable_bmdma) | |
1536 | new = *old | 1; | |
1537 | else | |
1538 | new = *old & ~1; | |
cae5a29d | 1539 | mv_write_cached_reg(mv_ap_base(ap) + EDMA_UNKNOWN_RSVD, old, new); |
c01e8a23 ML |
1540 | } |
1541 | ||
000b344f ML |
1542 | /* |
1543 | * SOC chips have an issue whereby the HDD LEDs don't always blink | |
1544 | * during I/O when NCQ is enabled. Enabling a special "LED blink" mode | |
1545 | * of the SOC takes care of it, generating a steady blink rate when | |
1546 | * any drive on the chip is active. | |
1547 | * | |
1548 | * Unfortunately, the blink mode is a global hardware setting for the SOC, | |
1549 | * so we must use it whenever at least one port on the SOC has NCQ enabled. | |
1550 | * | |
1551 | * We turn "LED blink" off when NCQ is not in use anywhere, because the normal | |
1552 | * LED operation works then, and provides better (more accurate) feedback. | |
1553 | * | |
1554 | * Note that this code assumes that an SOC never has more than one HC onboard. | |
1555 | */ | |
1556 | static void mv_soc_led_blink_enable(struct ata_port *ap) | |
1557 | { | |
1558 | struct ata_host *host = ap->host; | |
1559 | struct mv_host_priv *hpriv = host->private_data; | |
1560 | void __iomem *hc_mmio; | |
1561 | u32 led_ctrl; | |
1562 | ||
1563 | if (hpriv->hp_flags & MV_HP_QUIRK_LED_BLINK_EN) | |
1564 | return; | |
1565 | hpriv->hp_flags |= MV_HP_QUIRK_LED_BLINK_EN; | |
1566 | hc_mmio = mv_hc_base_from_port(mv_host_base(host), ap->port_no); | |
cae5a29d ML |
1567 | led_ctrl = readl(hc_mmio + SOC_LED_CTRL); |
1568 | writel(led_ctrl | SOC_LED_CTRL_BLINK, hc_mmio + SOC_LED_CTRL); | |
000b344f ML |
1569 | } |
1570 | ||
1571 | static void mv_soc_led_blink_disable(struct ata_port *ap) | |
1572 | { | |
1573 | struct ata_host *host = ap->host; | |
1574 | struct mv_host_priv *hpriv = host->private_data; | |
1575 | void __iomem *hc_mmio; | |
1576 | u32 led_ctrl; | |
1577 | unsigned int port; | |
1578 | ||
1579 | if (!(hpriv->hp_flags & MV_HP_QUIRK_LED_BLINK_EN)) | |
1580 | return; | |
1581 | ||
1582 | /* disable led-blink only if no ports are using NCQ */ | |
1583 | for (port = 0; port < hpriv->n_ports; port++) { | |
1584 | struct ata_port *this_ap = host->ports[port]; | |
1585 | struct mv_port_priv *pp = this_ap->private_data; | |
1586 | ||
1587 | if (pp->pp_flags & MV_PP_FLAG_NCQ_EN) | |
1588 | return; | |
1589 | } | |
1590 | ||
1591 | hpriv->hp_flags &= ~MV_HP_QUIRK_LED_BLINK_EN; | |
1592 | hc_mmio = mv_hc_base_from_port(mv_host_base(host), ap->port_no); | |
cae5a29d ML |
1593 | led_ctrl = readl(hc_mmio + SOC_LED_CTRL); |
1594 | writel(led_ctrl & ~SOC_LED_CTRL_BLINK, hc_mmio + SOC_LED_CTRL); | |
000b344f ML |
1595 | } |
1596 | ||
00b81235 | 1597 | static void mv_edma_cfg(struct ata_port *ap, int want_ncq, int want_edma) |
e4e7b892 | 1598 | { |
0c58912e | 1599 | u32 cfg; |
e12bef50 ML |
1600 | struct mv_port_priv *pp = ap->private_data; |
1601 | struct mv_host_priv *hpriv = ap->host->private_data; | |
1602 | void __iomem *port_mmio = mv_ap_base(ap); | |
e4e7b892 JG |
1603 | |
1604 | /* set up non-NCQ EDMA configuration */ | |
0c58912e | 1605 | cfg = EDMA_CFG_Q_DEPTH; /* always 0x1f for *all* chips */ |
d16ab3f6 ML |
1606 | pp->pp_flags &= |
1607 | ~(MV_PP_FLAG_FBS_EN | MV_PP_FLAG_NCQ_EN | MV_PP_FLAG_FAKE_ATA_BUSY); | |
e4e7b892 | 1608 | |
0c58912e | 1609 | if (IS_GEN_I(hpriv)) |
e4e7b892 JG |
1610 | cfg |= (1 << 8); /* enab config burst size mask */ |
1611 | ||
dd2890f6 | 1612 | else if (IS_GEN_II(hpriv)) { |
e4e7b892 | 1613 | cfg |= EDMA_CFG_RD_BRST_EXT | EDMA_CFG_WR_BUFF_LEN; |
dd2890f6 | 1614 | mv_60x1_errata_sata25(ap, want_ncq); |
e4e7b892 | 1615 | |
dd2890f6 | 1616 | } else if (IS_GEN_IIE(hpriv)) { |
00f42eab ML |
1617 | int want_fbs = sata_pmp_attached(ap); |
1618 | /* | |
1619 | * Possible future enhancement: | |
1620 | * | |
1621 | * The chip can use FBS with non-NCQ, if we allow it, | |
1622 | * But first we need to have the error handling in place | |
1623 | * for this mode (datasheet section 7.3.15.4.2.3). | |
1624 | * So disallow non-NCQ FBS for now. | |
1625 | */ | |
1626 | want_fbs &= want_ncq; | |
1627 | ||
08da1759 | 1628 | mv_config_fbs(ap, want_ncq, want_fbs); |
00f42eab ML |
1629 | |
1630 | if (want_fbs) { | |
1631 | pp->pp_flags |= MV_PP_FLAG_FBS_EN; | |
1632 | cfg |= EDMA_CFG_EDMA_FBS; /* FIS-based switching */ | |
1633 | } | |
1634 | ||
e728eabe | 1635 | cfg |= (1 << 23); /* do not mask PM field in rx'd FIS */ |
00b81235 ML |
1636 | if (want_edma) { |
1637 | cfg |= (1 << 22); /* enab 4-entry host queue cache */ | |
1638 | if (!IS_SOC(hpriv)) | |
1639 | cfg |= (1 << 18); /* enab early completion */ | |
1640 | } | |
616d4a98 ML |
1641 | if (hpriv->hp_flags & MV_HP_CUT_THROUGH) |
1642 | cfg |= (1 << 17); /* enab cut-thru (dis stor&forwrd) */ | |
c01e8a23 | 1643 | mv_bmdma_enable_iie(ap, !want_edma); |
000b344f ML |
1644 | |
1645 | if (IS_SOC(hpriv)) { | |
1646 | if (want_ncq) | |
1647 | mv_soc_led_blink_enable(ap); | |
1648 | else | |
1649 | mv_soc_led_blink_disable(ap); | |
1650 | } | |
e4e7b892 JG |
1651 | } |
1652 | ||
72109168 ML |
1653 | if (want_ncq) { |
1654 | cfg |= EDMA_CFG_NCQ; | |
1655 | pp->pp_flags |= MV_PP_FLAG_NCQ_EN; | |
00b81235 | 1656 | } |
72109168 | 1657 | |
cae5a29d | 1658 | writelfl(cfg, port_mmio + EDMA_CFG); |
e4e7b892 JG |
1659 | } |
1660 | ||
da2fa9ba ML |
1661 | static void mv_port_free_dma_mem(struct ata_port *ap) |
1662 | { | |
1663 | struct mv_host_priv *hpriv = ap->host->private_data; | |
1664 | struct mv_port_priv *pp = ap->private_data; | |
eb73d558 | 1665 | int tag; |
da2fa9ba ML |
1666 | |
1667 | if (pp->crqb) { | |
1668 | dma_pool_free(hpriv->crqb_pool, pp->crqb, pp->crqb_dma); | |
1669 | pp->crqb = NULL; | |
1670 | } | |
1671 | if (pp->crpb) { | |
1672 | dma_pool_free(hpriv->crpb_pool, pp->crpb, pp->crpb_dma); | |
1673 | pp->crpb = NULL; | |
1674 | } | |
eb73d558 ML |
1675 | /* |
1676 | * For GEN_I, there's no NCQ, so we have only a single sg_tbl. | |
1677 | * For later hardware, we have one unique sg_tbl per NCQ tag. | |
1678 | */ | |
1679 | for (tag = 0; tag < MV_MAX_Q_DEPTH; ++tag) { | |
1680 | if (pp->sg_tbl[tag]) { | |
1681 | if (tag == 0 || !IS_GEN_I(hpriv)) | |
1682 | dma_pool_free(hpriv->sg_tbl_pool, | |
1683 | pp->sg_tbl[tag], | |
1684 | pp->sg_tbl_dma[tag]); | |
1685 | pp->sg_tbl[tag] = NULL; | |
1686 | } | |
da2fa9ba ML |
1687 | } |
1688 | } | |
1689 | ||
05b308e1 BR |
1690 | /** |
1691 | * mv_port_start - Port specific init/start routine. | |
1692 | * @ap: ATA channel to manipulate | |
1693 | * | |
1694 | * Allocate and point to DMA memory, init port private memory, | |
1695 | * zero indices. | |
1696 | * | |
1697 | * LOCKING: | |
1698 | * Inherited from caller. | |
1699 | */ | |
31961943 BR |
1700 | static int mv_port_start(struct ata_port *ap) |
1701 | { | |
cca3974e JG |
1702 | struct device *dev = ap->host->dev; |
1703 | struct mv_host_priv *hpriv = ap->host->private_data; | |
31961943 | 1704 | struct mv_port_priv *pp; |
933cb8e5 | 1705 | unsigned long flags; |
dde20207 | 1706 | int tag; |
31961943 | 1707 | |
24dc5f33 | 1708 | pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL); |
6037d6bb | 1709 | if (!pp) |
24dc5f33 | 1710 | return -ENOMEM; |
da2fa9ba | 1711 | ap->private_data = pp; |
31961943 | 1712 | |
6ec76070 | 1713 | pp->crqb = dma_pool_zalloc(hpriv->crqb_pool, GFP_KERNEL, &pp->crqb_dma); |
da2fa9ba ML |
1714 | if (!pp->crqb) |
1715 | return -ENOMEM; | |
31961943 | 1716 | |
6ec76070 | 1717 | pp->crpb = dma_pool_zalloc(hpriv->crpb_pool, GFP_KERNEL, &pp->crpb_dma); |
da2fa9ba ML |
1718 | if (!pp->crpb) |
1719 | goto out_port_free_dma_mem; | |
31961943 | 1720 | |
3bd0a70e ML |
1721 | /* 6041/6081 Rev. "C0" (and newer) are okay with async notify */ |
1722 | if (hpriv->hp_flags & MV_HP_ERRATA_60X1C0) | |
1723 | ap->flags |= ATA_FLAG_AN; | |
eb73d558 ML |
1724 | /* |
1725 | * For GEN_I, there's no NCQ, so we only allocate a single sg_tbl. | |
1726 | * For later hardware, we need one unique sg_tbl per NCQ tag. | |
1727 | */ | |
1728 | for (tag = 0; tag < MV_MAX_Q_DEPTH; ++tag) { | |
1729 | if (tag == 0 || !IS_GEN_I(hpriv)) { | |
1730 | pp->sg_tbl[tag] = dma_pool_alloc(hpriv->sg_tbl_pool, | |
1731 | GFP_KERNEL, &pp->sg_tbl_dma[tag]); | |
1732 | if (!pp->sg_tbl[tag]) | |
1733 | goto out_port_free_dma_mem; | |
1734 | } else { | |
1735 | pp->sg_tbl[tag] = pp->sg_tbl[0]; | |
1736 | pp->sg_tbl_dma[tag] = pp->sg_tbl_dma[0]; | |
1737 | } | |
1738 | } | |
933cb8e5 ML |
1739 | |
1740 | spin_lock_irqsave(ap->lock, flags); | |
08da1759 | 1741 | mv_save_cached_regs(ap); |
66e57a2c | 1742 | mv_edma_cfg(ap, 0, 0); |
933cb8e5 ML |
1743 | spin_unlock_irqrestore(ap->lock, flags); |
1744 | ||
31961943 | 1745 | return 0; |
da2fa9ba ML |
1746 | |
1747 | out_port_free_dma_mem: | |
1748 | mv_port_free_dma_mem(ap); | |
1749 | return -ENOMEM; | |
31961943 BR |
1750 | } |
1751 | ||
05b308e1 BR |
1752 | /** |
1753 | * mv_port_stop - Port specific cleanup/stop routine. | |
1754 | * @ap: ATA channel to manipulate | |
1755 | * | |
1756 | * Stop DMA, cleanup port memory. | |
1757 | * | |
1758 | * LOCKING: | |
cca3974e | 1759 | * This routine uses the host lock to protect the DMA stop. |
05b308e1 | 1760 | */ |
31961943 BR |
1761 | static void mv_port_stop(struct ata_port *ap) |
1762 | { | |
933cb8e5 ML |
1763 | unsigned long flags; |
1764 | ||
1765 | spin_lock_irqsave(ap->lock, flags); | |
e12bef50 | 1766 | mv_stop_edma(ap); |
88e675e1 | 1767 | mv_enable_port_irqs(ap, 0); |
933cb8e5 | 1768 | spin_unlock_irqrestore(ap->lock, flags); |
da2fa9ba | 1769 | mv_port_free_dma_mem(ap); |
31961943 BR |
1770 | } |
1771 | ||
05b308e1 BR |
1772 | /** |
1773 | * mv_fill_sg - Fill out the Marvell ePRD (scatter gather) entries | |
1774 | * @qc: queued command whose SG list to source from | |
1775 | * | |
1776 | * Populate the SG list and mark the last entry. | |
1777 | * | |
1778 | * LOCKING: | |
1779 | * Inherited from caller. | |
1780 | */ | |
6c08772e | 1781 | static void mv_fill_sg(struct ata_queued_cmd *qc) |
31961943 BR |
1782 | { |
1783 | struct mv_port_priv *pp = qc->ap->private_data; | |
972c26bd | 1784 | struct scatterlist *sg; |
3be6cbd7 | 1785 | struct mv_sg *mv_sg, *last_sg = NULL; |
ff2aeb1e | 1786 | unsigned int si; |
31961943 | 1787 | |
4e5b6260 | 1788 | mv_sg = pp->sg_tbl[qc->hw_tag]; |
ff2aeb1e | 1789 | for_each_sg(qc->sg, sg, qc->n_elem, si) { |
d88184fb JG |
1790 | dma_addr_t addr = sg_dma_address(sg); |
1791 | u32 sg_len = sg_dma_len(sg); | |
22374677 | 1792 | |
4007b493 OJ |
1793 | while (sg_len) { |
1794 | u32 offset = addr & 0xffff; | |
1795 | u32 len = sg_len; | |
22374677 | 1796 | |
32cd11a6 | 1797 | if (offset + len > 0x10000) |
4007b493 OJ |
1798 | len = 0x10000 - offset; |
1799 | ||
1800 | mv_sg->addr = cpu_to_le32(addr & 0xffffffff); | |
1801 | mv_sg->addr_hi = cpu_to_le32((addr >> 16) >> 16); | |
6c08772e | 1802 | mv_sg->flags_size = cpu_to_le32(len & 0xffff); |
32cd11a6 | 1803 | mv_sg->reserved = 0; |
4007b493 OJ |
1804 | |
1805 | sg_len -= len; | |
1806 | addr += len; | |
1807 | ||
3be6cbd7 | 1808 | last_sg = mv_sg; |
4007b493 | 1809 | mv_sg++; |
4007b493 | 1810 | } |
31961943 | 1811 | } |
3be6cbd7 JG |
1812 | |
1813 | if (likely(last_sg)) | |
1814 | last_sg->flags_size |= cpu_to_le32(EPRD_FLAG_END_OF_TBL); | |
32cd11a6 | 1815 | mb(); /* ensure data structure is visible to the chipset */ |
31961943 BR |
1816 | } |
1817 | ||
5796d1c4 | 1818 | static void mv_crqb_pack_cmd(__le16 *cmdw, u8 data, u8 addr, unsigned last) |
31961943 | 1819 | { |
559eedad | 1820 | u16 tmp = data | (addr << CRQB_CMD_ADDR_SHIFT) | CRQB_CMD_CS | |
31961943 | 1821 | (last ? CRQB_CMD_LAST : 0); |
559eedad | 1822 | *cmdw = cpu_to_le16(tmp); |
31961943 BR |
1823 | } |
1824 | ||
da14265e ML |
1825 | /** |
1826 | * mv_sff_irq_clear - Clear hardware interrupt after DMA. | |
1827 | * @ap: Port associated with this ATA transaction. | |
1828 | * | |
1829 | * We need this only for ATAPI bmdma transactions, | |
1830 | * as otherwise we experience spurious interrupts | |
1831 | * after libata-sff handles the bmdma interrupts. | |
1832 | */ | |
1833 | static void mv_sff_irq_clear(struct ata_port *ap) | |
1834 | { | |
1835 | mv_clear_and_enable_port_irqs(ap, mv_ap_base(ap), ERR_IRQ); | |
1836 | } | |
1837 | ||
1838 | /** | |
1839 | * mv_check_atapi_dma - Filter ATAPI cmds which are unsuitable for DMA. | |
1840 | * @qc: queued command to check for chipset/DMA compatibility. | |
1841 | * | |
1842 | * The bmdma engines cannot handle speculative data sizes | |
1843 | * (bytecount under/over flow). So only allow DMA for | |
1844 | * data transfer commands with known data sizes. | |
1845 | * | |
1846 | * LOCKING: | |
1847 | * Inherited from caller. | |
1848 | */ | |
1849 | static int mv_check_atapi_dma(struct ata_queued_cmd *qc) | |
1850 | { | |
1851 | struct scsi_cmnd *scmd = qc->scsicmd; | |
1852 | ||
1853 | if (scmd) { | |
1854 | switch (scmd->cmnd[0]) { | |
1855 | case READ_6: | |
1856 | case READ_10: | |
1857 | case READ_12: | |
1858 | case WRITE_6: | |
1859 | case WRITE_10: | |
1860 | case WRITE_12: | |
1861 | case GPCMD_READ_CD: | |
1862 | case GPCMD_SEND_DVD_STRUCTURE: | |
1863 | case GPCMD_SEND_CUE_SHEET: | |
1864 | return 0; /* DMA is safe */ | |
1865 | } | |
1866 | } | |
1867 | return -EOPNOTSUPP; /* use PIO instead */ | |
1868 | } | |
1869 | ||
1870 | /** | |
1871 | * mv_bmdma_setup - Set up BMDMA transaction | |
1872 | * @qc: queued command to prepare DMA for. | |
1873 | * | |
1874 | * LOCKING: | |
1875 | * Inherited from caller. | |
1876 | */ | |
1877 | static void mv_bmdma_setup(struct ata_queued_cmd *qc) | |
1878 | { | |
1879 | struct ata_port *ap = qc->ap; | |
1880 | void __iomem *port_mmio = mv_ap_base(ap); | |
1881 | struct mv_port_priv *pp = ap->private_data; | |
1882 | ||
1883 | mv_fill_sg(qc); | |
1884 | ||
1885 | /* clear all DMA cmd bits */ | |
cae5a29d | 1886 | writel(0, port_mmio + BMDMA_CMD); |
da14265e ML |
1887 | |
1888 | /* load PRD table addr. */ | |
4e5b6260 | 1889 | writel((pp->sg_tbl_dma[qc->hw_tag] >> 16) >> 16, |
cae5a29d | 1890 | port_mmio + BMDMA_PRD_HIGH); |
4e5b6260 | 1891 | writelfl(pp->sg_tbl_dma[qc->hw_tag], |
cae5a29d | 1892 | port_mmio + BMDMA_PRD_LOW); |
da14265e ML |
1893 | |
1894 | /* issue r/w command */ | |
1895 | ap->ops->sff_exec_command(ap, &qc->tf); | |
1896 | } | |
1897 | ||
1898 | /** | |
1899 | * mv_bmdma_start - Start a BMDMA transaction | |
1900 | * @qc: queued command to start DMA on. | |
1901 | * | |
1902 | * LOCKING: | |
1903 | * Inherited from caller. | |
1904 | */ | |
1905 | static void mv_bmdma_start(struct ata_queued_cmd *qc) | |
1906 | { | |
1907 | struct ata_port *ap = qc->ap; | |
1908 | void __iomem *port_mmio = mv_ap_base(ap); | |
1909 | unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE); | |
1910 | u32 cmd = (rw ? 0 : ATA_DMA_WR) | ATA_DMA_START; | |
1911 | ||
1912 | /* start host DMA transaction */ | |
cae5a29d | 1913 | writelfl(cmd, port_mmio + BMDMA_CMD); |
da14265e ML |
1914 | } |
1915 | ||
1916 | /** | |
c172b359 | 1917 | * mv_bmdma_stop_ap - Stop BMDMA transfer |
f3a23c2c | 1918 | * @ap: port to stop |
da14265e ML |
1919 | * |
1920 | * Clears the ATA_DMA_START flag in the bmdma control register | |
1921 | * | |
1922 | * LOCKING: | |
1923 | * Inherited from caller. | |
1924 | */ | |
44b73380 | 1925 | static void mv_bmdma_stop_ap(struct ata_port *ap) |
da14265e | 1926 | { |
da14265e ML |
1927 | void __iomem *port_mmio = mv_ap_base(ap); |
1928 | u32 cmd; | |
1929 | ||
1930 | /* clear start/stop bit */ | |
cae5a29d | 1931 | cmd = readl(port_mmio + BMDMA_CMD); |
44b73380 ML |
1932 | if (cmd & ATA_DMA_START) { |
1933 | cmd &= ~ATA_DMA_START; | |
1934 | writelfl(cmd, port_mmio + BMDMA_CMD); | |
1935 | ||
1936 | /* one-PIO-cycle guaranteed wait, per spec, for HDMA1:0 transition */ | |
1937 | ata_sff_dma_pause(ap); | |
1938 | } | |
1939 | } | |
da14265e | 1940 | |
44b73380 ML |
1941 | static void mv_bmdma_stop(struct ata_queued_cmd *qc) |
1942 | { | |
1943 | mv_bmdma_stop_ap(qc->ap); | |
da14265e ML |
1944 | } |
1945 | ||
1946 | /** | |
1947 | * mv_bmdma_status - Read BMDMA status | |
1948 | * @ap: port for which to retrieve DMA status. | |
1949 | * | |
1950 | * Read and return equivalent of the sff BMDMA status register. | |
1951 | * | |
1952 | * LOCKING: | |
1953 | * Inherited from caller. | |
1954 | */ | |
1955 | static u8 mv_bmdma_status(struct ata_port *ap) | |
1956 | { | |
1957 | void __iomem *port_mmio = mv_ap_base(ap); | |
1958 | u32 reg, status; | |
1959 | ||
1960 | /* | |
1961 | * Other bits are valid only if ATA_DMA_ACTIVE==0, | |
1962 | * and the ATA_DMA_INTR bit doesn't exist. | |
1963 | */ | |
cae5a29d | 1964 | reg = readl(port_mmio + BMDMA_STATUS); |
da14265e ML |
1965 | if (reg & ATA_DMA_ACTIVE) |
1966 | status = ATA_DMA_ACTIVE; | |
44b73380 | 1967 | else if (reg & ATA_DMA_ERR) |
da14265e | 1968 | status = (reg & ATA_DMA_ERR) | ATA_DMA_INTR; |
44b73380 ML |
1969 | else { |
1970 | /* | |
1971 | * Just because DMA_ACTIVE is 0 (DMA completed), | |
1972 | * this does _not_ mean the device is "done". | |
1973 | * So we should not yet be signalling ATA_DMA_INTR | |
1974 | * in some cases. Eg. DSM/TRIM, and perhaps others. | |
1975 | */ | |
1976 | mv_bmdma_stop_ap(ap); | |
1977 | if (ioread8(ap->ioaddr.altstatus_addr) & ATA_BUSY) | |
1978 | status = 0; | |
1979 | else | |
1980 | status = ATA_DMA_INTR; | |
1981 | } | |
da14265e ML |
1982 | return status; |
1983 | } | |
1984 | ||
299b3f8d ML |
1985 | static void mv_rw_multi_errata_sata24(struct ata_queued_cmd *qc) |
1986 | { | |
1987 | struct ata_taskfile *tf = &qc->tf; | |
1988 | /* | |
1989 | * Workaround for 88SX60x1 FEr SATA#24. | |
1990 | * | |
1991 | * Chip may corrupt WRITEs if multi_count >= 4kB. | |
1992 | * Note that READs are unaffected. | |
1993 | * | |
1994 | * It's not clear if this errata really means "4K bytes", | |
1995 | * or if it always happens for multi_count > 7 | |
1996 | * regardless of device sector_size. | |
1997 | * | |
1998 | * So, for safety, any write with multi_count > 7 | |
1999 | * gets converted here into a regular PIO write instead: | |
2000 | */ | |
2001 | if ((tf->flags & ATA_TFLAG_WRITE) && is_multi_taskfile(tf)) { | |
2002 | if (qc->dev->multi_count > 7) { | |
2003 | switch (tf->command) { | |
2004 | case ATA_CMD_WRITE_MULTI: | |
2005 | tf->command = ATA_CMD_PIO_WRITE; | |
2006 | break; | |
2007 | case ATA_CMD_WRITE_MULTI_FUA_EXT: | |
2008 | tf->flags &= ~ATA_TFLAG_FUA; /* ugh */ | |
df561f66 | 2009 | fallthrough; |
299b3f8d ML |
2010 | case ATA_CMD_WRITE_MULTI_EXT: |
2011 | tf->command = ATA_CMD_PIO_WRITE_EXT; | |
2012 | break; | |
2013 | } | |
2014 | } | |
2015 | } | |
2016 | } | |
2017 | ||
05b308e1 BR |
2018 | /** |
2019 | * mv_qc_prep - Host specific command preparation. | |
2020 | * @qc: queued command to prepare | |
2021 | * | |
2022 | * This routine simply redirects to the general purpose routine | |
2023 | * if command is not DMA. Else, it handles prep of the CRQB | |
2024 | * (command request block), does some sanity checking, and calls | |
2025 | * the SG load routine. | |
2026 | * | |
2027 | * LOCKING: | |
2028 | * Inherited from caller. | |
2029 | */ | |
95364f36 | 2030 | static enum ata_completion_errors mv_qc_prep(struct ata_queued_cmd *qc) |
31961943 BR |
2031 | { |
2032 | struct ata_port *ap = qc->ap; | |
2033 | struct mv_port_priv *pp = ap->private_data; | |
e1469874 | 2034 | __le16 *cw; |
8d2b450d | 2035 | struct ata_taskfile *tf = &qc->tf; |
31961943 | 2036 | u16 flags = 0; |
a6432436 | 2037 | unsigned in_index; |
31961943 | 2038 | |
299b3f8d ML |
2039 | switch (tf->protocol) { |
2040 | case ATA_PROT_DMA: | |
44b73380 | 2041 | if (tf->command == ATA_CMD_DSM) |
95364f36 | 2042 | return AC_ERR_OK; |
df561f66 | 2043 | fallthrough; |
299b3f8d ML |
2044 | case ATA_PROT_NCQ: |
2045 | break; /* continue below */ | |
2046 | case ATA_PROT_PIO: | |
2047 | mv_rw_multi_errata_sata24(qc); | |
95364f36 | 2048 | return AC_ERR_OK; |
299b3f8d | 2049 | default: |
95364f36 | 2050 | return AC_ERR_OK; |
299b3f8d | 2051 | } |
20f733e7 | 2052 | |
31961943 BR |
2053 | /* Fill in command request block |
2054 | */ | |
8d2b450d | 2055 | if (!(tf->flags & ATA_TFLAG_WRITE)) |
31961943 | 2056 | flags |= CRQB_FLAG_READ; |
4e5b6260 JA |
2057 | WARN_ON(MV_MAX_Q_DEPTH <= qc->hw_tag); |
2058 | flags |= qc->hw_tag << CRQB_TAG_SHIFT; | |
e49856d8 | 2059 | flags |= (qc->dev->link->pmp & 0xf) << CRQB_PMP_SHIFT; |
31961943 | 2060 | |
bdd4ddde | 2061 | /* get current queue index from software */ |
fcfb1f77 | 2062 | in_index = pp->req_idx; |
a6432436 ML |
2063 | |
2064 | pp->crqb[in_index].sg_addr = | |
4e5b6260 | 2065 | cpu_to_le32(pp->sg_tbl_dma[qc->hw_tag] & 0xffffffff); |
a6432436 | 2066 | pp->crqb[in_index].sg_addr_hi = |
4e5b6260 | 2067 | cpu_to_le32((pp->sg_tbl_dma[qc->hw_tag] >> 16) >> 16); |
a6432436 | 2068 | pp->crqb[in_index].ctrl_flags = cpu_to_le16(flags); |
31961943 | 2069 | |
a6432436 | 2070 | cw = &pp->crqb[in_index].ata_cmd[0]; |
31961943 | 2071 | |
25985edc | 2072 | /* Sadly, the CRQB cannot accommodate all registers--there are |
31961943 BR |
2073 | * only 11 bytes...so we must pick and choose required |
2074 | * registers based on the command. So, we drop feature and | |
2075 | * hob_feature for [RW] DMA commands, but they are needed for | |
cd12e1f7 ML |
2076 | * NCQ. NCQ will drop hob_nsect, which is not needed there |
2077 | * (nsect is used only for the tag; feat/hob_feat hold true nsect). | |
20f733e7 | 2078 | */ |
31961943 BR |
2079 | switch (tf->command) { |
2080 | case ATA_CMD_READ: | |
2081 | case ATA_CMD_READ_EXT: | |
2082 | case ATA_CMD_WRITE: | |
2083 | case ATA_CMD_WRITE_EXT: | |
c15d85c8 | 2084 | case ATA_CMD_WRITE_FUA_EXT: |
31961943 BR |
2085 | mv_crqb_pack_cmd(cw++, tf->hob_nsect, ATA_REG_NSECT, 0); |
2086 | break; | |
31961943 BR |
2087 | case ATA_CMD_FPDMA_READ: |
2088 | case ATA_CMD_FPDMA_WRITE: | |
8b260248 | 2089 | mv_crqb_pack_cmd(cw++, tf->hob_feature, ATA_REG_FEATURE, 0); |
31961943 BR |
2090 | mv_crqb_pack_cmd(cw++, tf->feature, ATA_REG_FEATURE, 0); |
2091 | break; | |
31961943 BR |
2092 | default: |
2093 | /* The only other commands EDMA supports in non-queued and | |
2094 | * non-NCQ mode are: [RW] STREAM DMA and W DMA FUA EXT, none | |
2095 | * of which are defined/used by Linux. If we get here, this | |
2096 | * driver needs work. | |
31961943 | 2097 | */ |
e9f691d8 JS |
2098 | ata_port_err(ap, "%s: unsupported command: %.2x\n", __func__, |
2099 | tf->command); | |
2100 | return AC_ERR_INVALID; | |
31961943 BR |
2101 | } |
2102 | mv_crqb_pack_cmd(cw++, tf->nsect, ATA_REG_NSECT, 0); | |
2103 | mv_crqb_pack_cmd(cw++, tf->hob_lbal, ATA_REG_LBAL, 0); | |
2104 | mv_crqb_pack_cmd(cw++, tf->lbal, ATA_REG_LBAL, 0); | |
2105 | mv_crqb_pack_cmd(cw++, tf->hob_lbam, ATA_REG_LBAM, 0); | |
2106 | mv_crqb_pack_cmd(cw++, tf->lbam, ATA_REG_LBAM, 0); | |
2107 | mv_crqb_pack_cmd(cw++, tf->hob_lbah, ATA_REG_LBAH, 0); | |
2108 | mv_crqb_pack_cmd(cw++, tf->lbah, ATA_REG_LBAH, 0); | |
2109 | mv_crqb_pack_cmd(cw++, tf->device, ATA_REG_DEVICE, 0); | |
2110 | mv_crqb_pack_cmd(cw++, tf->command, ATA_REG_CMD, 1); /* last */ | |
2111 | ||
e4e7b892 | 2112 | if (!(qc->flags & ATA_QCFLAG_DMAMAP)) |
95364f36 | 2113 | return AC_ERR_OK; |
e4e7b892 | 2114 | mv_fill_sg(qc); |
95364f36 JS |
2115 | |
2116 | return AC_ERR_OK; | |
e4e7b892 JG |
2117 | } |
2118 | ||
2119 | /** | |
2120 | * mv_qc_prep_iie - Host specific command preparation. | |
2121 | * @qc: queued command to prepare | |
2122 | * | |
2123 | * This routine simply redirects to the general purpose routine | |
2124 | * if command is not DMA. Else, it handles prep of the CRQB | |
2125 | * (command request block), does some sanity checking, and calls | |
2126 | * the SG load routine. | |
2127 | * | |
2128 | * LOCKING: | |
2129 | * Inherited from caller. | |
2130 | */ | |
95364f36 | 2131 | static enum ata_completion_errors mv_qc_prep_iie(struct ata_queued_cmd *qc) |
e4e7b892 JG |
2132 | { |
2133 | struct ata_port *ap = qc->ap; | |
2134 | struct mv_port_priv *pp = ap->private_data; | |
2135 | struct mv_crqb_iie *crqb; | |
8d2b450d | 2136 | struct ata_taskfile *tf = &qc->tf; |
a6432436 | 2137 | unsigned in_index; |
e4e7b892 JG |
2138 | u32 flags = 0; |
2139 | ||
8d2b450d ML |
2140 | if ((tf->protocol != ATA_PROT_DMA) && |
2141 | (tf->protocol != ATA_PROT_NCQ)) | |
95364f36 | 2142 | return AC_ERR_OK; |
44b73380 | 2143 | if (tf->command == ATA_CMD_DSM) |
95364f36 | 2144 | return AC_ERR_OK; /* use bmdma for this */ |
e4e7b892 | 2145 | |
e12bef50 | 2146 | /* Fill in Gen IIE command request block */ |
8d2b450d | 2147 | if (!(tf->flags & ATA_TFLAG_WRITE)) |
e4e7b892 JG |
2148 | flags |= CRQB_FLAG_READ; |
2149 | ||
4e5b6260 JA |
2150 | WARN_ON(MV_MAX_Q_DEPTH <= qc->hw_tag); |
2151 | flags |= qc->hw_tag << CRQB_TAG_SHIFT; | |
2152 | flags |= qc->hw_tag << CRQB_HOSTQ_SHIFT; | |
e49856d8 | 2153 | flags |= (qc->dev->link->pmp & 0xf) << CRQB_PMP_SHIFT; |
e4e7b892 | 2154 | |
bdd4ddde | 2155 | /* get current queue index from software */ |
fcfb1f77 | 2156 | in_index = pp->req_idx; |
a6432436 ML |
2157 | |
2158 | crqb = (struct mv_crqb_iie *) &pp->crqb[in_index]; | |
4e5b6260 JA |
2159 | crqb->addr = cpu_to_le32(pp->sg_tbl_dma[qc->hw_tag] & 0xffffffff); |
2160 | crqb->addr_hi = cpu_to_le32((pp->sg_tbl_dma[qc->hw_tag] >> 16) >> 16); | |
e4e7b892 JG |
2161 | crqb->flags = cpu_to_le32(flags); |
2162 | ||
e4e7b892 JG |
2163 | crqb->ata_cmd[0] = cpu_to_le32( |
2164 | (tf->command << 16) | | |
2165 | (tf->feature << 24) | |
2166 | ); | |
2167 | crqb->ata_cmd[1] = cpu_to_le32( | |
2168 | (tf->lbal << 0) | | |
2169 | (tf->lbam << 8) | | |
2170 | (tf->lbah << 16) | | |
2171 | (tf->device << 24) | |
2172 | ); | |
2173 | crqb->ata_cmd[2] = cpu_to_le32( | |
2174 | (tf->hob_lbal << 0) | | |
2175 | (tf->hob_lbam << 8) | | |
2176 | (tf->hob_lbah << 16) | | |
2177 | (tf->hob_feature << 24) | |
2178 | ); | |
2179 | crqb->ata_cmd[3] = cpu_to_le32( | |
2180 | (tf->nsect << 0) | | |
2181 | (tf->hob_nsect << 8) | |
2182 | ); | |
2183 | ||
2184 | if (!(qc->flags & ATA_QCFLAG_DMAMAP)) | |
95364f36 | 2185 | return AC_ERR_OK; |
31961943 | 2186 | mv_fill_sg(qc); |
95364f36 JS |
2187 | |
2188 | return AC_ERR_OK; | |
31961943 BR |
2189 | } |
2190 | ||
d16ab3f6 ML |
2191 | /** |
2192 | * mv_sff_check_status - fetch device status, if valid | |
2193 | * @ap: ATA port to fetch status from | |
2194 | * | |
2195 | * When using command issue via mv_qc_issue_fis(), | |
2196 | * the initial ATA_BUSY state does not show up in the | |
2197 | * ATA status (shadow) register. This can confuse libata! | |
2198 | * | |
2199 | * So we have a hook here to fake ATA_BUSY for that situation, | |
2200 | * until the first time a BUSY, DRQ, or ERR bit is seen. | |
2201 | * | |
2202 | * The rest of the time, it simply returns the ATA status register. | |
2203 | */ | |
2204 | static u8 mv_sff_check_status(struct ata_port *ap) | |
2205 | { | |
2206 | u8 stat = ioread8(ap->ioaddr.status_addr); | |
2207 | struct mv_port_priv *pp = ap->private_data; | |
2208 | ||
2209 | if (pp->pp_flags & MV_PP_FLAG_FAKE_ATA_BUSY) { | |
2210 | if (stat & (ATA_BUSY | ATA_DRQ | ATA_ERR)) | |
2211 | pp->pp_flags &= ~MV_PP_FLAG_FAKE_ATA_BUSY; | |
2212 | else | |
2213 | stat = ATA_BUSY; | |
2214 | } | |
2215 | return stat; | |
2216 | } | |
2217 | ||
70f8b79c ML |
2218 | /** |
2219 | * mv_send_fis - Send a FIS, using the "Vendor-Unique FIS" register | |
f3a23c2c | 2220 | * @ap: ATA port to send a FIS |
70f8b79c ML |
2221 | * @fis: fis to be sent |
2222 | * @nwords: number of 32-bit words in the fis | |
2223 | */ | |
2224 | static unsigned int mv_send_fis(struct ata_port *ap, u32 *fis, int nwords) | |
2225 | { | |
2226 | void __iomem *port_mmio = mv_ap_base(ap); | |
2227 | u32 ifctl, old_ifctl, ifstat; | |
2228 | int i, timeout = 200, final_word = nwords - 1; | |
2229 | ||
2230 | /* Initiate FIS transmission mode */ | |
cae5a29d | 2231 | old_ifctl = readl(port_mmio + SATA_IFCTL); |
70f8b79c | 2232 | ifctl = 0x100 | (old_ifctl & 0xf); |
cae5a29d | 2233 | writelfl(ifctl, port_mmio + SATA_IFCTL); |
70f8b79c ML |
2234 | |
2235 | /* Send all words of the FIS except for the final word */ | |
2236 | for (i = 0; i < final_word; ++i) | |
cae5a29d | 2237 | writel(fis[i], port_mmio + VENDOR_UNIQUE_FIS); |
70f8b79c ML |
2238 | |
2239 | /* Flag end-of-transmission, and then send the final word */ | |
cae5a29d ML |
2240 | writelfl(ifctl | 0x200, port_mmio + SATA_IFCTL); |
2241 | writelfl(fis[final_word], port_mmio + VENDOR_UNIQUE_FIS); | |
70f8b79c ML |
2242 | |
2243 | /* | |
2244 | * Wait for FIS transmission to complete. | |
2245 | * This typically takes just a single iteration. | |
2246 | */ | |
2247 | do { | |
cae5a29d | 2248 | ifstat = readl(port_mmio + SATA_IFSTAT); |
70f8b79c ML |
2249 | } while (!(ifstat & 0x1000) && --timeout); |
2250 | ||
2251 | /* Restore original port configuration */ | |
cae5a29d | 2252 | writelfl(old_ifctl, port_mmio + SATA_IFCTL); |
70f8b79c ML |
2253 | |
2254 | /* See if it worked */ | |
2255 | if ((ifstat & 0x3000) != 0x1000) { | |
a9a79dfe JP |
2256 | ata_port_warn(ap, "%s transmission error, ifstat=%08x\n", |
2257 | __func__, ifstat); | |
70f8b79c ML |
2258 | return AC_ERR_OTHER; |
2259 | } | |
2260 | return 0; | |
2261 | } | |
2262 | ||
2263 | /** | |
2264 | * mv_qc_issue_fis - Issue a command directly as a FIS | |
2265 | * @qc: queued command to start | |
2266 | * | |
2267 | * Note that the ATA shadow registers are not updated | |
2268 | * after command issue, so the device will appear "READY" | |
2269 | * if polled, even while it is BUSY processing the command. | |
2270 | * | |
2271 | * So we use a status hook to fake ATA_BUSY until the drive changes state. | |
2272 | * | |
2273 | * Note: we don't get updated shadow regs on *completion* | |
2274 | * of non-data commands. So avoid sending them via this function, | |
2275 | * as they will appear to have completed immediately. | |
2276 | * | |
2277 | * GEN_IIE has special registers that we could get the result tf from, | |
2278 | * but earlier chipsets do not. For now, we ignore those registers. | |
2279 | */ | |
2280 | static unsigned int mv_qc_issue_fis(struct ata_queued_cmd *qc) | |
2281 | { | |
2282 | struct ata_port *ap = qc->ap; | |
2283 | struct mv_port_priv *pp = ap->private_data; | |
2284 | struct ata_link *link = qc->dev->link; | |
2285 | u32 fis[5]; | |
2286 | int err = 0; | |
2287 | ||
2288 | ata_tf_to_fis(&qc->tf, link->pmp, 1, (void *)fis); | |
4c4a90fd | 2289 | err = mv_send_fis(ap, fis, ARRAY_SIZE(fis)); |
70f8b79c ML |
2290 | if (err) |
2291 | return err; | |
2292 | ||
2293 | switch (qc->tf.protocol) { | |
2294 | case ATAPI_PROT_PIO: | |
2295 | pp->pp_flags |= MV_PP_FLAG_FAKE_ATA_BUSY; | |
df561f66 | 2296 | fallthrough; |
70f8b79c ML |
2297 | case ATAPI_PROT_NODATA: |
2298 | ap->hsm_task_state = HSM_ST_FIRST; | |
2299 | break; | |
2300 | case ATA_PROT_PIO: | |
2301 | pp->pp_flags |= MV_PP_FLAG_FAKE_ATA_BUSY; | |
2302 | if (qc->tf.flags & ATA_TFLAG_WRITE) | |
2303 | ap->hsm_task_state = HSM_ST_FIRST; | |
2304 | else | |
2305 | ap->hsm_task_state = HSM_ST; | |
2306 | break; | |
2307 | default: | |
2308 | ap->hsm_task_state = HSM_ST_LAST; | |
2309 | break; | |
2310 | } | |
2311 | ||
2312 | if (qc->tf.flags & ATA_TFLAG_POLLING) | |
ea3c6450 | 2313 | ata_sff_queue_pio_task(link, 0); |
70f8b79c ML |
2314 | return 0; |
2315 | } | |
2316 | ||
05b308e1 BR |
2317 | /** |
2318 | * mv_qc_issue - Initiate a command to the host | |
2319 | * @qc: queued command to start | |
2320 | * | |
2321 | * This routine simply redirects to the general purpose routine | |
2322 | * if command is not DMA. Else, it sanity checks our local | |
2323 | * caches of the request producer/consumer indices then enables | |
2324 | * DMA and bumps the request producer index. | |
2325 | * | |
2326 | * LOCKING: | |
2327 | * Inherited from caller. | |
2328 | */ | |
9a3d9eb0 | 2329 | static unsigned int mv_qc_issue(struct ata_queued_cmd *qc) |
31961943 | 2330 | { |
f48765cc | 2331 | static int limit_warnings = 10; |
c5d3e45a JG |
2332 | struct ata_port *ap = qc->ap; |
2333 | void __iomem *port_mmio = mv_ap_base(ap); | |
2334 | struct mv_port_priv *pp = ap->private_data; | |
bdd4ddde | 2335 | u32 in_index; |
42ed893d | 2336 | unsigned int port_irqs; |
f48765cc | 2337 | |
d16ab3f6 ML |
2338 | pp->pp_flags &= ~MV_PP_FLAG_FAKE_ATA_BUSY; /* paranoia */ |
2339 | ||
f48765cc ML |
2340 | switch (qc->tf.protocol) { |
2341 | case ATA_PROT_DMA: | |
44b73380 ML |
2342 | if (qc->tf.command == ATA_CMD_DSM) { |
2343 | if (!ap->ops->bmdma_setup) /* no bmdma on GEN_I */ | |
2344 | return AC_ERR_OTHER; | |
2345 | break; /* use bmdma for this */ | |
2346 | } | |
df561f66 | 2347 | fallthrough; |
f48765cc ML |
2348 | case ATA_PROT_NCQ: |
2349 | mv_start_edma(ap, port_mmio, pp, qc->tf.protocol); | |
2350 | pp->req_idx = (pp->req_idx + 1) & MV_MAX_Q_DEPTH_MASK; | |
2351 | in_index = pp->req_idx << EDMA_REQ_Q_PTR_SHIFT; | |
2352 | ||
2353 | /* Write the request in pointer to kick the EDMA to life */ | |
2354 | writelfl((pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK) | in_index, | |
cae5a29d | 2355 | port_mmio + EDMA_REQ_Q_IN_PTR); |
f48765cc | 2356 | return 0; |
31961943 | 2357 | |
f48765cc | 2358 | case ATA_PROT_PIO: |
c6112bd8 ML |
2359 | /* |
2360 | * Errata SATA#16, SATA#24: warn if multiple DRQs expected. | |
2361 | * | |
2362 | * Someday, we might implement special polling workarounds | |
2363 | * for these, but it all seems rather unnecessary since we | |
2364 | * normally use only DMA for commands which transfer more | |
2365 | * than a single block of data. | |
2366 | * | |
2367 | * Much of the time, this could just work regardless. | |
2368 | * So for now, just log the incident, and allow the attempt. | |
2369 | */ | |
c7843e8f | 2370 | if (limit_warnings > 0 && (qc->nbytes / qc->sect_size) > 1) { |
c6112bd8 | 2371 | --limit_warnings; |
a9a79dfe JP |
2372 | ata_link_warn(qc->dev->link, DRV_NAME |
2373 | ": attempting PIO w/multiple DRQ: " | |
2374 | "this may fail due to h/w errata\n"); | |
c6112bd8 | 2375 | } |
df561f66 | 2376 | fallthrough; |
42ed893d | 2377 | case ATA_PROT_NODATA: |
f48765cc | 2378 | case ATAPI_PROT_PIO: |
42ed893d ML |
2379 | case ATAPI_PROT_NODATA: |
2380 | if (ap->flags & ATA_FLAG_PIO_POLLING) | |
2381 | qc->tf.flags |= ATA_TFLAG_POLLING; | |
2382 | break; | |
31961943 | 2383 | } |
42ed893d ML |
2384 | |
2385 | if (qc->tf.flags & ATA_TFLAG_POLLING) | |
2386 | port_irqs = ERR_IRQ; /* mask device interrupt when polling */ | |
2387 | else | |
2388 | port_irqs = ERR_IRQ | DONE_IRQ; /* unmask all interrupts */ | |
2389 | ||
2390 | /* | |
2391 | * We're about to send a non-EDMA capable command to the | |
2392 | * port. Turn off EDMA so there won't be problems accessing | |
2393 | * shadow block, etc registers. | |
2394 | */ | |
2395 | mv_stop_edma(ap); | |
2396 | mv_clear_and_enable_port_irqs(ap, mv_ap_base(ap), port_irqs); | |
2397 | mv_pmp_select(ap, qc->dev->link->pmp); | |
70f8b79c ML |
2398 | |
2399 | if (qc->tf.command == ATA_CMD_READ_LOG_EXT) { | |
2400 | struct mv_host_priv *hpriv = ap->host->private_data; | |
2401 | /* | |
2402 | * Workaround for 88SX60x1 FEr SATA#25 (part 2). | |
40f21b11 | 2403 | * |
70f8b79c ML |
2404 | * After any NCQ error, the READ_LOG_EXT command |
2405 | * from libata-eh *must* use mv_qc_issue_fis(). | |
2406 | * Otherwise it might fail, due to chip errata. | |
2407 | * | |
2408 | * Rather than special-case it, we'll just *always* | |
2409 | * use this method here for READ_LOG_EXT, making for | |
2410 | * easier testing. | |
2411 | */ | |
2412 | if (IS_GEN_II(hpriv)) | |
2413 | return mv_qc_issue_fis(qc); | |
2414 | } | |
360ff783 | 2415 | return ata_bmdma_qc_issue(qc); |
31961943 BR |
2416 | } |
2417 | ||
8f767f8a ML |
2418 | static struct ata_queued_cmd *mv_get_active_qc(struct ata_port *ap) |
2419 | { | |
2420 | struct mv_port_priv *pp = ap->private_data; | |
2421 | struct ata_queued_cmd *qc; | |
2422 | ||
2423 | if (pp->pp_flags & MV_PP_FLAG_NCQ_EN) | |
2424 | return NULL; | |
2425 | qc = ata_qc_from_tag(ap, ap->link.active_tag); | |
3e4ec344 TH |
2426 | if (qc && !(qc->tf.flags & ATA_TFLAG_POLLING)) |
2427 | return qc; | |
2428 | return NULL; | |
8f767f8a ML |
2429 | } |
2430 | ||
29d187bb ML |
2431 | static void mv_pmp_error_handler(struct ata_port *ap) |
2432 | { | |
2433 | unsigned int pmp, pmp_map; | |
2434 | struct mv_port_priv *pp = ap->private_data; | |
2435 | ||
2436 | if (pp->pp_flags & MV_PP_FLAG_DELAYED_EH) { | |
2437 | /* | |
2438 | * Perform NCQ error analysis on failed PMPs | |
2439 | * before we freeze the port entirely. | |
2440 | * | |
2441 | * The failed PMPs are marked earlier by mv_pmp_eh_prep(). | |
2442 | */ | |
2443 | pmp_map = pp->delayed_eh_pmp_map; | |
2444 | pp->pp_flags &= ~MV_PP_FLAG_DELAYED_EH; | |
2445 | for (pmp = 0; pmp_map != 0; pmp++) { | |
2446 | unsigned int this_pmp = (1 << pmp); | |
2447 | if (pmp_map & this_pmp) { | |
2448 | struct ata_link *link = &ap->pmp_link[pmp]; | |
2449 | pmp_map &= ~this_pmp; | |
2450 | ata_eh_analyze_ncq_error(link); | |
2451 | } | |
2452 | } | |
2453 | ata_port_freeze(ap); | |
2454 | } | |
2455 | sata_pmp_error_handler(ap); | |
2456 | } | |
2457 | ||
4c299ca3 ML |
2458 | static unsigned int mv_get_err_pmp_map(struct ata_port *ap) |
2459 | { | |
2460 | void __iomem *port_mmio = mv_ap_base(ap); | |
2461 | ||
cae5a29d | 2462 | return readl(port_mmio + SATA_TESTCTL) >> 16; |
4c299ca3 ML |
2463 | } |
2464 | ||
4c299ca3 ML |
2465 | static void mv_pmp_eh_prep(struct ata_port *ap, unsigned int pmp_map) |
2466 | { | |
4c299ca3 ML |
2467 | unsigned int pmp; |
2468 | ||
2469 | /* | |
2470 | * Initialize EH info for PMPs which saw device errors | |
2471 | */ | |
4c299ca3 ML |
2472 | for (pmp = 0; pmp_map != 0; pmp++) { |
2473 | unsigned int this_pmp = (1 << pmp); | |
2474 | if (pmp_map & this_pmp) { | |
2475 | struct ata_link *link = &ap->pmp_link[pmp]; | |
14d7045c | 2476 | struct ata_eh_info *ehi = &link->eh_info; |
4c299ca3 ML |
2477 | |
2478 | pmp_map &= ~this_pmp; | |
4c299ca3 ML |
2479 | ata_ehi_clear_desc(ehi); |
2480 | ata_ehi_push_desc(ehi, "dev err"); | |
2481 | ehi->err_mask |= AC_ERR_DEV; | |
2482 | ehi->action |= ATA_EH_RESET; | |
2483 | ata_link_abort(link); | |
2484 | } | |
2485 | } | |
2486 | } | |
2487 | ||
06aaca3f ML |
2488 | static int mv_req_q_empty(struct ata_port *ap) |
2489 | { | |
2490 | void __iomem *port_mmio = mv_ap_base(ap); | |
2491 | u32 in_ptr, out_ptr; | |
2492 | ||
cae5a29d | 2493 | in_ptr = (readl(port_mmio + EDMA_REQ_Q_IN_PTR) |
06aaca3f | 2494 | >> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK; |
cae5a29d | 2495 | out_ptr = (readl(port_mmio + EDMA_REQ_Q_OUT_PTR) |
06aaca3f ML |
2496 | >> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK; |
2497 | return (in_ptr == out_ptr); /* 1 == queue_is_empty */ | |
2498 | } | |
2499 | ||
4c299ca3 ML |
2500 | static int mv_handle_fbs_ncq_dev_err(struct ata_port *ap) |
2501 | { | |
2502 | struct mv_port_priv *pp = ap->private_data; | |
2503 | int failed_links; | |
2504 | unsigned int old_map, new_map; | |
2505 | ||
2506 | /* | |
2507 | * Device error during FBS+NCQ operation: | |
2508 | * | |
2509 | * Set a port flag to prevent further I/O being enqueued. | |
2510 | * Leave the EDMA running to drain outstanding commands from this port. | |
2511 | * Perform the post-mortem/EH only when all responses are complete. | |
2512 | * Follow recovery sequence from 6042/7042 datasheet (7.3.15.4.2.2). | |
2513 | */ | |
2514 | if (!(pp->pp_flags & MV_PP_FLAG_DELAYED_EH)) { | |
2515 | pp->pp_flags |= MV_PP_FLAG_DELAYED_EH; | |
2516 | pp->delayed_eh_pmp_map = 0; | |
2517 | } | |
2518 | old_map = pp->delayed_eh_pmp_map; | |
2519 | new_map = old_map | mv_get_err_pmp_map(ap); | |
2520 | ||
2521 | if (old_map != new_map) { | |
2522 | pp->delayed_eh_pmp_map = new_map; | |
2523 | mv_pmp_eh_prep(ap, new_map & ~old_map); | |
2524 | } | |
c46938cc | 2525 | failed_links = hweight16(new_map); |
4c299ca3 | 2526 | |
a9a79dfe | 2527 | ata_port_info(ap, |
e3ed8939 | 2528 | "%s: pmp_map=%04x qc_map=%04llx failed_links=%d nr_active_links=%d\n", |
a9a79dfe JP |
2529 | __func__, pp->delayed_eh_pmp_map, |
2530 | ap->qc_active, failed_links, | |
2531 | ap->nr_active_links); | |
4c299ca3 | 2532 | |
06aaca3f | 2533 | if (ap->nr_active_links <= failed_links && mv_req_q_empty(ap)) { |
4c299ca3 ML |
2534 | mv_process_crpb_entries(ap, pp); |
2535 | mv_stop_edma(ap); | |
2536 | mv_eh_freeze(ap); | |
a9a79dfe | 2537 | ata_port_info(ap, "%s: done\n", __func__); |
4c299ca3 ML |
2538 | return 1; /* handled */ |
2539 | } | |
a9a79dfe | 2540 | ata_port_info(ap, "%s: waiting\n", __func__); |
4c299ca3 ML |
2541 | return 1; /* handled */ |
2542 | } | |
2543 | ||
2544 | static int mv_handle_fbs_non_ncq_dev_err(struct ata_port *ap) | |
2545 | { | |
2546 | /* | |
2547 | * Possible future enhancement: | |
2548 | * | |
2549 | * FBS+non-NCQ operation is not yet implemented. | |
2550 | * See related notes in mv_edma_cfg(). | |
2551 | * | |
2552 | * Device error during FBS+non-NCQ operation: | |
2553 | * | |
2554 | * We need to snapshot the shadow registers for each failed command. | |
2555 | * Follow recovery sequence from 6042/7042 datasheet (7.3.15.4.2.3). | |
2556 | */ | |
2557 | return 0; /* not handled */ | |
2558 | } | |
2559 | ||
2560 | static int mv_handle_dev_err(struct ata_port *ap, u32 edma_err_cause) | |
2561 | { | |
2562 | struct mv_port_priv *pp = ap->private_data; | |
2563 | ||
2564 | if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN)) | |
2565 | return 0; /* EDMA was not active: not handled */ | |
2566 | if (!(pp->pp_flags & MV_PP_FLAG_FBS_EN)) | |
2567 | return 0; /* FBS was not active: not handled */ | |
2568 | ||
2569 | if (!(edma_err_cause & EDMA_ERR_DEV)) | |
2570 | return 0; /* non DEV error: not handled */ | |
2571 | edma_err_cause &= ~EDMA_ERR_IRQ_TRANSIENT; | |
2572 | if (edma_err_cause & ~(EDMA_ERR_DEV | EDMA_ERR_SELF_DIS)) | |
2573 | return 0; /* other problems: not handled */ | |
2574 | ||
2575 | if (pp->pp_flags & MV_PP_FLAG_NCQ_EN) { | |
2576 | /* | |
2577 | * EDMA should NOT have self-disabled for this case. | |
2578 | * If it did, then something is wrong elsewhere, | |
2579 | * and we cannot handle it here. | |
2580 | */ | |
2581 | if (edma_err_cause & EDMA_ERR_SELF_DIS) { | |
a9a79dfe JP |
2582 | ata_port_warn(ap, "%s: err_cause=0x%x pp_flags=0x%x\n", |
2583 | __func__, edma_err_cause, pp->pp_flags); | |
4c299ca3 ML |
2584 | return 0; /* not handled */ |
2585 | } | |
2586 | return mv_handle_fbs_ncq_dev_err(ap); | |
2587 | } else { | |
2588 | /* | |
2589 | * EDMA should have self-disabled for this case. | |
2590 | * If it did not, then something is wrong elsewhere, | |
2591 | * and we cannot handle it here. | |
2592 | */ | |
2593 | if (!(edma_err_cause & EDMA_ERR_SELF_DIS)) { | |
a9a79dfe JP |
2594 | ata_port_warn(ap, "%s: err_cause=0x%x pp_flags=0x%x\n", |
2595 | __func__, edma_err_cause, pp->pp_flags); | |
4c299ca3 ML |
2596 | return 0; /* not handled */ |
2597 | } | |
2598 | return mv_handle_fbs_non_ncq_dev_err(ap); | |
2599 | } | |
2600 | return 0; /* not handled */ | |
2601 | } | |
2602 | ||
a9010329 | 2603 | static void mv_unexpected_intr(struct ata_port *ap, int edma_was_enabled) |
8f767f8a | 2604 | { |
8f767f8a | 2605 | struct ata_eh_info *ehi = &ap->link.eh_info; |
a9010329 | 2606 | char *when = "idle"; |
8f767f8a | 2607 | |
8f767f8a | 2608 | ata_ehi_clear_desc(ehi); |
3e4ec344 | 2609 | if (edma_was_enabled) { |
a9010329 | 2610 | when = "EDMA enabled"; |
8f767f8a ML |
2611 | } else { |
2612 | struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->link.active_tag); | |
2613 | if (qc && (qc->tf.flags & ATA_TFLAG_POLLING)) | |
a9010329 | 2614 | when = "polling"; |
8f767f8a | 2615 | } |
a9010329 | 2616 | ata_ehi_push_desc(ehi, "unexpected device interrupt while %s", when); |
8f767f8a ML |
2617 | ehi->err_mask |= AC_ERR_OTHER; |
2618 | ehi->action |= ATA_EH_RESET; | |
2619 | ata_port_freeze(ap); | |
2620 | } | |
2621 | ||
05b308e1 BR |
2622 | /** |
2623 | * mv_err_intr - Handle error interrupts on the port | |
2624 | * @ap: ATA channel to manipulate | |
2625 | * | |
8d07379d ML |
2626 | * Most cases require a full reset of the chip's state machine, |
2627 | * which also performs a COMRESET. | |
2628 | * Also, if the port disabled DMA, update our cached copy to match. | |
05b308e1 BR |
2629 | * |
2630 | * LOCKING: | |
2631 | * Inherited from caller. | |
2632 | */ | |
37b9046a | 2633 | static void mv_err_intr(struct ata_port *ap) |
31961943 BR |
2634 | { |
2635 | void __iomem *port_mmio = mv_ap_base(ap); | |
bdd4ddde | 2636 | u32 edma_err_cause, eh_freeze_mask, serr = 0; |
e4006077 | 2637 | u32 fis_cause = 0; |
bdd4ddde JG |
2638 | struct mv_port_priv *pp = ap->private_data; |
2639 | struct mv_host_priv *hpriv = ap->host->private_data; | |
bdd4ddde | 2640 | unsigned int action = 0, err_mask = 0; |
9af5c9c9 | 2641 | struct ata_eh_info *ehi = &ap->link.eh_info; |
37b9046a ML |
2642 | struct ata_queued_cmd *qc; |
2643 | int abort = 0; | |
20f733e7 | 2644 | |
8d07379d | 2645 | /* |
37b9046a | 2646 | * Read and clear the SError and err_cause bits. |
e4006077 ML |
2647 | * For GenIIe, if EDMA_ERR_TRANS_IRQ_7 is set, we also must read/clear |
2648 | * the FIS_IRQ_CAUSE register before clearing edma_err_cause. | |
8d07379d | 2649 | */ |
37b9046a ML |
2650 | sata_scr_read(&ap->link, SCR_ERROR, &serr); |
2651 | sata_scr_write_flush(&ap->link, SCR_ERROR, serr); | |
2652 | ||
cae5a29d | 2653 | edma_err_cause = readl(port_mmio + EDMA_ERR_IRQ_CAUSE); |
e4006077 | 2654 | if (IS_GEN_IIE(hpriv) && (edma_err_cause & EDMA_ERR_TRANS_IRQ_7)) { |
cae5a29d ML |
2655 | fis_cause = readl(port_mmio + FIS_IRQ_CAUSE); |
2656 | writelfl(~fis_cause, port_mmio + FIS_IRQ_CAUSE); | |
e4006077 | 2657 | } |
cae5a29d | 2658 | writelfl(~edma_err_cause, port_mmio + EDMA_ERR_IRQ_CAUSE); |
bdd4ddde | 2659 | |
4c299ca3 ML |
2660 | if (edma_err_cause & EDMA_ERR_DEV) { |
2661 | /* | |
2662 | * Device errors during FIS-based switching operation | |
2663 | * require special handling. | |
2664 | */ | |
2665 | if (mv_handle_dev_err(ap, edma_err_cause)) | |
2666 | return; | |
2667 | } | |
2668 | ||
37b9046a ML |
2669 | qc = mv_get_active_qc(ap); |
2670 | ata_ehi_clear_desc(ehi); | |
2671 | ata_ehi_push_desc(ehi, "edma_err_cause=%08x pp_flags=%08x", | |
2672 | edma_err_cause, pp->pp_flags); | |
e4006077 | 2673 | |
c443c500 | 2674 | if (IS_GEN_IIE(hpriv) && (edma_err_cause & EDMA_ERR_TRANS_IRQ_7)) { |
e4006077 | 2675 | ata_ehi_push_desc(ehi, "fis_cause=%08x", fis_cause); |
cae5a29d | 2676 | if (fis_cause & FIS_IRQ_CAUSE_AN) { |
c443c500 ML |
2677 | u32 ec = edma_err_cause & |
2678 | ~(EDMA_ERR_TRANS_IRQ_7 | EDMA_ERR_IRQ_TRANSIENT); | |
2679 | sata_async_notification(ap); | |
2680 | if (!ec) | |
2681 | return; /* Just an AN; no need for the nukes */ | |
2682 | ata_ehi_push_desc(ehi, "SDB notify"); | |
2683 | } | |
2684 | } | |
bdd4ddde | 2685 | /* |
352fab70 | 2686 | * All generations share these EDMA error cause bits: |
bdd4ddde | 2687 | */ |
37b9046a | 2688 | if (edma_err_cause & EDMA_ERR_DEV) { |
bdd4ddde | 2689 | err_mask |= AC_ERR_DEV; |
37b9046a ML |
2690 | action |= ATA_EH_RESET; |
2691 | ata_ehi_push_desc(ehi, "dev error"); | |
2692 | } | |
bdd4ddde | 2693 | if (edma_err_cause & (EDMA_ERR_D_PAR | EDMA_ERR_PRD_PAR | |
6c1153e0 | 2694 | EDMA_ERR_CRQB_PAR | EDMA_ERR_CRPB_PAR | |
bdd4ddde JG |
2695 | EDMA_ERR_INTRL_PAR)) { |
2696 | err_mask |= AC_ERR_ATA_BUS; | |
cf480626 | 2697 | action |= ATA_EH_RESET; |
b64bbc39 | 2698 | ata_ehi_push_desc(ehi, "parity error"); |
bdd4ddde JG |
2699 | } |
2700 | if (edma_err_cause & (EDMA_ERR_DEV_DCON | EDMA_ERR_DEV_CON)) { | |
2701 | ata_ehi_hotplugged(ehi); | |
2702 | ata_ehi_push_desc(ehi, edma_err_cause & EDMA_ERR_DEV_DCON ? | |
b64bbc39 | 2703 | "dev disconnect" : "dev connect"); |
cf480626 | 2704 | action |= ATA_EH_RESET; |
bdd4ddde JG |
2705 | } |
2706 | ||
352fab70 ML |
2707 | /* |
2708 | * Gen-I has a different SELF_DIS bit, | |
2709 | * different FREEZE bits, and no SERR bit: | |
2710 | */ | |
ee9ccdf7 | 2711 | if (IS_GEN_I(hpriv)) { |
bdd4ddde | 2712 | eh_freeze_mask = EDMA_EH_FREEZE_5; |
bdd4ddde | 2713 | if (edma_err_cause & EDMA_ERR_SELF_DIS_5) { |
bdd4ddde | 2714 | pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN; |
b64bbc39 | 2715 | ata_ehi_push_desc(ehi, "EDMA self-disable"); |
bdd4ddde JG |
2716 | } |
2717 | } else { | |
2718 | eh_freeze_mask = EDMA_EH_FREEZE; | |
bdd4ddde | 2719 | if (edma_err_cause & EDMA_ERR_SELF_DIS) { |
bdd4ddde | 2720 | pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN; |
b64bbc39 | 2721 | ata_ehi_push_desc(ehi, "EDMA self-disable"); |
bdd4ddde | 2722 | } |
bdd4ddde | 2723 | if (edma_err_cause & EDMA_ERR_SERR) { |
8d07379d ML |
2724 | ata_ehi_push_desc(ehi, "SError=%08x", serr); |
2725 | err_mask |= AC_ERR_ATA_BUS; | |
cf480626 | 2726 | action |= ATA_EH_RESET; |
bdd4ddde | 2727 | } |
afb0edd9 | 2728 | } |
20f733e7 | 2729 | |
bdd4ddde JG |
2730 | if (!err_mask) { |
2731 | err_mask = AC_ERR_OTHER; | |
cf480626 | 2732 | action |= ATA_EH_RESET; |
bdd4ddde JG |
2733 | } |
2734 | ||
2735 | ehi->serror |= serr; | |
2736 | ehi->action |= action; | |
2737 | ||
2738 | if (qc) | |
2739 | qc->err_mask |= err_mask; | |
2740 | else | |
2741 | ehi->err_mask |= err_mask; | |
2742 | ||
37b9046a ML |
2743 | if (err_mask == AC_ERR_DEV) { |
2744 | /* | |
2745 | * Cannot do ata_port_freeze() here, | |
2746 | * because it would kill PIO access, | |
2747 | * which is needed for further diagnosis. | |
2748 | */ | |
2749 | mv_eh_freeze(ap); | |
2750 | abort = 1; | |
2751 | } else if (edma_err_cause & eh_freeze_mask) { | |
2752 | /* | |
2753 | * Note to self: ata_port_freeze() calls ata_port_abort() | |
2754 | */ | |
bdd4ddde | 2755 | ata_port_freeze(ap); |
37b9046a ML |
2756 | } else { |
2757 | abort = 1; | |
2758 | } | |
2759 | ||
2760 | if (abort) { | |
2761 | if (qc) | |
2762 | ata_link_abort(qc->dev->link); | |
2763 | else | |
2764 | ata_port_abort(ap); | |
2765 | } | |
bdd4ddde JG |
2766 | } |
2767 | ||
1aadf5c3 | 2768 | static bool mv_process_crpb_response(struct ata_port *ap, |
fcfb1f77 ML |
2769 | struct mv_crpb *response, unsigned int tag, int ncq_enabled) |
2770 | { | |
752e386c TH |
2771 | u8 ata_status; |
2772 | u16 edma_status = le16_to_cpu(response->flags); | |
752e386c TH |
2773 | |
2774 | /* | |
2775 | * edma_status from a response queue entry: | |
2776 | * LSB is from EDMA_ERR_IRQ_CAUSE (non-NCQ only). | |
2777 | * MSB is saved ATA status from command completion. | |
2778 | */ | |
2779 | if (!ncq_enabled) { | |
2780 | u8 err_cause = edma_status & 0xff & ~EDMA_ERR_DEV; | |
2781 | if (err_cause) { | |
2782 | /* | |
2783 | * Error will be seen/handled by | |
2784 | * mv_err_intr(). So do nothing at all here. | |
2785 | */ | |
1aadf5c3 | 2786 | return false; |
752e386c | 2787 | } |
fcfb1f77 | 2788 | } |
752e386c TH |
2789 | ata_status = edma_status >> CRPB_FLAG_STATUS_SHIFT; |
2790 | if (!ac_err_mask(ata_status)) | |
1aadf5c3 | 2791 | return true; |
752e386c | 2792 | /* else: leave it for mv_err_intr() */ |
1aadf5c3 | 2793 | return false; |
fcfb1f77 ML |
2794 | } |
2795 | ||
2796 | static void mv_process_crpb_entries(struct ata_port *ap, struct mv_port_priv *pp) | |
bdd4ddde JG |
2797 | { |
2798 | void __iomem *port_mmio = mv_ap_base(ap); | |
2799 | struct mv_host_priv *hpriv = ap->host->private_data; | |
fcfb1f77 | 2800 | u32 in_index; |
bdd4ddde | 2801 | bool work_done = false; |
1aadf5c3 | 2802 | u32 done_mask = 0; |
fcfb1f77 | 2803 | int ncq_enabled = (pp->pp_flags & MV_PP_FLAG_NCQ_EN); |
bdd4ddde | 2804 | |
fcfb1f77 | 2805 | /* Get the hardware queue position index */ |
cae5a29d | 2806 | in_index = (readl(port_mmio + EDMA_RSP_Q_IN_PTR) |
bdd4ddde JG |
2807 | >> EDMA_RSP_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK; |
2808 | ||
fcfb1f77 ML |
2809 | /* Process new responses from since the last time we looked */ |
2810 | while (in_index != pp->resp_idx) { | |
6c1153e0 | 2811 | unsigned int tag; |
fcfb1f77 | 2812 | struct mv_crpb *response = &pp->crpb[pp->resp_idx]; |
bdd4ddde | 2813 | |
fcfb1f77 | 2814 | pp->resp_idx = (pp->resp_idx + 1) & MV_MAX_Q_DEPTH_MASK; |
bdd4ddde | 2815 | |
fcfb1f77 ML |
2816 | if (IS_GEN_I(hpriv)) { |
2817 | /* 50xx: no NCQ, only one command active at a time */ | |
9af5c9c9 | 2818 | tag = ap->link.active_tag; |
fcfb1f77 ML |
2819 | } else { |
2820 | /* Gen II/IIE: get command tag from CRPB entry */ | |
2821 | tag = le16_to_cpu(response->id) & 0x1f; | |
bdd4ddde | 2822 | } |
1aadf5c3 TH |
2823 | if (mv_process_crpb_response(ap, response, tag, ncq_enabled)) |
2824 | done_mask |= 1 << tag; | |
bdd4ddde | 2825 | work_done = true; |
bdd4ddde JG |
2826 | } |
2827 | ||
1aadf5c3 | 2828 | if (work_done) { |
8385d756 | 2829 | ata_qc_complete_multiple(ap, ata_qc_get_active(ap) ^ done_mask); |
1aadf5c3 TH |
2830 | |
2831 | /* Update the software queue position index in hardware */ | |
bdd4ddde | 2832 | writelfl((pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK) | |
fcfb1f77 | 2833 | (pp->resp_idx << EDMA_RSP_Q_PTR_SHIFT), |
cae5a29d | 2834 | port_mmio + EDMA_RSP_Q_OUT_PTR); |
1aadf5c3 | 2835 | } |
20f733e7 BR |
2836 | } |
2837 | ||
a9010329 ML |
2838 | static void mv_port_intr(struct ata_port *ap, u32 port_cause) |
2839 | { | |
2840 | struct mv_port_priv *pp; | |
2841 | int edma_was_enabled; | |
2842 | ||
a9010329 ML |
2843 | /* |
2844 | * Grab a snapshot of the EDMA_EN flag setting, | |
2845 | * so that we have a consistent view for this port, | |
2846 | * even if something we call of our routines changes it. | |
2847 | */ | |
2848 | pp = ap->private_data; | |
2849 | edma_was_enabled = (pp->pp_flags & MV_PP_FLAG_EDMA_EN); | |
2850 | /* | |
2851 | * Process completed CRPB response(s) before other events. | |
2852 | */ | |
2853 | if (edma_was_enabled && (port_cause & DONE_IRQ)) { | |
2854 | mv_process_crpb_entries(ap, pp); | |
4c299ca3 ML |
2855 | if (pp->pp_flags & MV_PP_FLAG_DELAYED_EH) |
2856 | mv_handle_fbs_ncq_dev_err(ap); | |
a9010329 ML |
2857 | } |
2858 | /* | |
2859 | * Handle chip-reported errors, or continue on to handle PIO. | |
2860 | */ | |
2861 | if (unlikely(port_cause & ERR_IRQ)) { | |
2862 | mv_err_intr(ap); | |
2863 | } else if (!edma_was_enabled) { | |
2864 | struct ata_queued_cmd *qc = mv_get_active_qc(ap); | |
2865 | if (qc) | |
c3b28894 | 2866 | ata_bmdma_port_intr(ap, qc); |
a9010329 ML |
2867 | else |
2868 | mv_unexpected_intr(ap, edma_was_enabled); | |
2869 | } | |
2870 | } | |
2871 | ||
05b308e1 BR |
2872 | /** |
2873 | * mv_host_intr - Handle all interrupts on the given host controller | |
cca3974e | 2874 | * @host: host specific structure |
7368f919 | 2875 | * @main_irq_cause: Main interrupt cause register for the chip. |
05b308e1 BR |
2876 | * |
2877 | * LOCKING: | |
2878 | * Inherited from caller. | |
2879 | */ | |
7368f919 | 2880 | static int mv_host_intr(struct ata_host *host, u32 main_irq_cause) |
20f733e7 | 2881 | { |
f351b2d6 | 2882 | struct mv_host_priv *hpriv = host->private_data; |
eabd5eb1 | 2883 | void __iomem *mmio = hpriv->base, *hc_mmio; |
a3718c1f | 2884 | unsigned int handled = 0, port; |
20f733e7 | 2885 | |
2b748a0a ML |
2886 | /* If asserted, clear the "all ports" IRQ coalescing bit */ |
2887 | if (main_irq_cause & ALL_PORTS_COAL_DONE) | |
cae5a29d | 2888 | writel(~ALL_PORTS_COAL_IRQ, mmio + IRQ_COAL_CAUSE); |
2b748a0a | 2889 | |
a3718c1f | 2890 | for (port = 0; port < hpriv->n_ports; port++) { |
cca3974e | 2891 | struct ata_port *ap = host->ports[port]; |
eabd5eb1 ML |
2892 | unsigned int p, shift, hardport, port_cause; |
2893 | ||
a3718c1f | 2894 | MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport); |
a3718c1f | 2895 | /* |
eabd5eb1 ML |
2896 | * Each hc within the host has its own hc_irq_cause register, |
2897 | * where the interrupting ports bits get ack'd. | |
a3718c1f | 2898 | */ |
eabd5eb1 ML |
2899 | if (hardport == 0) { /* first port on this hc ? */ |
2900 | u32 hc_cause = (main_irq_cause >> shift) & HC0_IRQ_PEND; | |
2901 | u32 port_mask, ack_irqs; | |
2902 | /* | |
2903 | * Skip this entire hc if nothing pending for any ports | |
2904 | */ | |
2905 | if (!hc_cause) { | |
2906 | port += MV_PORTS_PER_HC - 1; | |
2907 | continue; | |
2908 | } | |
2909 | /* | |
2910 | * We don't need/want to read the hc_irq_cause register, | |
2911 | * because doing so hurts performance, and | |
2912 | * main_irq_cause already gives us everything we need. | |
2913 | * | |
2914 | * But we do have to *write* to the hc_irq_cause to ack | |
2915 | * the ports that we are handling this time through. | |
2916 | * | |
2917 | * This requires that we create a bitmap for those | |
2918 | * ports which interrupted us, and use that bitmap | |
2919 | * to ack (only) those ports via hc_irq_cause. | |
2920 | */ | |
2921 | ack_irqs = 0; | |
2b748a0a ML |
2922 | if (hc_cause & PORTS_0_3_COAL_DONE) |
2923 | ack_irqs = HC_COAL_IRQ; | |
eabd5eb1 ML |
2924 | for (p = 0; p < MV_PORTS_PER_HC; ++p) { |
2925 | if ((port + p) >= hpriv->n_ports) | |
2926 | break; | |
2927 | port_mask = (DONE_IRQ | ERR_IRQ) << (p * 2); | |
2928 | if (hc_cause & port_mask) | |
2929 | ack_irqs |= (DMA_IRQ | DEV_IRQ) << p; | |
2930 | } | |
a3718c1f | 2931 | hc_mmio = mv_hc_base_from_port(mmio, port); |
cae5a29d | 2932 | writelfl(~ack_irqs, hc_mmio + HC_IRQ_CAUSE); |
a3718c1f ML |
2933 | handled = 1; |
2934 | } | |
8f767f8a | 2935 | /* |
a9010329 | 2936 | * Handle interrupts signalled for this port: |
8f767f8a | 2937 | */ |
a9010329 ML |
2938 | port_cause = (main_irq_cause >> shift) & (DONE_IRQ | ERR_IRQ); |
2939 | if (port_cause) | |
2940 | mv_port_intr(ap, port_cause); | |
20f733e7 | 2941 | } |
a3718c1f | 2942 | return handled; |
20f733e7 BR |
2943 | } |
2944 | ||
a3718c1f | 2945 | static int mv_pci_error(struct ata_host *host, void __iomem *mmio) |
bdd4ddde | 2946 | { |
02a121da | 2947 | struct mv_host_priv *hpriv = host->private_data; |
bdd4ddde JG |
2948 | struct ata_port *ap; |
2949 | struct ata_queued_cmd *qc; | |
2950 | struct ata_eh_info *ehi; | |
2951 | unsigned int i, err_mask, printed = 0; | |
2952 | u32 err_cause; | |
2953 | ||
cae5a29d | 2954 | err_cause = readl(mmio + hpriv->irq_cause_offset); |
bdd4ddde | 2955 | |
a44fec1f | 2956 | dev_err(host->dev, "PCI ERROR; PCI IRQ cause=0x%08x\n", err_cause); |
bdd4ddde | 2957 | |
a2715a42 | 2958 | dev_dbg(host->dev, "%s: All regs @ PCI error\n", __func__); |
37fcfade | 2959 | mv_dump_all_regs(mmio, to_pci_dev(host->dev)); |
bdd4ddde | 2960 | |
cae5a29d | 2961 | writelfl(0, mmio + hpriv->irq_cause_offset); |
bdd4ddde JG |
2962 | |
2963 | for (i = 0; i < host->n_ports; i++) { | |
2964 | ap = host->ports[i]; | |
936fd732 | 2965 | if (!ata_link_offline(&ap->link)) { |
9af5c9c9 | 2966 | ehi = &ap->link.eh_info; |
bdd4ddde JG |
2967 | ata_ehi_clear_desc(ehi); |
2968 | if (!printed++) | |
2969 | ata_ehi_push_desc(ehi, | |
2970 | "PCI err cause 0x%08x", err_cause); | |
2971 | err_mask = AC_ERR_HOST_BUS; | |
cf480626 | 2972 | ehi->action = ATA_EH_RESET; |
9af5c9c9 | 2973 | qc = ata_qc_from_tag(ap, ap->link.active_tag); |
bdd4ddde JG |
2974 | if (qc) |
2975 | qc->err_mask |= err_mask; | |
2976 | else | |
2977 | ehi->err_mask |= err_mask; | |
2978 | ||
2979 | ata_port_freeze(ap); | |
2980 | } | |
2981 | } | |
a3718c1f | 2982 | return 1; /* handled */ |
bdd4ddde JG |
2983 | } |
2984 | ||
05b308e1 | 2985 | /** |
c5d3e45a | 2986 | * mv_interrupt - Main interrupt event handler |
05b308e1 BR |
2987 | * @irq: unused |
2988 | * @dev_instance: private data; in this case the host structure | |
05b308e1 BR |
2989 | * |
2990 | * Read the read only register to determine if any host | |
2991 | * controllers have pending interrupts. If so, call lower level | |
2992 | * routine to handle. Also check for PCI errors which are only | |
2993 | * reported here. | |
2994 | * | |
8b260248 | 2995 | * LOCKING: |
cca3974e | 2996 | * This routine holds the host lock while processing pending |
05b308e1 BR |
2997 | * interrupts. |
2998 | */ | |
7d12e780 | 2999 | static irqreturn_t mv_interrupt(int irq, void *dev_instance) |
20f733e7 | 3000 | { |
cca3974e | 3001 | struct ata_host *host = dev_instance; |
f351b2d6 | 3002 | struct mv_host_priv *hpriv = host->private_data; |
a3718c1f | 3003 | unsigned int handled = 0; |
6d3c30ef | 3004 | int using_msi = hpriv->hp_flags & MV_HP_FLAG_MSI; |
96e2c487 | 3005 | u32 main_irq_cause, pending_irqs; |
20f733e7 | 3006 | |
646a4da5 | 3007 | spin_lock(&host->lock); |
6d3c30ef ML |
3008 | |
3009 | /* for MSI: block new interrupts while in here */ | |
3010 | if (using_msi) | |
2b748a0a | 3011 | mv_write_main_irq_mask(0, hpriv); |
6d3c30ef | 3012 | |
7368f919 | 3013 | main_irq_cause = readl(hpriv->main_irq_cause_addr); |
96e2c487 | 3014 | pending_irqs = main_irq_cause & hpriv->main_irq_mask; |
352fab70 ML |
3015 | /* |
3016 | * Deal with cases where we either have nothing pending, or have read | |
3017 | * a bogus register value which can indicate HW removal or PCI fault. | |
20f733e7 | 3018 | */ |
a44253d2 | 3019 | if (pending_irqs && main_irq_cause != 0xffffffffU) { |
1f398472 | 3020 | if (unlikely((pending_irqs & PCI_ERR) && !IS_SOC(hpriv))) |
a3718c1f ML |
3021 | handled = mv_pci_error(host, hpriv->base); |
3022 | else | |
a44253d2 | 3023 | handled = mv_host_intr(host, pending_irqs); |
bdd4ddde | 3024 | } |
6d3c30ef ML |
3025 | |
3026 | /* for MSI: unmask; interrupt cause bits will retrigger now */ | |
3027 | if (using_msi) | |
2b748a0a | 3028 | mv_write_main_irq_mask(hpriv->main_irq_mask, hpriv); |
6d3c30ef | 3029 | |
9d51af7b ML |
3030 | spin_unlock(&host->lock); |
3031 | ||
20f733e7 BR |
3032 | return IRQ_RETVAL(handled); |
3033 | } | |
3034 | ||
c9d39130 JG |
3035 | static unsigned int mv5_scr_offset(unsigned int sc_reg_in) |
3036 | { | |
3037 | unsigned int ofs; | |
3038 | ||
3039 | switch (sc_reg_in) { | |
3040 | case SCR_STATUS: | |
3041 | case SCR_ERROR: | |
3042 | case SCR_CONTROL: | |
3043 | ofs = sc_reg_in * sizeof(u32); | |
3044 | break; | |
3045 | default: | |
3046 | ofs = 0xffffffffU; | |
3047 | break; | |
3048 | } | |
3049 | return ofs; | |
3050 | } | |
3051 | ||
82ef04fb | 3052 | static int mv5_scr_read(struct ata_link *link, unsigned int sc_reg_in, u32 *val) |
c9d39130 | 3053 | { |
82ef04fb | 3054 | struct mv_host_priv *hpriv = link->ap->host->private_data; |
f351b2d6 | 3055 | void __iomem *mmio = hpriv->base; |
82ef04fb | 3056 | void __iomem *addr = mv5_phy_base(mmio, link->ap->port_no); |
c9d39130 JG |
3057 | unsigned int ofs = mv5_scr_offset(sc_reg_in); |
3058 | ||
da3dbb17 TH |
3059 | if (ofs != 0xffffffffU) { |
3060 | *val = readl(addr + ofs); | |
3061 | return 0; | |
3062 | } else | |
3063 | return -EINVAL; | |
c9d39130 JG |
3064 | } |
3065 | ||
82ef04fb | 3066 | static int mv5_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val) |
c9d39130 | 3067 | { |
82ef04fb | 3068 | struct mv_host_priv *hpriv = link->ap->host->private_data; |
f351b2d6 | 3069 | void __iomem *mmio = hpriv->base; |
82ef04fb | 3070 | void __iomem *addr = mv5_phy_base(mmio, link->ap->port_no); |
c9d39130 JG |
3071 | unsigned int ofs = mv5_scr_offset(sc_reg_in); |
3072 | ||
da3dbb17 | 3073 | if (ofs != 0xffffffffU) { |
0d5ff566 | 3074 | writelfl(val, addr + ofs); |
da3dbb17 TH |
3075 | return 0; |
3076 | } else | |
3077 | return -EINVAL; | |
c9d39130 JG |
3078 | } |
3079 | ||
7bb3c529 | 3080 | static void mv5_reset_bus(struct ata_host *host, void __iomem *mmio) |
522479fb | 3081 | { |
7bb3c529 | 3082 | struct pci_dev *pdev = to_pci_dev(host->dev); |
522479fb JG |
3083 | int early_5080; |
3084 | ||
44c10138 | 3085 | early_5080 = (pdev->device == 0x5080) && (pdev->revision == 0); |
522479fb JG |
3086 | |
3087 | if (!early_5080) { | |
3088 | u32 tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL); | |
3089 | tmp |= (1 << 0); | |
3090 | writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL); | |
3091 | } | |
3092 | ||
7bb3c529 | 3093 | mv_reset_pci_bus(host, mmio); |
522479fb JG |
3094 | } |
3095 | ||
3096 | static void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio) | |
3097 | { | |
cae5a29d | 3098 | writel(0x0fcfffff, mmio + FLASH_CTL); |
522479fb JG |
3099 | } |
3100 | ||
47c2b677 | 3101 | static void mv5_read_preamp(struct mv_host_priv *hpriv, int idx, |
ba3fe8fb JG |
3102 | void __iomem *mmio) |
3103 | { | |
c9d39130 JG |
3104 | void __iomem *phy_mmio = mv5_phy_base(mmio, idx); |
3105 | u32 tmp; | |
3106 | ||
3107 | tmp = readl(phy_mmio + MV5_PHY_MODE); | |
3108 | ||
3109 | hpriv->signal[idx].pre = tmp & 0x1800; /* bits 12:11 */ | |
3110 | hpriv->signal[idx].amps = tmp & 0xe0; /* bits 7:5 */ | |
ba3fe8fb JG |
3111 | } |
3112 | ||
47c2b677 | 3113 | static void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio) |
ba3fe8fb | 3114 | { |
522479fb JG |
3115 | u32 tmp; |
3116 | ||
cae5a29d | 3117 | writel(0, mmio + GPIO_PORT_CTL); |
522479fb JG |
3118 | |
3119 | /* FIXME: handle MV_HP_ERRATA_50XXB2 errata */ | |
3120 | ||
3121 | tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL); | |
3122 | tmp |= ~(1 << 0); | |
3123 | writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL); | |
ba3fe8fb JG |
3124 | } |
3125 | ||
2a47ce06 JG |
3126 | static void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio, |
3127 | unsigned int port) | |
bca1c4eb | 3128 | { |
c9d39130 JG |
3129 | void __iomem *phy_mmio = mv5_phy_base(mmio, port); |
3130 | const u32 mask = (1<<12) | (1<<11) | (1<<7) | (1<<6) | (1<<5); | |
3131 | u32 tmp; | |
3132 | int fix_apm_sq = (hpriv->hp_flags & MV_HP_ERRATA_50XXB0); | |
3133 | ||
3134 | if (fix_apm_sq) { | |
cae5a29d | 3135 | tmp = readl(phy_mmio + MV5_LTMODE); |
c9d39130 | 3136 | tmp |= (1 << 19); |
cae5a29d | 3137 | writel(tmp, phy_mmio + MV5_LTMODE); |
c9d39130 | 3138 | |
cae5a29d | 3139 | tmp = readl(phy_mmio + MV5_PHY_CTL); |
c9d39130 JG |
3140 | tmp &= ~0x3; |
3141 | tmp |= 0x1; | |
cae5a29d | 3142 | writel(tmp, phy_mmio + MV5_PHY_CTL); |
c9d39130 JG |
3143 | } |
3144 | ||
3145 | tmp = readl(phy_mmio + MV5_PHY_MODE); | |
3146 | tmp &= ~mask; | |
3147 | tmp |= hpriv->signal[port].pre; | |
3148 | tmp |= hpriv->signal[port].amps; | |
3149 | writel(tmp, phy_mmio + MV5_PHY_MODE); | |
bca1c4eb JG |
3150 | } |
3151 | ||
c9d39130 JG |
3152 | |
3153 | #undef ZERO | |
3154 | #define ZERO(reg) writel(0, port_mmio + (reg)) | |
3155 | static void mv5_reset_hc_port(struct mv_host_priv *hpriv, void __iomem *mmio, | |
3156 | unsigned int port) | |
3157 | { | |
3158 | void __iomem *port_mmio = mv_port_base(mmio, port); | |
3159 | ||
e12bef50 | 3160 | mv_reset_channel(hpriv, mmio, port); |
c9d39130 JG |
3161 | |
3162 | ZERO(0x028); /* command */ | |
cae5a29d | 3163 | writel(0x11f, port_mmio + EDMA_CFG); |
c9d39130 JG |
3164 | ZERO(0x004); /* timer */ |
3165 | ZERO(0x008); /* irq err cause */ | |
3166 | ZERO(0x00c); /* irq err mask */ | |
3167 | ZERO(0x010); /* rq bah */ | |
3168 | ZERO(0x014); /* rq inp */ | |
3169 | ZERO(0x018); /* rq outp */ | |
3170 | ZERO(0x01c); /* respq bah */ | |
3171 | ZERO(0x024); /* respq outp */ | |
3172 | ZERO(0x020); /* respq inp */ | |
3173 | ZERO(0x02c); /* test control */ | |
cae5a29d | 3174 | writel(0xbc, port_mmio + EDMA_IORDY_TMOUT); |
c9d39130 JG |
3175 | } |
3176 | #undef ZERO | |
3177 | ||
3178 | #define ZERO(reg) writel(0, hc_mmio + (reg)) | |
3179 | static void mv5_reset_one_hc(struct mv_host_priv *hpriv, void __iomem *mmio, | |
3180 | unsigned int hc) | |
47c2b677 | 3181 | { |
c9d39130 JG |
3182 | void __iomem *hc_mmio = mv_hc_base(mmio, hc); |
3183 | u32 tmp; | |
3184 | ||
3185 | ZERO(0x00c); | |
3186 | ZERO(0x010); | |
3187 | ZERO(0x014); | |
3188 | ZERO(0x018); | |
3189 | ||
3190 | tmp = readl(hc_mmio + 0x20); | |
3191 | tmp &= 0x1c1c1c1c; | |
3192 | tmp |= 0x03030303; | |
3193 | writel(tmp, hc_mmio + 0x20); | |
3194 | } | |
3195 | #undef ZERO | |
3196 | ||
f76ba003 | 3197 | static int mv5_reset_hc(struct ata_host *host, void __iomem *mmio, |
c9d39130 JG |
3198 | unsigned int n_hc) |
3199 | { | |
f76ba003 | 3200 | struct mv_host_priv *hpriv = host->private_data; |
c9d39130 JG |
3201 | unsigned int hc, port; |
3202 | ||
3203 | for (hc = 0; hc < n_hc; hc++) { | |
3204 | for (port = 0; port < MV_PORTS_PER_HC; port++) | |
3205 | mv5_reset_hc_port(hpriv, mmio, | |
3206 | (hc * MV_PORTS_PER_HC) + port); | |
3207 | ||
3208 | mv5_reset_one_hc(hpriv, mmio, hc); | |
3209 | } | |
3210 | ||
3211 | return 0; | |
47c2b677 JG |
3212 | } |
3213 | ||
101ffae2 JG |
3214 | #undef ZERO |
3215 | #define ZERO(reg) writel(0, mmio + (reg)) | |
7bb3c529 | 3216 | static void mv_reset_pci_bus(struct ata_host *host, void __iomem *mmio) |
101ffae2 | 3217 | { |
02a121da | 3218 | struct mv_host_priv *hpriv = host->private_data; |
101ffae2 JG |
3219 | u32 tmp; |
3220 | ||
cae5a29d | 3221 | tmp = readl(mmio + MV_PCI_MODE); |
101ffae2 | 3222 | tmp &= 0xff00ffff; |
cae5a29d | 3223 | writel(tmp, mmio + MV_PCI_MODE); |
101ffae2 JG |
3224 | |
3225 | ZERO(MV_PCI_DISC_TIMER); | |
3226 | ZERO(MV_PCI_MSI_TRIGGER); | |
cae5a29d | 3227 | writel(0x000100ff, mmio + MV_PCI_XBAR_TMOUT); |
101ffae2 | 3228 | ZERO(MV_PCI_SERR_MASK); |
cae5a29d ML |
3229 | ZERO(hpriv->irq_cause_offset); |
3230 | ZERO(hpriv->irq_mask_offset); | |
101ffae2 JG |
3231 | ZERO(MV_PCI_ERR_LOW_ADDRESS); |
3232 | ZERO(MV_PCI_ERR_HIGH_ADDRESS); | |
3233 | ZERO(MV_PCI_ERR_ATTRIBUTE); | |
3234 | ZERO(MV_PCI_ERR_COMMAND); | |
3235 | } | |
3236 | #undef ZERO | |
3237 | ||
3238 | static void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio) | |
3239 | { | |
3240 | u32 tmp; | |
3241 | ||
3242 | mv5_reset_flash(hpriv, mmio); | |
3243 | ||
cae5a29d | 3244 | tmp = readl(mmio + GPIO_PORT_CTL); |
101ffae2 JG |
3245 | tmp &= 0x3; |
3246 | tmp |= (1 << 5) | (1 << 6); | |
cae5a29d | 3247 | writel(tmp, mmio + GPIO_PORT_CTL); |
101ffae2 JG |
3248 | } |
3249 | ||
f3a23c2c | 3250 | /* |
101ffae2 JG |
3251 | * mv6_reset_hc - Perform the 6xxx global soft reset |
3252 | * @mmio: base address of the HBA | |
3253 | * | |
3254 | * This routine only applies to 6xxx parts. | |
3255 | * | |
3256 | * LOCKING: | |
3257 | * Inherited from caller. | |
3258 | */ | |
f76ba003 | 3259 | static int mv6_reset_hc(struct ata_host *host, void __iomem *mmio, |
c9d39130 | 3260 | unsigned int n_hc) |
101ffae2 | 3261 | { |
cae5a29d | 3262 | void __iomem *reg = mmio + PCI_MAIN_CMD_STS; |
101ffae2 JG |
3263 | int i, rc = 0; |
3264 | u32 t; | |
3265 | ||
3266 | /* Following procedure defined in PCI "main command and status | |
3267 | * register" table. | |
3268 | */ | |
3269 | t = readl(reg); | |
3270 | writel(t | STOP_PCI_MASTER, reg); | |
3271 | ||
3272 | for (i = 0; i < 1000; i++) { | |
3273 | udelay(1); | |
3274 | t = readl(reg); | |
2dcb407e | 3275 | if (PCI_MASTER_EMPTY & t) |
101ffae2 | 3276 | break; |
101ffae2 JG |
3277 | } |
3278 | if (!(PCI_MASTER_EMPTY & t)) { | |
f76ba003 | 3279 | dev_err(host->dev, "PCI master won't flush\n"); |
101ffae2 JG |
3280 | rc = 1; |
3281 | goto done; | |
3282 | } | |
3283 | ||
3284 | /* set reset */ | |
3285 | i = 5; | |
3286 | do { | |
3287 | writel(t | GLOB_SFT_RST, reg); | |
3288 | t = readl(reg); | |
3289 | udelay(1); | |
3290 | } while (!(GLOB_SFT_RST & t) && (i-- > 0)); | |
3291 | ||
3292 | if (!(GLOB_SFT_RST & t)) { | |
f76ba003 | 3293 | dev_err(host->dev, "can't set global reset\n"); |
101ffae2 JG |
3294 | rc = 1; |
3295 | goto done; | |
3296 | } | |
3297 | ||
3298 | /* clear reset and *reenable the PCI master* (not mentioned in spec) */ | |
3299 | i = 5; | |
3300 | do { | |
3301 | writel(t & ~(GLOB_SFT_RST | STOP_PCI_MASTER), reg); | |
3302 | t = readl(reg); | |
3303 | udelay(1); | |
3304 | } while ((GLOB_SFT_RST & t) && (i-- > 0)); | |
3305 | ||
3306 | if (GLOB_SFT_RST & t) { | |
f76ba003 | 3307 | dev_err(host->dev, "can't clear global reset\n"); |
101ffae2 JG |
3308 | rc = 1; |
3309 | } | |
3310 | done: | |
3311 | return rc; | |
3312 | } | |
3313 | ||
47c2b677 | 3314 | static void mv6_read_preamp(struct mv_host_priv *hpriv, int idx, |
ba3fe8fb JG |
3315 | void __iomem *mmio) |
3316 | { | |
3317 | void __iomem *port_mmio; | |
3318 | u32 tmp; | |
3319 | ||
cae5a29d | 3320 | tmp = readl(mmio + RESET_CFG); |
ba3fe8fb | 3321 | if ((tmp & (1 << 0)) == 0) { |
47c2b677 | 3322 | hpriv->signal[idx].amps = 0x7 << 8; |
ba3fe8fb JG |
3323 | hpriv->signal[idx].pre = 0x1 << 5; |
3324 | return; | |
3325 | } | |
3326 | ||
3327 | port_mmio = mv_port_base(mmio, idx); | |
3328 | tmp = readl(port_mmio + PHY_MODE2); | |
3329 | ||
3330 | hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */ | |
3331 | hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */ | |
3332 | } | |
3333 | ||
47c2b677 | 3334 | static void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio) |
ba3fe8fb | 3335 | { |
cae5a29d | 3336 | writel(0x00000060, mmio + GPIO_PORT_CTL); |
ba3fe8fb JG |
3337 | } |
3338 | ||
c9d39130 | 3339 | static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio, |
2a47ce06 | 3340 | unsigned int port) |
bca1c4eb | 3341 | { |
c9d39130 JG |
3342 | void __iomem *port_mmio = mv_port_base(mmio, port); |
3343 | ||
bca1c4eb | 3344 | u32 hp_flags = hpriv->hp_flags; |
47c2b677 JG |
3345 | int fix_phy_mode2 = |
3346 | hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0); | |
bca1c4eb | 3347 | int fix_phy_mode4 = |
47c2b677 | 3348 | hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0); |
8c30a8b9 | 3349 | u32 m2, m3; |
47c2b677 JG |
3350 | |
3351 | if (fix_phy_mode2) { | |
3352 | m2 = readl(port_mmio + PHY_MODE2); | |
3353 | m2 &= ~(1 << 16); | |
3354 | m2 |= (1 << 31); | |
3355 | writel(m2, port_mmio + PHY_MODE2); | |
3356 | ||
3357 | udelay(200); | |
3358 | ||
3359 | m2 = readl(port_mmio + PHY_MODE2); | |
3360 | m2 &= ~((1 << 16) | (1 << 31)); | |
3361 | writel(m2, port_mmio + PHY_MODE2); | |
3362 | ||
3363 | udelay(200); | |
3364 | } | |
3365 | ||
8c30a8b9 ML |
3366 | /* |
3367 | * Gen-II/IIe PHY_MODE3 errata RM#2: | |
3368 | * Achieves better receiver noise performance than the h/w default: | |
3369 | */ | |
3370 | m3 = readl(port_mmio + PHY_MODE3); | |
3371 | m3 = (m3 & 0x1f) | (0x5555601 << 5); | |
bca1c4eb | 3372 | |
0388a8c0 ML |
3373 | /* Guideline 88F5182 (GL# SATA-S11) */ |
3374 | if (IS_SOC(hpriv)) | |
3375 | m3 &= ~0x1c; | |
3376 | ||
bca1c4eb | 3377 | if (fix_phy_mode4) { |
ba069e37 ML |
3378 | u32 m4 = readl(port_mmio + PHY_MODE4); |
3379 | /* | |
3380 | * Enforce reserved-bit restrictions on GenIIe devices only. | |
3381 | * For earlier chipsets, force only the internal config field | |
3382 | * (workaround for errata FEr SATA#10 part 1). | |
3383 | */ | |
8c30a8b9 | 3384 | if (IS_GEN_IIE(hpriv)) |
ba069e37 ML |
3385 | m4 = (m4 & ~PHY_MODE4_RSVD_ZEROS) | PHY_MODE4_RSVD_ONES; |
3386 | else | |
3387 | m4 = (m4 & ~PHY_MODE4_CFG_MASK) | PHY_MODE4_CFG_VALUE; | |
8c30a8b9 | 3388 | writel(m4, port_mmio + PHY_MODE4); |
bca1c4eb | 3389 | } |
b406c7a6 ML |
3390 | /* |
3391 | * Workaround for 60x1-B2 errata SATA#13: | |
3392 | * Any write to PHY_MODE4 (above) may corrupt PHY_MODE3, | |
3393 | * so we must always rewrite PHY_MODE3 after PHY_MODE4. | |
ba68460b | 3394 | * Or ensure we use writelfl() when writing PHY_MODE4. |
b406c7a6 ML |
3395 | */ |
3396 | writel(m3, port_mmio + PHY_MODE3); | |
bca1c4eb JG |
3397 | |
3398 | /* Revert values of pre-emphasis and signal amps to the saved ones */ | |
3399 | m2 = readl(port_mmio + PHY_MODE2); | |
3400 | ||
3401 | m2 &= ~MV_M2_PREAMP_MASK; | |
2a47ce06 JG |
3402 | m2 |= hpriv->signal[port].amps; |
3403 | m2 |= hpriv->signal[port].pre; | |
47c2b677 | 3404 | m2 &= ~(1 << 16); |
bca1c4eb | 3405 | |
e4e7b892 JG |
3406 | /* according to mvSata 3.6.1, some IIE values are fixed */ |
3407 | if (IS_GEN_IIE(hpriv)) { | |
3408 | m2 &= ~0xC30FF01F; | |
3409 | m2 |= 0x0000900F; | |
3410 | } | |
3411 | ||
bca1c4eb JG |
3412 | writel(m2, port_mmio + PHY_MODE2); |
3413 | } | |
3414 | ||
f351b2d6 SB |
3415 | /* TODO: use the generic LED interface to configure the SATA Presence */ |
3416 | /* & Acitivy LEDs on the board */ | |
3417 | static void mv_soc_enable_leds(struct mv_host_priv *hpriv, | |
3418 | void __iomem *mmio) | |
3419 | { | |
3420 | return; | |
3421 | } | |
3422 | ||
3423 | static void mv_soc_read_preamp(struct mv_host_priv *hpriv, int idx, | |
3424 | void __iomem *mmio) | |
3425 | { | |
3426 | void __iomem *port_mmio; | |
3427 | u32 tmp; | |
3428 | ||
3429 | port_mmio = mv_port_base(mmio, idx); | |
3430 | tmp = readl(port_mmio + PHY_MODE2); | |
3431 | ||
3432 | hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */ | |
3433 | hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */ | |
3434 | } | |
3435 | ||
3436 | #undef ZERO | |
3437 | #define ZERO(reg) writel(0, port_mmio + (reg)) | |
3438 | static void mv_soc_reset_hc_port(struct mv_host_priv *hpriv, | |
3439 | void __iomem *mmio, unsigned int port) | |
3440 | { | |
3441 | void __iomem *port_mmio = mv_port_base(mmio, port); | |
3442 | ||
e12bef50 | 3443 | mv_reset_channel(hpriv, mmio, port); |
f351b2d6 SB |
3444 | |
3445 | ZERO(0x028); /* command */ | |
cae5a29d | 3446 | writel(0x101f, port_mmio + EDMA_CFG); |
f351b2d6 SB |
3447 | ZERO(0x004); /* timer */ |
3448 | ZERO(0x008); /* irq err cause */ | |
3449 | ZERO(0x00c); /* irq err mask */ | |
3450 | ZERO(0x010); /* rq bah */ | |
3451 | ZERO(0x014); /* rq inp */ | |
3452 | ZERO(0x018); /* rq outp */ | |
3453 | ZERO(0x01c); /* respq bah */ | |
3454 | ZERO(0x024); /* respq outp */ | |
3455 | ZERO(0x020); /* respq inp */ | |
3456 | ZERO(0x02c); /* test control */ | |
d7b0c143 | 3457 | writel(0x800, port_mmio + EDMA_IORDY_TMOUT); |
f351b2d6 SB |
3458 | } |
3459 | ||
3460 | #undef ZERO | |
3461 | ||
3462 | #define ZERO(reg) writel(0, hc_mmio + (reg)) | |
3463 | static void mv_soc_reset_one_hc(struct mv_host_priv *hpriv, | |
3464 | void __iomem *mmio) | |
3465 | { | |
3466 | void __iomem *hc_mmio = mv_hc_base(mmio, 0); | |
3467 | ||
3468 | ZERO(0x00c); | |
3469 | ZERO(0x010); | |
3470 | ZERO(0x014); | |
3471 | ||
3472 | } | |
3473 | ||
3474 | #undef ZERO | |
3475 | ||
f76ba003 | 3476 | static int mv_soc_reset_hc(struct ata_host *host, |
f351b2d6 SB |
3477 | void __iomem *mmio, unsigned int n_hc) |
3478 | { | |
f76ba003 | 3479 | struct mv_host_priv *hpriv = host->private_data; |
f351b2d6 SB |
3480 | unsigned int port; |
3481 | ||
3482 | for (port = 0; port < hpriv->n_ports; port++) | |
3483 | mv_soc_reset_hc_port(hpriv, mmio, port); | |
3484 | ||
3485 | mv_soc_reset_one_hc(hpriv, mmio); | |
3486 | ||
3487 | return 0; | |
3488 | } | |
3489 | ||
3490 | static void mv_soc_reset_flash(struct mv_host_priv *hpriv, | |
3491 | void __iomem *mmio) | |
3492 | { | |
3493 | return; | |
3494 | } | |
3495 | ||
3496 | static void mv_soc_reset_bus(struct ata_host *host, void __iomem *mmio) | |
3497 | { | |
3498 | return; | |
3499 | } | |
3500 | ||
29b7e43c MM |
3501 | static void mv_soc_65n_phy_errata(struct mv_host_priv *hpriv, |
3502 | void __iomem *mmio, unsigned int port) | |
3503 | { | |
3504 | void __iomem *port_mmio = mv_port_base(mmio, port); | |
3505 | u32 reg; | |
3506 | ||
3507 | reg = readl(port_mmio + PHY_MODE3); | |
3508 | reg &= ~(0x3 << 27); /* SELMUPF (bits 28:27) to 1 */ | |
3509 | reg |= (0x1 << 27); | |
3510 | reg &= ~(0x3 << 29); /* SELMUPI (bits 30:29) to 1 */ | |
3511 | reg |= (0x1 << 29); | |
3512 | writel(reg, port_mmio + PHY_MODE3); | |
3513 | ||
3514 | reg = readl(port_mmio + PHY_MODE4); | |
3515 | reg &= ~0x1; /* SATU_OD8 (bit 0) to 0, reserved bit 16 must be set */ | |
3516 | reg |= (0x1 << 16); | |
3517 | writel(reg, port_mmio + PHY_MODE4); | |
3518 | ||
3519 | reg = readl(port_mmio + PHY_MODE9_GEN2); | |
3520 | reg &= ~0xf; /* TXAMP[3:0] (bits 3:0) to 8 */ | |
3521 | reg |= 0x8; | |
3522 | reg &= ~(0x1 << 14); /* TXAMP[4] (bit 14) to 0 */ | |
3523 | writel(reg, port_mmio + PHY_MODE9_GEN2); | |
3524 | ||
3525 | reg = readl(port_mmio + PHY_MODE9_GEN1); | |
3526 | reg &= ~0xf; /* TXAMP[3:0] (bits 3:0) to 8 */ | |
3527 | reg |= 0x8; | |
3528 | reg &= ~(0x1 << 14); /* TXAMP[4] (bit 14) to 0 */ | |
3529 | writel(reg, port_mmio + PHY_MODE9_GEN1); | |
3530 | } | |
3531 | ||
f3a23c2c | 3532 | /* |
29b7e43c MM |
3533 | * soc_is_65 - check if the soc is 65 nano device |
3534 | * | |
3535 | * Detect the type of the SoC, this is done by reading the PHYCFG_OFS | |
3536 | * register, this register should contain non-zero value and it exists only | |
3537 | * in the 65 nano devices, when reading it from older devices we get 0. | |
3538 | */ | |
3539 | static bool soc_is_65n(struct mv_host_priv *hpriv) | |
3540 | { | |
3541 | void __iomem *port0_mmio = mv_port_base(hpriv->base, 0); | |
3542 | ||
3543 | if (readl(port0_mmio + PHYCFG_OFS)) | |
3544 | return true; | |
3545 | return false; | |
3546 | } | |
3547 | ||
8e7decdb | 3548 | static void mv_setup_ifcfg(void __iomem *port_mmio, int want_gen2i) |
b67a1064 | 3549 | { |
cae5a29d | 3550 | u32 ifcfg = readl(port_mmio + SATA_IFCFG); |
b67a1064 | 3551 | |
8e7decdb | 3552 | ifcfg = (ifcfg & 0xf7f) | 0x9b1000; /* from chip spec */ |
b67a1064 | 3553 | if (want_gen2i) |
8e7decdb | 3554 | ifcfg |= (1 << 7); /* enable gen2i speed */ |
cae5a29d | 3555 | writelfl(ifcfg, port_mmio + SATA_IFCFG); |
b67a1064 ML |
3556 | } |
3557 | ||
e12bef50 | 3558 | static void mv_reset_channel(struct mv_host_priv *hpriv, void __iomem *mmio, |
c9d39130 JG |
3559 | unsigned int port_no) |
3560 | { | |
3561 | void __iomem *port_mmio = mv_port_base(mmio, port_no); | |
3562 | ||
8e7decdb ML |
3563 | /* |
3564 | * The datasheet warns against setting EDMA_RESET when EDMA is active | |
3565 | * (but doesn't say what the problem might be). So we first try | |
3566 | * to disable the EDMA engine before doing the EDMA_RESET operation. | |
3567 | */ | |
0d8be5cb | 3568 | mv_stop_edma_engine(port_mmio); |
cae5a29d | 3569 | writelfl(EDMA_RESET, port_mmio + EDMA_CMD); |
c9d39130 | 3570 | |
b67a1064 | 3571 | if (!IS_GEN_I(hpriv)) { |
8e7decdb ML |
3572 | /* Enable 3.0gb/s link speed: this survives EDMA_RESET */ |
3573 | mv_setup_ifcfg(port_mmio, 1); | |
c9d39130 | 3574 | } |
b67a1064 | 3575 | /* |
8e7decdb | 3576 | * Strobing EDMA_RESET here causes a hard reset of the SATA transport, |
b67a1064 | 3577 | * link, and physical layers. It resets all SATA interface registers |
cae5a29d | 3578 | * (except for SATA_IFCFG), and issues a COMRESET to the dev. |
c9d39130 | 3579 | */ |
cae5a29d | 3580 | writelfl(EDMA_RESET, port_mmio + EDMA_CMD); |
b67a1064 | 3581 | udelay(25); /* allow reset propagation */ |
cae5a29d | 3582 | writelfl(0, port_mmio + EDMA_CMD); |
c9d39130 JG |
3583 | |
3584 | hpriv->ops->phy_errata(hpriv, mmio, port_no); | |
3585 | ||
ee9ccdf7 | 3586 | if (IS_GEN_I(hpriv)) |
e72685db | 3587 | usleep_range(500, 1000); |
c9d39130 JG |
3588 | } |
3589 | ||
e49856d8 | 3590 | static void mv_pmp_select(struct ata_port *ap, int pmp) |
20f733e7 | 3591 | { |
e49856d8 ML |
3592 | if (sata_pmp_supported(ap)) { |
3593 | void __iomem *port_mmio = mv_ap_base(ap); | |
cae5a29d | 3594 | u32 reg = readl(port_mmio + SATA_IFCTL); |
e49856d8 | 3595 | int old = reg & 0xf; |
22374677 | 3596 | |
e49856d8 ML |
3597 | if (old != pmp) { |
3598 | reg = (reg & ~0xf) | pmp; | |
cae5a29d | 3599 | writelfl(reg, port_mmio + SATA_IFCTL); |
e49856d8 | 3600 | } |
22374677 | 3601 | } |
20f733e7 BR |
3602 | } |
3603 | ||
e49856d8 ML |
3604 | static int mv_pmp_hardreset(struct ata_link *link, unsigned int *class, |
3605 | unsigned long deadline) | |
22374677 | 3606 | { |
e49856d8 ML |
3607 | mv_pmp_select(link->ap, sata_srst_pmp(link)); |
3608 | return sata_std_hardreset(link, class, deadline); | |
3609 | } | |
bdd4ddde | 3610 | |
e49856d8 ML |
3611 | static int mv_softreset(struct ata_link *link, unsigned int *class, |
3612 | unsigned long deadline) | |
3613 | { | |
3614 | mv_pmp_select(link->ap, sata_srst_pmp(link)); | |
3615 | return ata_sff_softreset(link, class, deadline); | |
22374677 JG |
3616 | } |
3617 | ||
cc0680a5 | 3618 | static int mv_hardreset(struct ata_link *link, unsigned int *class, |
bdd4ddde | 3619 | unsigned long deadline) |
31961943 | 3620 | { |
cc0680a5 | 3621 | struct ata_port *ap = link->ap; |
bdd4ddde | 3622 | struct mv_host_priv *hpriv = ap->host->private_data; |
b562468c | 3623 | struct mv_port_priv *pp = ap->private_data; |
f351b2d6 | 3624 | void __iomem *mmio = hpriv->base; |
0d8be5cb ML |
3625 | int rc, attempts = 0, extra = 0; |
3626 | u32 sstatus; | |
3627 | bool online; | |
31961943 | 3628 | |
e12bef50 | 3629 | mv_reset_channel(hpriv, mmio, ap->port_no); |
b562468c | 3630 | pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN; |
d16ab3f6 ML |
3631 | pp->pp_flags &= |
3632 | ~(MV_PP_FLAG_FBS_EN | MV_PP_FLAG_NCQ_EN | MV_PP_FLAG_FAKE_ATA_BUSY); | |
bdd4ddde | 3633 | |
0d8be5cb ML |
3634 | /* Workaround for errata FEr SATA#10 (part 2) */ |
3635 | do { | |
d14d41cc | 3636 | const unsigned int *timing = |
17c5aab5 | 3637 | sata_ehc_deb_timing(&link->eh_context); |
bdd4ddde | 3638 | |
17c5aab5 ML |
3639 | rc = sata_link_hardreset(link, timing, deadline + extra, |
3640 | &online, NULL); | |
9dcffd99 | 3641 | rc = online ? -EAGAIN : rc; |
17c5aab5 | 3642 | if (rc) |
0d8be5cb | 3643 | return rc; |
0d8be5cb ML |
3644 | sata_scr_read(link, SCR_STATUS, &sstatus); |
3645 | if (!IS_GEN_I(hpriv) && ++attempts >= 5 && sstatus == 0x121) { | |
3646 | /* Force 1.5gb/s link speed and try again */ | |
8e7decdb | 3647 | mv_setup_ifcfg(mv_ap_base(ap), 0); |
0d8be5cb ML |
3648 | if (time_after(jiffies + HZ, deadline)) |
3649 | extra = HZ; /* only extend it once, max */ | |
3650 | } | |
3651 | } while (sstatus != 0x0 && sstatus != 0x113 && sstatus != 0x123); | |
08da1759 | 3652 | mv_save_cached_regs(ap); |
66e57a2c | 3653 | mv_edma_cfg(ap, 0, 0); |
bdd4ddde | 3654 | |
17c5aab5 | 3655 | return rc; |
bdd4ddde JG |
3656 | } |
3657 | ||
bdd4ddde JG |
3658 | static void mv_eh_freeze(struct ata_port *ap) |
3659 | { | |
1cfd19ae | 3660 | mv_stop_edma(ap); |
c4de573b | 3661 | mv_enable_port_irqs(ap, 0); |
bdd4ddde JG |
3662 | } |
3663 | ||
3664 | static void mv_eh_thaw(struct ata_port *ap) | |
3665 | { | |
f351b2d6 | 3666 | struct mv_host_priv *hpriv = ap->host->private_data; |
c4de573b ML |
3667 | unsigned int port = ap->port_no; |
3668 | unsigned int hardport = mv_hardport_from_port(port); | |
1cfd19ae | 3669 | void __iomem *hc_mmio = mv_hc_base_from_port(hpriv->base, port); |
bdd4ddde | 3670 | void __iomem *port_mmio = mv_ap_base(ap); |
c4de573b | 3671 | u32 hc_irq_cause; |
bdd4ddde | 3672 | |
bdd4ddde | 3673 | /* clear EDMA errors on this port */ |
cae5a29d | 3674 | writel(0, port_mmio + EDMA_ERR_IRQ_CAUSE); |
bdd4ddde JG |
3675 | |
3676 | /* clear pending irq events */ | |
cae6edc3 | 3677 | hc_irq_cause = ~((DEV_IRQ | DMA_IRQ) << hardport); |
cae5a29d | 3678 | writelfl(hc_irq_cause, hc_mmio + HC_IRQ_CAUSE); |
bdd4ddde | 3679 | |
88e675e1 | 3680 | mv_enable_port_irqs(ap, ERR_IRQ); |
31961943 BR |
3681 | } |
3682 | ||
05b308e1 BR |
3683 | /** |
3684 | * mv_port_init - Perform some early initialization on a single port. | |
3685 | * @port: libata data structure storing shadow register addresses | |
3686 | * @port_mmio: base address of the port | |
3687 | * | |
3688 | * Initialize shadow register mmio addresses, clear outstanding | |
3689 | * interrupts on the port, and unmask interrupts for the future | |
3690 | * start of the port. | |
3691 | * | |
3692 | * LOCKING: | |
3693 | * Inherited from caller. | |
3694 | */ | |
31961943 | 3695 | static void mv_port_init(struct ata_ioports *port, void __iomem *port_mmio) |
20f733e7 | 3696 | { |
cae5a29d | 3697 | void __iomem *serr, *shd_base = port_mmio + SHD_BLK; |
31961943 | 3698 | |
8b260248 | 3699 | /* PIO related setup |
31961943 BR |
3700 | */ |
3701 | port->data_addr = shd_base + (sizeof(u32) * ATA_REG_DATA); | |
8b260248 | 3702 | port->error_addr = |
31961943 BR |
3703 | port->feature_addr = shd_base + (sizeof(u32) * ATA_REG_ERR); |
3704 | port->nsect_addr = shd_base + (sizeof(u32) * ATA_REG_NSECT); | |
3705 | port->lbal_addr = shd_base + (sizeof(u32) * ATA_REG_LBAL); | |
3706 | port->lbam_addr = shd_base + (sizeof(u32) * ATA_REG_LBAM); | |
3707 | port->lbah_addr = shd_base + (sizeof(u32) * ATA_REG_LBAH); | |
3708 | port->device_addr = shd_base + (sizeof(u32) * ATA_REG_DEVICE); | |
8b260248 | 3709 | port->status_addr = |
31961943 BR |
3710 | port->command_addr = shd_base + (sizeof(u32) * ATA_REG_STATUS); |
3711 | /* special case: control/altstatus doesn't have ATA_REG_ address */ | |
cae5a29d | 3712 | port->altstatus_addr = port->ctl_addr = shd_base + SHD_CTL_AST; |
31961943 | 3713 | |
31961943 | 3714 | /* Clear any currently outstanding port interrupt conditions */ |
cae5a29d ML |
3715 | serr = port_mmio + mv_scr_offset(SCR_ERROR); |
3716 | writelfl(readl(serr), serr); | |
3717 | writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE); | |
31961943 | 3718 | |
646a4da5 | 3719 | /* unmask all non-transient EDMA error interrupts */ |
cae5a29d | 3720 | writelfl(~EDMA_ERR_IRQ_TRANSIENT, port_mmio + EDMA_ERR_IRQ_MASK); |
20f733e7 BR |
3721 | } |
3722 | ||
616d4a98 ML |
3723 | static unsigned int mv_in_pcix_mode(struct ata_host *host) |
3724 | { | |
3725 | struct mv_host_priv *hpriv = host->private_data; | |
3726 | void __iomem *mmio = hpriv->base; | |
3727 | u32 reg; | |
3728 | ||
1f398472 | 3729 | if (IS_SOC(hpriv) || !IS_PCIE(hpriv)) |
616d4a98 | 3730 | return 0; /* not PCI-X capable */ |
cae5a29d | 3731 | reg = readl(mmio + MV_PCI_MODE); |
616d4a98 ML |
3732 | if ((reg & MV_PCI_MODE_MASK) == 0) |
3733 | return 0; /* conventional PCI mode */ | |
3734 | return 1; /* chip is in PCI-X mode */ | |
3735 | } | |
3736 | ||
3737 | static int mv_pci_cut_through_okay(struct ata_host *host) | |
3738 | { | |
3739 | struct mv_host_priv *hpriv = host->private_data; | |
3740 | void __iomem *mmio = hpriv->base; | |
3741 | u32 reg; | |
3742 | ||
3743 | if (!mv_in_pcix_mode(host)) { | |
cae5a29d ML |
3744 | reg = readl(mmio + MV_PCI_COMMAND); |
3745 | if (reg & MV_PCI_COMMAND_MRDTRIG) | |
616d4a98 ML |
3746 | return 0; /* not okay */ |
3747 | } | |
3748 | return 1; /* okay */ | |
3749 | } | |
3750 | ||
65ad7fef ML |
3751 | static void mv_60x1b2_errata_pci7(struct ata_host *host) |
3752 | { | |
3753 | struct mv_host_priv *hpriv = host->private_data; | |
3754 | void __iomem *mmio = hpriv->base; | |
3755 | ||
3756 | /* workaround for 60x1-B2 errata PCI#7 */ | |
3757 | if (mv_in_pcix_mode(host)) { | |
cae5a29d ML |
3758 | u32 reg = readl(mmio + MV_PCI_COMMAND); |
3759 | writelfl(reg & ~MV_PCI_COMMAND_MWRCOM, mmio + MV_PCI_COMMAND); | |
65ad7fef ML |
3760 | } |
3761 | } | |
3762 | ||
4447d351 | 3763 | static int mv_chip_id(struct ata_host *host, unsigned int board_idx) |
bca1c4eb | 3764 | { |
4447d351 TH |
3765 | struct pci_dev *pdev = to_pci_dev(host->dev); |
3766 | struct mv_host_priv *hpriv = host->private_data; | |
bca1c4eb JG |
3767 | u32 hp_flags = hpriv->hp_flags; |
3768 | ||
5796d1c4 | 3769 | switch (board_idx) { |
47c2b677 JG |
3770 | case chip_5080: |
3771 | hpriv->ops = &mv5xxx_ops; | |
ee9ccdf7 | 3772 | hp_flags |= MV_HP_GEN_I; |
47c2b677 | 3773 | |
44c10138 | 3774 | switch (pdev->revision) { |
47c2b677 JG |
3775 | case 0x1: |
3776 | hp_flags |= MV_HP_ERRATA_50XXB0; | |
3777 | break; | |
3778 | case 0x3: | |
3779 | hp_flags |= MV_HP_ERRATA_50XXB2; | |
3780 | break; | |
3781 | default: | |
a44fec1f JP |
3782 | dev_warn(&pdev->dev, |
3783 | "Applying 50XXB2 workarounds to unknown rev\n"); | |
47c2b677 JG |
3784 | hp_flags |= MV_HP_ERRATA_50XXB2; |
3785 | break; | |
3786 | } | |
3787 | break; | |
3788 | ||
bca1c4eb JG |
3789 | case chip_504x: |
3790 | case chip_508x: | |
47c2b677 | 3791 | hpriv->ops = &mv5xxx_ops; |
ee9ccdf7 | 3792 | hp_flags |= MV_HP_GEN_I; |
bca1c4eb | 3793 | |
44c10138 | 3794 | switch (pdev->revision) { |
47c2b677 JG |
3795 | case 0x0: |
3796 | hp_flags |= MV_HP_ERRATA_50XXB0; | |
3797 | break; | |
3798 | case 0x3: | |
3799 | hp_flags |= MV_HP_ERRATA_50XXB2; | |
3800 | break; | |
3801 | default: | |
a44fec1f JP |
3802 | dev_warn(&pdev->dev, |
3803 | "Applying B2 workarounds to unknown rev\n"); | |
47c2b677 JG |
3804 | hp_flags |= MV_HP_ERRATA_50XXB2; |
3805 | break; | |
bca1c4eb JG |
3806 | } |
3807 | break; | |
3808 | ||
3809 | case chip_604x: | |
3810 | case chip_608x: | |
47c2b677 | 3811 | hpriv->ops = &mv6xxx_ops; |
ee9ccdf7 | 3812 | hp_flags |= MV_HP_GEN_II; |
47c2b677 | 3813 | |
44c10138 | 3814 | switch (pdev->revision) { |
47c2b677 | 3815 | case 0x7: |
65ad7fef | 3816 | mv_60x1b2_errata_pci7(host); |
47c2b677 JG |
3817 | hp_flags |= MV_HP_ERRATA_60X1B2; |
3818 | break; | |
3819 | case 0x9: | |
3820 | hp_flags |= MV_HP_ERRATA_60X1C0; | |
bca1c4eb JG |
3821 | break; |
3822 | default: | |
a44fec1f JP |
3823 | dev_warn(&pdev->dev, |
3824 | "Applying B2 workarounds to unknown rev\n"); | |
47c2b677 | 3825 | hp_flags |= MV_HP_ERRATA_60X1B2; |
bca1c4eb JG |
3826 | break; |
3827 | } | |
3828 | break; | |
3829 | ||
e4e7b892 | 3830 | case chip_7042: |
616d4a98 | 3831 | hp_flags |= MV_HP_PCIE | MV_HP_CUT_THROUGH; |
306b30f7 ML |
3832 | if (pdev->vendor == PCI_VENDOR_ID_TTI && |
3833 | (pdev->device == 0x2300 || pdev->device == 0x2310)) | |
3834 | { | |
4e520033 ML |
3835 | /* |
3836 | * Highpoint RocketRAID PCIe 23xx series cards: | |
3837 | * | |
3838 | * Unconfigured drives are treated as "Legacy" | |
3839 | * by the BIOS, and it overwrites sector 8 with | |
3840 | * a "Lgcy" metadata block prior to Linux boot. | |
3841 | * | |
3842 | * Configured drives (RAID or JBOD) leave sector 8 | |
3843 | * alone, but instead overwrite a high numbered | |
3844 | * sector for the RAID metadata. This sector can | |
3845 | * be determined exactly, by truncating the physical | |
3846 | * drive capacity to a nice even GB value. | |
3847 | * | |
3848 | * RAID metadata is at: (dev->n_sectors & ~0xfffff) | |
3849 | * | |
3850 | * Warn the user, lest they think we're just buggy. | |
3851 | */ | |
f76ba003 | 3852 | dev_warn(&pdev->dev, "Highpoint RocketRAID" |
4e520033 ML |
3853 | " BIOS CORRUPTS DATA on all attached drives," |
3854 | " regardless of if/how they are configured." | |
3855 | " BEWARE!\n"); | |
f76ba003 | 3856 | dev_warn(&pdev->dev, "For data safety, do not" |
4e520033 ML |
3857 | " use sectors 8-9 on \"Legacy\" drives," |
3858 | " and avoid the final two gigabytes on" | |
3859 | " all RocketRAID BIOS initialized drives.\n"); | |
306b30f7 | 3860 | } |
df561f66 | 3861 | fallthrough; |
e4e7b892 JG |
3862 | case chip_6042: |
3863 | hpriv->ops = &mv6xxx_ops; | |
e4e7b892 | 3864 | hp_flags |= MV_HP_GEN_IIE; |
616d4a98 ML |
3865 | if (board_idx == chip_6042 && mv_pci_cut_through_okay(host)) |
3866 | hp_flags |= MV_HP_CUT_THROUGH; | |
e4e7b892 | 3867 | |
44c10138 | 3868 | switch (pdev->revision) { |
5cf73bfb | 3869 | case 0x2: /* Rev.B0: the first/only public release */ |
e4e7b892 JG |
3870 | hp_flags |= MV_HP_ERRATA_60X1C0; |
3871 | break; | |
3872 | default: | |
a44fec1f JP |
3873 | dev_warn(&pdev->dev, |
3874 | "Applying 60X1C0 workarounds to unknown rev\n"); | |
e4e7b892 JG |
3875 | hp_flags |= MV_HP_ERRATA_60X1C0; |
3876 | break; | |
3877 | } | |
3878 | break; | |
f351b2d6 | 3879 | case chip_soc: |
29b7e43c MM |
3880 | if (soc_is_65n(hpriv)) |
3881 | hpriv->ops = &mv_soc_65n_ops; | |
3882 | else | |
3883 | hpriv->ops = &mv_soc_ops; | |
eb3a55a9 SB |
3884 | hp_flags |= MV_HP_FLAG_SOC | MV_HP_GEN_IIE | |
3885 | MV_HP_ERRATA_60X1C0; | |
f351b2d6 | 3886 | break; |
e4e7b892 | 3887 | |
bca1c4eb | 3888 | default: |
a0023bb9 ZM |
3889 | dev_alert(host->dev, "BUG: invalid board index %u\n", board_idx); |
3890 | return -EINVAL; | |
bca1c4eb JG |
3891 | } |
3892 | ||
3893 | hpriv->hp_flags = hp_flags; | |
02a121da | 3894 | if (hp_flags & MV_HP_PCIE) { |
cae5a29d ML |
3895 | hpriv->irq_cause_offset = PCIE_IRQ_CAUSE; |
3896 | hpriv->irq_mask_offset = PCIE_IRQ_MASK; | |
02a121da ML |
3897 | hpriv->unmask_all_irqs = PCIE_UNMASK_ALL_IRQS; |
3898 | } else { | |
cae5a29d ML |
3899 | hpriv->irq_cause_offset = PCI_IRQ_CAUSE; |
3900 | hpriv->irq_mask_offset = PCI_IRQ_MASK; | |
02a121da ML |
3901 | hpriv->unmask_all_irqs = PCI_UNMASK_ALL_IRQS; |
3902 | } | |
bca1c4eb JG |
3903 | |
3904 | return 0; | |
3905 | } | |
3906 | ||
05b308e1 | 3907 | /** |
47c2b677 | 3908 | * mv_init_host - Perform some early initialization of the host. |
4447d351 | 3909 | * @host: ATA host to initialize |
05b308e1 BR |
3910 | * |
3911 | * If possible, do an early global reset of the host. Then do | |
3912 | * our port init and clear/unmask all/relevant host interrupts. | |
3913 | * | |
3914 | * LOCKING: | |
3915 | * Inherited from caller. | |
3916 | */ | |
1bfeff03 | 3917 | static int mv_init_host(struct ata_host *host) |
20f733e7 BR |
3918 | { |
3919 | int rc = 0, n_hc, port, hc; | |
4447d351 | 3920 | struct mv_host_priv *hpriv = host->private_data; |
f351b2d6 | 3921 | void __iomem *mmio = hpriv->base; |
47c2b677 | 3922 | |
1bfeff03 | 3923 | rc = mv_chip_id(host, hpriv->board_idx); |
bca1c4eb | 3924 | if (rc) |
352fab70 | 3925 | goto done; |
f351b2d6 | 3926 | |
1f398472 | 3927 | if (IS_SOC(hpriv)) { |
cae5a29d ML |
3928 | hpriv->main_irq_cause_addr = mmio + SOC_HC_MAIN_IRQ_CAUSE; |
3929 | hpriv->main_irq_mask_addr = mmio + SOC_HC_MAIN_IRQ_MASK; | |
1f398472 | 3930 | } else { |
cae5a29d ML |
3931 | hpriv->main_irq_cause_addr = mmio + PCI_HC_MAIN_IRQ_CAUSE; |
3932 | hpriv->main_irq_mask_addr = mmio + PCI_HC_MAIN_IRQ_MASK; | |
f351b2d6 | 3933 | } |
352fab70 | 3934 | |
5d0fb2e7 TR |
3935 | /* initialize shadow irq mask with register's value */ |
3936 | hpriv->main_irq_mask = readl(hpriv->main_irq_mask_addr); | |
3937 | ||
352fab70 | 3938 | /* global interrupt mask: 0 == mask everything */ |
c4de573b | 3939 | mv_set_main_irq_mask(host, ~0, 0); |
bca1c4eb | 3940 | |
4447d351 | 3941 | n_hc = mv_get_hc_count(host->ports[0]->flags); |
bca1c4eb | 3942 | |
4447d351 | 3943 | for (port = 0; port < host->n_ports; port++) |
29b7e43c MM |
3944 | if (hpriv->ops->read_preamp) |
3945 | hpriv->ops->read_preamp(hpriv, port, mmio); | |
20f733e7 | 3946 | |
f76ba003 | 3947 | rc = hpriv->ops->reset_hc(host, mmio, n_hc); |
47c2b677 | 3948 | if (rc) |
20f733e7 | 3949 | goto done; |
20f733e7 | 3950 | |
522479fb | 3951 | hpriv->ops->reset_flash(hpriv, mmio); |
7bb3c529 | 3952 | hpriv->ops->reset_bus(host, mmio); |
47c2b677 | 3953 | hpriv->ops->enable_leds(hpriv, mmio); |
20f733e7 | 3954 | |
4447d351 | 3955 | for (port = 0; port < host->n_ports; port++) { |
cbcdd875 | 3956 | struct ata_port *ap = host->ports[port]; |
2a47ce06 | 3957 | void __iomem *port_mmio = mv_port_base(mmio, port); |
cbcdd875 TH |
3958 | |
3959 | mv_port_init(&ap->ioaddr, port_mmio); | |
20f733e7 BR |
3960 | } |
3961 | ||
3962 | for (hc = 0; hc < n_hc; hc++) { | |
31961943 BR |
3963 | void __iomem *hc_mmio = mv_hc_base(mmio, hc); |
3964 | ||
23b87b9f | 3965 | dev_dbg(host->dev, "HC%i: HC config=0x%08x HC IRQ cause " |
31961943 | 3966 | "(before clear)=0x%08x\n", hc, |
cae5a29d ML |
3967 | readl(hc_mmio + HC_CFG), |
3968 | readl(hc_mmio + HC_IRQ_CAUSE)); | |
31961943 BR |
3969 | |
3970 | /* Clear any currently outstanding hc interrupt conditions */ | |
cae5a29d | 3971 | writelfl(0, hc_mmio + HC_IRQ_CAUSE); |
20f733e7 BR |
3972 | } |
3973 | ||
44c65d16 ML |
3974 | if (!IS_SOC(hpriv)) { |
3975 | /* Clear any currently outstanding host interrupt conditions */ | |
cae5a29d | 3976 | writelfl(0, mmio + hpriv->irq_cause_offset); |
31961943 | 3977 | |
44c65d16 | 3978 | /* and unmask interrupt generation for host regs */ |
cae5a29d | 3979 | writelfl(hpriv->unmask_all_irqs, mmio + hpriv->irq_mask_offset); |
44c65d16 | 3980 | } |
51de32d2 | 3981 | |
6be96ac1 ML |
3982 | /* |
3983 | * enable only global host interrupts for now. | |
3984 | * The per-port interrupts get done later as ports are set up. | |
3985 | */ | |
3986 | mv_set_main_irq_mask(host, 0, PCI_ERR); | |
2b748a0a ML |
3987 | mv_set_irq_coalescing(host, irq_coalescing_io_count, |
3988 | irq_coalescing_usecs); | |
f351b2d6 SB |
3989 | done: |
3990 | return rc; | |
3991 | } | |
fb621e2f | 3992 | |
fbf14e2f BB |
3993 | static int mv_create_dma_pools(struct mv_host_priv *hpriv, struct device *dev) |
3994 | { | |
3995 | hpriv->crqb_pool = dmam_pool_create("crqb_q", dev, MV_CRQB_Q_SZ, | |
3996 | MV_CRQB_Q_SZ, 0); | |
3997 | if (!hpriv->crqb_pool) | |
3998 | return -ENOMEM; | |
3999 | ||
4000 | hpriv->crpb_pool = dmam_pool_create("crpb_q", dev, MV_CRPB_Q_SZ, | |
4001 | MV_CRPB_Q_SZ, 0); | |
4002 | if (!hpriv->crpb_pool) | |
4003 | return -ENOMEM; | |
4004 | ||
4005 | hpriv->sg_tbl_pool = dmam_pool_create("sg_tbl", dev, MV_SG_TBL_SZ, | |
4006 | MV_SG_TBL_SZ, 0); | |
4007 | if (!hpriv->sg_tbl_pool) | |
4008 | return -ENOMEM; | |
4009 | ||
4010 | return 0; | |
4011 | } | |
4012 | ||
15a32632 | 4013 | static void mv_conf_mbus_windows(struct mv_host_priv *hpriv, |
63a9332b | 4014 | const struct mbus_dram_target_info *dram) |
15a32632 LB |
4015 | { |
4016 | int i; | |
4017 | ||
4018 | for (i = 0; i < 4; i++) { | |
4019 | writel(0, hpriv->base + WINDOW_CTRL(i)); | |
4020 | writel(0, hpriv->base + WINDOW_BASE(i)); | |
4021 | } | |
4022 | ||
4023 | for (i = 0; i < dram->num_cs; i++) { | |
63a9332b | 4024 | const struct mbus_dram_window *cs = dram->cs + i; |
15a32632 LB |
4025 | |
4026 | writel(((cs->size - 1) & 0xffff0000) | | |
4027 | (cs->mbus_attr << 8) | | |
4028 | (dram->mbus_dram_target_id << 4) | 1, | |
4029 | hpriv->base + WINDOW_CTRL(i)); | |
4030 | writel(cs->base, hpriv->base + WINDOW_BASE(i)); | |
4031 | } | |
4032 | } | |
4033 | ||
f351b2d6 SB |
4034 | /** |
4035 | * mv_platform_probe - handle a positive probe of an soc Marvell | |
4036 | * host | |
4037 | * @pdev: platform device found | |
4038 | * | |
4039 | * LOCKING: | |
4040 | * Inherited from caller. | |
4041 | */ | |
4042 | static int mv_platform_probe(struct platform_device *pdev) | |
4043 | { | |
f351b2d6 | 4044 | const struct mv_sata_platform_data *mv_platform_data; |
63a9332b | 4045 | const struct mbus_dram_target_info *dram; |
f351b2d6 SB |
4046 | const struct ata_port_info *ppi[] = |
4047 | { &mv_port_info[chip_soc], NULL }; | |
4048 | struct ata_host *host; | |
4049 | struct mv_host_priv *hpriv; | |
4050 | struct resource *res; | |
97b414e1 | 4051 | int n_ports = 0, irq = 0; |
99b80e97 | 4052 | int rc; |
eee98990 | 4053 | int port; |
20f733e7 | 4054 | |
06296a1e | 4055 | ata_print_version_once(&pdev->dev, DRV_VERSION); |
bca1c4eb | 4056 | |
f351b2d6 SB |
4057 | /* |
4058 | * Simple resource validation .. | |
4059 | */ | |
b3b2bec9 | 4060 | if (unlikely(pdev->num_resources != 1)) { |
f351b2d6 SB |
4061 | dev_err(&pdev->dev, "invalid number of resources\n"); |
4062 | return -EINVAL; | |
4063 | } | |
4064 | ||
4065 | /* | |
4066 | * Get the register base first | |
4067 | */ | |
4068 | res = platform_get_resource(pdev, IORESOURCE_MEM, 0); | |
3e4240da AL |
4069 | if (res == NULL) |
4070 | return -EINVAL; | |
f351b2d6 SB |
4071 | |
4072 | /* allocate host */ | |
97b414e1 | 4073 | if (pdev->dev.of_node) { |
5c3ef397 UKK |
4074 | rc = of_property_read_u32(pdev->dev.of_node, "nr-ports", |
4075 | &n_ports); | |
4076 | if (rc) { | |
4077 | dev_err(&pdev->dev, | |
4078 | "error parsing nr-ports property: %d\n", rc); | |
4079 | return rc; | |
4080 | } | |
4081 | ||
4082 | if (n_ports <= 0) { | |
4083 | dev_err(&pdev->dev, "nr-ports must be positive: %d\n", | |
4084 | n_ports); | |
4085 | return -EINVAL; | |
4086 | } | |
4087 | ||
97b414e1 AL |
4088 | irq = irq_of_parse_and_map(pdev->dev.of_node, 0); |
4089 | } else { | |
61b8c345 | 4090 | mv_platform_data = dev_get_platdata(&pdev->dev); |
97b414e1 AL |
4091 | n_ports = mv_platform_data->n_ports; |
4092 | irq = platform_get_irq(pdev, 0); | |
4093 | } | |
e6471a65 SS |
4094 | if (irq < 0) |
4095 | return irq; | |
4096 | if (!irq) | |
4097 | return -EINVAL; | |
f351b2d6 SB |
4098 | |
4099 | host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports); | |
4100 | hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL); | |
4101 | ||
4102 | if (!host || !hpriv) | |
4103 | return -ENOMEM; | |
a86854d0 KC |
4104 | hpriv->port_clks = devm_kcalloc(&pdev->dev, |
4105 | n_ports, sizeof(struct clk *), | |
eee98990 AL |
4106 | GFP_KERNEL); |
4107 | if (!hpriv->port_clks) | |
4108 | return -ENOMEM; | |
a86854d0 KC |
4109 | hpriv->port_phys = devm_kcalloc(&pdev->dev, |
4110 | n_ports, sizeof(struct phy *), | |
b7db4f2e AL |
4111 | GFP_KERNEL); |
4112 | if (!hpriv->port_phys) | |
4113 | return -ENOMEM; | |
f351b2d6 | 4114 | host->private_data = hpriv; |
1bfeff03 | 4115 | hpriv->board_idx = chip_soc; |
f351b2d6 SB |
4116 | |
4117 | host->iomap = NULL; | |
3e4240da AL |
4118 | hpriv->base = devm_ioremap(&pdev->dev, res->start, |
4119 | resource_size(res)); | |
4120 | if (!hpriv->base) | |
4121 | return -ENOMEM; | |
4122 | ||
4123 | hpriv->base -= SATAHC0_REG_BASE; | |
f351b2d6 | 4124 | |
c77a2f4e SB |
4125 | hpriv->clk = clk_get(&pdev->dev, NULL); |
4126 | if (IS_ERR(hpriv->clk)) | |
eee98990 | 4127 | dev_notice(&pdev->dev, "cannot get optional clkdev\n"); |
c77a2f4e | 4128 | else |
eee98990 AL |
4129 | clk_prepare_enable(hpriv->clk); |
4130 | ||
4131 | for (port = 0; port < n_ports; port++) { | |
4132 | char port_number[16]; | |
4133 | sprintf(port_number, "%d", port); | |
4134 | hpriv->port_clks[port] = clk_get(&pdev->dev, port_number); | |
4135 | if (!IS_ERR(hpriv->port_clks[port])) | |
4136 | clk_prepare_enable(hpriv->port_clks[port]); | |
b7db4f2e AL |
4137 | |
4138 | sprintf(port_number, "port%d", port); | |
90aa2997 AL |
4139 | hpriv->port_phys[port] = devm_phy_optional_get(&pdev->dev, |
4140 | port_number); | |
b7db4f2e AL |
4141 | if (IS_ERR(hpriv->port_phys[port])) { |
4142 | rc = PTR_ERR(hpriv->port_phys[port]); | |
4143 | hpriv->port_phys[port] = NULL; | |
90aa2997 | 4144 | if (rc != -EPROBE_DEFER) |
54dfffde | 4145 | dev_warn(&pdev->dev, "error getting phy %d", rc); |
8ad116e6 EG |
4146 | |
4147 | /* Cleanup only the initialized ports */ | |
4148 | hpriv->n_ports = port; | |
b7db4f2e AL |
4149 | goto err; |
4150 | } else | |
4151 | phy_power_on(hpriv->port_phys[port]); | |
eee98990 | 4152 | } |
c77a2f4e | 4153 | |
8ad116e6 EG |
4154 | /* All the ports have been initialized */ |
4155 | hpriv->n_ports = n_ports; | |
4156 | ||
15a32632 LB |
4157 | /* |
4158 | * (Re-)program MBUS remapping windows if we are asked to. | |
4159 | */ | |
63a9332b AL |
4160 | dram = mv_mbus_dram_info(); |
4161 | if (dram) | |
4162 | mv_conf_mbus_windows(hpriv, dram); | |
15a32632 | 4163 | |
fbf14e2f BB |
4164 | rc = mv_create_dma_pools(hpriv, &pdev->dev); |
4165 | if (rc) | |
c77a2f4e | 4166 | goto err; |
fbf14e2f | 4167 | |
9013d64e LA |
4168 | /* |
4169 | * To allow disk hotplug on Armada 370/XP SoCs, the PHY speed must be | |
4170 | * updated in the LP_PHY_CTL register. | |
4171 | */ | |
4172 | if (pdev->dev.of_node && | |
4173 | of_device_is_compatible(pdev->dev.of_node, | |
4174 | "marvell,armada-370-sata")) | |
4175 | hpriv->hp_flags |= MV_HP_FIX_LP_PHY_CTL; | |
4176 | ||
f351b2d6 | 4177 | /* initialize adapter */ |
1bfeff03 | 4178 | rc = mv_init_host(host); |
f351b2d6 | 4179 | if (rc) |
c77a2f4e | 4180 | goto err; |
f351b2d6 | 4181 | |
a44fec1f JP |
4182 | dev_info(&pdev->dev, "slots %u ports %d\n", |
4183 | (unsigned)MV_MAX_Q_DEPTH, host->n_ports); | |
f351b2d6 | 4184 | |
97b414e1 | 4185 | rc = ata_host_activate(host, irq, mv_interrupt, IRQF_SHARED, &mv6_sht); |
c00a4c9d SS |
4186 | if (!rc) |
4187 | return 0; | |
4188 | ||
c77a2f4e | 4189 | err: |
c77a2f4e | 4190 | if (!IS_ERR(hpriv->clk)) { |
eee98990 | 4191 | clk_disable_unprepare(hpriv->clk); |
c77a2f4e SB |
4192 | clk_put(hpriv->clk); |
4193 | } | |
8ad116e6 | 4194 | for (port = 0; port < hpriv->n_ports; port++) { |
eee98990 AL |
4195 | if (!IS_ERR(hpriv->port_clks[port])) { |
4196 | clk_disable_unprepare(hpriv->port_clks[port]); | |
4197 | clk_put(hpriv->port_clks[port]); | |
4198 | } | |
fad06016 | 4199 | phy_power_off(hpriv->port_phys[port]); |
eee98990 | 4200 | } |
c77a2f4e SB |
4201 | |
4202 | return rc; | |
f351b2d6 SB |
4203 | } |
4204 | ||
4205 | /* | |
4206 | * | |
4207 | * mv_platform_remove - unplug a platform interface | |
4208 | * @pdev: platform device | |
4209 | * | |
4210 | * A platform bus SATA device has been unplugged. Perform the needed | |
4211 | * cleanup. Also called on module unload for any active devices. | |
4212 | */ | |
3596b025 | 4213 | static void mv_platform_remove(struct platform_device *pdev) |
f351b2d6 | 4214 | { |
d8661921 | 4215 | struct ata_host *host = platform_get_drvdata(pdev); |
c77a2f4e | 4216 | struct mv_host_priv *hpriv = host->private_data; |
eee98990 | 4217 | int port; |
f351b2d6 | 4218 | ata_host_detach(host); |
c77a2f4e | 4219 | |
c77a2f4e | 4220 | if (!IS_ERR(hpriv->clk)) { |
eee98990 | 4221 | clk_disable_unprepare(hpriv->clk); |
c77a2f4e SB |
4222 | clk_put(hpriv->clk); |
4223 | } | |
eee98990 AL |
4224 | for (port = 0; port < host->n_ports; port++) { |
4225 | if (!IS_ERR(hpriv->port_clks[port])) { | |
4226 | clk_disable_unprepare(hpriv->port_clks[port]); | |
4227 | clk_put(hpriv->port_clks[port]); | |
4228 | } | |
fad06016 | 4229 | phy_power_off(hpriv->port_phys[port]); |
eee98990 | 4230 | } |
20f733e7 BR |
4231 | } |
4232 | ||
58eb8cd5 | 4233 | #ifdef CONFIG_PM_SLEEP |
6481f2b5 SB |
4234 | static int mv_platform_suspend(struct platform_device *pdev, pm_message_t state) |
4235 | { | |
d8661921 | 4236 | struct ata_host *host = platform_get_drvdata(pdev); |
ec87cf37 | 4237 | |
6481f2b5 | 4238 | if (host) |
ec87cf37 SS |
4239 | ata_host_suspend(host, state); |
4240 | return 0; | |
6481f2b5 SB |
4241 | } |
4242 | ||
4243 | static int mv_platform_resume(struct platform_device *pdev) | |
4244 | { | |
d8661921 | 4245 | struct ata_host *host = platform_get_drvdata(pdev); |
63a9332b | 4246 | const struct mbus_dram_target_info *dram; |
6481f2b5 SB |
4247 | int ret; |
4248 | ||
4249 | if (host) { | |
4250 | struct mv_host_priv *hpriv = host->private_data; | |
63a9332b | 4251 | |
6481f2b5 SB |
4252 | /* |
4253 | * (Re-)program MBUS remapping windows if we are asked to. | |
4254 | */ | |
63a9332b AL |
4255 | dram = mv_mbus_dram_info(); |
4256 | if (dram) | |
4257 | mv_conf_mbus_windows(hpriv, dram); | |
6481f2b5 SB |
4258 | |
4259 | /* initialize adapter */ | |
1bfeff03 | 4260 | ret = mv_init_host(host); |
6481f2b5 | 4261 | if (ret) { |
f76ba003 | 4262 | dev_err(&pdev->dev, "Error during HW init\n"); |
6481f2b5 SB |
4263 | return ret; |
4264 | } | |
4265 | ata_host_resume(host); | |
4266 | } | |
4267 | ||
4268 | return 0; | |
4269 | } | |
4270 | #else | |
4271 | #define mv_platform_suspend NULL | |
4272 | #define mv_platform_resume NULL | |
4273 | #endif | |
4274 | ||
97b414e1 | 4275 | #ifdef CONFIG_OF |
e3779f6a | 4276 | static const struct of_device_id mv_sata_dt_ids[] = { |
b1f5c73b | 4277 | { .compatible = "marvell,armada-370-sata", }, |
97b414e1 | 4278 | { .compatible = "marvell,orion-sata", }, |
5e776d7b | 4279 | { /* sentinel */ } |
97b414e1 AL |
4280 | }; |
4281 | MODULE_DEVICE_TABLE(of, mv_sata_dt_ids); | |
4282 | #endif | |
4283 | ||
f351b2d6 | 4284 | static struct platform_driver mv_platform_driver = { |
97b414e1 | 4285 | .probe = mv_platform_probe, |
3596b025 | 4286 | .remove_new = mv_platform_remove, |
97b414e1 AL |
4287 | .suspend = mv_platform_suspend, |
4288 | .resume = mv_platform_resume, | |
4289 | .driver = { | |
4290 | .name = DRV_NAME, | |
97b414e1 AL |
4291 | .of_match_table = of_match_ptr(mv_sata_dt_ids), |
4292 | }, | |
f351b2d6 SB |
4293 | }; |
4294 | ||
4295 | ||
7bb3c529 | 4296 | #ifdef CONFIG_PCI |
f351b2d6 SB |
4297 | static int mv_pci_init_one(struct pci_dev *pdev, |
4298 | const struct pci_device_id *ent); | |
58eb8cd5 | 4299 | #ifdef CONFIG_PM_SLEEP |
b2dec48c SB |
4300 | static int mv_pci_device_resume(struct pci_dev *pdev); |
4301 | #endif | |
f351b2d6 | 4302 | |
7bb3c529 SB |
4303 | |
4304 | static struct pci_driver mv_pci_driver = { | |
4305 | .name = DRV_NAME, | |
4306 | .id_table = mv_pci_tbl, | |
f351b2d6 | 4307 | .probe = mv_pci_init_one, |
7bb3c529 | 4308 | .remove = ata_pci_remove_one, |
58eb8cd5 | 4309 | #ifdef CONFIG_PM_SLEEP |
b2dec48c SB |
4310 | .suspend = ata_pci_device_suspend, |
4311 | .resume = mv_pci_device_resume, | |
4312 | #endif | |
4313 | ||
7bb3c529 SB |
4314 | }; |
4315 | ||
05b308e1 BR |
4316 | /** |
4317 | * mv_print_info - Dump key info to kernel log for perusal. | |
4447d351 | 4318 | * @host: ATA host to print info about |
05b308e1 BR |
4319 | * |
4320 | * FIXME: complete this. | |
4321 | * | |
4322 | * LOCKING: | |
4323 | * Inherited from caller. | |
4324 | */ | |
4447d351 | 4325 | static void mv_print_info(struct ata_host *host) |
31961943 | 4326 | { |
4447d351 TH |
4327 | struct pci_dev *pdev = to_pci_dev(host->dev); |
4328 | struct mv_host_priv *hpriv = host->private_data; | |
44c10138 | 4329 | u8 scc; |
c1e4fe71 | 4330 | const char *scc_s, *gen; |
31961943 BR |
4331 | |
4332 | /* Use this to determine the HW stepping of the chip so we know | |
4333 | * what errata to workaround | |
4334 | */ | |
31961943 BR |
4335 | pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &scc); |
4336 | if (scc == 0) | |
4337 | scc_s = "SCSI"; | |
4338 | else if (scc == 0x01) | |
4339 | scc_s = "RAID"; | |
4340 | else | |
c1e4fe71 JG |
4341 | scc_s = "?"; |
4342 | ||
4343 | if (IS_GEN_I(hpriv)) | |
4344 | gen = "I"; | |
4345 | else if (IS_GEN_II(hpriv)) | |
4346 | gen = "II"; | |
4347 | else if (IS_GEN_IIE(hpriv)) | |
4348 | gen = "IIE"; | |
4349 | else | |
4350 | gen = "?"; | |
31961943 | 4351 | |
a44fec1f JP |
4352 | dev_info(&pdev->dev, "Gen-%s %u slots %u ports %s mode IRQ via %s\n", |
4353 | gen, (unsigned)MV_MAX_Q_DEPTH, host->n_ports, | |
4354 | scc_s, (MV_HP_FLAG_MSI & hpriv->hp_flags) ? "MSI" : "INTx"); | |
31961943 BR |
4355 | } |
4356 | ||
05b308e1 | 4357 | /** |
f351b2d6 | 4358 | * mv_pci_init_one - handle a positive probe of a PCI Marvell host |
05b308e1 BR |
4359 | * @pdev: PCI device found |
4360 | * @ent: PCI device ID entry for the matched host | |
4361 | * | |
4362 | * LOCKING: | |
4363 | * Inherited from caller. | |
4364 | */ | |
f351b2d6 SB |
4365 | static int mv_pci_init_one(struct pci_dev *pdev, |
4366 | const struct pci_device_id *ent) | |
20f733e7 | 4367 | { |
20f733e7 | 4368 | unsigned int board_idx = (unsigned int)ent->driver_data; |
4447d351 TH |
4369 | const struct ata_port_info *ppi[] = { &mv_port_info[board_idx], NULL }; |
4370 | struct ata_host *host; | |
4371 | struct mv_host_priv *hpriv; | |
c4bc7d73 | 4372 | int n_ports, port, rc; |
20f733e7 | 4373 | |
06296a1e | 4374 | ata_print_version_once(&pdev->dev, DRV_VERSION); |
20f733e7 | 4375 | |
4447d351 TH |
4376 | /* allocate host */ |
4377 | n_ports = mv_get_hc_count(ppi[0]->flags) * MV_PORTS_PER_HC; | |
4378 | ||
4379 | host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports); | |
4380 | hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL); | |
4381 | if (!host || !hpriv) | |
4382 | return -ENOMEM; | |
4383 | host->private_data = hpriv; | |
f351b2d6 | 4384 | hpriv->n_ports = n_ports; |
1bfeff03 | 4385 | hpriv->board_idx = board_idx; |
4447d351 TH |
4386 | |
4387 | /* acquire resources */ | |
24dc5f33 TH |
4388 | rc = pcim_enable_device(pdev); |
4389 | if (rc) | |
20f733e7 | 4390 | return rc; |
20f733e7 | 4391 | |
0d5ff566 TH |
4392 | rc = pcim_iomap_regions(pdev, 1 << MV_PRIMARY_BAR, DRV_NAME); |
4393 | if (rc == -EBUSY) | |
24dc5f33 | 4394 | pcim_pin_device(pdev); |
0d5ff566 | 4395 | if (rc) |
24dc5f33 | 4396 | return rc; |
4447d351 | 4397 | host->iomap = pcim_iomap_table(pdev); |
f351b2d6 | 4398 | hpriv->base = host->iomap[MV_PRIMARY_BAR]; |
20f733e7 | 4399 | |
496d4575 CH |
4400 | rc = dma_set_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); |
4401 | if (rc) { | |
4402 | dev_err(&pdev->dev, "DMA enable failed\n"); | |
d88184fb | 4403 | return rc; |
496d4575 | 4404 | } |
d88184fb | 4405 | |
da2fa9ba ML |
4406 | rc = mv_create_dma_pools(hpriv, &pdev->dev); |
4407 | if (rc) | |
4408 | return rc; | |
4409 | ||
c4bc7d73 SB |
4410 | for (port = 0; port < host->n_ports; port++) { |
4411 | struct ata_port *ap = host->ports[port]; | |
4412 | void __iomem *port_mmio = mv_port_base(hpriv->base, port); | |
4413 | unsigned int offset = port_mmio - hpriv->base; | |
4414 | ||
4415 | ata_port_pbar_desc(ap, MV_PRIMARY_BAR, -1, "mmio"); | |
4416 | ata_port_pbar_desc(ap, MV_PRIMARY_BAR, offset, "port"); | |
4417 | } | |
4418 | ||
20f733e7 | 4419 | /* initialize adapter */ |
1bfeff03 | 4420 | rc = mv_init_host(host); |
24dc5f33 TH |
4421 | if (rc) |
4422 | return rc; | |
20f733e7 | 4423 | |
6d3c30ef ML |
4424 | /* Enable message-switched interrupts, if requested */ |
4425 | if (msi && pci_enable_msi(pdev) == 0) | |
4426 | hpriv->hp_flags |= MV_HP_FLAG_MSI; | |
20f733e7 | 4427 | |
31961943 | 4428 | mv_dump_pci_cfg(pdev, 0x68); |
4447d351 | 4429 | mv_print_info(host); |
20f733e7 | 4430 | |
4447d351 | 4431 | pci_set_master(pdev); |
ea8b4db9 | 4432 | pci_try_set_mwi(pdev); |
4447d351 | 4433 | return ata_host_activate(host, pdev->irq, mv_interrupt, IRQF_SHARED, |
c5d3e45a | 4434 | IS_GEN_I(hpriv) ? &mv5_sht : &mv6_sht); |
20f733e7 | 4435 | } |
b2dec48c | 4436 | |
58eb8cd5 | 4437 | #ifdef CONFIG_PM_SLEEP |
b2dec48c SB |
4438 | static int mv_pci_device_resume(struct pci_dev *pdev) |
4439 | { | |
d8661921 | 4440 | struct ata_host *host = pci_get_drvdata(pdev); |
b2dec48c SB |
4441 | int rc; |
4442 | ||
4443 | rc = ata_pci_device_do_resume(pdev); | |
4444 | if (rc) | |
4445 | return rc; | |
4446 | ||
4447 | /* initialize adapter */ | |
4448 | rc = mv_init_host(host); | |
4449 | if (rc) | |
4450 | return rc; | |
4451 | ||
4452 | ata_host_resume(host); | |
4453 | ||
4454 | return 0; | |
4455 | } | |
4456 | #endif | |
7bb3c529 | 4457 | #endif |
20f733e7 BR |
4458 | |
4459 | static int __init mv_init(void) | |
4460 | { | |
7bb3c529 SB |
4461 | int rc = -ENODEV; |
4462 | #ifdef CONFIG_PCI | |
4463 | rc = pci_register_driver(&mv_pci_driver); | |
f351b2d6 SB |
4464 | if (rc < 0) |
4465 | return rc; | |
4466 | #endif | |
4467 | rc = platform_driver_register(&mv_platform_driver); | |
4468 | ||
4469 | #ifdef CONFIG_PCI | |
4470 | if (rc < 0) | |
4471 | pci_unregister_driver(&mv_pci_driver); | |
7bb3c529 SB |
4472 | #endif |
4473 | return rc; | |
20f733e7 BR |
4474 | } |
4475 | ||
4476 | static void __exit mv_exit(void) | |
4477 | { | |
7bb3c529 | 4478 | #ifdef CONFIG_PCI |
20f733e7 | 4479 | pci_unregister_driver(&mv_pci_driver); |
7bb3c529 | 4480 | #endif |
f351b2d6 | 4481 | platform_driver_unregister(&mv_platform_driver); |
20f733e7 BR |
4482 | } |
4483 | ||
4484 | MODULE_AUTHOR("Brett Russ"); | |
4485 | MODULE_DESCRIPTION("SCSI low-level driver for Marvell SATA controllers"); | |
88af4bbd | 4486 | MODULE_LICENSE("GPL v2"); |
20f733e7 BR |
4487 | MODULE_DEVICE_TABLE(pci, mv_pci_tbl); |
4488 | MODULE_VERSION(DRV_VERSION); | |
17c5aab5 | 4489 | MODULE_ALIAS("platform:" DRV_NAME); |
20f733e7 BR |
4490 | |
4491 | module_init(mv_init); | |
4492 | module_exit(mv_exit); |