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Merge branch 'for-linus' of git://git.kernel.org/pub/scm/linux/kernel/git/sage/ceph...
[linux-2.6-block.git] / drivers / ata / sata_mv.c
CommitLineData
20f733e7
BR		 1/*
2 * sata_mv.c - Marvell SATA support
3 *
40f21b11 4 * Copyright 2008-2009: Marvell Corporation, all rights reserved.
8b260248 5 * Copyright 2005: EMC Corporation, all rights reserved.
e2b1be56 6 * Copyright 2005 Red Hat, Inc. All rights reserved.
20f733e7 7 *
40f21b11
ML		 8 * Originally written by Brett Russ.
9 * Extensive overhaul and enhancement by Mark Lord <mlord@pobox.com>.
10 *
20f733e7
BR		 11 * Please ALWAYS copy linux-ide@vger.kernel.org on emails.
12 *
13 * This program is free software; you can redistribute it and/or modify
14 * it under the terms of the GNU General Public License as published by
15 * the Free Software Foundation; version 2 of the License.
16 *
17 * This program is distributed in the hope that it will be useful,
18 * but WITHOUT ANY WARRANTY; without even the implied warranty of
19 * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
20 * GNU General Public License for more details.
21 *
22 * You should have received a copy of the GNU General Public License
23 * along with this program; if not, write to the Free Software
24 * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA
25 *
26 */
27
4a05e209 28/*
85afb934
ML		 29 * sata_mv TODO list:
30 *
85afb934
ML		 31 * --> Develop a low-power-consumption strategy, and implement it.
32 *
2b748a0a 33 * --> Add sysfs attributes for per-chip / per-HC IRQ coalescing thresholds.
85afb934
ML		 34 *
35 * --> [Experiment, Marvell value added] Is it possible to use target
36 * mode to cross-connect two Linux boxes with Marvell cards? If so,
37 * creating LibATA target mode support would be very interesting.
38 *
39 * Target mode, for those without docs, is the ability to directly
40 * connect two SATA ports.
41 */
4a05e209 42
65ad7fef
ML		 43/*
44 * 80x1-B2 errata PCI#11:
45 *
46 * Users of the 6041/6081 Rev.B2 chips (current is C0)
47 * should be careful to insert those cards only onto PCI-X bus #0,
48 * and only in device slots 0..7, not higher. The chips may not
49 * work correctly otherwise (note: this is a pretty rare condition).
50 */
51
20f733e7
BR		 52#include <linux/kernel.h>
53#include <linux/module.h>
54#include <linux/pci.h>
55#include <linux/init.h>
56#include <linux/blkdev.h>
57#include <linux/delay.h>
58#include <linux/interrupt.h>
8d8b6004 59#include <linux/dmapool.h>
20f733e7 60#include <linux/dma-mapping.h>
a9524a76 61#include <linux/device.h>
c77a2f4e 62#include <linux/clk.h>
f351b2d6
SB		 63#include <linux/platform_device.h>
64#include <linux/ata_platform.h>
15a32632 65#include <linux/mbus.h>
c46938cc 66#include <linux/bitops.h>
5a0e3ad6 67#include <linux/gfp.h>
20f733e7 68#include <scsi/scsi_host.h>
193515d5 69#include <scsi/scsi_cmnd.h>
6c08772e 70#include <scsi/scsi_device.h>
20f733e7 71#include <linux/libata.h>
20f733e7
BR		 72
73#define DRV_NAME "sata_mv"
cae5a29d 74#define DRV_VERSION "1.28"
20f733e7 75
40f21b11
ML		 76/*
77 * module options
78 */
79
80static int msi;
81#ifdef CONFIG_PCI
82module_param(msi, int, S_IRUGO);
83MODULE_PARM_DESC(msi, "Enable use of PCI MSI (0=off, 1=on)");
84#endif
85
2b748a0a
ML		 86static int irq_coalescing_io_count;
87module_param(irq_coalescing_io_count, int, S_IRUGO);
88MODULE_PARM_DESC(irq_coalescing_io_count,
89 "IRQ coalescing I/O count threshold (0..255)");
90
91static int irq_coalescing_usecs;
92module_param(irq_coalescing_usecs, int, S_IRUGO);
93MODULE_PARM_DESC(irq_coalescing_usecs,
94 "IRQ coalescing time threshold in usecs");
95
20f733e7
BR		 96enum {
97 /* BAR's are enumerated in terms of pci_resource_start() terms */
98 MV_PRIMARY_BAR = 0, /* offset 0x10: memory space */
99 MV_IO_BAR = 2, /* offset 0x18: IO space */
100 MV_MISC_BAR = 3, /* offset 0x1c: FLASH, NVRAM, SRAM */
101
102 MV_MAJOR_REG_AREA_SZ = 0x10000, /* 64KB */
103 MV_MINOR_REG_AREA_SZ = 0x2000, /* 8KB */
104
2b748a0a
ML		 105 /* For use with both IRQ coalescing methods ("all ports" or "per-HC" */
106 COAL_CLOCKS_PER_USEC = 150, /* for calculating COAL_TIMEs */
107 MAX_COAL_TIME_THRESHOLD = ((1 << 24) - 1), /* internal clocks count */
108 MAX_COAL_IO_COUNT = 255, /* completed I/O count */
109
20f733e7 110 MV_PCI_REG_BASE = 0,
615ab953 111
2b748a0a
ML		 112 /*
113 * Per-chip ("all ports") interrupt coalescing feature.
114 * This is only for GEN_II / GEN_IIE hardware.
115 *
116 * Coalescing defers the interrupt until either the IO_THRESHOLD
117 * (count of completed I/Os) is met, or the TIME_THRESHOLD is met.
118 */
cae5a29d
ML		 119 COAL_REG_BASE = 0x18000,
120 IRQ_COAL_CAUSE = (COAL_REG_BASE + 0x08),
2b748a0a
ML		 121 ALL_PORTS_COAL_IRQ = (1 << 4), /* all ports irq event */
122
cae5a29d
ML		 123 IRQ_COAL_IO_THRESHOLD = (COAL_REG_BASE + 0xcc),
124 IRQ_COAL_TIME_THRESHOLD = (COAL_REG_BASE + 0xd0),
2b748a0a
ML		 125
126 /*
127 * Registers for the (unused here) transaction coalescing feature:
128 */
cae5a29d
ML		 129 TRAN_COAL_CAUSE_LO = (COAL_REG_BASE + 0x88),
130 TRAN_COAL_CAUSE_HI = (COAL_REG_BASE + 0x8c),
2b748a0a 131
cae5a29d
ML		 132 SATAHC0_REG_BASE = 0x20000,
133 FLASH_CTL = 0x1046c,
134 GPIO_PORT_CTL = 0x104f0,
135 RESET_CFG = 0x180d8,
20f733e7
BR		 136
137 MV_PCI_REG_SZ = MV_MAJOR_REG_AREA_SZ,
138 MV_SATAHC_REG_SZ = MV_MAJOR_REG_AREA_SZ,
139 MV_SATAHC_ARBTR_REG_SZ = MV_MINOR_REG_AREA_SZ, /* arbiter */
140 MV_PORT_REG_SZ = MV_MINOR_REG_AREA_SZ,
141
31961943
BR		 142 MV_MAX_Q_DEPTH = 32,
143 MV_MAX_Q_DEPTH_MASK = MV_MAX_Q_DEPTH - 1,
144
145 /* CRQB needs alignment on a 1KB boundary. Size == 1KB
146 * CRPB needs alignment on a 256B boundary. Size == 256B
31961943
BR		 147 * ePRD (SG) entries need alignment on a 16B boundary. Size == 16B
148 */
149 MV_CRQB_Q_SZ = (32 * MV_MAX_Q_DEPTH),
150 MV_CRPB_Q_SZ = (8 * MV_MAX_Q_DEPTH),
da2fa9ba 151 MV_MAX_SG_CT = 256,
31961943 152 MV_SG_TBL_SZ = (16 * MV_MAX_SG_CT),
31961943 153
352fab70 154 /* Determine hc from 0-7 port: hc = port >> MV_PORT_HC_SHIFT */
20f733e7 155 MV_PORT_HC_SHIFT = 2,
352fab70
ML		 156 MV_PORTS_PER_HC = (1 << MV_PORT_HC_SHIFT), /* 4 */
157 /* Determine hc port from 0-7 port: hardport = port & MV_PORT_MASK */
158 MV_PORT_MASK = (MV_PORTS_PER_HC - 1), /* 3 */
20f733e7
BR		 159
160 /* Host Flags */
161 MV_FLAG_DUAL_HC = (1 << 30), /* two SATA Host Controllers */
7bb3c529 162
9cbe056f 163 MV_COMMON_FLAGS = ATA_FLAG_SATA | ATA_FLAG_PIO_POLLING,
ad3aef51 164
91b1a84c 165 MV_GEN_I_FLAGS = MV_COMMON_FLAGS | ATA_FLAG_NO_ATAPI,
20f733e7 166
40f21b11
ML		 167 MV_GEN_II_FLAGS = MV_COMMON_FLAGS | ATA_FLAG_NCQ |
168 ATA_FLAG_PMP | ATA_FLAG_ACPI_SATA,
91b1a84c
ML		 169
170 MV_GEN_IIE_FLAGS = MV_GEN_II_FLAGS | ATA_FLAG_AN,
ad3aef51 171
31961943
BR		 172 CRQB_FLAG_READ = (1 << 0),
173 CRQB_TAG_SHIFT = 1,
c5d3e45a 174 CRQB_IOID_SHIFT = 6, /* CRQB Gen-II/IIE IO Id shift */
e12bef50 175 CRQB_PMP_SHIFT = 12, /* CRQB Gen-II/IIE PMP shift */
c5d3e45a 176 CRQB_HOSTQ_SHIFT = 17, /* CRQB Gen-II/IIE HostQueTag shift */
31961943
BR		 177 CRQB_CMD_ADDR_SHIFT = 8,
178 CRQB_CMD_CS = (0x2 << 11),
179 CRQB_CMD_LAST = (1 << 15),
180
181 CRPB_FLAG_STATUS_SHIFT = 8,
c5d3e45a
JG		 182 CRPB_IOID_SHIFT_6 = 5, /* CRPB Gen-II IO Id shift */
183 CRPB_IOID_SHIFT_7 = 7, /* CRPB Gen-IIE IO Id shift */
31961943
BR		 184
185 EPRD_FLAG_END_OF_TBL = (1 << 31),
186
20f733e7
BR		 187 /* PCI interface registers */
188
cae5a29d
ML		 189 MV_PCI_COMMAND = 0xc00,
190 MV_PCI_COMMAND_MWRCOM = (1 << 4), /* PCI Master Write Combining */
191 MV_PCI_COMMAND_MRDTRIG = (1 << 7), /* PCI Master Read Trigger */
31961943 192
cae5a29d 193 PCI_MAIN_CMD_STS = 0xd30,
20f733e7
BR		 194 STOP_PCI_MASTER = (1 << 2),
195 PCI_MASTER_EMPTY = (1 << 3),
196 GLOB_SFT_RST = (1 << 4),
197
cae5a29d 198 MV_PCI_MODE = 0xd00,
8e7decdb
ML		 199 MV_PCI_MODE_MASK = 0x30,
200
522479fb
JG		 201 MV_PCI_EXP_ROM_BAR_CTL = 0xd2c,
202 MV_PCI_DISC_TIMER = 0xd04,
203 MV_PCI_MSI_TRIGGER = 0xc38,
204 MV_PCI_SERR_MASK = 0xc28,
cae5a29d 205 MV_PCI_XBAR_TMOUT = 0x1d04,
522479fb
JG		 206 MV_PCI_ERR_LOW_ADDRESS = 0x1d40,
207 MV_PCI_ERR_HIGH_ADDRESS = 0x1d44,
208 MV_PCI_ERR_ATTRIBUTE = 0x1d48,
209 MV_PCI_ERR_COMMAND = 0x1d50,
210
cae5a29d
ML		 211 PCI_IRQ_CAUSE = 0x1d58,
212 PCI_IRQ_MASK = 0x1d5c,
20f733e7
BR		 213 PCI_UNMASK_ALL_IRQS = 0x7fffff, /* bits 22-0 */
214
cae5a29d
ML		 215 PCIE_IRQ_CAUSE = 0x1900,
216 PCIE_IRQ_MASK = 0x1910,
646a4da5 217 PCIE_UNMASK_ALL_IRQS = 0x40a, /* assorted bits */
02a121da 218
7368f919 219 /* Host Controller Main Interrupt Cause/Mask registers (1 per-chip) */
cae5a29d
ML		 220 PCI_HC_MAIN_IRQ_CAUSE = 0x1d60,
221 PCI_HC_MAIN_IRQ_MASK = 0x1d64,
222 SOC_HC_MAIN_IRQ_CAUSE = 0x20020,
223 SOC_HC_MAIN_IRQ_MASK = 0x20024,
40f21b11
ML		 224 ERR_IRQ = (1 << 0), /* shift by (2 * port #) */
225 DONE_IRQ = (1 << 1), /* shift by (2 * port #) */
20f733e7
BR		 226 HC0_IRQ_PEND = 0x1ff, /* bits 0-8 = HC0's ports */
227 HC_SHIFT = 9, /* bits 9-17 = HC1's ports */
2b748a0a
ML		 228 DONE_IRQ_0_3 = 0x000000aa, /* DONE_IRQ ports 0,1,2,3 */
229 DONE_IRQ_4_7 = (DONE_IRQ_0_3 << HC_SHIFT), /* 4,5,6,7 */
20f733e7 230 PCI_ERR = (1 << 18),
40f21b11
ML		 231 TRAN_COAL_LO_DONE = (1 << 19), /* transaction coalescing */
232 TRAN_COAL_HI_DONE = (1 << 20), /* transaction coalescing */
233 PORTS_0_3_COAL_DONE = (1 << 8), /* HC0 IRQ coalescing */
234 PORTS_4_7_COAL_DONE = (1 << 17), /* HC1 IRQ coalescing */
235 ALL_PORTS_COAL_DONE = (1 << 21), /* GEN_II(E) IRQ coalescing */
20f733e7
BR		 236 GPIO_INT = (1 << 22),
237 SELF_INT = (1 << 23),
238 TWSI_INT = (1 << 24),
239 HC_MAIN_RSVD = (0x7f << 25), /* bits 31-25 */
fb621e2f 240 HC_MAIN_RSVD_5 = (0x1fff << 19), /* bits 31-19 */
e12bef50 241 HC_MAIN_RSVD_SOC = (0x3fffffb << 6), /* bits 31-9, 7-6 */
20f733e7
BR		 242
243 /* SATAHC registers */
cae5a29d 244 HC_CFG = 0x00,
20f733e7 245
cae5a29d 246 HC_IRQ_CAUSE = 0x14,
352fab70
ML		 247 DMA_IRQ = (1 << 0), /* shift by port # */
248 HC_COAL_IRQ = (1 << 4), /* IRQ coalescing */
20f733e7
BR		 249 DEV_IRQ = (1 << 8), /* shift by port # */
250
2b748a0a
ML		 251 /*
252 * Per-HC (Host-Controller) interrupt coalescing feature.
253 * This is present on all chip generations.
254 *
255 * Coalescing defers the interrupt until either the IO_THRESHOLD
256 * (count of completed I/Os) is met, or the TIME_THRESHOLD is met.
257 */
cae5a29d
ML		 258 HC_IRQ_COAL_IO_THRESHOLD = 0x000c,
259 HC_IRQ_COAL_TIME_THRESHOLD = 0x0010,
2b748a0a 260
cae5a29d 261 SOC_LED_CTRL = 0x2c,
000b344f
ML		 262 SOC_LED_CTRL_BLINK = (1 << 0), /* Active LED blink */
263 SOC_LED_CTRL_ACT_PRESENCE = (1 << 2), /* Multiplex dev presence */
264 /* with dev activity LED */
265
20f733e7 266 /* Shadow block registers */
cae5a29d
ML		 267 SHD_BLK = 0x100,
268 SHD_CTL_AST = 0x20, /* ofs from SHD_BLK */
20f733e7
BR		 269
270 /* SATA registers */
cae5a29d
ML		 271 SATA_STATUS = 0x300, /* ctrl, err regs follow status */
272 SATA_ACTIVE = 0x350,
273 FIS_IRQ_CAUSE = 0x364,
274 FIS_IRQ_CAUSE_AN = (1 << 9), /* async notification */
17c5aab5 275
cae5a29d 276 LTMODE = 0x30c, /* requires read-after-write */
17c5aab5
ML		 277 LTMODE_BIT8 = (1 << 8), /* unknown, but necessary */
278
cae5a29d 279 PHY_MODE2 = 0x330,
47c2b677 280 PHY_MODE3 = 0x310,
cae5a29d
ML		 281
282 PHY_MODE4 = 0x314, /* requires read-after-write */
ba069e37
ML		 283 PHY_MODE4_CFG_MASK = 0x00000003, /* phy internal config field */
284 PHY_MODE4_CFG_VALUE = 0x00000001, /* phy internal config field */
285 PHY_MODE4_RSVD_ZEROS = 0x5de3fffa, /* Gen2e always write zeros */
286 PHY_MODE4_RSVD_ONES = 0x00000005, /* Gen2e always write ones */
287
cae5a29d
ML		 288 SATA_IFCTL = 0x344,
289 SATA_TESTCTL = 0x348,
290 SATA_IFSTAT = 0x34c,
291 VENDOR_UNIQUE_FIS = 0x35c,
17c5aab5 292
cae5a29d 293 FISCFG = 0x360,
8e7decdb
ML		 294 FISCFG_WAIT_DEV_ERR = (1 << 8), /* wait for host on DevErr */
295 FISCFG_SINGLE_SYNC = (1 << 16), /* SYNC on DMA activation */
17c5aab5 296
29b7e43c
MM		 297 PHY_MODE9_GEN2 = 0x398,
298 PHY_MODE9_GEN1 = 0x39c,
299 PHYCFG_OFS = 0x3a0, /* only in 65n devices */
300
c9d39130 301 MV5_PHY_MODE = 0x74,
cae5a29d
ML		 302 MV5_LTMODE = 0x30,
303 MV5_PHY_CTL = 0x0C,
304 SATA_IFCFG = 0x050,
bca1c4eb
JG		 305
306 MV_M2_PREAMP_MASK = 0x7e0,
20f733e7
BR		 307
308 /* Port registers */
cae5a29d 309 EDMA_CFG = 0,
0c58912e
ML		 310 EDMA_CFG_Q_DEPTH = 0x1f, /* max device queue depth */
311 EDMA_CFG_NCQ = (1 << 5), /* for R/W FPDMA queued */
312 EDMA_CFG_NCQ_GO_ON_ERR = (1 << 14), /* continue on error */
313 EDMA_CFG_RD_BRST_EXT = (1 << 11), /* read burst 512B */
314 EDMA_CFG_WR_BUFF_LEN = (1 << 13), /* write buffer 512B */
e12bef50
ML		 315 EDMA_CFG_EDMA_FBS = (1 << 16), /* EDMA FIS-Based Switching */
316 EDMA_CFG_FBS = (1 << 26), /* FIS-Based Switching */
20f733e7 317
cae5a29d
ML		 318 EDMA_ERR_IRQ_CAUSE = 0x8,
319 EDMA_ERR_IRQ_MASK = 0xc,
6c1153e0
JG		 320 EDMA_ERR_D_PAR = (1 << 0), /* UDMA data parity err */
321 EDMA_ERR_PRD_PAR = (1 << 1), /* UDMA PRD parity err */
322 EDMA_ERR_DEV = (1 << 2), /* device error */
323 EDMA_ERR_DEV_DCON = (1 << 3), /* device disconnect */
324 EDMA_ERR_DEV_CON = (1 << 4), /* device connected */
325 EDMA_ERR_SERR = (1 << 5), /* SError bits [WBDST] raised */
c5d3e45a
JG		 326 EDMA_ERR_SELF_DIS = (1 << 7), /* Gen II/IIE self-disable */
327 EDMA_ERR_SELF_DIS_5 = (1 << 8), /* Gen I self-disable */
6c1153e0 328 EDMA_ERR_BIST_ASYNC = (1 << 8), /* BIST FIS or Async Notify */
c5d3e45a 329 EDMA_ERR_TRANS_IRQ_7 = (1 << 8), /* Gen IIE transprt layer irq */
6c1153e0
JG		 330 EDMA_ERR_CRQB_PAR = (1 << 9), /* CRQB parity error */
331 EDMA_ERR_CRPB_PAR = (1 << 10), /* CRPB parity error */
332 EDMA_ERR_INTRL_PAR = (1 << 11), /* internal parity error */
333 EDMA_ERR_IORDY = (1 << 12), /* IORdy timeout */
646a4da5 334
6c1153e0 335 EDMA_ERR_LNK_CTRL_RX = (0xf << 13), /* link ctrl rx error */
646a4da5
ML		 336 EDMA_ERR_LNK_CTRL_RX_0 = (1 << 13), /* transient: CRC err */
337 EDMA_ERR_LNK_CTRL_RX_1 = (1 << 14), /* transient: FIFO err */
338 EDMA_ERR_LNK_CTRL_RX_2 = (1 << 15), /* fatal: caught SYNC */
339 EDMA_ERR_LNK_CTRL_RX_3 = (1 << 16), /* transient: FIS rx err */
340
6c1153e0 341 EDMA_ERR_LNK_DATA_RX = (0xf << 17), /* link data rx error */
646a4da5 342
6c1153e0 343 EDMA_ERR_LNK_CTRL_TX = (0x1f << 21), /* link ctrl tx error */
646a4da5
ML		 344 EDMA_ERR_LNK_CTRL_TX_0 = (1 << 21), /* transient: CRC err */
345 EDMA_ERR_LNK_CTRL_TX_1 = (1 << 22), /* transient: FIFO err */
346 EDMA_ERR_LNK_CTRL_TX_2 = (1 << 23), /* transient: caught SYNC */
347 EDMA_ERR_LNK_CTRL_TX_3 = (1 << 24), /* transient: caught DMAT */
348 EDMA_ERR_LNK_CTRL_TX_4 = (1 << 25), /* transient: FIS collision */
349
6c1153e0 350 EDMA_ERR_LNK_DATA_TX = (0x1f << 26), /* link data tx error */
646a4da5 351
6c1153e0 352 EDMA_ERR_TRANS_PROTO = (1 << 31), /* transport protocol error */
c5d3e45a
JG		 353 EDMA_ERR_OVERRUN_5 = (1 << 5),
354 EDMA_ERR_UNDERRUN_5 = (1 << 6),
646a4da5
ML		 355
356 EDMA_ERR_IRQ_TRANSIENT = EDMA_ERR_LNK_CTRL_RX_0 |
357 EDMA_ERR_LNK_CTRL_RX_1 |
358 EDMA_ERR_LNK_CTRL_RX_3 |
85afb934 359 EDMA_ERR_LNK_CTRL_TX,
646a4da5 360
bdd4ddde
JG		 361 EDMA_EH_FREEZE = EDMA_ERR_D_PAR |
362 EDMA_ERR_PRD_PAR |
363 EDMA_ERR_DEV_DCON |
364 EDMA_ERR_DEV_CON |
365 EDMA_ERR_SERR |
366 EDMA_ERR_SELF_DIS |
6c1153e0 367 EDMA_ERR_CRQB_PAR |
bdd4ddde
JG		 368 EDMA_ERR_CRPB_PAR |
369 EDMA_ERR_INTRL_PAR |
370 EDMA_ERR_IORDY |
371 EDMA_ERR_LNK_CTRL_RX_2 |
372 EDMA_ERR_LNK_DATA_RX |
373 EDMA_ERR_LNK_DATA_TX |
374 EDMA_ERR_TRANS_PROTO,
e12bef50 375
bdd4ddde
JG		 376 EDMA_EH_FREEZE_5 = EDMA_ERR_D_PAR |
377 EDMA_ERR_PRD_PAR |
378 EDMA_ERR_DEV_DCON |
379 EDMA_ERR_DEV_CON |
380 EDMA_ERR_OVERRUN_5 |
381 EDMA_ERR_UNDERRUN_5 |
382 EDMA_ERR_SELF_DIS_5 |
6c1153e0 383 EDMA_ERR_CRQB_PAR |
bdd4ddde
JG		 384 EDMA_ERR_CRPB_PAR |
385 EDMA_ERR_INTRL_PAR |
386 EDMA_ERR_IORDY,
20f733e7 387
cae5a29d
ML		 388 EDMA_REQ_Q_BASE_HI = 0x10,
389 EDMA_REQ_Q_IN_PTR = 0x14, /* also contains BASE_LO */
31961943 390
cae5a29d 391 EDMA_REQ_Q_OUT_PTR = 0x18,
31961943
BR		 392 EDMA_REQ_Q_PTR_SHIFT = 5,
393
cae5a29d
ML		 394 EDMA_RSP_Q_BASE_HI = 0x1c,
395 EDMA_RSP_Q_IN_PTR = 0x20,
396 EDMA_RSP_Q_OUT_PTR = 0x24, /* also contains BASE_LO */
31961943
BR		 397 EDMA_RSP_Q_PTR_SHIFT = 3,
398
cae5a29d 399 EDMA_CMD = 0x28, /* EDMA command register */
0ea9e179
JG		 400 EDMA_EN = (1 << 0), /* enable EDMA */
401 EDMA_DS = (1 << 1), /* disable EDMA; self-negated */
8e7decdb
ML		 402 EDMA_RESET = (1 << 2), /* reset eng/trans/link/phy */
403
cae5a29d 404 EDMA_STATUS = 0x30, /* EDMA engine status */
8e7decdb
ML		 405 EDMA_STATUS_CACHE_EMPTY = (1 << 6), /* GenIIe command cache empty */
406 EDMA_STATUS_IDLE = (1 << 7), /* GenIIe EDMA enabled/idle */
20f733e7 407
cae5a29d
ML		 408 EDMA_IORDY_TMOUT = 0x34,
409 EDMA_ARB_CFG = 0x38,
8e7decdb 410
cae5a29d
ML		 411 EDMA_HALTCOND = 0x60, /* GenIIe halt conditions */
412 EDMA_UNKNOWN_RSVD = 0x6C, /* GenIIe unknown/reserved */
da14265e 413
cae5a29d
ML		 414 BMDMA_CMD = 0x224, /* bmdma command register */
415 BMDMA_STATUS = 0x228, /* bmdma status register */
416 BMDMA_PRD_LOW = 0x22c, /* bmdma PRD addr 31:0 */
417 BMDMA_PRD_HIGH = 0x230, /* bmdma PRD addr 63:32 */
da14265e 418
31961943
BR		 419 /* Host private flags (hp_flags) */
420 MV_HP_FLAG_MSI = (1 << 0),
47c2b677
JG		 421 MV_HP_ERRATA_50XXB0 = (1 << 1),
422 MV_HP_ERRATA_50XXB2 = (1 << 2),
423 MV_HP_ERRATA_60X1B2 = (1 << 3),
424 MV_HP_ERRATA_60X1C0 = (1 << 4),
0ea9e179
JG		 425 MV_HP_GEN_I = (1 << 6), /* Generation I: 50xx */
426 MV_HP_GEN_II = (1 << 7), /* Generation II: 60xx */
427 MV_HP_GEN_IIE = (1 << 8), /* Generation IIE: 6042/7042 */
02a121da 428 MV_HP_PCIE = (1 << 9), /* PCIe bus/regs: 7042 */
616d4a98 429 MV_HP_CUT_THROUGH = (1 << 10), /* can use EDMA cut-through */
1f398472 430 MV_HP_FLAG_SOC = (1 << 11), /* SystemOnChip, no PCI */
000b344f 431 MV_HP_QUIRK_LED_BLINK_EN = (1 << 12), /* is led blinking enabled? */
20f733e7 432
31961943 433 /* Port private flags (pp_flags) */
0ea9e179 434 MV_PP_FLAG_EDMA_EN = (1 << 0), /* is EDMA engine enabled? */
72109168 435 MV_PP_FLAG_NCQ_EN = (1 << 1), /* is EDMA set up for NCQ? */
00f42eab 436 MV_PP_FLAG_FBS_EN = (1 << 2), /* is EDMA set up for FBS? */
29d187bb 437 MV_PP_FLAG_DELAYED_EH = (1 << 3), /* delayed dev err handling */
d16ab3f6 438 MV_PP_FLAG_FAKE_ATA_BUSY = (1 << 4), /* ignore initial ATA_DRDY */
20f733e7
BR		 439};
440
ee9ccdf7
JG		 441#define IS_GEN_I(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_I)
442#define IS_GEN_II(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_II)
e4e7b892 443#define IS_GEN_IIE(hpriv) ((hpriv)->hp_flags & MV_HP_GEN_IIE)
8e7decdb 444#define IS_PCIE(hpriv) ((hpriv)->hp_flags & MV_HP_PCIE)
1f398472 445#define IS_SOC(hpriv) ((hpriv)->hp_flags & MV_HP_FLAG_SOC)
bca1c4eb 446
15a32632
LB		 447#define WINDOW_CTRL(i) (0x20030 + ((i) << 4))
448#define WINDOW_BASE(i) (0x20034 + ((i) << 4))
449
095fec88 450enum {
baf14aa1
JG		 451 /* DMA boundary 0xffff is required by the s/g splitting
452 * we need on /length/ in mv_fill-sg().
453 */
454 MV_DMA_BOUNDARY = 0xffffU,
095fec88 455
0ea9e179
JG		 456 /* mask of register bits containing lower 32 bits
457 * of EDMA request queue DMA address
458 */
095fec88
JG		 459 EDMA_REQ_Q_BASE_LO_MASK = 0xfffffc00U,
460
0ea9e179 461 /* ditto, for response queue */
095fec88
JG		 462 EDMA_RSP_Q_BASE_LO_MASK = 0xffffff00U,
463};
464
522479fb
JG		 465enum chip_type {
466 chip_504x,
467 chip_508x,
468 chip_5080,
469 chip_604x,
470 chip_608x,
e4e7b892
JG		 471 chip_6042,
472 chip_7042,
f351b2d6 473 chip_soc,
522479fb
JG		 474};
475
31961943
BR		 476/* Command ReQuest Block: 32B */
477struct mv_crqb {
e1469874
ML		 478 __le32 sg_addr;
479 __le32 sg_addr_hi;
480 __le16 ctrl_flags;
481 __le16 ata_cmd[11];
31961943 482};
20f733e7 483
e4e7b892 484struct mv_crqb_iie {
e1469874
ML		 485 __le32 addr;
486 __le32 addr_hi;
487 __le32 flags;
488 __le32 len;
489 __le32 ata_cmd[4];
e4e7b892
JG		 490};
491
31961943
BR		 492/* Command ResPonse Block: 8B */
493struct mv_crpb {
e1469874
ML		 494 __le16 id;
495 __le16 flags;
496 __le32 tmstmp;
20f733e7
BR		 497};
498
31961943
BR		 499/* EDMA Physical Region Descriptor (ePRD); A.K.A. SG */
500struct mv_sg {
e1469874
ML		 501 __le32 addr;
502 __le32 flags_size;
503 __le32 addr_hi;
504 __le32 reserved;
31961943 505};
20f733e7 506
08da1759
ML		 507/*
508 * We keep a local cache of a few frequently accessed port
509 * registers here, to avoid having to read them (very slow)
510 * when switching between EDMA and non-EDMA modes.
511 */
512struct mv_cached_regs {
513 u32 fiscfg;
514 u32 ltmode;
515 u32 haltcond;
c01e8a23 516 u32 unknown_rsvd;
08da1759
ML		 517};
518
31961943
BR		 519struct mv_port_priv {
520 struct mv_crqb *crqb;
521 dma_addr_t crqb_dma;
522 struct mv_crpb *crpb;
523 dma_addr_t crpb_dma;
eb73d558
ML		 524 struct mv_sg *sg_tbl[MV_MAX_Q_DEPTH];
525 dma_addr_t sg_tbl_dma[MV_MAX_Q_DEPTH];
bdd4ddde
JG		 526
527 unsigned int req_idx;
528 unsigned int resp_idx;
529
31961943 530 u32 pp_flags;
08da1759 531 struct mv_cached_regs cached;
29d187bb 532 unsigned int delayed_eh_pmp_map;
31961943
BR		 533};
534
bca1c4eb
JG		 535struct mv_port_signal {
536 u32 amps;
537 u32 pre;
538};
539
02a121da
ML		 540struct mv_host_priv {
541 u32 hp_flags;
1bfeff03 542 unsigned int board_idx;
96e2c487 543 u32 main_irq_mask;
02a121da
ML		 544 struct mv_port_signal signal[8];
545 const struct mv_hw_ops *ops;
f351b2d6
SB		 546 int n_ports;
547 void __iomem *base;
7368f919
ML		 548 void __iomem *main_irq_cause_addr;
549 void __iomem *main_irq_mask_addr;
cae5a29d
ML		 550 u32 irq_cause_offset;
551 u32 irq_mask_offset;
02a121da 552 u32 unmask_all_irqs;
c77a2f4e
SB		 553
554#if defined(CONFIG_HAVE_CLK)
555 struct clk *clk;
eee98990 556 struct clk **port_clks;
c77a2f4e 557#endif
da2fa9ba
ML		 558 /*
559 * These consistent DMA memory pools give us guaranteed
560 * alignment for hardware-accessed data structures,
561 * and less memory waste in accomplishing the alignment.
562 */
563 struct dma_pool *crqb_pool;
564 struct dma_pool *crpb_pool;
565 struct dma_pool *sg_tbl_pool;
02a121da
ML		 566};
567
47c2b677 568struct mv_hw_ops {
2a47ce06
JG		 569 void (*phy_errata)(struct mv_host_priv *hpriv, void __iomem *mmio,
570 unsigned int port);
47c2b677
JG		 571 void (*enable_leds)(struct mv_host_priv *hpriv, void __iomem *mmio);
572 void (*read_preamp)(struct mv_host_priv *hpriv, int idx,
573 void __iomem *mmio);
c9d39130
JG		 574 int (*reset_hc)(struct mv_host_priv *hpriv, void __iomem *mmio,
575 unsigned int n_hc);
522479fb 576 void (*reset_flash)(struct mv_host_priv *hpriv, void __iomem *mmio);
7bb3c529 577 void (*reset_bus)(struct ata_host *host, void __iomem *mmio);
47c2b677
JG		 578};
579
82ef04fb
TH		 580static int mv_scr_read(struct ata_link *link, unsigned int sc_reg_in, u32 *val);
581static int mv_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val);
582static int mv5_scr_read(struct ata_link *link, unsigned int sc_reg_in, u32 *val);
583static int mv5_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val);
31961943
BR		 584static int mv_port_start(struct ata_port *ap);
585static void mv_port_stop(struct ata_port *ap);
3e4a1391 586static int mv_qc_defer(struct ata_queued_cmd *qc);
31961943 587static void mv_qc_prep(struct ata_queued_cmd *qc);
e4e7b892 588static void mv_qc_prep_iie(struct ata_queued_cmd *qc);
9a3d9eb0 589static unsigned int mv_qc_issue(struct ata_queued_cmd *qc);
a1efdaba
TH		 590static int mv_hardreset(struct ata_link *link, unsigned int *class,
591 unsigned long deadline);
bdd4ddde
JG		 592static void mv_eh_freeze(struct ata_port *ap);
593static void mv_eh_thaw(struct ata_port *ap);
f273827e 594static void mv6_dev_config(struct ata_device *dev);
20f733e7 595
2a47ce06
JG		 596static void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
597 unsigned int port);
47c2b677
JG		 598static void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio);
599static void mv5_read_preamp(struct mv_host_priv *hpriv, int idx,
600 void __iomem *mmio);
c9d39130
JG		 601static int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
602 unsigned int n_hc);
522479fb 603static void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio);
7bb3c529 604static void mv5_reset_bus(struct ata_host *host, void __iomem *mmio);
47c2b677 605
2a47ce06
JG		 606static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
607 unsigned int port);
47c2b677
JG		 608static void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio);
609static void mv6_read_preamp(struct mv_host_priv *hpriv, int idx,
610 void __iomem *mmio);
c9d39130
JG		 611static int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
612 unsigned int n_hc);
522479fb 613static void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio);
f351b2d6
SB		 614static void mv_soc_enable_leds(struct mv_host_priv *hpriv,
615 void __iomem *mmio);
616static void mv_soc_read_preamp(struct mv_host_priv *hpriv, int idx,
617 void __iomem *mmio);
618static int mv_soc_reset_hc(struct mv_host_priv *hpriv,
619 void __iomem *mmio, unsigned int n_hc);
620static void mv_soc_reset_flash(struct mv_host_priv *hpriv,
621 void __iomem *mmio);
622static void mv_soc_reset_bus(struct ata_host *host, void __iomem *mmio);
29b7e43c
MM		 623static void mv_soc_65n_phy_errata(struct mv_host_priv *hpriv,
624 void __iomem *mmio, unsigned int port);
7bb3c529 625static void mv_reset_pci_bus(struct ata_host *host, void __iomem *mmio);
e12bef50 626static void mv_reset_channel(struct mv_host_priv *hpriv, void __iomem *mmio,
c9d39130 627 unsigned int port_no);
e12bef50 628static int mv_stop_edma(struct ata_port *ap);
b562468c 629static int mv_stop_edma_engine(void __iomem *port_mmio);
00b81235 630static void mv_edma_cfg(struct ata_port *ap, int want_ncq, int want_edma);
47c2b677 631
e49856d8
ML		 632static void mv_pmp_select(struct ata_port *ap, int pmp);
633static int mv_pmp_hardreset(struct ata_link *link, unsigned int *class,
634 unsigned long deadline);
635static int mv_softreset(struct ata_link *link, unsigned int *class,
636 unsigned long deadline);
29d187bb 637static void mv_pmp_error_handler(struct ata_port *ap);
4c299ca3
ML		 638static void mv_process_crpb_entries(struct ata_port *ap,
639 struct mv_port_priv *pp);
47c2b677 640
da14265e
ML		 641static void mv_sff_irq_clear(struct ata_port *ap);
642static int mv_check_atapi_dma(struct ata_queued_cmd *qc);
643static void mv_bmdma_setup(struct ata_queued_cmd *qc);
644static void mv_bmdma_start(struct ata_queued_cmd *qc);
645static void mv_bmdma_stop(struct ata_queued_cmd *qc);
646static u8 mv_bmdma_status(struct ata_port *ap);
d16ab3f6 647static u8 mv_sff_check_status(struct ata_port *ap);
da14265e 648
eb73d558
ML		 649/* .sg_tablesize is (MV_MAX_SG_CT / 2) in the structures below
650 * because we have to allow room for worst case splitting of
651 * PRDs for 64K boundaries in mv_fill_sg().
652 */
c5d3e45a 653static struct scsi_host_template mv5_sht = {
68d1d07b 654 ATA_BASE_SHT(DRV_NAME),
baf14aa1 655 .sg_tablesize = MV_MAX_SG_CT / 2,
c5d3e45a 656 .dma_boundary = MV_DMA_BOUNDARY,
c5d3e45a
JG		 657};
658
659static struct scsi_host_template mv6_sht = {
68d1d07b 660 ATA_NCQ_SHT(DRV_NAME),
138bfdd0 661 .can_queue = MV_MAX_Q_DEPTH - 1,
baf14aa1 662 .sg_tablesize = MV_MAX_SG_CT / 2,
20f733e7 663 .dma_boundary = MV_DMA_BOUNDARY,
20f733e7
BR		 664};
665
029cfd6b
TH		 666static struct ata_port_operations mv5_ops = {
667 .inherits = &ata_sff_port_ops,
c9d39130 668
c96f1732
AC		 669 .lost_interrupt = ATA_OP_NULL,
670
3e4a1391 671 .qc_defer = mv_qc_defer,
c9d39130
JG		 672 .qc_prep = mv_qc_prep,
673 .qc_issue = mv_qc_issue,
c9d39130 674
bdd4ddde
JG		 675 .freeze = mv_eh_freeze,
676 .thaw = mv_eh_thaw,
a1efdaba 677 .hardreset = mv_hardreset,
bdd4ddde 678
c9d39130
JG		 679 .scr_read = mv5_scr_read,
680 .scr_write = mv5_scr_write,
681
682 .port_start = mv_port_start,
683 .port_stop = mv_port_stop,
c9d39130
JG		 684};
685
029cfd6b 686static struct ata_port_operations mv6_ops = {
8930ff25
TH		 687 .inherits = &ata_bmdma_port_ops,
688
689 .lost_interrupt = ATA_OP_NULL,
690
691 .qc_defer = mv_qc_defer,
692 .qc_prep = mv_qc_prep,
693 .qc_issue = mv_qc_issue,
694
f273827e 695 .dev_config = mv6_dev_config,
20f733e7 696
8930ff25
TH		 697 .freeze = mv_eh_freeze,
698 .thaw = mv_eh_thaw,
699 .hardreset = mv_hardreset,
700 .softreset = mv_softreset,
e49856d8
ML		 701 .pmp_hardreset = mv_pmp_hardreset,
702 .pmp_softreset = mv_softreset,
29d187bb 703 .error_handler = mv_pmp_error_handler,
da14265e 704
8930ff25
TH		 705 .scr_read = mv_scr_read,
706 .scr_write = mv_scr_write,
707
40f21b11 708 .sff_check_status = mv_sff_check_status,
da14265e
ML		 709 .sff_irq_clear = mv_sff_irq_clear,
710 .check_atapi_dma = mv_check_atapi_dma,
711 .bmdma_setup = mv_bmdma_setup,
712 .bmdma_start = mv_bmdma_start,
713 .bmdma_stop = mv_bmdma_stop,
714 .bmdma_status = mv_bmdma_status,
8930ff25
TH		 715
716 .port_start = mv_port_start,
717 .port_stop = mv_port_stop,
20f733e7
BR		 718};
719
029cfd6b
TH		 720static struct ata_port_operations mv_iie_ops = {
721 .inherits = &mv6_ops,
722 .dev_config = ATA_OP_NULL,
e4e7b892 723 .qc_prep = mv_qc_prep_iie,
e4e7b892
JG		 724};
725
98ac62de 726static const struct ata_port_info mv_port_info[] = {
20f733e7 727 { /* chip_504x */
91b1a84c 728 .flags = MV_GEN_I_FLAGS,
c361acbc 729 .pio_mask = ATA_PIO4,
bf6263a8 730 .udma_mask = ATA_UDMA6,
c9d39130 731 .port_ops = &mv5_ops,
20f733e7
BR		 732 },
733 { /* chip_508x */
91b1a84c 734 .flags = MV_GEN_I_FLAGS | MV_FLAG_DUAL_HC,
c361acbc 735 .pio_mask = ATA_PIO4,
bf6263a8 736 .udma_mask = ATA_UDMA6,
c9d39130 737 .port_ops = &mv5_ops,
20f733e7 738 },
47c2b677 739 { /* chip_5080 */
91b1a84c 740 .flags = MV_GEN_I_FLAGS | MV_FLAG_DUAL_HC,
c361acbc 741 .pio_mask = ATA_PIO4,
bf6263a8 742 .udma_mask = ATA_UDMA6,
c9d39130 743 .port_ops = &mv5_ops,
47c2b677 744 },
20f733e7 745 { /* chip_604x */
91b1a84c 746 .flags = MV_GEN_II_FLAGS,
c361acbc 747 .pio_mask = ATA_PIO4,
bf6263a8 748 .udma_mask = ATA_UDMA6,
c9d39130 749 .port_ops = &mv6_ops,
20f733e7
BR		 750 },
751 { /* chip_608x */
91b1a84c 752 .flags = MV_GEN_II_FLAGS | MV_FLAG_DUAL_HC,
c361acbc 753 .pio_mask = ATA_PIO4,
bf6263a8 754 .udma_mask = ATA_UDMA6,
c9d39130 755 .port_ops = &mv6_ops,
20f733e7 756 },
e4e7b892 757 { /* chip_6042 */
91b1a84c 758 .flags = MV_GEN_IIE_FLAGS,
c361acbc 759 .pio_mask = ATA_PIO4,
bf6263a8 760 .udma_mask = ATA_UDMA6,
e4e7b892
JG		 761 .port_ops = &mv_iie_ops,
762 },
763 { /* chip_7042 */
91b1a84c 764 .flags = MV_GEN_IIE_FLAGS,
c361acbc 765 .pio_mask = ATA_PIO4,
bf6263a8 766 .udma_mask = ATA_UDMA6,
e4e7b892
JG		 767 .port_ops = &mv_iie_ops,
768 },
f351b2d6 769 { /* chip_soc */
91b1a84c 770 .flags = MV_GEN_IIE_FLAGS,
c361acbc 771 .pio_mask = ATA_PIO4,
17c5aab5
ML		 772 .udma_mask = ATA_UDMA6,
773 .port_ops = &mv_iie_ops,
f351b2d6 774 },
20f733e7
BR		 775};
776
3b7d697d 777static const struct pci_device_id mv_pci_tbl[] = {
2d2744fc
JG		 778 { PCI_VDEVICE(MARVELL, 0x5040), chip_504x },
779 { PCI_VDEVICE(MARVELL, 0x5041), chip_504x },
780 { PCI_VDEVICE(MARVELL, 0x5080), chip_5080 },
781 { PCI_VDEVICE(MARVELL, 0x5081), chip_508x },
46c5784c
ML		 782 /* RocketRAID 1720/174x have different identifiers */
783 { PCI_VDEVICE(TTI, 0x1720), chip_6042 },
4462254a
ML		 784 { PCI_VDEVICE(TTI, 0x1740), chip_6042 },
785 { PCI_VDEVICE(TTI, 0x1742), chip_6042 },
2d2744fc
JG		 786
787 { PCI_VDEVICE(MARVELL, 0x6040), chip_604x },
788 { PCI_VDEVICE(MARVELL, 0x6041), chip_604x },
789 { PCI_VDEVICE(MARVELL, 0x6042), chip_6042 },
790 { PCI_VDEVICE(MARVELL, 0x6080), chip_608x },
791 { PCI_VDEVICE(MARVELL, 0x6081), chip_608x },
792
793 { PCI_VDEVICE(ADAPTEC2, 0x0241), chip_604x },
794
d9f9c6bc
FA		 795 /* Adaptec 1430SA */
796 { PCI_VDEVICE(ADAPTEC2, 0x0243), chip_7042 },
797
02a121da 798 /* Marvell 7042 support */
6a3d586d
MT		 799 { PCI_VDEVICE(MARVELL, 0x7042), chip_7042 },
800
02a121da
ML		 801 /* Highpoint RocketRAID PCIe series */
802 { PCI_VDEVICE(TTI, 0x2300), chip_7042 },
803 { PCI_VDEVICE(TTI, 0x2310), chip_7042 },
804
2d2744fc 805 { } /* terminate list */
20f733e7
BR		 806};
807
47c2b677
JG		 808static const struct mv_hw_ops mv5xxx_ops = {
809 .phy_errata = mv5_phy_errata,
810 .enable_leds = mv5_enable_leds,
811 .read_preamp = mv5_read_preamp,
812 .reset_hc = mv5_reset_hc,
522479fb
JG		 813 .reset_flash = mv5_reset_flash,
814 .reset_bus = mv5_reset_bus,
47c2b677
JG		 815};
816
817static const struct mv_hw_ops mv6xxx_ops = {
818 .phy_errata = mv6_phy_errata,
819 .enable_leds = mv6_enable_leds,
820 .read_preamp = mv6_read_preamp,
821 .reset_hc = mv6_reset_hc,
522479fb
JG		 822 .reset_flash = mv6_reset_flash,
823 .reset_bus = mv_reset_pci_bus,
47c2b677
JG		 824};
825
f351b2d6
SB		 826static const struct mv_hw_ops mv_soc_ops = {
827 .phy_errata = mv6_phy_errata,
828 .enable_leds = mv_soc_enable_leds,
829 .read_preamp = mv_soc_read_preamp,
830 .reset_hc = mv_soc_reset_hc,
831 .reset_flash = mv_soc_reset_flash,
832 .reset_bus = mv_soc_reset_bus,
833};
834
29b7e43c
MM		 835static const struct mv_hw_ops mv_soc_65n_ops = {
836 .phy_errata = mv_soc_65n_phy_errata,
837 .enable_leds = mv_soc_enable_leds,
838 .reset_hc = mv_soc_reset_hc,
839 .reset_flash = mv_soc_reset_flash,
840 .reset_bus = mv_soc_reset_bus,
841};
842
20f733e7
BR		 843/*
844 * Functions
845 */
846
847static inline void writelfl(unsigned long data, void __iomem *addr)
848{
849 writel(data, addr);
850 (void) readl(addr); /* flush to avoid PCI posted write */
851}
852
c9d39130
JG		 853static inline unsigned int mv_hc_from_port(unsigned int port)
854{
855 return port >> MV_PORT_HC_SHIFT;
856}
857
858static inline unsigned int mv_hardport_from_port(unsigned int port)
859{
860 return port & MV_PORT_MASK;
861}
862
1cfd19ae
ML		 863/*
864 * Consolidate some rather tricky bit shift calculations.
865 * This is hot-path stuff, so not a function.
866 * Simple code, with two return values, so macro rather than inline.
867 *
868 * port is the sole input, in range 0..7.
7368f919
ML		 869 * shift is one output, for use with main_irq_cause / main_irq_mask registers.
870 * hardport is the other output, in range 0..3.
1cfd19ae
ML		 871 *
872 * Note that port and hardport may be the same variable in some cases.
873 */
874#define MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport) \
875{ \
876 shift = mv_hc_from_port(port) * HC_SHIFT; \
877 hardport = mv_hardport_from_port(port); \
878 shift += hardport * 2; \
879}
880
352fab70
ML		 881static inline void __iomem *mv_hc_base(void __iomem *base, unsigned int hc)
882{
cae5a29d 883 return (base + SATAHC0_REG_BASE + (hc * MV_SATAHC_REG_SZ));
352fab70
ML		 884}
885
c9d39130
JG		 886static inline void __iomem *mv_hc_base_from_port(void __iomem *base,
887 unsigned int port)
888{
889 return mv_hc_base(base, mv_hc_from_port(port));
890}
891
20f733e7
BR		 892static inline void __iomem *mv_port_base(void __iomem *base, unsigned int port)
893{
c9d39130 894 return mv_hc_base_from_port(base, port) +
8b260248 895 MV_SATAHC_ARBTR_REG_SZ +
c9d39130 896 (mv_hardport_from_port(port) * MV_PORT_REG_SZ);
20f733e7
BR		 897}
898
e12bef50
ML		 899static void __iomem *mv5_phy_base(void __iomem *mmio, unsigned int port)
900{
901 void __iomem *hc_mmio = mv_hc_base_from_port(mmio, port);
902 unsigned long ofs = (mv_hardport_from_port(port) + 1) * 0x100UL;
903
904 return hc_mmio + ofs;
905}
906
f351b2d6
SB		 907static inline void __iomem *mv_host_base(struct ata_host *host)
908{
909 struct mv_host_priv *hpriv = host->private_data;
910 return hpriv->base;
911}
912
20f733e7
BR		 913static inline void __iomem *mv_ap_base(struct ata_port *ap)
914{
f351b2d6 915 return mv_port_base(mv_host_base(ap->host), ap->port_no);
20f733e7
BR		 916}
917
cca3974e 918static inline int mv_get_hc_count(unsigned long port_flags)
31961943 919{
cca3974e 920 return ((port_flags & MV_FLAG_DUAL_HC) ? 2 : 1);
31961943
BR		 921}
922
08da1759
ML		 923/**
924 * mv_save_cached_regs - (re-)initialize cached port registers
925 * @ap: the port whose registers we are caching
926 *
927 * Initialize the local cache of port registers,
928 * so that reading them over and over again can
929 * be avoided on the hotter paths of this driver.
930 * This saves a few microseconds each time we switch
931 * to/from EDMA mode to perform (eg.) a drive cache flush.
932 */
933static void mv_save_cached_regs(struct ata_port *ap)
934{
935 void __iomem *port_mmio = mv_ap_base(ap);
936 struct mv_port_priv *pp = ap->private_data;
937
cae5a29d
ML		 938 pp->cached.fiscfg = readl(port_mmio + FISCFG);
939 pp->cached.ltmode = readl(port_mmio + LTMODE);
940 pp->cached.haltcond = readl(port_mmio + EDMA_HALTCOND);
941 pp->cached.unknown_rsvd = readl(port_mmio + EDMA_UNKNOWN_RSVD);
08da1759
ML		 942}
943
944/**
945 * mv_write_cached_reg - write to a cached port register
946 * @addr: hardware address of the register
947 * @old: pointer to cached value of the register
948 * @new: new value for the register
949 *
950 * Write a new value to a cached register,
951 * but only if the value is different from before.
952 */
953static inline void mv_write_cached_reg(void __iomem *addr, u32 *old, u32 new)
954{
955 if (new != *old) {
12f3b6d7 956 unsigned long laddr;
08da1759 957 *old = new;
12f3b6d7
ML		 958 /*
959 * Workaround for 88SX60x1-B2 FEr SATA#13:
960 * Read-after-write is needed to prevent generating 64-bit
961 * write cycles on the PCI bus for SATA interface registers
962 * at offsets ending in 0x4 or 0xc.
963 *
964 * Looks like a lot of fuss, but it avoids an unnecessary
965 * +1 usec read-after-write delay for unaffected registers.
966 */
967 laddr = (long)addr & 0xffff;
968 if (laddr >= 0x300 && laddr <= 0x33c) {
969 laddr &= 0x000f;
970 if (laddr == 0x4 || laddr == 0xc) {
971 writelfl(new, addr); /* read after write */
972 return;
973 }
974 }
975 writel(new, addr); /* unaffected by the errata */
08da1759
ML		 976 }
977}
978
c5d3e45a
JG		 979static void mv_set_edma_ptrs(void __iomem *port_mmio,
980 struct mv_host_priv *hpriv,
981 struct mv_port_priv *pp)
982{
bdd4ddde
JG		 983 u32 index;
984
c5d3e45a
JG		 985 /*
986 * initialize request queue
987 */
fcfb1f77
ML		 988 pp->req_idx &= MV_MAX_Q_DEPTH_MASK; /* paranoia */
989 index = pp->req_idx << EDMA_REQ_Q_PTR_SHIFT;
bdd4ddde 990
c5d3e45a 991 WARN_ON(pp->crqb_dma & 0x3ff);
cae5a29d 992 writel((pp->crqb_dma >> 16) >> 16, port_mmio + EDMA_REQ_Q_BASE_HI);
bdd4ddde 993 writelfl((pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK) | index,
cae5a29d
ML		 994 port_mmio + EDMA_REQ_Q_IN_PTR);
995 writelfl(index, port_mmio + EDMA_REQ_Q_OUT_PTR);
c5d3e45a
JG		 996
997 /*
998 * initialize response queue
999 */
fcfb1f77
ML		 1000 pp->resp_idx &= MV_MAX_Q_DEPTH_MASK; /* paranoia */
1001 index = pp->resp_idx << EDMA_RSP_Q_PTR_SHIFT;
bdd4ddde 1002
c5d3e45a 1003 WARN_ON(pp->crpb_dma & 0xff);
cae5a29d
ML		 1004 writel((pp->crpb_dma >> 16) >> 16, port_mmio + EDMA_RSP_Q_BASE_HI);
1005 writelfl(index, port_mmio + EDMA_RSP_Q_IN_PTR);
bdd4ddde 1006 writelfl((pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK) | index,
cae5a29d 1007 port_mmio + EDMA_RSP_Q_OUT_PTR);
c5d3e45a
JG		 1008}
1009
2b748a0a
ML		 1010static void mv_write_main_irq_mask(u32 mask, struct mv_host_priv *hpriv)
1011{
1012 /*
1013 * When writing to the main_irq_mask in hardware,
1014 * we must ensure exclusivity between the interrupt coalescing bits
1015 * and the corresponding individual port DONE_IRQ bits.
1016 *
1017 * Note that this register is really an "IRQ enable" register,
1018 * not an "IRQ mask" register as Marvell's naming might suggest.
1019 */
1020 if (mask & (ALL_PORTS_COAL_DONE | PORTS_0_3_COAL_DONE))
1021 mask &= ~DONE_IRQ_0_3;
1022 if (mask & (ALL_PORTS_COAL_DONE | PORTS_4_7_COAL_DONE))
1023 mask &= ~DONE_IRQ_4_7;
1024 writelfl(mask, hpriv->main_irq_mask_addr);
1025}
1026
c4de573b
ML		 1027static void mv_set_main_irq_mask(struct ata_host *host,
1028 u32 disable_bits, u32 enable_bits)
1029{
1030 struct mv_host_priv *hpriv = host->private_data;
1031 u32 old_mask, new_mask;
1032
96e2c487 1033 old_mask = hpriv->main_irq_mask;
c4de573b 1034 new_mask = (old_mask & ~disable_bits) | enable_bits;
96e2c487
ML		 1035 if (new_mask != old_mask) {
1036 hpriv->main_irq_mask = new_mask;
2b748a0a 1037 mv_write_main_irq_mask(new_mask, hpriv);
96e2c487 1038 }
c4de573b
ML		 1039}
1040
1041static void mv_enable_port_irqs(struct ata_port *ap,
1042 unsigned int port_bits)
1043{
1044 unsigned int shift, hardport, port = ap->port_no;
1045 u32 disable_bits, enable_bits;
1046
1047 MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport);
1048
1049 disable_bits = (DONE_IRQ | ERR_IRQ) << shift;
1050 enable_bits = port_bits << shift;
1051 mv_set_main_irq_mask(ap->host, disable_bits, enable_bits);
1052}
1053
00b81235
ML		 1054static void mv_clear_and_enable_port_irqs(struct ata_port *ap,
1055 void __iomem *port_mmio,
1056 unsigned int port_irqs)
1057{
1058 struct mv_host_priv *hpriv = ap->host->private_data;
1059 int hardport = mv_hardport_from_port(ap->port_no);
1060 void __iomem *hc_mmio = mv_hc_base_from_port(
1061 mv_host_base(ap->host), ap->port_no);
1062 u32 hc_irq_cause;
1063
1064 /* clear EDMA event indicators, if any */
cae5a29d 1065 writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE);
00b81235
ML		 1066
1067 /* clear pending irq events */
1068 hc_irq_cause = ~((DEV_IRQ | DMA_IRQ) << hardport);
cae5a29d 1069 writelfl(hc_irq_cause, hc_mmio + HC_IRQ_CAUSE);
00b81235
ML		 1070
1071 /* clear FIS IRQ Cause */
1072 if (IS_GEN_IIE(hpriv))
cae5a29d 1073 writelfl(0, port_mmio + FIS_IRQ_CAUSE);
00b81235
ML		 1074
1075 mv_enable_port_irqs(ap, port_irqs);
1076}
1077
2b748a0a
ML		 1078static void mv_set_irq_coalescing(struct ata_host *host,
1079 unsigned int count, unsigned int usecs)
1080{
1081 struct mv_host_priv *hpriv = host->private_data;
1082 void __iomem *mmio = hpriv->base, *hc_mmio;
1083 u32 coal_enable = 0;
1084 unsigned long flags;
6abf4678 1085 unsigned int clks, is_dual_hc = hpriv->n_ports > MV_PORTS_PER_HC;
2b748a0a
ML		 1086 const u32 coal_disable = PORTS_0_3_COAL_DONE | PORTS_4_7_COAL_DONE |
1087 ALL_PORTS_COAL_DONE;
1088
1089 /* Disable IRQ coalescing if either threshold is zero */
1090 if (!usecs || !count) {
1091 clks = count = 0;
1092 } else {
1093 /* Respect maximum limits of the hardware */
1094 clks = usecs * COAL_CLOCKS_PER_USEC;
1095 if (clks > MAX_COAL_TIME_THRESHOLD)
1096 clks = MAX_COAL_TIME_THRESHOLD;
1097 if (count > MAX_COAL_IO_COUNT)
1098 count = MAX_COAL_IO_COUNT;
1099 }
1100
1101 spin_lock_irqsave(&host->lock, flags);
6abf4678 1102 mv_set_main_irq_mask(host, coal_disable, 0);
2b748a0a 1103
6abf4678 1104 if (is_dual_hc && !IS_GEN_I(hpriv)) {
2b748a0a 1105 /*
6abf4678
ML		 1106 * GEN_II/GEN_IIE with dual host controllers:
1107 * one set of global thresholds for the entire chip.
2b748a0a 1108 */
cae5a29d
ML		 1109 writel(clks, mmio + IRQ_COAL_TIME_THRESHOLD);
1110 writel(count, mmio + IRQ_COAL_IO_THRESHOLD);
2b748a0a 1111 /* clear leftover coal IRQ bit */
cae5a29d 1112 writel(~ALL_PORTS_COAL_IRQ, mmio + IRQ_COAL_CAUSE);
6abf4678
ML		 1113 if (count)
1114 coal_enable = ALL_PORTS_COAL_DONE;
1115 clks = count = 0; /* force clearing of regular regs below */
2b748a0a 1116 }
6abf4678 1117
2b748a0a
ML		 1118 /*
1119 * All chips: independent thresholds for each HC on the chip.
1120 */
1121 hc_mmio = mv_hc_base_from_port(mmio, 0);
cae5a29d
ML		 1122 writel(clks, hc_mmio + HC_IRQ_COAL_TIME_THRESHOLD);
1123 writel(count, hc_mmio + HC_IRQ_COAL_IO_THRESHOLD);
1124 writel(~HC_COAL_IRQ, hc_mmio + HC_IRQ_CAUSE);
6abf4678
ML		 1125 if (count)
1126 coal_enable |= PORTS_0_3_COAL_DONE;
1127 if (is_dual_hc) {
2b748a0a 1128 hc_mmio = mv_hc_base_from_port(mmio, MV_PORTS_PER_HC);
cae5a29d
ML		 1129 writel(clks, hc_mmio + HC_IRQ_COAL_TIME_THRESHOLD);
1130 writel(count, hc_mmio + HC_IRQ_COAL_IO_THRESHOLD);
1131 writel(~HC_COAL_IRQ, hc_mmio + HC_IRQ_CAUSE);
6abf4678
ML		 1132 if (count)
1133 coal_enable |= PORTS_4_7_COAL_DONE;
2b748a0a 1134 }
2b748a0a 1135
6abf4678 1136 mv_set_main_irq_mask(host, 0, coal_enable);
2b748a0a
ML		 1137 spin_unlock_irqrestore(&host->lock, flags);
1138}
1139
05b308e1 1140/**
00b81235 1141 * mv_start_edma - Enable eDMA engine
05b308e1
BR		 1142 * @base: port base address
1143 * @pp: port private data
1144 *
beec7dbc
TH		 1145 * Verify the local cache of the eDMA state is accurate with a
1146 * WARN_ON.
05b308e1
BR		 1147 *
1148 * LOCKING:
1149 * Inherited from caller.
1150 */
00b81235 1151static void mv_start_edma(struct ata_port *ap, void __iomem *port_mmio,
72109168 1152 struct mv_port_priv *pp, u8 protocol)
20f733e7 1153{
72109168
ML		 1154 int want_ncq = (protocol == ATA_PROT_NCQ);
1155
1156 if (pp->pp_flags & MV_PP_FLAG_EDMA_EN) {
1157 int using_ncq = ((pp->pp_flags & MV_PP_FLAG_NCQ_EN) != 0);
1158 if (want_ncq != using_ncq)
b562468c 1159 mv_stop_edma(ap);
72109168 1160 }
c5d3e45a 1161 if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN)) {
0c58912e 1162 struct mv_host_priv *hpriv = ap->host->private_data;
0c58912e 1163
00b81235 1164 mv_edma_cfg(ap, want_ncq, 1);
0c58912e 1165
f630d562 1166 mv_set_edma_ptrs(port_mmio, hpriv, pp);
00b81235 1167 mv_clear_and_enable_port_irqs(ap, port_mmio, DONE_IRQ|ERR_IRQ);
bdd4ddde 1168
cae5a29d 1169 writelfl(EDMA_EN, port_mmio + EDMA_CMD);
afb0edd9
BR		 1170 pp->pp_flags |= MV_PP_FLAG_EDMA_EN;
1171 }
20f733e7
BR		 1172}
1173
9b2c4e0b
ML		 1174static void mv_wait_for_edma_empty_idle(struct ata_port *ap)
1175{
1176 void __iomem *port_mmio = mv_ap_base(ap);
1177 const u32 empty_idle = (EDMA_STATUS_CACHE_EMPTY | EDMA_STATUS_IDLE);
1178 const int per_loop = 5, timeout = (15 * 1000 / per_loop);
1179 int i;
1180
1181 /*
1182 * Wait for the EDMA engine to finish transactions in progress.
c46938cc
ML		 1183 * No idea what a good "timeout" value might be, but measurements
1184 * indicate that it often requires hundreds of microseconds
1185 * with two drives in-use. So we use the 15msec value above
1186 * as a rough guess at what even more drives might require.
9b2c4e0b
ML		 1187 */
1188 for (i = 0; i < timeout; ++i) {
cae5a29d 1189 u32 edma_stat = readl(port_mmio + EDMA_STATUS);
9b2c4e0b
ML		 1190 if ((edma_stat & empty_idle) == empty_idle)
1191 break;
1192 udelay(per_loop);
1193 }
a9a79dfe 1194 /* ata_port_info(ap, "%s: %u+ usecs\n", __func__, i); */
9b2c4e0b
ML		 1195}
1196
05b308e1 1197/**
e12bef50 1198 * mv_stop_edma_engine - Disable eDMA engine
b562468c 1199 * @port_mmio: io base address
05b308e1
BR		 1200 *
1201 * LOCKING:
1202 * Inherited from caller.
1203 */
b562468c 1204static int mv_stop_edma_engine(void __iomem *port_mmio)
20f733e7 1205{
b562468c 1206 int i;
31961943 1207
b562468c 1208 /* Disable eDMA. The disable bit auto clears. */
cae5a29d 1209 writelfl(EDMA_DS, port_mmio + EDMA_CMD);
8b260248 1210
b562468c
ML		 1211 /* Wait for the chip to confirm eDMA is off. */
1212 for (i = 10000; i > 0; i--) {
cae5a29d 1213 u32 reg = readl(port_mmio + EDMA_CMD);
4537deb5 1214 if (!(reg & EDMA_EN))
b562468c
ML		 1215 return 0;
1216 udelay(10);
31961943 1217 }
b562468c 1218 return -EIO;
20f733e7
BR		 1219}
1220
e12bef50 1221static int mv_stop_edma(struct ata_port *ap)
0ea9e179 1222{
b562468c
ML		 1223 void __iomem *port_mmio = mv_ap_base(ap);
1224 struct mv_port_priv *pp = ap->private_data;
66e57a2c 1225 int err = 0;
0ea9e179 1226
b562468c
ML		 1227 if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN))
1228 return 0;
1229 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
9b2c4e0b 1230 mv_wait_for_edma_empty_idle(ap);
b562468c 1231 if (mv_stop_edma_engine(port_mmio)) {
a9a79dfe 1232 ata_port_err(ap, "Unable to stop eDMA\n");
66e57a2c 1233 err = -EIO;
b562468c 1234 }
66e57a2c
ML		 1235 mv_edma_cfg(ap, 0, 0);
1236 return err;
0ea9e179
JG		 1237}
1238
8a70f8dc 1239#ifdef ATA_DEBUG
31961943 1240static void mv_dump_mem(void __iomem *start, unsigned bytes)
20f733e7 1241{
31961943
BR		 1242 int b, w;
1243 for (b = 0; b < bytes; ) {
1244 DPRINTK("%p: ", start + b);
1245 for (w = 0; b < bytes && w < 4; w++) {
2dcb407e 1246 printk("%08x ", readl(start + b));
31961943
BR		 1247 b += sizeof(u32);
1248 }
1249 printk("\n");
1250 }
31961943 1251}
8a70f8dc
JG		 1252#endif
1253
31961943
BR		 1254static void mv_dump_pci_cfg(struct pci_dev *pdev, unsigned bytes)
1255{
1256#ifdef ATA_DEBUG
1257 int b, w;
1258 u32 dw;
1259 for (b = 0; b < bytes; ) {
1260 DPRINTK("%02x: ", b);
1261 for (w = 0; b < bytes && w < 4; w++) {
2dcb407e
JG		 1262 (void) pci_read_config_dword(pdev, b, &dw);
1263 printk("%08x ", dw);
31961943
BR		 1264 b += sizeof(u32);
1265 }
1266 printk("\n");
1267 }
1268#endif
1269}
1270static void mv_dump_all_regs(void __iomem *mmio_base, int port,
1271 struct pci_dev *pdev)
1272{
1273#ifdef ATA_DEBUG
8b260248 1274 void __iomem *hc_base = mv_hc_base(mmio_base,
31961943
BR		 1275 port >> MV_PORT_HC_SHIFT);
1276 void __iomem *port_base;
1277 int start_port, num_ports, p, start_hc, num_hcs, hc;
1278
1279 if (0 > port) {
1280 start_hc = start_port = 0;
1281 num_ports = 8; /* shld be benign for 4 port devs */
1282 num_hcs = 2;
1283 } else {
1284 start_hc = port >> MV_PORT_HC_SHIFT;
1285 start_port = port;
1286 num_ports = num_hcs = 1;
1287 }
8b260248 1288 DPRINTK("All registers for port(s) %u-%u:\n", start_port,
31961943
BR		 1289 num_ports > 1 ? num_ports - 1 : start_port);
1290
1291 if (NULL != pdev) {
1292 DPRINTK("PCI config space regs:\n");
1293 mv_dump_pci_cfg(pdev, 0x68);
1294 }
1295 DPRINTK("PCI regs:\n");
1296 mv_dump_mem(mmio_base+0xc00, 0x3c);
1297 mv_dump_mem(mmio_base+0xd00, 0x34);
1298 mv_dump_mem(mmio_base+0xf00, 0x4);
1299 mv_dump_mem(mmio_base+0x1d00, 0x6c);
1300 for (hc = start_hc; hc < start_hc + num_hcs; hc++) {
d220c37e 1301 hc_base = mv_hc_base(mmio_base, hc);
31961943
BR		 1302 DPRINTK("HC regs (HC %i):\n", hc);
1303 mv_dump_mem(hc_base, 0x1c);
1304 }
1305 for (p = start_port; p < start_port + num_ports; p++) {
1306 port_base = mv_port_base(mmio_base, p);
2dcb407e 1307 DPRINTK("EDMA regs (port %i):\n", p);
31961943 1308 mv_dump_mem(port_base, 0x54);
2dcb407e 1309 DPRINTK("SATA regs (port %i):\n", p);
31961943
BR		 1310 mv_dump_mem(port_base+0x300, 0x60);
1311 }
1312#endif
20f733e7
BR		 1313}
1314
1315static unsigned int mv_scr_offset(unsigned int sc_reg_in)
1316{
1317 unsigned int ofs;
1318
1319 switch (sc_reg_in) {
1320 case SCR_STATUS:
1321 case SCR_CONTROL:
1322 case SCR_ERROR:
cae5a29d 1323 ofs = SATA_STATUS + (sc_reg_in * sizeof(u32));
20f733e7
BR		 1324 break;
1325 case SCR_ACTIVE:
cae5a29d 1326 ofs = SATA_ACTIVE; /* active is not with the others */
20f733e7
BR		 1327 break;
1328 default:
1329 ofs = 0xffffffffU;
1330 break;
1331 }
1332 return ofs;
1333}
1334
82ef04fb 1335static int mv_scr_read(struct ata_link *link, unsigned int sc_reg_in, u32 *val)
20f733e7
BR		 1336{
1337 unsigned int ofs = mv_scr_offset(sc_reg_in);
1338
da3dbb17 1339 if (ofs != 0xffffffffU) {
82ef04fb 1340 *val = readl(mv_ap_base(link->ap) + ofs);
da3dbb17
TH		 1341 return 0;
1342 } else
1343 return -EINVAL;
20f733e7
BR		 1344}
1345
82ef04fb 1346static int mv_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val)
20f733e7
BR		 1347{
1348 unsigned int ofs = mv_scr_offset(sc_reg_in);
1349
da3dbb17 1350 if (ofs != 0xffffffffU) {
20091773
ML		 1351 void __iomem *addr = mv_ap_base(link->ap) + ofs;
1352 if (sc_reg_in == SCR_CONTROL) {
1353 /*
1354 * Workaround for 88SX60x1 FEr SATA#26:
1355 *
25985edc 1356 * COMRESETs have to take care not to accidentally
20091773
ML		 1357 * put the drive to sleep when writing SCR_CONTROL.
1358 * Setting bits 12..15 prevents this problem.
1359 *
1360 * So if we see an outbound COMMRESET, set those bits.
1361 * Ditto for the followup write that clears the reset.
1362 *
1363 * The proprietary driver does this for
1364 * all chip versions, and so do we.
1365 */
1366 if ((val & 0xf) == 1 || (readl(addr) & 0xf) == 1)
1367 val |= 0xf000;
1368 }
1369 writelfl(val, addr);
da3dbb17
TH		 1370 return 0;
1371 } else
1372 return -EINVAL;
20f733e7
BR		 1373}
1374
f273827e
ML		 1375static void mv6_dev_config(struct ata_device *adev)
1376{
1377 /*
e49856d8
ML		 1378 * Deal with Gen-II ("mv6") hardware quirks/restrictions:
1379 *
1380 * Gen-II does not support NCQ over a port multiplier
1381 * (no FIS-based switching).
f273827e 1382 */
e49856d8 1383 if (adev->flags & ATA_DFLAG_NCQ) {
352fab70 1384 if (sata_pmp_attached(adev->link->ap)) {
e49856d8 1385 adev->flags &= ~ATA_DFLAG_NCQ;
a9a79dfe 1386 ata_dev_info(adev,
352fab70 1387 "NCQ disabled for command-based switching\n");
352fab70 1388 }
e49856d8 1389 }
f273827e
ML		 1390}
1391
3e4a1391
ML		 1392static int mv_qc_defer(struct ata_queued_cmd *qc)
1393{
1394 struct ata_link *link = qc->dev->link;
1395 struct ata_port *ap = link->ap;
1396 struct mv_port_priv *pp = ap->private_data;
1397
29d187bb
ML		 1398 /*
1399 * Don't allow new commands if we're in a delayed EH state
1400 * for NCQ and/or FIS-based switching.
1401 */
1402 if (pp->pp_flags & MV_PP_FLAG_DELAYED_EH)
1403 return ATA_DEFER_PORT;
159a7ff7
GG		 1404
1405 /* PIO commands need exclusive link: no other commands [DMA or PIO]
1406 * can run concurrently.
1407 * set excl_link when we want to send a PIO command in DMA mode
1408 * or a non-NCQ command in NCQ mode.
1409 * When we receive a command from that link, and there are no
1410 * outstanding commands, mark a flag to clear excl_link and let
1411 * the command go through.
1412 */
1413 if (unlikely(ap->excl_link)) {
1414 if (link == ap->excl_link) {
1415 if (ap->nr_active_links)
1416 return ATA_DEFER_PORT;
1417 qc->flags |= ATA_QCFLAG_CLEAR_EXCL;
1418 return 0;
1419 } else
1420 return ATA_DEFER_PORT;
1421 }
1422
3e4a1391
ML		 1423 /*
1424 * If the port is completely idle, then allow the new qc.
1425 */
1426 if (ap->nr_active_links == 0)
1427 return 0;
1428
4bdee6c5
TH		 1429 /*
1430 * The port is operating in host queuing mode (EDMA) with NCQ
1431 * enabled, allow multiple NCQ commands. EDMA also allows
1432 * queueing multiple DMA commands but libata core currently
1433 * doesn't allow it.
1434 */
1435 if ((pp->pp_flags & MV_PP_FLAG_EDMA_EN) &&
159a7ff7
GG		 1436 (pp->pp_flags & MV_PP_FLAG_NCQ_EN)) {
1437 if (ata_is_ncq(qc->tf.protocol))
1438 return 0;
1439 else {
1440 ap->excl_link = link;
1441 return ATA_DEFER_PORT;
1442 }
1443 }
4bdee6c5 1444
3e4a1391
ML		 1445 return ATA_DEFER_PORT;
1446}
1447
08da1759 1448static void mv_config_fbs(struct ata_port *ap, int want_ncq, int want_fbs)
e49856d8 1449{
08da1759
ML		 1450 struct mv_port_priv *pp = ap->private_data;
1451 void __iomem *port_mmio;
00f42eab 1452
08da1759
ML		 1453 u32 fiscfg, *old_fiscfg = &pp->cached.fiscfg;
1454 u32 ltmode, *old_ltmode = &pp->cached.ltmode;
1455 u32 haltcond, *old_haltcond = &pp->cached.haltcond;
00f42eab 1456
08da1759
ML		 1457 ltmode = *old_ltmode & ~LTMODE_BIT8;
1458 haltcond = *old_haltcond | EDMA_ERR_DEV;
00f42eab
ML		 1459
1460 if (want_fbs) {
08da1759
ML		 1461 fiscfg = *old_fiscfg | FISCFG_SINGLE_SYNC;
1462 ltmode = *old_ltmode | LTMODE_BIT8;
4c299ca3 1463 if (want_ncq)
08da1759 1464 haltcond &= ~EDMA_ERR_DEV;
4c299ca3 1465 else
08da1759
ML		 1466 fiscfg |= FISCFG_WAIT_DEV_ERR;
1467 } else {
1468 fiscfg = *old_fiscfg & ~(FISCFG_SINGLE_SYNC | FISCFG_WAIT_DEV_ERR);
e49856d8 1469 }
00f42eab 1470
08da1759 1471 port_mmio = mv_ap_base(ap);
cae5a29d
ML		 1472 mv_write_cached_reg(port_mmio + FISCFG, old_fiscfg, fiscfg);
1473 mv_write_cached_reg(port_mmio + LTMODE, old_ltmode, ltmode);
1474 mv_write_cached_reg(port_mmio + EDMA_HALTCOND, old_haltcond, haltcond);
f273827e
ML		 1475}
1476
dd2890f6
ML		 1477static void mv_60x1_errata_sata25(struct ata_port *ap, int want_ncq)
1478{
1479 struct mv_host_priv *hpriv = ap->host->private_data;
1480 u32 old, new;
1481
1482 /* workaround for 88SX60x1 FEr SATA#25 (part 1) */
cae5a29d 1483 old = readl(hpriv->base + GPIO_PORT_CTL);
dd2890f6
ML		 1484 if (want_ncq)
1485 new = old | (1 << 22);
1486 else
1487 new = old & ~(1 << 22);
1488 if (new != old)
cae5a29d 1489 writel(new, hpriv->base + GPIO_PORT_CTL);
dd2890f6
ML		 1490}
1491
c01e8a23 1492/**
40f21b11
ML		 1493 * mv_bmdma_enable - set a magic bit on GEN_IIE to allow bmdma
1494 * @ap: Port being initialized
c01e8a23
ML		 1495 *
1496 * There are two DMA modes on these chips: basic DMA, and EDMA.
1497 *
1498 * Bit-0 of the "EDMA RESERVED" register enables/disables use
1499 * of basic DMA on the GEN_IIE versions of the chips.
1500 *
1501 * This bit survives EDMA resets, and must be set for basic DMA
1502 * to function, and should be cleared when EDMA is active.
1503 */
1504static void mv_bmdma_enable_iie(struct ata_port *ap, int enable_bmdma)
1505{
1506 struct mv_port_priv *pp = ap->private_data;
1507 u32 new, *old = &pp->cached.unknown_rsvd;
1508
1509 if (enable_bmdma)
1510 new = *old | 1;
1511 else
1512 new = *old & ~1;
cae5a29d 1513 mv_write_cached_reg(mv_ap_base(ap) + EDMA_UNKNOWN_RSVD, old, new);
c01e8a23
ML		 1514}
1515
000b344f
ML		 1516/*
1517 * SOC chips have an issue whereby the HDD LEDs don't always blink
1518 * during I/O when NCQ is enabled. Enabling a special "LED blink" mode
1519 * of the SOC takes care of it, generating a steady blink rate when
1520 * any drive on the chip is active.
1521 *
1522 * Unfortunately, the blink mode is a global hardware setting for the SOC,
1523 * so we must use it whenever at least one port on the SOC has NCQ enabled.
1524 *
1525 * We turn "LED blink" off when NCQ is not in use anywhere, because the normal
1526 * LED operation works then, and provides better (more accurate) feedback.
1527 *
1528 * Note that this code assumes that an SOC never has more than one HC onboard.
1529 */
1530static void mv_soc_led_blink_enable(struct ata_port *ap)
1531{
1532 struct ata_host *host = ap->host;
1533 struct mv_host_priv *hpriv = host->private_data;
1534 void __iomem *hc_mmio;
1535 u32 led_ctrl;
1536
1537 if (hpriv->hp_flags & MV_HP_QUIRK_LED_BLINK_EN)
1538 return;
1539 hpriv->hp_flags |= MV_HP_QUIRK_LED_BLINK_EN;
1540 hc_mmio = mv_hc_base_from_port(mv_host_base(host), ap->port_no);
cae5a29d
ML		 1541 led_ctrl = readl(hc_mmio + SOC_LED_CTRL);
1542 writel(led_ctrl | SOC_LED_CTRL_BLINK, hc_mmio + SOC_LED_CTRL);
000b344f
ML		 1543}
1544
1545static void mv_soc_led_blink_disable(struct ata_port *ap)
1546{
1547 struct ata_host *host = ap->host;
1548 struct mv_host_priv *hpriv = host->private_data;
1549 void __iomem *hc_mmio;
1550 u32 led_ctrl;
1551 unsigned int port;
1552
1553 if (!(hpriv->hp_flags & MV_HP_QUIRK_LED_BLINK_EN))
1554 return;
1555
1556 /* disable led-blink only if no ports are using NCQ */
1557 for (port = 0; port < hpriv->n_ports; port++) {
1558 struct ata_port *this_ap = host->ports[port];
1559 struct mv_port_priv *pp = this_ap->private_data;
1560
1561 if (pp->pp_flags & MV_PP_FLAG_NCQ_EN)
1562 return;
1563 }
1564
1565 hpriv->hp_flags &= ~MV_HP_QUIRK_LED_BLINK_EN;
1566 hc_mmio = mv_hc_base_from_port(mv_host_base(host), ap->port_no);
cae5a29d
ML		 1567 led_ctrl = readl(hc_mmio + SOC_LED_CTRL);
1568 writel(led_ctrl & ~SOC_LED_CTRL_BLINK, hc_mmio + SOC_LED_CTRL);
000b344f
ML		 1569}
1570
00b81235 1571static void mv_edma_cfg(struct ata_port *ap, int want_ncq, int want_edma)
e4e7b892 1572{
0c58912e 1573 u32 cfg;
e12bef50
ML		 1574 struct mv_port_priv *pp = ap->private_data;
1575 struct mv_host_priv *hpriv = ap->host->private_data;
1576 void __iomem *port_mmio = mv_ap_base(ap);
e4e7b892
JG		 1577
1578 /* set up non-NCQ EDMA configuration */
0c58912e 1579 cfg = EDMA_CFG_Q_DEPTH; /* always 0x1f for *all* chips */
d16ab3f6
ML		 1580 pp->pp_flags &=
1581 ~(MV_PP_FLAG_FBS_EN | MV_PP_FLAG_NCQ_EN | MV_PP_FLAG_FAKE_ATA_BUSY);
e4e7b892 1582
0c58912e 1583 if (IS_GEN_I(hpriv))
e4e7b892
JG		 1584 cfg |= (1 << 8); /* enab config burst size mask */
1585
dd2890f6 1586 else if (IS_GEN_II(hpriv)) {
e4e7b892 1587 cfg |= EDMA_CFG_RD_BRST_EXT | EDMA_CFG_WR_BUFF_LEN;
dd2890f6 1588 mv_60x1_errata_sata25(ap, want_ncq);
e4e7b892 1589
dd2890f6 1590 } else if (IS_GEN_IIE(hpriv)) {
00f42eab
ML		 1591 int want_fbs = sata_pmp_attached(ap);
1592 /*
1593 * Possible future enhancement:
1594 *
1595 * The chip can use FBS with non-NCQ, if we allow it,
1596 * But first we need to have the error handling in place
1597 * for this mode (datasheet section 7.3.15.4.2.3).
1598 * So disallow non-NCQ FBS for now.
1599 */
1600 want_fbs &= want_ncq;
1601
08da1759 1602 mv_config_fbs(ap, want_ncq, want_fbs);
00f42eab
ML		 1603
1604 if (want_fbs) {
1605 pp->pp_flags |= MV_PP_FLAG_FBS_EN;
1606 cfg |= EDMA_CFG_EDMA_FBS; /* FIS-based switching */
1607 }
1608
e728eabe 1609 cfg |= (1 << 23); /* do not mask PM field in rx'd FIS */
00b81235
ML		 1610 if (want_edma) {
1611 cfg |= (1 << 22); /* enab 4-entry host queue cache */
1612 if (!IS_SOC(hpriv))
1613 cfg |= (1 << 18); /* enab early completion */
1614 }
616d4a98
ML		 1615 if (hpriv->hp_flags & MV_HP_CUT_THROUGH)
1616 cfg |= (1 << 17); /* enab cut-thru (dis stor&forwrd) */
c01e8a23 1617 mv_bmdma_enable_iie(ap, !want_edma);
000b344f
ML		 1618
1619 if (IS_SOC(hpriv)) {
1620 if (want_ncq)
1621 mv_soc_led_blink_enable(ap);
1622 else
1623 mv_soc_led_blink_disable(ap);
1624 }
e4e7b892
JG		 1625 }
1626
72109168
ML		 1627 if (want_ncq) {
1628 cfg |= EDMA_CFG_NCQ;
1629 pp->pp_flags |= MV_PP_FLAG_NCQ_EN;
00b81235 1630 }
72109168 1631
cae5a29d 1632 writelfl(cfg, port_mmio + EDMA_CFG);
e4e7b892
JG		 1633}
1634
da2fa9ba
ML		 1635static void mv_port_free_dma_mem(struct ata_port *ap)
1636{
1637 struct mv_host_priv *hpriv = ap->host->private_data;
1638 struct mv_port_priv *pp = ap->private_data;
eb73d558 1639 int tag;
da2fa9ba
ML		 1640
1641 if (pp->crqb) {
1642 dma_pool_free(hpriv->crqb_pool, pp->crqb, pp->crqb_dma);
1643 pp->crqb = NULL;
1644 }
1645 if (pp->crpb) {
1646 dma_pool_free(hpriv->crpb_pool, pp->crpb, pp->crpb_dma);
1647 pp->crpb = NULL;
1648 }
eb73d558
ML		 1649 /*
1650 * For GEN_I, there's no NCQ, so we have only a single sg_tbl.
1651 * For later hardware, we have one unique sg_tbl per NCQ tag.
1652 */
1653 for (tag = 0; tag < MV_MAX_Q_DEPTH; ++tag) {
1654 if (pp->sg_tbl[tag]) {
1655 if (tag == 0 || !IS_GEN_I(hpriv))
1656 dma_pool_free(hpriv->sg_tbl_pool,
1657 pp->sg_tbl[tag],
1658 pp->sg_tbl_dma[tag]);
1659 pp->sg_tbl[tag] = NULL;
1660 }
da2fa9ba
ML		 1661 }
1662}
1663
05b308e1
BR		 1664/**
1665 * mv_port_start - Port specific init/start routine.
1666 * @ap: ATA channel to manipulate
1667 *
1668 * Allocate and point to DMA memory, init port private memory,
1669 * zero indices.
1670 *
1671 * LOCKING:
1672 * Inherited from caller.
1673 */
31961943
BR		 1674static int mv_port_start(struct ata_port *ap)
1675{
cca3974e
JG		 1676 struct device *dev = ap->host->dev;
1677 struct mv_host_priv *hpriv = ap->host->private_data;
31961943 1678 struct mv_port_priv *pp;
933cb8e5 1679 unsigned long flags;
dde20207 1680 int tag;
31961943 1681
24dc5f33 1682 pp = devm_kzalloc(dev, sizeof(*pp), GFP_KERNEL);
6037d6bb 1683 if (!pp)
24dc5f33 1684 return -ENOMEM;
da2fa9ba 1685 ap->private_data = pp;
31961943 1686
da2fa9ba
ML		 1687 pp->crqb = dma_pool_alloc(hpriv->crqb_pool, GFP_KERNEL, &pp->crqb_dma);
1688 if (!pp->crqb)
1689 return -ENOMEM;
1690 memset(pp->crqb, 0, MV_CRQB_Q_SZ);
31961943 1691
da2fa9ba
ML		 1692 pp->crpb = dma_pool_alloc(hpriv->crpb_pool, GFP_KERNEL, &pp->crpb_dma);
1693 if (!pp->crpb)
1694 goto out_port_free_dma_mem;
1695 memset(pp->crpb, 0, MV_CRPB_Q_SZ);
31961943 1696
3bd0a70e
ML		 1697 /* 6041/6081 Rev. "C0" (and newer) are okay with async notify */
1698 if (hpriv->hp_flags & MV_HP_ERRATA_60X1C0)
1699 ap->flags |= ATA_FLAG_AN;
eb73d558
ML		 1700 /*
1701 * For GEN_I, there's no NCQ, so we only allocate a single sg_tbl.
1702 * For later hardware, we need one unique sg_tbl per NCQ tag.
1703 */
1704 for (tag = 0; tag < MV_MAX_Q_DEPTH; ++tag) {
1705 if (tag == 0 || !IS_GEN_I(hpriv)) {
1706 pp->sg_tbl[tag] = dma_pool_alloc(hpriv->sg_tbl_pool,
1707 GFP_KERNEL, &pp->sg_tbl_dma[tag]);
1708 if (!pp->sg_tbl[tag])
1709 goto out_port_free_dma_mem;
1710 } else {
1711 pp->sg_tbl[tag] = pp->sg_tbl[0];
1712 pp->sg_tbl_dma[tag] = pp->sg_tbl_dma[0];
1713 }
1714 }
933cb8e5
ML		 1715
1716 spin_lock_irqsave(ap->lock, flags);
08da1759 1717 mv_save_cached_regs(ap);
66e57a2c 1718 mv_edma_cfg(ap, 0, 0);
933cb8e5
ML		 1719 spin_unlock_irqrestore(ap->lock, flags);
1720
31961943 1721 return 0;
da2fa9ba
ML		 1722
1723out_port_free_dma_mem:
1724 mv_port_free_dma_mem(ap);
1725 return -ENOMEM;
31961943
BR		 1726}
1727
05b308e1
BR		 1728/**
1729 * mv_port_stop - Port specific cleanup/stop routine.
1730 * @ap: ATA channel to manipulate
1731 *
1732 * Stop DMA, cleanup port memory.
1733 *
1734 * LOCKING:
cca3974e 1735 * This routine uses the host lock to protect the DMA stop.
05b308e1 1736 */
31961943
BR		 1737static void mv_port_stop(struct ata_port *ap)
1738{
933cb8e5
ML		 1739 unsigned long flags;
1740
1741 spin_lock_irqsave(ap->lock, flags);
e12bef50 1742 mv_stop_edma(ap);
88e675e1 1743 mv_enable_port_irqs(ap, 0);
933cb8e5 1744 spin_unlock_irqrestore(ap->lock, flags);
da2fa9ba 1745 mv_port_free_dma_mem(ap);
31961943
BR		 1746}
1747
05b308e1
BR		 1748/**
1749 * mv_fill_sg - Fill out the Marvell ePRD (scatter gather) entries
1750 * @qc: queued command whose SG list to source from
1751 *
1752 * Populate the SG list and mark the last entry.
1753 *
1754 * LOCKING:
1755 * Inherited from caller.
1756 */
6c08772e 1757static void mv_fill_sg(struct ata_queued_cmd *qc)
31961943
BR		 1758{
1759 struct mv_port_priv *pp = qc->ap->private_data;
972c26bd 1760 struct scatterlist *sg;
3be6cbd7 1761 struct mv_sg *mv_sg, *last_sg = NULL;
ff2aeb1e 1762 unsigned int si;
31961943 1763
eb73d558 1764 mv_sg = pp->sg_tbl[qc->tag];
ff2aeb1e 1765 for_each_sg(qc->sg, sg, qc->n_elem, si) {
d88184fb
JG		 1766 dma_addr_t addr = sg_dma_address(sg);
1767 u32 sg_len = sg_dma_len(sg);
22374677 1768
4007b493
OJ		 1769 while (sg_len) {
1770 u32 offset = addr & 0xffff;
1771 u32 len = sg_len;
22374677 1772
32cd11a6 1773 if (offset + len > 0x10000)
4007b493
OJ		 1774 len = 0x10000 - offset;
1775
1776 mv_sg->addr = cpu_to_le32(addr & 0xffffffff);
1777 mv_sg->addr_hi = cpu_to_le32((addr >> 16) >> 16);
6c08772e 1778 mv_sg->flags_size = cpu_to_le32(len & 0xffff);
32cd11a6 1779 mv_sg->reserved = 0;
4007b493
OJ		 1780
1781 sg_len -= len;
1782 addr += len;
1783
3be6cbd7 1784 last_sg = mv_sg;
4007b493 1785 mv_sg++;
4007b493 1786 }
31961943 1787 }
3be6cbd7
JG		 1788
1789 if (likely(last_sg))
1790 last_sg->flags_size |= cpu_to_le32(EPRD_FLAG_END_OF_TBL);
32cd11a6 1791 mb(); /* ensure data structure is visible to the chipset */
31961943
BR		 1792}
1793
5796d1c4 1794static void mv_crqb_pack_cmd(__le16 *cmdw, u8 data, u8 addr, unsigned last)
31961943 1795{
559eedad 1796 u16 tmp = data | (addr << CRQB_CMD_ADDR_SHIFT) | CRQB_CMD_CS |
31961943 1797 (last ? CRQB_CMD_LAST : 0);
559eedad 1798 *cmdw = cpu_to_le16(tmp);
31961943
BR		 1799}
1800
da14265e
ML		 1801/**
1802 * mv_sff_irq_clear - Clear hardware interrupt after DMA.
1803 * @ap: Port associated with this ATA transaction.
1804 *
1805 * We need this only for ATAPI bmdma transactions,
1806 * as otherwise we experience spurious interrupts
1807 * after libata-sff handles the bmdma interrupts.
1808 */
1809static void mv_sff_irq_clear(struct ata_port *ap)
1810{
1811 mv_clear_and_enable_port_irqs(ap, mv_ap_base(ap), ERR_IRQ);
1812}
1813
1814/**
1815 * mv_check_atapi_dma - Filter ATAPI cmds which are unsuitable for DMA.
1816 * @qc: queued command to check for chipset/DMA compatibility.
1817 *
1818 * The bmdma engines cannot handle speculative data sizes
1819 * (bytecount under/over flow). So only allow DMA for
1820 * data transfer commands with known data sizes.
1821 *
1822 * LOCKING:
1823 * Inherited from caller.
1824 */
1825static int mv_check_atapi_dma(struct ata_queued_cmd *qc)
1826{
1827 struct scsi_cmnd *scmd = qc->scsicmd;
1828
1829 if (scmd) {
1830 switch (scmd->cmnd[0]) {
1831 case READ_6:
1832 case READ_10:
1833 case READ_12:
1834 case WRITE_6:
1835 case WRITE_10:
1836 case WRITE_12:
1837 case GPCMD_READ_CD:
1838 case GPCMD_SEND_DVD_STRUCTURE:
1839 case GPCMD_SEND_CUE_SHEET:
1840 return 0; /* DMA is safe */
1841 }
1842 }
1843 return -EOPNOTSUPP; /* use PIO instead */
1844}
1845
1846/**
1847 * mv_bmdma_setup - Set up BMDMA transaction
1848 * @qc: queued command to prepare DMA for.
1849 *
1850 * LOCKING:
1851 * Inherited from caller.
1852 */
1853static void mv_bmdma_setup(struct ata_queued_cmd *qc)
1854{
1855 struct ata_port *ap = qc->ap;
1856 void __iomem *port_mmio = mv_ap_base(ap);
1857 struct mv_port_priv *pp = ap->private_data;
1858
1859 mv_fill_sg(qc);
1860
1861 /* clear all DMA cmd bits */
cae5a29d 1862 writel(0, port_mmio + BMDMA_CMD);
da14265e
ML		 1863
1864 /* load PRD table addr. */
1865 writel((pp->sg_tbl_dma[qc->tag] >> 16) >> 16,
cae5a29d 1866 port_mmio + BMDMA_PRD_HIGH);
da14265e 1867 writelfl(pp->sg_tbl_dma[qc->tag],
cae5a29d 1868 port_mmio + BMDMA_PRD_LOW);
da14265e
ML		 1869
1870 /* issue r/w command */
1871 ap->ops->sff_exec_command(ap, &qc->tf);
1872}
1873
1874/**
1875 * mv_bmdma_start - Start a BMDMA transaction
1876 * @qc: queued command to start DMA on.
1877 *
1878 * LOCKING:
1879 * Inherited from caller.
1880 */
1881static void mv_bmdma_start(struct ata_queued_cmd *qc)
1882{
1883 struct ata_port *ap = qc->ap;
1884 void __iomem *port_mmio = mv_ap_base(ap);
1885 unsigned int rw = (qc->tf.flags & ATA_TFLAG_WRITE);
1886 u32 cmd = (rw ? 0 : ATA_DMA_WR) | ATA_DMA_START;
1887
1888 /* start host DMA transaction */
cae5a29d 1889 writelfl(cmd, port_mmio + BMDMA_CMD);
da14265e
ML		 1890}
1891
1892/**
1893 * mv_bmdma_stop - Stop BMDMA transfer
1894 * @qc: queued command to stop DMA on.
1895 *
1896 * Clears the ATA_DMA_START flag in the bmdma control register
1897 *
1898 * LOCKING:
1899 * Inherited from caller.
1900 */
44b73380 1901static void mv_bmdma_stop_ap(struct ata_port *ap)
da14265e 1902{
da14265e
ML		 1903 void __iomem *port_mmio = mv_ap_base(ap);
1904 u32 cmd;
1905
1906 /* clear start/stop bit */
cae5a29d 1907 cmd = readl(port_mmio + BMDMA_CMD);
44b73380
ML		 1908 if (cmd & ATA_DMA_START) {
1909 cmd &= ~ATA_DMA_START;
1910 writelfl(cmd, port_mmio + BMDMA_CMD);
1911
1912 /* one-PIO-cycle guaranteed wait, per spec, for HDMA1:0 transition */
1913 ata_sff_dma_pause(ap);
1914 }
1915}
da14265e 1916
44b73380
ML		 1917static void mv_bmdma_stop(struct ata_queued_cmd *qc)
1918{
1919 mv_bmdma_stop_ap(qc->ap);
da14265e
ML		 1920}
1921
1922/**
1923 * mv_bmdma_status - Read BMDMA status
1924 * @ap: port for which to retrieve DMA status.
1925 *
1926 * Read and return equivalent of the sff BMDMA status register.
1927 *
1928 * LOCKING:
1929 * Inherited from caller.
1930 */
1931static u8 mv_bmdma_status(struct ata_port *ap)
1932{
1933 void __iomem *port_mmio = mv_ap_base(ap);
1934 u32 reg, status;
1935
1936 /*
1937 * Other bits are valid only if ATA_DMA_ACTIVE==0,
1938 * and the ATA_DMA_INTR bit doesn't exist.
1939 */
cae5a29d 1940 reg = readl(port_mmio + BMDMA_STATUS);
da14265e
ML		 1941 if (reg & ATA_DMA_ACTIVE)
1942 status = ATA_DMA_ACTIVE;
44b73380 1943 else if (reg & ATA_DMA_ERR)
da14265e 1944 status = (reg & ATA_DMA_ERR) | ATA_DMA_INTR;
44b73380
ML		 1945 else {
1946 /*
1947 * Just because DMA_ACTIVE is 0 (DMA completed),
1948 * this does _not_ mean the device is "done".
1949 * So we should not yet be signalling ATA_DMA_INTR
1950 * in some cases. Eg. DSM/TRIM, and perhaps others.
1951 */
1952 mv_bmdma_stop_ap(ap);
1953 if (ioread8(ap->ioaddr.altstatus_addr) & ATA_BUSY)
1954 status = 0;
1955 else
1956 status = ATA_DMA_INTR;
1957 }
da14265e
ML		 1958 return status;
1959}
1960
299b3f8d
ML		 1961static void mv_rw_multi_errata_sata24(struct ata_queued_cmd *qc)
1962{
1963 struct ata_taskfile *tf = &qc->tf;
1964 /*
1965 * Workaround for 88SX60x1 FEr SATA#24.
1966 *
1967 * Chip may corrupt WRITEs if multi_count >= 4kB.
1968 * Note that READs are unaffected.
1969 *
1970 * It's not clear if this errata really means "4K bytes",
1971 * or if it always happens for multi_count > 7
1972 * regardless of device sector_size.
1973 *
1974 * So, for safety, any write with multi_count > 7
1975 * gets converted here into a regular PIO write instead:
1976 */
1977 if ((tf->flags & ATA_TFLAG_WRITE) && is_multi_taskfile(tf)) {
1978 if (qc->dev->multi_count > 7) {
1979 switch (tf->command) {
1980 case ATA_CMD_WRITE_MULTI:
1981 tf->command = ATA_CMD_PIO_WRITE;
1982 break;
1983 case ATA_CMD_WRITE_MULTI_FUA_EXT:
1984 tf->flags &= ~ATA_TFLAG_FUA; /* ugh */
1985 /* fall through */
1986 case ATA_CMD_WRITE_MULTI_EXT:
1987 tf->command = ATA_CMD_PIO_WRITE_EXT;
1988 break;
1989 }
1990 }
1991 }
1992}
1993
05b308e1
BR		 1994/**
1995 * mv_qc_prep - Host specific command preparation.
1996 * @qc: queued command to prepare
1997 *
1998 * This routine simply redirects to the general purpose routine
1999 * if command is not DMA. Else, it handles prep of the CRQB
2000 * (command request block), does some sanity checking, and calls
2001 * the SG load routine.
2002 *
2003 * LOCKING:
2004 * Inherited from caller.
2005 */
31961943
BR		 2006static void mv_qc_prep(struct ata_queued_cmd *qc)
2007{
2008 struct ata_port *ap = qc->ap;
2009 struct mv_port_priv *pp = ap->private_data;
e1469874 2010 __le16 *cw;
8d2b450d 2011 struct ata_taskfile *tf = &qc->tf;
31961943 2012 u16 flags = 0;
a6432436 2013 unsigned in_index;
31961943 2014
299b3f8d
ML		 2015 switch (tf->protocol) {
2016 case ATA_PROT_DMA:
44b73380
ML		 2017 if (tf->command == ATA_CMD_DSM)
2018 return;
2019 /* fall-thru */
299b3f8d
ML		 2020 case ATA_PROT_NCQ:
2021 break; /* continue below */
2022 case ATA_PROT_PIO:
2023 mv_rw_multi_errata_sata24(qc);
31961943 2024 return;
299b3f8d
ML		 2025 default:
2026 return;
2027 }
20f733e7 2028
31961943
BR		 2029 /* Fill in command request block
2030 */
8d2b450d 2031 if (!(tf->flags & ATA_TFLAG_WRITE))
31961943 2032 flags |= CRQB_FLAG_READ;
beec7dbc 2033 WARN_ON(MV_MAX_Q_DEPTH <= qc->tag);
31961943 2034 flags |= qc->tag << CRQB_TAG_SHIFT;
e49856d8 2035 flags |= (qc->dev->link->pmp & 0xf) << CRQB_PMP_SHIFT;
31961943 2036
bdd4ddde 2037 /* get current queue index from software */
fcfb1f77 2038 in_index = pp->req_idx;
a6432436
ML		 2039
2040 pp->crqb[in_index].sg_addr =
eb73d558 2041 cpu_to_le32(pp->sg_tbl_dma[qc->tag] & 0xffffffff);
a6432436 2042 pp->crqb[in_index].sg_addr_hi =
eb73d558 2043 cpu_to_le32((pp->sg_tbl_dma[qc->tag] >> 16) >> 16);
a6432436 2044 pp->crqb[in_index].ctrl_flags = cpu_to_le16(flags);
31961943 2045
a6432436 2046 cw = &pp->crqb[in_index].ata_cmd[0];
31961943 2047
25985edc 2048 /* Sadly, the CRQB cannot accommodate all registers--there are
31961943
BR		 2049 * only 11 bytes...so we must pick and choose required
2050 * registers based on the command. So, we drop feature and
2051 * hob_feature for [RW] DMA commands, but they are needed for
cd12e1f7
ML		 2052 * NCQ. NCQ will drop hob_nsect, which is not needed there
2053 * (nsect is used only for the tag; feat/hob_feat hold true nsect).
20f733e7 2054 */
31961943
BR		 2055 switch (tf->command) {
2056 case ATA_CMD_READ:
2057 case ATA_CMD_READ_EXT:
2058 case ATA_CMD_WRITE:
2059 case ATA_CMD_WRITE_EXT:
c15d85c8 2060 case ATA_CMD_WRITE_FUA_EXT:
31961943
BR		 2061 mv_crqb_pack_cmd(cw++, tf->hob_nsect, ATA_REG_NSECT, 0);
2062 break;
31961943
BR		 2063 case ATA_CMD_FPDMA_READ:
2064 case ATA_CMD_FPDMA_WRITE:
8b260248 2065 mv_crqb_pack_cmd(cw++, tf->hob_feature, ATA_REG_FEATURE, 0);
31961943
BR		 2066 mv_crqb_pack_cmd(cw++, tf->feature, ATA_REG_FEATURE, 0);
2067 break;
31961943
BR		 2068 default:
2069 /* The only other commands EDMA supports in non-queued and
2070 * non-NCQ mode are: [RW] STREAM DMA and W DMA FUA EXT, none
2071 * of which are defined/used by Linux. If we get here, this
2072 * driver needs work.
2073 *
2074 * FIXME: modify libata to give qc_prep a return value and
2075 * return error here.
2076 */
2077 BUG_ON(tf->command);
2078 break;
2079 }
2080 mv_crqb_pack_cmd(cw++, tf->nsect, ATA_REG_NSECT, 0);
2081 mv_crqb_pack_cmd(cw++, tf->hob_lbal, ATA_REG_LBAL, 0);
2082 mv_crqb_pack_cmd(cw++, tf->lbal, ATA_REG_LBAL, 0);
2083 mv_crqb_pack_cmd(cw++, tf->hob_lbam, ATA_REG_LBAM, 0);
2084 mv_crqb_pack_cmd(cw++, tf->lbam, ATA_REG_LBAM, 0);
2085 mv_crqb_pack_cmd(cw++, tf->hob_lbah, ATA_REG_LBAH, 0);
2086 mv_crqb_pack_cmd(cw++, tf->lbah, ATA_REG_LBAH, 0);
2087 mv_crqb_pack_cmd(cw++, tf->device, ATA_REG_DEVICE, 0);
2088 mv_crqb_pack_cmd(cw++, tf->command, ATA_REG_CMD, 1); /* last */
2089
e4e7b892
JG		 2090 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
2091 return;
2092 mv_fill_sg(qc);
2093}
2094
2095/**
2096 * mv_qc_prep_iie - Host specific command preparation.
2097 * @qc: queued command to prepare
2098 *
2099 * This routine simply redirects to the general purpose routine
2100 * if command is not DMA. Else, it handles prep of the CRQB
2101 * (command request block), does some sanity checking, and calls
2102 * the SG load routine.
2103 *
2104 * LOCKING:
2105 * Inherited from caller.
2106 */
2107static void mv_qc_prep_iie(struct ata_queued_cmd *qc)
2108{
2109 struct ata_port *ap = qc->ap;
2110 struct mv_port_priv *pp = ap->private_data;
2111 struct mv_crqb_iie *crqb;
8d2b450d 2112 struct ata_taskfile *tf = &qc->tf;
a6432436 2113 unsigned in_index;
e4e7b892
JG		 2114 u32 flags = 0;
2115
8d2b450d
ML		 2116 if ((tf->protocol != ATA_PROT_DMA) &&
2117 (tf->protocol != ATA_PROT_NCQ))
e4e7b892 2118 return;
44b73380
ML		 2119 if (tf->command == ATA_CMD_DSM)
2120 return; /* use bmdma for this */
e4e7b892 2121
e12bef50 2122 /* Fill in Gen IIE command request block */
8d2b450d 2123 if (!(tf->flags & ATA_TFLAG_WRITE))
e4e7b892
JG		 2124 flags |= CRQB_FLAG_READ;
2125
beec7dbc 2126 WARN_ON(MV_MAX_Q_DEPTH <= qc->tag);
e4e7b892 2127 flags |= qc->tag << CRQB_TAG_SHIFT;
8c0aeb4a 2128 flags |= qc->tag << CRQB_HOSTQ_SHIFT;
e49856d8 2129 flags |= (qc->dev->link->pmp & 0xf) << CRQB_PMP_SHIFT;
e4e7b892 2130
bdd4ddde 2131 /* get current queue index from software */
fcfb1f77 2132 in_index = pp->req_idx;
a6432436
ML		 2133
2134 crqb = (struct mv_crqb_iie *) &pp->crqb[in_index];
eb73d558
ML		 2135 crqb->addr = cpu_to_le32(pp->sg_tbl_dma[qc->tag] & 0xffffffff);
2136 crqb->addr_hi = cpu_to_le32((pp->sg_tbl_dma[qc->tag] >> 16) >> 16);
e4e7b892
JG		 2137 crqb->flags = cpu_to_le32(flags);
2138
e4e7b892
JG		 2139 crqb->ata_cmd[0] = cpu_to_le32(
2140 (tf->command << 16) |
2141 (tf->feature << 24)
2142 );
2143 crqb->ata_cmd[1] = cpu_to_le32(
2144 (tf->lbal << 0) |
2145 (tf->lbam << 8) |
2146 (tf->lbah << 16) |
2147 (tf->device << 24)
2148 );
2149 crqb->ata_cmd[2] = cpu_to_le32(
2150 (tf->hob_lbal << 0) |
2151 (tf->hob_lbam << 8) |
2152 (tf->hob_lbah << 16) |
2153 (tf->hob_feature << 24)
2154 );
2155 crqb->ata_cmd[3] = cpu_to_le32(
2156 (tf->nsect << 0) |
2157 (tf->hob_nsect << 8)
2158 );
2159
2160 if (!(qc->flags & ATA_QCFLAG_DMAMAP))
31961943 2161 return;
31961943
BR		 2162 mv_fill_sg(qc);
2163}
2164
d16ab3f6
ML		 2165/**
2166 * mv_sff_check_status - fetch device status, if valid
2167 * @ap: ATA port to fetch status from
2168 *
2169 * When using command issue via mv_qc_issue_fis(),
2170 * the initial ATA_BUSY state does not show up in the
2171 * ATA status (shadow) register. This can confuse libata!
2172 *
2173 * So we have a hook here to fake ATA_BUSY for that situation,
2174 * until the first time a BUSY, DRQ, or ERR bit is seen.
2175 *
2176 * The rest of the time, it simply returns the ATA status register.
2177 */
2178static u8 mv_sff_check_status(struct ata_port *ap)
2179{
2180 u8 stat = ioread8(ap->ioaddr.status_addr);
2181 struct mv_port_priv *pp = ap->private_data;
2182
2183 if (pp->pp_flags & MV_PP_FLAG_FAKE_ATA_BUSY) {
2184 if (stat & (ATA_BUSY | ATA_DRQ | ATA_ERR))
2185 pp->pp_flags &= ~MV_PP_FLAG_FAKE_ATA_BUSY;
2186 else
2187 stat = ATA_BUSY;
2188 }
2189 return stat;
2190}
2191
70f8b79c
ML		 2192/**
2193 * mv_send_fis - Send a FIS, using the "Vendor-Unique FIS" register
2194 * @fis: fis to be sent
2195 * @nwords: number of 32-bit words in the fis
2196 */
2197static unsigned int mv_send_fis(struct ata_port *ap, u32 *fis, int nwords)
2198{
2199 void __iomem *port_mmio = mv_ap_base(ap);
2200 u32 ifctl, old_ifctl, ifstat;
2201 int i, timeout = 200, final_word = nwords - 1;
2202
2203 /* Initiate FIS transmission mode */
cae5a29d 2204 old_ifctl = readl(port_mmio + SATA_IFCTL);
70f8b79c 2205 ifctl = 0x100 | (old_ifctl & 0xf);
cae5a29d 2206 writelfl(ifctl, port_mmio + SATA_IFCTL);
70f8b79c
ML		 2207
2208 /* Send all words of the FIS except for the final word */
2209 for (i = 0; i < final_word; ++i)
cae5a29d 2210 writel(fis[i], port_mmio + VENDOR_UNIQUE_FIS);
70f8b79c
ML		 2211
2212 /* Flag end-of-transmission, and then send the final word */
cae5a29d
ML		 2213 writelfl(ifctl | 0x200, port_mmio + SATA_IFCTL);
2214 writelfl(fis[final_word], port_mmio + VENDOR_UNIQUE_FIS);
70f8b79c
ML		 2215
2216 /*
2217 * Wait for FIS transmission to complete.
2218 * This typically takes just a single iteration.
2219 */
2220 do {
cae5a29d 2221 ifstat = readl(port_mmio + SATA_IFSTAT);
70f8b79c
ML		 2222 } while (!(ifstat & 0x1000) && --timeout);
2223
2224 /* Restore original port configuration */
cae5a29d 2225 writelfl(old_ifctl, port_mmio + SATA_IFCTL);
70f8b79c
ML		 2226
2227 /* See if it worked */
2228 if ((ifstat & 0x3000) != 0x1000) {
a9a79dfe
JP		 2229 ata_port_warn(ap, "%s transmission error, ifstat=%08x\n",
2230 __func__, ifstat);
70f8b79c
ML		 2231 return AC_ERR_OTHER;
2232 }
2233 return 0;
2234}
2235
2236/**
2237 * mv_qc_issue_fis - Issue a command directly as a FIS
2238 * @qc: queued command to start
2239 *
2240 * Note that the ATA shadow registers are not updated
2241 * after command issue, so the device will appear "READY"
2242 * if polled, even while it is BUSY processing the command.
2243 *
2244 * So we use a status hook to fake ATA_BUSY until the drive changes state.
2245 *
2246 * Note: we don't get updated shadow regs on *completion*
2247 * of non-data commands. So avoid sending them via this function,
2248 * as they will appear to have completed immediately.
2249 *
2250 * GEN_IIE has special registers that we could get the result tf from,
2251 * but earlier chipsets do not. For now, we ignore those registers.
2252 */
2253static unsigned int mv_qc_issue_fis(struct ata_queued_cmd *qc)
2254{
2255 struct ata_port *ap = qc->ap;
2256 struct mv_port_priv *pp = ap->private_data;
2257 struct ata_link *link = qc->dev->link;
2258 u32 fis[5];
2259 int err = 0;
2260
2261 ata_tf_to_fis(&qc->tf, link->pmp, 1, (void *)fis);
4c4a90fd 2262 err = mv_send_fis(ap, fis, ARRAY_SIZE(fis));
70f8b79c
ML		 2263 if (err)
2264 return err;
2265
2266 switch (qc->tf.protocol) {
2267 case ATAPI_PROT_PIO:
2268 pp->pp_flags |= MV_PP_FLAG_FAKE_ATA_BUSY;
2269 /* fall through */
2270 case ATAPI_PROT_NODATA:
2271 ap->hsm_task_state = HSM_ST_FIRST;
2272 break;
2273 case ATA_PROT_PIO:
2274 pp->pp_flags |= MV_PP_FLAG_FAKE_ATA_BUSY;
2275 if (qc->tf.flags & ATA_TFLAG_WRITE)
2276 ap->hsm_task_state = HSM_ST_FIRST;
2277 else
2278 ap->hsm_task_state = HSM_ST;
2279 break;
2280 default:
2281 ap->hsm_task_state = HSM_ST_LAST;
2282 break;
2283 }
2284
2285 if (qc->tf.flags & ATA_TFLAG_POLLING)
ea3c6450 2286 ata_sff_queue_pio_task(link, 0);
70f8b79c
ML		 2287 return 0;
2288}
2289
05b308e1
BR		 2290/**
2291 * mv_qc_issue - Initiate a command to the host
2292 * @qc: queued command to start
2293 *
2294 * This routine simply redirects to the general purpose routine
2295 * if command is not DMA. Else, it sanity checks our local
2296 * caches of the request producer/consumer indices then enables
2297 * DMA and bumps the request producer index.
2298 *
2299 * LOCKING:
2300 * Inherited from caller.
2301 */
9a3d9eb0 2302static unsigned int mv_qc_issue(struct ata_queued_cmd *qc)
31961943 2303{
f48765cc 2304 static int limit_warnings = 10;
c5d3e45a
JG		 2305 struct ata_port *ap = qc->ap;
2306 void __iomem *port_mmio = mv_ap_base(ap);
2307 struct mv_port_priv *pp = ap->private_data;
bdd4ddde 2308 u32 in_index;
42ed893d 2309 unsigned int port_irqs;
f48765cc 2310
d16ab3f6
ML		 2311 pp->pp_flags &= ~MV_PP_FLAG_FAKE_ATA_BUSY; /* paranoia */
2312
f48765cc
ML		 2313 switch (qc->tf.protocol) {
2314 case ATA_PROT_DMA:
44b73380
ML		 2315 if (qc->tf.command == ATA_CMD_DSM) {
2316 if (!ap->ops->bmdma_setup) /* no bmdma on GEN_I */
2317 return AC_ERR_OTHER;
2318 break; /* use bmdma for this */
2319 }
2320 /* fall thru */
f48765cc
ML		 2321 case ATA_PROT_NCQ:
2322 mv_start_edma(ap, port_mmio, pp, qc->tf.protocol);
2323 pp->req_idx = (pp->req_idx + 1) & MV_MAX_Q_DEPTH_MASK;
2324 in_index = pp->req_idx << EDMA_REQ_Q_PTR_SHIFT;
2325
2326 /* Write the request in pointer to kick the EDMA to life */
2327 writelfl((pp->crqb_dma & EDMA_REQ_Q_BASE_LO_MASK) | in_index,
cae5a29d 2328 port_mmio + EDMA_REQ_Q_IN_PTR);
f48765cc 2329 return 0;
31961943 2330
f48765cc 2331 case ATA_PROT_PIO:
c6112bd8
ML		 2332 /*
2333 * Errata SATA#16, SATA#24: warn if multiple DRQs expected.
2334 *
2335 * Someday, we might implement special polling workarounds
2336 * for these, but it all seems rather unnecessary since we
2337 * normally use only DMA for commands which transfer more
2338 * than a single block of data.
2339 *
2340 * Much of the time, this could just work regardless.
2341 * So for now, just log the incident, and allow the attempt.
2342 */
c7843e8f 2343 if (limit_warnings > 0 && (qc->nbytes / qc->sect_size) > 1) {
c6112bd8 2344 --limit_warnings;
a9a79dfe
JP		 2345 ata_link_warn(qc->dev->link, DRV_NAME
2346 ": attempting PIO w/multiple DRQ: "
2347 "this may fail due to h/w errata\n");
c6112bd8 2348 }
f48765cc 2349 /* drop through */
42ed893d 2350 case ATA_PROT_NODATA:
f48765cc 2351 case ATAPI_PROT_PIO:
42ed893d
ML		 2352 case ATAPI_PROT_NODATA:
2353 if (ap->flags & ATA_FLAG_PIO_POLLING)
2354 qc->tf.flags |= ATA_TFLAG_POLLING;
2355 break;
31961943 2356 }
42ed893d
ML		 2357
2358 if (qc->tf.flags & ATA_TFLAG_POLLING)
2359 port_irqs = ERR_IRQ; /* mask device interrupt when polling */
2360 else
2361 port_irqs = ERR_IRQ | DONE_IRQ; /* unmask all interrupts */
2362
2363 /*
2364 * We're about to send a non-EDMA capable command to the
2365 * port. Turn off EDMA so there won't be problems accessing
2366 * shadow block, etc registers.
2367 */
2368 mv_stop_edma(ap);
2369 mv_clear_and_enable_port_irqs(ap, mv_ap_base(ap), port_irqs);
2370 mv_pmp_select(ap, qc->dev->link->pmp);
70f8b79c
ML		 2371
2372 if (qc->tf.command == ATA_CMD_READ_LOG_EXT) {
2373 struct mv_host_priv *hpriv = ap->host->private_data;
2374 /*
2375 * Workaround for 88SX60x1 FEr SATA#25 (part 2).
40f21b11 2376 *
70f8b79c
ML		 2377 * After any NCQ error, the READ_LOG_EXT command
2378 * from libata-eh *must* use mv_qc_issue_fis().
2379 * Otherwise it might fail, due to chip errata.
2380 *
2381 * Rather than special-case it, we'll just *always*
2382 * use this method here for READ_LOG_EXT, making for
2383 * easier testing.
2384 */
2385 if (IS_GEN_II(hpriv))
2386 return mv_qc_issue_fis(qc);
2387 }
360ff783 2388 return ata_bmdma_qc_issue(qc);
31961943
BR		 2389}
2390
8f767f8a
ML		 2391static struct ata_queued_cmd *mv_get_active_qc(struct ata_port *ap)
2392{
2393 struct mv_port_priv *pp = ap->private_data;
2394 struct ata_queued_cmd *qc;
2395
2396 if (pp->pp_flags & MV_PP_FLAG_NCQ_EN)
2397 return NULL;
2398 qc = ata_qc_from_tag(ap, ap->link.active_tag);
3e4ec344
TH		 2399 if (qc && !(qc->tf.flags & ATA_TFLAG_POLLING))
2400 return qc;
2401 return NULL;
8f767f8a
ML		 2402}
2403
29d187bb
ML		 2404static void mv_pmp_error_handler(struct ata_port *ap)
2405{
2406 unsigned int pmp, pmp_map;
2407 struct mv_port_priv *pp = ap->private_data;
2408
2409 if (pp->pp_flags & MV_PP_FLAG_DELAYED_EH) {
2410 /*
2411 * Perform NCQ error analysis on failed PMPs
2412 * before we freeze the port entirely.
2413 *
2414 * The failed PMPs are marked earlier by mv_pmp_eh_prep().
2415 */
2416 pmp_map = pp->delayed_eh_pmp_map;
2417 pp->pp_flags &= ~MV_PP_FLAG_DELAYED_EH;
2418 for (pmp = 0; pmp_map != 0; pmp++) {
2419 unsigned int this_pmp = (1 << pmp);
2420 if (pmp_map & this_pmp) {
2421 struct ata_link *link = &ap->pmp_link[pmp];
2422 pmp_map &= ~this_pmp;
2423 ata_eh_analyze_ncq_error(link);
2424 }
2425 }
2426 ata_port_freeze(ap);
2427 }
2428 sata_pmp_error_handler(ap);
2429}
2430
4c299ca3
ML		 2431static unsigned int mv_get_err_pmp_map(struct ata_port *ap)
2432{
2433 void __iomem *port_mmio = mv_ap_base(ap);
2434
cae5a29d 2435 return readl(port_mmio + SATA_TESTCTL) >> 16;
4c299ca3
ML		 2436}
2437
4c299ca3
ML		 2438static void mv_pmp_eh_prep(struct ata_port *ap, unsigned int pmp_map)
2439{
2440 struct ata_eh_info *ehi;
2441 unsigned int pmp;
2442
2443 /*
2444 * Initialize EH info for PMPs which saw device errors
2445 */
2446 ehi = &ap->link.eh_info;
2447 for (pmp = 0; pmp_map != 0; pmp++) {
2448 unsigned int this_pmp = (1 << pmp);
2449 if (pmp_map & this_pmp) {
2450 struct ata_link *link = &ap->pmp_link[pmp];
2451
2452 pmp_map &= ~this_pmp;
2453 ehi = &link->eh_info;
2454 ata_ehi_clear_desc(ehi);
2455 ata_ehi_push_desc(ehi, "dev err");
2456 ehi->err_mask |= AC_ERR_DEV;
2457 ehi->action |= ATA_EH_RESET;
2458 ata_link_abort(link);
2459 }
2460 }
2461}
2462
06aaca3f
ML		 2463static int mv_req_q_empty(struct ata_port *ap)
2464{
2465 void __iomem *port_mmio = mv_ap_base(ap);
2466 u32 in_ptr, out_ptr;
2467
cae5a29d 2468 in_ptr = (readl(port_mmio + EDMA_REQ_Q_IN_PTR)
06aaca3f 2469 >> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK;
cae5a29d 2470 out_ptr = (readl(port_mmio + EDMA_REQ_Q_OUT_PTR)
06aaca3f
ML		 2471 >> EDMA_REQ_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK;
2472 return (in_ptr == out_ptr); /* 1 == queue_is_empty */
2473}
2474
4c299ca3
ML		 2475static int mv_handle_fbs_ncq_dev_err(struct ata_port *ap)
2476{
2477 struct mv_port_priv *pp = ap->private_data;
2478 int failed_links;
2479 unsigned int old_map, new_map;
2480
2481 /*
2482 * Device error during FBS+NCQ operation:
2483 *
2484 * Set a port flag to prevent further I/O being enqueued.
2485 * Leave the EDMA running to drain outstanding commands from this port.
2486 * Perform the post-mortem/EH only when all responses are complete.
2487 * Follow recovery sequence from 6042/7042 datasheet (7.3.15.4.2.2).
2488 */
2489 if (!(pp->pp_flags & MV_PP_FLAG_DELAYED_EH)) {
2490 pp->pp_flags |= MV_PP_FLAG_DELAYED_EH;
2491 pp->delayed_eh_pmp_map = 0;
2492 }
2493 old_map = pp->delayed_eh_pmp_map;
2494 new_map = old_map | mv_get_err_pmp_map(ap);
2495
2496 if (old_map != new_map) {
2497 pp->delayed_eh_pmp_map = new_map;
2498 mv_pmp_eh_prep(ap, new_map & ~old_map);
2499 }
c46938cc 2500 failed_links = hweight16(new_map);
4c299ca3 2501
a9a79dfe
JP		 2502 ata_port_info(ap,
2503 "%s: pmp_map=%04x qc_map=%04x failed_links=%d nr_active_links=%d\n",
2504 __func__, pp->delayed_eh_pmp_map,
2505 ap->qc_active, failed_links,
2506 ap->nr_active_links);
4c299ca3 2507
06aaca3f 2508 if (ap->nr_active_links <= failed_links && mv_req_q_empty(ap)) {
4c299ca3
ML		 2509 mv_process_crpb_entries(ap, pp);
2510 mv_stop_edma(ap);
2511 mv_eh_freeze(ap);
a9a79dfe 2512 ata_port_info(ap, "%s: done\n", __func__);
4c299ca3
ML		 2513 return 1; /* handled */
2514 }
a9a79dfe 2515 ata_port_info(ap, "%s: waiting\n", __func__);
4c299ca3
ML		 2516 return 1; /* handled */
2517}
2518
2519static int mv_handle_fbs_non_ncq_dev_err(struct ata_port *ap)
2520{
2521 /*
2522 * Possible future enhancement:
2523 *
2524 * FBS+non-NCQ operation is not yet implemented.
2525 * See related notes in mv_edma_cfg().
2526 *
2527 * Device error during FBS+non-NCQ operation:
2528 *
2529 * We need to snapshot the shadow registers for each failed command.
2530 * Follow recovery sequence from 6042/7042 datasheet (7.3.15.4.2.3).
2531 */
2532 return 0; /* not handled */
2533}
2534
2535static int mv_handle_dev_err(struct ata_port *ap, u32 edma_err_cause)
2536{
2537 struct mv_port_priv *pp = ap->private_data;
2538
2539 if (!(pp->pp_flags & MV_PP_FLAG_EDMA_EN))
2540 return 0; /* EDMA was not active: not handled */
2541 if (!(pp->pp_flags & MV_PP_FLAG_FBS_EN))
2542 return 0; /* FBS was not active: not handled */
2543
2544 if (!(edma_err_cause & EDMA_ERR_DEV))
2545 return 0; /* non DEV error: not handled */
2546 edma_err_cause &= ~EDMA_ERR_IRQ_TRANSIENT;
2547 if (edma_err_cause & ~(EDMA_ERR_DEV | EDMA_ERR_SELF_DIS))
2548 return 0; /* other problems: not handled */
2549
2550 if (pp->pp_flags & MV_PP_FLAG_NCQ_EN) {
2551 /*
2552 * EDMA should NOT have self-disabled for this case.
2553 * If it did, then something is wrong elsewhere,
2554 * and we cannot handle it here.
2555 */
2556 if (edma_err_cause & EDMA_ERR_SELF_DIS) {
a9a79dfe
JP		 2557 ata_port_warn(ap, "%s: err_cause=0x%x pp_flags=0x%x\n",
2558 __func__, edma_err_cause, pp->pp_flags);
4c299ca3
ML		 2559 return 0; /* not handled */
2560 }
2561 return mv_handle_fbs_ncq_dev_err(ap);
2562 } else {
2563 /*
2564 * EDMA should have self-disabled for this case.
2565 * If it did not, then something is wrong elsewhere,
2566 * and we cannot handle it here.
2567 */
2568 if (!(edma_err_cause & EDMA_ERR_SELF_DIS)) {
a9a79dfe
JP		 2569 ata_port_warn(ap, "%s: err_cause=0x%x pp_flags=0x%x\n",
2570 __func__, edma_err_cause, pp->pp_flags);
4c299ca3
ML		 2571 return 0; /* not handled */
2572 }
2573 return mv_handle_fbs_non_ncq_dev_err(ap);
2574 }
2575 return 0; /* not handled */
2576}
2577
a9010329 2578static void mv_unexpected_intr(struct ata_port *ap, int edma_was_enabled)
8f767f8a 2579{
8f767f8a 2580 struct ata_eh_info *ehi = &ap->link.eh_info;
a9010329 2581 char *when = "idle";
8f767f8a 2582
8f767f8a 2583 ata_ehi_clear_desc(ehi);
3e4ec344 2584 if (edma_was_enabled) {
a9010329 2585 when = "EDMA enabled";
8f767f8a
ML		 2586 } else {
2587 struct ata_queued_cmd *qc = ata_qc_from_tag(ap, ap->link.active_tag);
2588 if (qc && (qc->tf.flags & ATA_TFLAG_POLLING))
a9010329 2589 when = "polling";
8f767f8a 2590 }
a9010329 2591 ata_ehi_push_desc(ehi, "unexpected device interrupt while %s", when);
8f767f8a
ML		 2592 ehi->err_mask |= AC_ERR_OTHER;
2593 ehi->action |= ATA_EH_RESET;
2594 ata_port_freeze(ap);
2595}
2596
05b308e1
BR		 2597/**
2598 * mv_err_intr - Handle error interrupts on the port
2599 * @ap: ATA channel to manipulate
2600 *
8d07379d
ML		 2601 * Most cases require a full reset of the chip's state machine,
2602 * which also performs a COMRESET.
2603 * Also, if the port disabled DMA, update our cached copy to match.
05b308e1
BR		 2604 *
2605 * LOCKING:
2606 * Inherited from caller.
2607 */
37b9046a 2608static void mv_err_intr(struct ata_port *ap)
31961943
BR		 2609{
2610 void __iomem *port_mmio = mv_ap_base(ap);
bdd4ddde 2611 u32 edma_err_cause, eh_freeze_mask, serr = 0;
e4006077 2612 u32 fis_cause = 0;
bdd4ddde
JG		 2613 struct mv_port_priv *pp = ap->private_data;
2614 struct mv_host_priv *hpriv = ap->host->private_data;
bdd4ddde 2615 unsigned int action = 0, err_mask = 0;
9af5c9c9 2616 struct ata_eh_info *ehi = &ap->link.eh_info;
37b9046a
ML		 2617 struct ata_queued_cmd *qc;
2618 int abort = 0;
20f733e7 2619
8d07379d 2620 /*
37b9046a 2621 * Read and clear the SError and err_cause bits.
e4006077
ML		 2622 * For GenIIe, if EDMA_ERR_TRANS_IRQ_7 is set, we also must read/clear
2623 * the FIS_IRQ_CAUSE register before clearing edma_err_cause.
8d07379d 2624 */
37b9046a
ML		 2625 sata_scr_read(&ap->link, SCR_ERROR, &serr);
2626 sata_scr_write_flush(&ap->link, SCR_ERROR, serr);
2627
cae5a29d 2628 edma_err_cause = readl(port_mmio + EDMA_ERR_IRQ_CAUSE);
e4006077 2629 if (IS_GEN_IIE(hpriv) && (edma_err_cause & EDMA_ERR_TRANS_IRQ_7)) {
cae5a29d
ML		 2630 fis_cause = readl(port_mmio + FIS_IRQ_CAUSE);
2631 writelfl(~fis_cause, port_mmio + FIS_IRQ_CAUSE);
e4006077 2632 }
cae5a29d 2633 writelfl(~edma_err_cause, port_mmio + EDMA_ERR_IRQ_CAUSE);
bdd4ddde 2634
4c299ca3
ML		 2635 if (edma_err_cause & EDMA_ERR_DEV) {
2636 /*
2637 * Device errors during FIS-based switching operation
2638 * require special handling.
2639 */
2640 if (mv_handle_dev_err(ap, edma_err_cause))
2641 return;
2642 }
2643
37b9046a
ML		 2644 qc = mv_get_active_qc(ap);
2645 ata_ehi_clear_desc(ehi);
2646 ata_ehi_push_desc(ehi, "edma_err_cause=%08x pp_flags=%08x",
2647 edma_err_cause, pp->pp_flags);
e4006077 2648
c443c500 2649 if (IS_GEN_IIE(hpriv) && (edma_err_cause & EDMA_ERR_TRANS_IRQ_7)) {
e4006077 2650 ata_ehi_push_desc(ehi, "fis_cause=%08x", fis_cause);
cae5a29d 2651 if (fis_cause & FIS_IRQ_CAUSE_AN) {
c443c500
ML		 2652 u32 ec = edma_err_cause &
2653 ~(EDMA_ERR_TRANS_IRQ_7 | EDMA_ERR_IRQ_TRANSIENT);
2654 sata_async_notification(ap);
2655 if (!ec)
2656 return; /* Just an AN; no need for the nukes */
2657 ata_ehi_push_desc(ehi, "SDB notify");
2658 }
2659 }
bdd4ddde 2660 /*
352fab70 2661 * All generations share these EDMA error cause bits:
bdd4ddde 2662 */
37b9046a 2663 if (edma_err_cause & EDMA_ERR_DEV) {
bdd4ddde 2664 err_mask |= AC_ERR_DEV;
37b9046a
ML		 2665 action |= ATA_EH_RESET;
2666 ata_ehi_push_desc(ehi, "dev error");
2667 }
bdd4ddde 2668 if (edma_err_cause & (EDMA_ERR_D_PAR | EDMA_ERR_PRD_PAR |
6c1153e0 2669 EDMA_ERR_CRQB_PAR | EDMA_ERR_CRPB_PAR |
bdd4ddde
JG		 2670 EDMA_ERR_INTRL_PAR)) {
2671 err_mask |= AC_ERR_ATA_BUS;
cf480626 2672 action |= ATA_EH_RESET;
b64bbc39 2673 ata_ehi_push_desc(ehi, "parity error");
bdd4ddde
JG		 2674 }
2675 if (edma_err_cause & (EDMA_ERR_DEV_DCON | EDMA_ERR_DEV_CON)) {
2676 ata_ehi_hotplugged(ehi);
2677 ata_ehi_push_desc(ehi, edma_err_cause & EDMA_ERR_DEV_DCON ?
b64bbc39 2678 "dev disconnect" : "dev connect");
cf480626 2679 action |= ATA_EH_RESET;
bdd4ddde
JG		 2680 }
2681
352fab70
ML		 2682 /*
2683 * Gen-I has a different SELF_DIS bit,
2684 * different FREEZE bits, and no SERR bit:
2685 */
ee9ccdf7 2686 if (IS_GEN_I(hpriv)) {
bdd4ddde 2687 eh_freeze_mask = EDMA_EH_FREEZE_5;
bdd4ddde 2688 if (edma_err_cause & EDMA_ERR_SELF_DIS_5) {
bdd4ddde 2689 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
b64bbc39 2690 ata_ehi_push_desc(ehi, "EDMA self-disable");
bdd4ddde
JG		 2691 }
2692 } else {
2693 eh_freeze_mask = EDMA_EH_FREEZE;
bdd4ddde 2694 if (edma_err_cause & EDMA_ERR_SELF_DIS) {
bdd4ddde 2695 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
b64bbc39 2696 ata_ehi_push_desc(ehi, "EDMA self-disable");
bdd4ddde 2697 }
bdd4ddde 2698 if (edma_err_cause & EDMA_ERR_SERR) {
8d07379d
ML		 2699 ata_ehi_push_desc(ehi, "SError=%08x", serr);
2700 err_mask |= AC_ERR_ATA_BUS;
cf480626 2701 action |= ATA_EH_RESET;
bdd4ddde 2702 }
afb0edd9 2703 }
20f733e7 2704
bdd4ddde
JG		 2705 if (!err_mask) {
2706 err_mask = AC_ERR_OTHER;
cf480626 2707 action |= ATA_EH_RESET;
bdd4ddde
JG		 2708 }
2709
2710 ehi->serror |= serr;
2711 ehi->action |= action;
2712
2713 if (qc)
2714 qc->err_mask |= err_mask;
2715 else
2716 ehi->err_mask |= err_mask;
2717
37b9046a
ML		 2718 if (err_mask == AC_ERR_DEV) {
2719 /*
2720 * Cannot do ata_port_freeze() here,
2721 * because it would kill PIO access,
2722 * which is needed for further diagnosis.
2723 */
2724 mv_eh_freeze(ap);
2725 abort = 1;
2726 } else if (edma_err_cause & eh_freeze_mask) {
2727 /*
2728 * Note to self: ata_port_freeze() calls ata_port_abort()
2729 */
bdd4ddde 2730 ata_port_freeze(ap);
37b9046a
ML		 2731 } else {
2732 abort = 1;
2733 }
2734
2735 if (abort) {
2736 if (qc)
2737 ata_link_abort(qc->dev->link);
2738 else
2739 ata_port_abort(ap);
2740 }
bdd4ddde
JG		 2741}
2742
1aadf5c3 2743static bool mv_process_crpb_response(struct ata_port *ap,
fcfb1f77
ML		 2744 struct mv_crpb *response, unsigned int tag, int ncq_enabled)
2745{
752e386c
TH		 2746 u8 ata_status;
2747 u16 edma_status = le16_to_cpu(response->flags);
752e386c
TH		 2748
2749 /*
2750 * edma_status from a response queue entry:
2751 * LSB is from EDMA_ERR_IRQ_CAUSE (non-NCQ only).
2752 * MSB is saved ATA status from command completion.
2753 */
2754 if (!ncq_enabled) {
2755 u8 err_cause = edma_status & 0xff & ~EDMA_ERR_DEV;
2756 if (err_cause) {
2757 /*
2758 * Error will be seen/handled by
2759 * mv_err_intr(). So do nothing at all here.
2760 */
1aadf5c3 2761 return false;
752e386c 2762 }
fcfb1f77 2763 }
752e386c
TH		 2764 ata_status = edma_status >> CRPB_FLAG_STATUS_SHIFT;
2765 if (!ac_err_mask(ata_status))
1aadf5c3 2766 return true;
752e386c 2767 /* else: leave it for mv_err_intr() */
1aadf5c3 2768 return false;
fcfb1f77
ML		 2769}
2770
2771static void mv_process_crpb_entries(struct ata_port *ap, struct mv_port_priv *pp)
bdd4ddde
JG		 2772{
2773 void __iomem *port_mmio = mv_ap_base(ap);
2774 struct mv_host_priv *hpriv = ap->host->private_data;
fcfb1f77 2775 u32 in_index;
bdd4ddde 2776 bool work_done = false;
1aadf5c3 2777 u32 done_mask = 0;
fcfb1f77 2778 int ncq_enabled = (pp->pp_flags & MV_PP_FLAG_NCQ_EN);
bdd4ddde 2779
fcfb1f77 2780 /* Get the hardware queue position index */
cae5a29d 2781 in_index = (readl(port_mmio + EDMA_RSP_Q_IN_PTR)
bdd4ddde
JG		 2782 >> EDMA_RSP_Q_PTR_SHIFT) & MV_MAX_Q_DEPTH_MASK;
2783
fcfb1f77
ML		 2784 /* Process new responses from since the last time we looked */
2785 while (in_index != pp->resp_idx) {
6c1153e0 2786 unsigned int tag;
fcfb1f77 2787 struct mv_crpb *response = &pp->crpb[pp->resp_idx];
bdd4ddde 2788
fcfb1f77 2789 pp->resp_idx = (pp->resp_idx + 1) & MV_MAX_Q_DEPTH_MASK;
bdd4ddde 2790
fcfb1f77
ML		 2791 if (IS_GEN_I(hpriv)) {
2792 /* 50xx: no NCQ, only one command active at a time */
9af5c9c9 2793 tag = ap->link.active_tag;
fcfb1f77
ML		 2794 } else {
2795 /* Gen II/IIE: get command tag from CRPB entry */
2796 tag = le16_to_cpu(response->id) & 0x1f;
bdd4ddde 2797 }
1aadf5c3
TH		 2798 if (mv_process_crpb_response(ap, response, tag, ncq_enabled))
2799 done_mask |= 1 << tag;
bdd4ddde 2800 work_done = true;
bdd4ddde
JG		 2801 }
2802
1aadf5c3
TH		 2803 if (work_done) {
2804 ata_qc_complete_multiple(ap, ap->qc_active ^ done_mask);
2805
2806 /* Update the software queue position index in hardware */
bdd4ddde 2807 writelfl((pp->crpb_dma & EDMA_RSP_Q_BASE_LO_MASK) |
fcfb1f77 2808 (pp->resp_idx << EDMA_RSP_Q_PTR_SHIFT),
cae5a29d 2809 port_mmio + EDMA_RSP_Q_OUT_PTR);
1aadf5c3 2810 }
20f733e7
BR		 2811}
2812
a9010329
ML		 2813static void mv_port_intr(struct ata_port *ap, u32 port_cause)
2814{
2815 struct mv_port_priv *pp;
2816 int edma_was_enabled;
2817
a9010329
ML		 2818 /*
2819 * Grab a snapshot of the EDMA_EN flag setting,
2820 * so that we have a consistent view for this port,
2821 * even if something we call of our routines changes it.
2822 */
2823 pp = ap->private_data;
2824 edma_was_enabled = (pp->pp_flags & MV_PP_FLAG_EDMA_EN);
2825 /*
2826 * Process completed CRPB response(s) before other events.
2827 */
2828 if (edma_was_enabled && (port_cause & DONE_IRQ)) {
2829 mv_process_crpb_entries(ap, pp);
4c299ca3
ML		 2830 if (pp->pp_flags & MV_PP_FLAG_DELAYED_EH)
2831 mv_handle_fbs_ncq_dev_err(ap);
a9010329
ML		 2832 }
2833 /*
2834 * Handle chip-reported errors, or continue on to handle PIO.
2835 */
2836 if (unlikely(port_cause & ERR_IRQ)) {
2837 mv_err_intr(ap);
2838 } else if (!edma_was_enabled) {
2839 struct ata_queued_cmd *qc = mv_get_active_qc(ap);
2840 if (qc)
c3b28894 2841 ata_bmdma_port_intr(ap, qc);
a9010329
ML		 2842 else
2843 mv_unexpected_intr(ap, edma_was_enabled);
2844 }
2845}
2846
05b308e1
BR		 2847/**
2848 * mv_host_intr - Handle all interrupts on the given host controller
cca3974e 2849 * @host: host specific structure
7368f919 2850 * @main_irq_cause: Main interrupt cause register for the chip.
05b308e1
BR		 2851 *
2852 * LOCKING:
2853 * Inherited from caller.
2854 */
7368f919 2855static int mv_host_intr(struct ata_host *host, u32 main_irq_cause)
20f733e7 2856{
f351b2d6 2857 struct mv_host_priv *hpriv = host->private_data;
eabd5eb1 2858 void __iomem *mmio = hpriv->base, *hc_mmio;
a3718c1f 2859 unsigned int handled = 0, port;
20f733e7 2860
2b748a0a
ML		 2861 /* If asserted, clear the "all ports" IRQ coalescing bit */
2862 if (main_irq_cause & ALL_PORTS_COAL_DONE)
cae5a29d 2863 writel(~ALL_PORTS_COAL_IRQ, mmio + IRQ_COAL_CAUSE);
2b748a0a 2864
a3718c1f 2865 for (port = 0; port < hpriv->n_ports; port++) {
cca3974e 2866 struct ata_port *ap = host->ports[port];
eabd5eb1
ML		 2867 unsigned int p, shift, hardport, port_cause;
2868
a3718c1f 2869 MV_PORT_TO_SHIFT_AND_HARDPORT(port, shift, hardport);
a3718c1f 2870 /*
eabd5eb1
ML		 2871 * Each hc within the host has its own hc_irq_cause register,
2872 * where the interrupting ports bits get ack'd.
a3718c1f 2873 */
eabd5eb1
ML		 2874 if (hardport == 0) { /* first port on this hc ? */
2875 u32 hc_cause = (main_irq_cause >> shift) & HC0_IRQ_PEND;
2876 u32 port_mask, ack_irqs;
2877 /*
2878 * Skip this entire hc if nothing pending for any ports
2879 */
2880 if (!hc_cause) {
2881 port += MV_PORTS_PER_HC - 1;
2882 continue;
2883 }
2884 /*
2885 * We don't need/want to read the hc_irq_cause register,
2886 * because doing so hurts performance, and
2887 * main_irq_cause already gives us everything we need.
2888 *
2889 * But we do have to *write* to the hc_irq_cause to ack
2890 * the ports that we are handling this time through.
2891 *
2892 * This requires that we create a bitmap for those
2893 * ports which interrupted us, and use that bitmap
2894 * to ack (only) those ports via hc_irq_cause.
2895 */
2896 ack_irqs = 0;
2b748a0a
ML		 2897 if (hc_cause & PORTS_0_3_COAL_DONE)
2898 ack_irqs = HC_COAL_IRQ;
eabd5eb1
ML		 2899 for (p = 0; p < MV_PORTS_PER_HC; ++p) {
2900 if ((port + p) >= hpriv->n_ports)
2901 break;
2902 port_mask = (DONE_IRQ | ERR_IRQ) << (p * 2);
2903 if (hc_cause & port_mask)
2904 ack_irqs |= (DMA_IRQ | DEV_IRQ) << p;
2905 }
a3718c1f 2906 hc_mmio = mv_hc_base_from_port(mmio, port);
cae5a29d 2907 writelfl(~ack_irqs, hc_mmio + HC_IRQ_CAUSE);
a3718c1f
ML		 2908 handled = 1;
2909 }
8f767f8a 2910 /*
a9010329 2911 * Handle interrupts signalled for this port:
8f767f8a 2912 */
a9010329
ML		 2913 port_cause = (main_irq_cause >> shift) & (DONE_IRQ | ERR_IRQ);
2914 if (port_cause)
2915 mv_port_intr(ap, port_cause);
20f733e7 2916 }
a3718c1f 2917 return handled;
20f733e7
BR		 2918}
2919
a3718c1f 2920static int mv_pci_error(struct ata_host *host, void __iomem *mmio)
bdd4ddde 2921{
02a121da 2922 struct mv_host_priv *hpriv = host->private_data;
bdd4ddde
JG		 2923 struct ata_port *ap;
2924 struct ata_queued_cmd *qc;
2925 struct ata_eh_info *ehi;
2926 unsigned int i, err_mask, printed = 0;
2927 u32 err_cause;
2928
cae5a29d 2929 err_cause = readl(mmio + hpriv->irq_cause_offset);
bdd4ddde 2930
a44fec1f 2931 dev_err(host->dev, "PCI ERROR; PCI IRQ cause=0x%08x\n", err_cause);
bdd4ddde
JG		 2932
2933 DPRINTK("All regs @ PCI error\n");
2934 mv_dump_all_regs(mmio, -1, to_pci_dev(host->dev));
2935
cae5a29d 2936 writelfl(0, mmio + hpriv->irq_cause_offset);
bdd4ddde
JG		 2937
2938 for (i = 0; i < host->n_ports; i++) {
2939 ap = host->ports[i];
936fd732 2940 if (!ata_link_offline(&ap->link)) {
9af5c9c9 2941 ehi = &ap->link.eh_info;
bdd4ddde
JG		 2942 ata_ehi_clear_desc(ehi);
2943 if (!printed++)
2944 ata_ehi_push_desc(ehi,
2945 "PCI err cause 0x%08x", err_cause);
2946 err_mask = AC_ERR_HOST_BUS;
cf480626 2947 ehi->action = ATA_EH_RESET;
9af5c9c9 2948 qc = ata_qc_from_tag(ap, ap->link.active_tag);
bdd4ddde
JG		 2949 if (qc)
2950 qc->err_mask |= err_mask;
2951 else
2952 ehi->err_mask |= err_mask;
2953
2954 ata_port_freeze(ap);
2955 }
2956 }
a3718c1f 2957 return 1; /* handled */
bdd4ddde
JG		 2958}
2959
05b308e1 2960/**
c5d3e45a 2961 * mv_interrupt - Main interrupt event handler
05b308e1
BR		 2962 * @irq: unused
2963 * @dev_instance: private data; in this case the host structure
05b308e1
BR		 2964 *
2965 * Read the read only register to determine if any host
2966 * controllers have pending interrupts. If so, call lower level
2967 * routine to handle. Also check for PCI errors which are only
2968 * reported here.
2969 *
8b260248 2970 * LOCKING:
cca3974e 2971 * This routine holds the host lock while processing pending
05b308e1
BR		 2972 * interrupts.
2973 */
7d12e780 2974static irqreturn_t mv_interrupt(int irq, void *dev_instance)
20f733e7 2975{
cca3974e 2976 struct ata_host *host = dev_instance;
f351b2d6 2977 struct mv_host_priv *hpriv = host->private_data;
a3718c1f 2978 unsigned int handled = 0;
6d3c30ef 2979 int using_msi = hpriv->hp_flags & MV_HP_FLAG_MSI;
96e2c487 2980 u32 main_irq_cause, pending_irqs;
20f733e7 2981
646a4da5 2982 spin_lock(&host->lock);
6d3c30ef
ML		 2983
2984 /* for MSI: block new interrupts while in here */
2985 if (using_msi)
2b748a0a 2986 mv_write_main_irq_mask(0, hpriv);
6d3c30ef 2987
7368f919 2988 main_irq_cause = readl(hpriv->main_irq_cause_addr);
96e2c487 2989 pending_irqs = main_irq_cause & hpriv->main_irq_mask;
352fab70
ML		 2990 /*
2991 * Deal with cases where we either have nothing pending, or have read
2992 * a bogus register value which can indicate HW removal or PCI fault.
20f733e7 2993 */
a44253d2 2994 if (pending_irqs && main_irq_cause != 0xffffffffU) {
1f398472 2995 if (unlikely((pending_irqs & PCI_ERR) && !IS_SOC(hpriv)))
a3718c1f
ML		 2996 handled = mv_pci_error(host, hpriv->base);
2997 else
a44253d2 2998 handled = mv_host_intr(host, pending_irqs);
bdd4ddde 2999 }
6d3c30ef
ML		 3000
3001 /* for MSI: unmask; interrupt cause bits will retrigger now */
3002 if (using_msi)
2b748a0a 3003 mv_write_main_irq_mask(hpriv->main_irq_mask, hpriv);
6d3c30ef 3004
9d51af7b
ML		 3005 spin_unlock(&host->lock);
3006
20f733e7
BR		 3007 return IRQ_RETVAL(handled);
3008}
3009
c9d39130
JG		 3010static unsigned int mv5_scr_offset(unsigned int sc_reg_in)
3011{
3012 unsigned int ofs;
3013
3014 switch (sc_reg_in) {
3015 case SCR_STATUS:
3016 case SCR_ERROR:
3017 case SCR_CONTROL:
3018 ofs = sc_reg_in * sizeof(u32);
3019 break;
3020 default:
3021 ofs = 0xffffffffU;
3022 break;
3023 }
3024 return ofs;
3025}
3026
82ef04fb 3027static int mv5_scr_read(struct ata_link *link, unsigned int sc_reg_in, u32 *val)
c9d39130 3028{
82ef04fb 3029 struct mv_host_priv *hpriv = link->ap->host->private_data;
f351b2d6 3030 void __iomem *mmio = hpriv->base;
82ef04fb 3031 void __iomem *addr = mv5_phy_base(mmio, link->ap->port_no);
c9d39130
JG		 3032 unsigned int ofs = mv5_scr_offset(sc_reg_in);
3033
da3dbb17
TH		 3034 if (ofs != 0xffffffffU) {
3035 *val = readl(addr + ofs);
3036 return 0;
3037 } else
3038 return -EINVAL;
c9d39130
JG		 3039}
3040
82ef04fb 3041static int mv5_scr_write(struct ata_link *link, unsigned int sc_reg_in, u32 val)
c9d39130 3042{
82ef04fb 3043 struct mv_host_priv *hpriv = link->ap->host->private_data;
f351b2d6 3044 void __iomem *mmio = hpriv->base;
82ef04fb 3045 void __iomem *addr = mv5_phy_base(mmio, link->ap->port_no);
c9d39130
JG		 3046 unsigned int ofs = mv5_scr_offset(sc_reg_in);
3047
da3dbb17 3048 if (ofs != 0xffffffffU) {
0d5ff566 3049 writelfl(val, addr + ofs);
da3dbb17
TH		 3050 return 0;
3051 } else
3052 return -EINVAL;
c9d39130
JG		 3053}
3054
7bb3c529 3055static void mv5_reset_bus(struct ata_host *host, void __iomem *mmio)
522479fb 3056{
7bb3c529 3057 struct pci_dev *pdev = to_pci_dev(host->dev);
522479fb
JG		 3058 int early_5080;
3059
44c10138 3060 early_5080 = (pdev->device == 0x5080) && (pdev->revision == 0);
522479fb
JG		 3061
3062 if (!early_5080) {
3063 u32 tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL);
3064 tmp |= (1 << 0);
3065 writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL);
3066 }
3067
7bb3c529 3068 mv_reset_pci_bus(host, mmio);
522479fb
JG		 3069}
3070
3071static void mv5_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio)
3072{
cae5a29d 3073 writel(0x0fcfffff, mmio + FLASH_CTL);
522479fb
JG		 3074}
3075
47c2b677 3076static void mv5_read_preamp(struct mv_host_priv *hpriv, int idx,
ba3fe8fb
JG		 3077 void __iomem *mmio)
3078{
c9d39130
JG		 3079 void __iomem *phy_mmio = mv5_phy_base(mmio, idx);
3080 u32 tmp;
3081
3082 tmp = readl(phy_mmio + MV5_PHY_MODE);
3083
3084 hpriv->signal[idx].pre = tmp & 0x1800; /* bits 12:11 */
3085 hpriv->signal[idx].amps = tmp & 0xe0; /* bits 7:5 */
ba3fe8fb
JG		 3086}
3087
47c2b677 3088static void mv5_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio)
ba3fe8fb 3089{
522479fb
JG		 3090 u32 tmp;
3091
cae5a29d 3092 writel(0, mmio + GPIO_PORT_CTL);
522479fb
JG		 3093
3094 /* FIXME: handle MV_HP_ERRATA_50XXB2 errata */
3095
3096 tmp = readl(mmio + MV_PCI_EXP_ROM_BAR_CTL);
3097 tmp |= ~(1 << 0);
3098 writel(tmp, mmio + MV_PCI_EXP_ROM_BAR_CTL);
ba3fe8fb
JG		 3099}
3100
2a47ce06
JG		 3101static void mv5_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
3102 unsigned int port)
bca1c4eb 3103{
c9d39130
JG		 3104 void __iomem *phy_mmio = mv5_phy_base(mmio, port);
3105 const u32 mask = (1<<12) | (1<<11) | (1<<7) | (1<<6) | (1<<5);
3106 u32 tmp;
3107 int fix_apm_sq = (hpriv->hp_flags & MV_HP_ERRATA_50XXB0);
3108
3109 if (fix_apm_sq) {
cae5a29d 3110 tmp = readl(phy_mmio + MV5_LTMODE);
c9d39130 3111 tmp |= (1 << 19);
cae5a29d 3112 writel(tmp, phy_mmio + MV5_LTMODE);
c9d39130 3113
cae5a29d 3114 tmp = readl(phy_mmio + MV5_PHY_CTL);
c9d39130
JG		 3115 tmp &= ~0x3;
3116 tmp |= 0x1;
cae5a29d 3117 writel(tmp, phy_mmio + MV5_PHY_CTL);
c9d39130
JG		 3118 }
3119
3120 tmp = readl(phy_mmio + MV5_PHY_MODE);
3121 tmp &= ~mask;
3122 tmp |= hpriv->signal[port].pre;
3123 tmp |= hpriv->signal[port].amps;
3124 writel(tmp, phy_mmio + MV5_PHY_MODE);
bca1c4eb
JG		 3125}
3126
c9d39130
JG		 3127
3128#undef ZERO
3129#define ZERO(reg) writel(0, port_mmio + (reg))
3130static void mv5_reset_hc_port(struct mv_host_priv *hpriv, void __iomem *mmio,
3131 unsigned int port)
3132{
3133 void __iomem *port_mmio = mv_port_base(mmio, port);
3134
e12bef50 3135 mv_reset_channel(hpriv, mmio, port);
c9d39130
JG		 3136
3137 ZERO(0x028); /* command */
cae5a29d 3138 writel(0x11f, port_mmio + EDMA_CFG);
c9d39130
JG		 3139 ZERO(0x004); /* timer */
3140 ZERO(0x008); /* irq err cause */
3141 ZERO(0x00c); /* irq err mask */
3142 ZERO(0x010); /* rq bah */
3143 ZERO(0x014); /* rq inp */
3144 ZERO(0x018); /* rq outp */
3145 ZERO(0x01c); /* respq bah */
3146 ZERO(0x024); /* respq outp */
3147 ZERO(0x020); /* respq inp */
3148 ZERO(0x02c); /* test control */
cae5a29d 3149 writel(0xbc, port_mmio + EDMA_IORDY_TMOUT);
c9d39130
JG		 3150}
3151#undef ZERO
3152
3153#define ZERO(reg) writel(0, hc_mmio + (reg))
3154static void mv5_reset_one_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
3155 unsigned int hc)
47c2b677 3156{
c9d39130
JG		 3157 void __iomem *hc_mmio = mv_hc_base(mmio, hc);
3158 u32 tmp;
3159
3160 ZERO(0x00c);
3161 ZERO(0x010);
3162 ZERO(0x014);
3163 ZERO(0x018);
3164
3165 tmp = readl(hc_mmio + 0x20);
3166 tmp &= 0x1c1c1c1c;
3167 tmp |= 0x03030303;
3168 writel(tmp, hc_mmio + 0x20);
3169}
3170#undef ZERO
3171
3172static int mv5_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
3173 unsigned int n_hc)
3174{
3175 unsigned int hc, port;
3176
3177 for (hc = 0; hc < n_hc; hc++) {
3178 for (port = 0; port < MV_PORTS_PER_HC; port++)
3179 mv5_reset_hc_port(hpriv, mmio,
3180 (hc * MV_PORTS_PER_HC) + port);
3181
3182 mv5_reset_one_hc(hpriv, mmio, hc);
3183 }
3184
3185 return 0;
47c2b677
JG		 3186}
3187
101ffae2
JG		 3188#undef ZERO
3189#define ZERO(reg) writel(0, mmio + (reg))
7bb3c529 3190static void mv_reset_pci_bus(struct ata_host *host, void __iomem *mmio)
101ffae2 3191{
02a121da 3192 struct mv_host_priv *hpriv = host->private_data;
101ffae2
JG		 3193 u32 tmp;
3194
cae5a29d 3195 tmp = readl(mmio + MV_PCI_MODE);
101ffae2 3196 tmp &= 0xff00ffff;
cae5a29d 3197 writel(tmp, mmio + MV_PCI_MODE);
101ffae2
JG		 3198
3199 ZERO(MV_PCI_DISC_TIMER);
3200 ZERO(MV_PCI_MSI_TRIGGER);
cae5a29d 3201 writel(0x000100ff, mmio + MV_PCI_XBAR_TMOUT);
101ffae2 3202 ZERO(MV_PCI_SERR_MASK);
cae5a29d
ML		 3203 ZERO(hpriv->irq_cause_offset);
3204 ZERO(hpriv->irq_mask_offset);
101ffae2
JG		 3205 ZERO(MV_PCI_ERR_LOW_ADDRESS);
3206 ZERO(MV_PCI_ERR_HIGH_ADDRESS);
3207 ZERO(MV_PCI_ERR_ATTRIBUTE);
3208 ZERO(MV_PCI_ERR_COMMAND);
3209}
3210#undef ZERO
3211
3212static void mv6_reset_flash(struct mv_host_priv *hpriv, void __iomem *mmio)
3213{
3214 u32 tmp;
3215
3216 mv5_reset_flash(hpriv, mmio);
3217
cae5a29d 3218 tmp = readl(mmio + GPIO_PORT_CTL);
101ffae2
JG		 3219 tmp &= 0x3;
3220 tmp |= (1 << 5) | (1 << 6);
cae5a29d 3221 writel(tmp, mmio + GPIO_PORT_CTL);
101ffae2
JG		 3222}
3223
3224/**
3225 * mv6_reset_hc - Perform the 6xxx global soft reset
3226 * @mmio: base address of the HBA
3227 *
3228 * This routine only applies to 6xxx parts.
3229 *
3230 * LOCKING:
3231 * Inherited from caller.
3232 */
c9d39130
JG		 3233static int mv6_reset_hc(struct mv_host_priv *hpriv, void __iomem *mmio,
3234 unsigned int n_hc)
101ffae2 3235{
cae5a29d 3236 void __iomem *reg = mmio + PCI_MAIN_CMD_STS;
101ffae2
JG		 3237 int i, rc = 0;
3238 u32 t;
3239
3240 /* Following procedure defined in PCI "main command and status
3241 * register" table.
3242 */
3243 t = readl(reg);
3244 writel(t | STOP_PCI_MASTER, reg);
3245
3246 for (i = 0; i < 1000; i++) {
3247 udelay(1);
3248 t = readl(reg);
2dcb407e 3249 if (PCI_MASTER_EMPTY & t)
101ffae2 3250 break;
101ffae2
JG		 3251 }
3252 if (!(PCI_MASTER_EMPTY & t)) {
3253 printk(KERN_ERR DRV_NAME ": PCI master won't flush\n");
3254 rc = 1;
3255 goto done;
3256 }
3257
3258 /* set reset */
3259 i = 5;
3260 do {
3261 writel(t | GLOB_SFT_RST, reg);
3262 t = readl(reg);
3263 udelay(1);
3264 } while (!(GLOB_SFT_RST & t) && (i-- > 0));
3265
3266 if (!(GLOB_SFT_RST & t)) {
3267 printk(KERN_ERR DRV_NAME ": can't set global reset\n");
3268 rc = 1;
3269 goto done;
3270 }
3271
3272 /* clear reset and *reenable the PCI master* (not mentioned in spec) */
3273 i = 5;
3274 do {
3275 writel(t & ~(GLOB_SFT_RST | STOP_PCI_MASTER), reg);
3276 t = readl(reg);
3277 udelay(1);
3278 } while ((GLOB_SFT_RST & t) && (i-- > 0));
3279
3280 if (GLOB_SFT_RST & t) {
3281 printk(KERN_ERR DRV_NAME ": can't clear global reset\n");
3282 rc = 1;
3283 }
3284done:
3285 return rc;
3286}
3287
47c2b677 3288static void mv6_read_preamp(struct mv_host_priv *hpriv, int idx,
ba3fe8fb
JG		 3289 void __iomem *mmio)
3290{
3291 void __iomem *port_mmio;
3292 u32 tmp;
3293
cae5a29d 3294 tmp = readl(mmio + RESET_CFG);
ba3fe8fb 3295 if ((tmp & (1 << 0)) == 0) {
47c2b677 3296 hpriv->signal[idx].amps = 0x7 << 8;
ba3fe8fb
JG		 3297 hpriv->signal[idx].pre = 0x1 << 5;
3298 return;
3299 }
3300
3301 port_mmio = mv_port_base(mmio, idx);
3302 tmp = readl(port_mmio + PHY_MODE2);
3303
3304 hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */
3305 hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */
3306}
3307
47c2b677 3308static void mv6_enable_leds(struct mv_host_priv *hpriv, void __iomem *mmio)
ba3fe8fb 3309{
cae5a29d 3310 writel(0x00000060, mmio + GPIO_PORT_CTL);
ba3fe8fb
JG		 3311}
3312
c9d39130 3313static void mv6_phy_errata(struct mv_host_priv *hpriv, void __iomem *mmio,
2a47ce06 3314 unsigned int port)
bca1c4eb 3315{
c9d39130
JG		 3316 void __iomem *port_mmio = mv_port_base(mmio, port);
3317
bca1c4eb 3318 u32 hp_flags = hpriv->hp_flags;
47c2b677
JG		 3319 int fix_phy_mode2 =
3320 hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0);
bca1c4eb 3321 int fix_phy_mode4 =
47c2b677 3322 hp_flags & (MV_HP_ERRATA_60X1B2 | MV_HP_ERRATA_60X1C0);
8c30a8b9 3323 u32 m2, m3;
47c2b677
JG		 3324
3325 if (fix_phy_mode2) {
3326 m2 = readl(port_mmio + PHY_MODE2);
3327 m2 &= ~(1 << 16);
3328 m2 |= (1 << 31);
3329 writel(m2, port_mmio + PHY_MODE2);
3330
3331 udelay(200);
3332
3333 m2 = readl(port_mmio + PHY_MODE2);
3334 m2 &= ~((1 << 16) | (1 << 31));
3335 writel(m2, port_mmio + PHY_MODE2);
3336
3337 udelay(200);
3338 }
3339
8c30a8b9
ML		 3340 /*
3341 * Gen-II/IIe PHY_MODE3 errata RM#2:
3342 * Achieves better receiver noise performance than the h/w default:
3343 */
3344 m3 = readl(port_mmio + PHY_MODE3);
3345 m3 = (m3 & 0x1f) | (0x5555601 << 5);
bca1c4eb 3346
0388a8c0
ML		 3347 /* Guideline 88F5182 (GL# SATA-S11) */
3348 if (IS_SOC(hpriv))
3349 m3 &= ~0x1c;
3350
bca1c4eb 3351 if (fix_phy_mode4) {
ba069e37
ML		 3352 u32 m4 = readl(port_mmio + PHY_MODE4);
3353 /*
3354 * Enforce reserved-bit restrictions on GenIIe devices only.
3355 * For earlier chipsets, force only the internal config field
3356 * (workaround for errata FEr SATA#10 part 1).
3357 */
8c30a8b9 3358 if (IS_GEN_IIE(hpriv))
ba069e37
ML		 3359 m4 = (m4 & ~PHY_MODE4_RSVD_ZEROS) | PHY_MODE4_RSVD_ONES;
3360 else
3361 m4 = (m4 & ~PHY_MODE4_CFG_MASK) | PHY_MODE4_CFG_VALUE;
8c30a8b9 3362 writel(m4, port_mmio + PHY_MODE4);
bca1c4eb 3363 }
b406c7a6
ML		 3364 /*
3365 * Workaround for 60x1-B2 errata SATA#13:
3366 * Any write to PHY_MODE4 (above) may corrupt PHY_MODE3,
3367 * so we must always rewrite PHY_MODE3 after PHY_MODE4.
ba68460b 3368 * Or ensure we use writelfl() when writing PHY_MODE4.
b406c7a6
ML		 3369 */
3370 writel(m3, port_mmio + PHY_MODE3);
bca1c4eb
JG		 3371
3372 /* Revert values of pre-emphasis and signal amps to the saved ones */
3373 m2 = readl(port_mmio + PHY_MODE2);
3374
3375 m2 &= ~MV_M2_PREAMP_MASK;
2a47ce06
JG		 3376 m2 |= hpriv->signal[port].amps;
3377 m2 |= hpriv->signal[port].pre;
47c2b677 3378 m2 &= ~(1 << 16);
bca1c4eb 3379
e4e7b892
JG		 3380 /* according to mvSata 3.6.1, some IIE values are fixed */
3381 if (IS_GEN_IIE(hpriv)) {
3382 m2 &= ~0xC30FF01F;
3383 m2 |= 0x0000900F;
3384 }
3385
bca1c4eb
JG		 3386 writel(m2, port_mmio + PHY_MODE2);
3387}
3388
f351b2d6
SB		 3389/* TODO: use the generic LED interface to configure the SATA Presence */
3390/* & Acitivy LEDs on the board */
3391static void mv_soc_enable_leds(struct mv_host_priv *hpriv,
3392 void __iomem *mmio)
3393{
3394 return;
3395}
3396
3397static void mv_soc_read_preamp(struct mv_host_priv *hpriv, int idx,
3398 void __iomem *mmio)
3399{
3400 void __iomem *port_mmio;
3401 u32 tmp;
3402
3403 port_mmio = mv_port_base(mmio, idx);
3404 tmp = readl(port_mmio + PHY_MODE2);
3405
3406 hpriv->signal[idx].amps = tmp & 0x700; /* bits 10:8 */
3407 hpriv->signal[idx].pre = tmp & 0xe0; /* bits 7:5 */
3408}
3409
3410#undef ZERO
3411#define ZERO(reg) writel(0, port_mmio + (reg))
3412static void mv_soc_reset_hc_port(struct mv_host_priv *hpriv,
3413 void __iomem *mmio, unsigned int port)
3414{
3415 void __iomem *port_mmio = mv_port_base(mmio, port);
3416
e12bef50 3417 mv_reset_channel(hpriv, mmio, port);
f351b2d6
SB		 3418
3419 ZERO(0x028); /* command */
cae5a29d 3420 writel(0x101f, port_mmio + EDMA_CFG);
f351b2d6
SB		 3421 ZERO(0x004); /* timer */
3422 ZERO(0x008); /* irq err cause */
3423 ZERO(0x00c); /* irq err mask */
3424 ZERO(0x010); /* rq bah */
3425 ZERO(0x014); /* rq inp */
3426 ZERO(0x018); /* rq outp */
3427 ZERO(0x01c); /* respq bah */
3428 ZERO(0x024); /* respq outp */
3429 ZERO(0x020); /* respq inp */
3430 ZERO(0x02c); /* test control */
d7b0c143 3431 writel(0x800, port_mmio + EDMA_IORDY_TMOUT);
f351b2d6
SB		 3432}
3433
3434#undef ZERO
3435
3436#define ZERO(reg) writel(0, hc_mmio + (reg))
3437static void mv_soc_reset_one_hc(struct mv_host_priv *hpriv,
3438 void __iomem *mmio)
3439{
3440 void __iomem *hc_mmio = mv_hc_base(mmio, 0);
3441
3442 ZERO(0x00c);
3443 ZERO(0x010);
3444 ZERO(0x014);
3445
3446}
3447
3448#undef ZERO
3449
3450static int mv_soc_reset_hc(struct mv_host_priv *hpriv,
3451 void __iomem *mmio, unsigned int n_hc)
3452{
3453 unsigned int port;
3454
3455 for (port = 0; port < hpriv->n_ports; port++)
3456 mv_soc_reset_hc_port(hpriv, mmio, port);
3457
3458 mv_soc_reset_one_hc(hpriv, mmio);
3459
3460 return 0;
3461}
3462
3463static void mv_soc_reset_flash(struct mv_host_priv *hpriv,
3464 void __iomem *mmio)
3465{
3466 return;
3467}
3468
3469static void mv_soc_reset_bus(struct ata_host *host, void __iomem *mmio)
3470{
3471 return;
3472}
3473
29b7e43c
MM		 3474static void mv_soc_65n_phy_errata(struct mv_host_priv *hpriv,
3475 void __iomem *mmio, unsigned int port)
3476{
3477 void __iomem *port_mmio = mv_port_base(mmio, port);
3478 u32 reg;
3479
3480 reg = readl(port_mmio + PHY_MODE3);
3481 reg &= ~(0x3 << 27); /* SELMUPF (bits 28:27) to 1 */
3482 reg |= (0x1 << 27);
3483 reg &= ~(0x3 << 29); /* SELMUPI (bits 30:29) to 1 */
3484 reg |= (0x1 << 29);
3485 writel(reg, port_mmio + PHY_MODE3);
3486
3487 reg = readl(port_mmio + PHY_MODE4);
3488 reg &= ~0x1; /* SATU_OD8 (bit 0) to 0, reserved bit 16 must be set */
3489 reg |= (0x1 << 16);
3490 writel(reg, port_mmio + PHY_MODE4);
3491
3492 reg = readl(port_mmio + PHY_MODE9_GEN2);
3493 reg &= ~0xf; /* TXAMP[3:0] (bits 3:0) to 8 */
3494 reg |= 0x8;
3495 reg &= ~(0x1 << 14); /* TXAMP[4] (bit 14) to 0 */
3496 writel(reg, port_mmio + PHY_MODE9_GEN2);
3497
3498 reg = readl(port_mmio + PHY_MODE9_GEN1);
3499 reg &= ~0xf; /* TXAMP[3:0] (bits 3:0) to 8 */
3500 reg |= 0x8;
3501 reg &= ~(0x1 << 14); /* TXAMP[4] (bit 14) to 0 */
3502 writel(reg, port_mmio + PHY_MODE9_GEN1);
3503}
3504
3505/**
3506 * soc_is_65 - check if the soc is 65 nano device
3507 *
3508 * Detect the type of the SoC, this is done by reading the PHYCFG_OFS
3509 * register, this register should contain non-zero value and it exists only
3510 * in the 65 nano devices, when reading it from older devices we get 0.
3511 */
3512static bool soc_is_65n(struct mv_host_priv *hpriv)
3513{
3514 void __iomem *port0_mmio = mv_port_base(hpriv->base, 0);
3515
3516 if (readl(port0_mmio + PHYCFG_OFS))
3517 return true;
3518 return false;
3519}
3520
8e7decdb 3521static void mv_setup_ifcfg(void __iomem *port_mmio, int want_gen2i)
b67a1064 3522{
cae5a29d 3523 u32 ifcfg = readl(port_mmio + SATA_IFCFG);
b67a1064 3524
8e7decdb 3525 ifcfg = (ifcfg & 0xf7f) | 0x9b1000; /* from chip spec */
b67a1064 3526 if (want_gen2i)
8e7decdb 3527 ifcfg |= (1 << 7); /* enable gen2i speed */
cae5a29d 3528 writelfl(ifcfg, port_mmio + SATA_IFCFG);
b67a1064
ML		 3529}
3530
e12bef50 3531static void mv_reset_channel(struct mv_host_priv *hpriv, void __iomem *mmio,
c9d39130
JG		 3532 unsigned int port_no)
3533{
3534 void __iomem *port_mmio = mv_port_base(mmio, port_no);
3535
8e7decdb
ML		 3536 /*
3537 * The datasheet warns against setting EDMA_RESET when EDMA is active
3538 * (but doesn't say what the problem might be). So we first try
3539 * to disable the EDMA engine before doing the EDMA_RESET operation.
3540 */
0d8be5cb 3541 mv_stop_edma_engine(port_mmio);
cae5a29d 3542 writelfl(EDMA_RESET, port_mmio + EDMA_CMD);
c9d39130 3543
b67a1064 3544 if (!IS_GEN_I(hpriv)) {
8e7decdb
ML		 3545 /* Enable 3.0gb/s link speed: this survives EDMA_RESET */
3546 mv_setup_ifcfg(port_mmio, 1);
c9d39130 3547 }
b67a1064 3548 /*
8e7decdb 3549 * Strobing EDMA_RESET here causes a hard reset of the SATA transport,
b67a1064 3550 * link, and physical layers. It resets all SATA interface registers
cae5a29d 3551 * (except for SATA_IFCFG), and issues a COMRESET to the dev.
c9d39130 3552 */
cae5a29d 3553 writelfl(EDMA_RESET, port_mmio + EDMA_CMD);
b67a1064 3554 udelay(25); /* allow reset propagation */
cae5a29d 3555 writelfl(0, port_mmio + EDMA_CMD);
c9d39130
JG		 3556
3557 hpriv->ops->phy_errata(hpriv, mmio, port_no);
3558
ee9ccdf7 3559 if (IS_GEN_I(hpriv))
c9d39130
JG		 3560 mdelay(1);
3561}
3562
e49856d8 3563static void mv_pmp_select(struct ata_port *ap, int pmp)
20f733e7 3564{
e49856d8
ML		 3565 if (sata_pmp_supported(ap)) {
3566 void __iomem *port_mmio = mv_ap_base(ap);
cae5a29d 3567 u32 reg = readl(port_mmio + SATA_IFCTL);
e49856d8 3568 int old = reg & 0xf;
22374677 3569
e49856d8
ML		 3570 if (old != pmp) {
3571 reg = (reg & ~0xf) | pmp;
cae5a29d 3572 writelfl(reg, port_mmio + SATA_IFCTL);
e49856d8 3573 }
22374677 3574 }
20f733e7
BR		 3575}
3576
e49856d8
ML		 3577static int mv_pmp_hardreset(struct ata_link *link, unsigned int *class,
3578 unsigned long deadline)
22374677 3579{
e49856d8
ML		 3580 mv_pmp_select(link->ap, sata_srst_pmp(link));
3581 return sata_std_hardreset(link, class, deadline);
3582}
bdd4ddde 3583
e49856d8
ML		 3584static int mv_softreset(struct ata_link *link, unsigned int *class,
3585 unsigned long deadline)
3586{
3587 mv_pmp_select(link->ap, sata_srst_pmp(link));
3588 return ata_sff_softreset(link, class, deadline);
22374677
JG		 3589}
3590
cc0680a5 3591static int mv_hardreset(struct ata_link *link, unsigned int *class,
bdd4ddde 3592 unsigned long deadline)
31961943 3593{
cc0680a5 3594 struct ata_port *ap = link->ap;
bdd4ddde 3595 struct mv_host_priv *hpriv = ap->host->private_data;
b562468c 3596 struct mv_port_priv *pp = ap->private_data;
f351b2d6 3597 void __iomem *mmio = hpriv->base;
0d8be5cb
ML		 3598 int rc, attempts = 0, extra = 0;
3599 u32 sstatus;
3600 bool online;
31961943 3601
e12bef50 3602 mv_reset_channel(hpriv, mmio, ap->port_no);
b562468c 3603 pp->pp_flags &= ~MV_PP_FLAG_EDMA_EN;
d16ab3f6
ML		 3604 pp->pp_flags &=
3605 ~(MV_PP_FLAG_FBS_EN | MV_PP_FLAG_NCQ_EN | MV_PP_FLAG_FAKE_ATA_BUSY);
bdd4ddde 3606
0d8be5cb
ML		 3607 /* Workaround for errata FEr SATA#10 (part 2) */
3608 do {
17c5aab5
ML		 3609 const unsigned long *timing =
3610 sata_ehc_deb_timing(&link->eh_context);
bdd4ddde 3611
17c5aab5
ML		 3612 rc = sata_link_hardreset(link, timing, deadline + extra,
3613 &online, NULL);
9dcffd99 3614 rc = online ? -EAGAIN : rc;
17c5aab5 3615 if (rc)
0d8be5cb 3616 return rc;
0d8be5cb
ML		 3617 sata_scr_read(link, SCR_STATUS, &sstatus);
3618 if (!IS_GEN_I(hpriv) && ++attempts >= 5 && sstatus == 0x121) {
3619 /* Force 1.5gb/s link speed and try again */
8e7decdb 3620 mv_setup_ifcfg(mv_ap_base(ap), 0);
0d8be5cb
ML		 3621 if (time_after(jiffies + HZ, deadline))
3622 extra = HZ; /* only extend it once, max */
3623 }
3624 } while (sstatus != 0x0 && sstatus != 0x113 && sstatus != 0x123);
08da1759 3625 mv_save_cached_regs(ap);
66e57a2c 3626 mv_edma_cfg(ap, 0, 0);
bdd4ddde 3627
17c5aab5 3628 return rc;
bdd4ddde
JG		 3629}
3630
bdd4ddde
JG		 3631static void mv_eh_freeze(struct ata_port *ap)
3632{
1cfd19ae 3633 mv_stop_edma(ap);
c4de573b 3634 mv_enable_port_irqs(ap, 0);
bdd4ddde
JG		 3635}
3636
3637static void mv_eh_thaw(struct ata_port *ap)
3638{
f351b2d6 3639 struct mv_host_priv *hpriv = ap->host->private_data;
c4de573b
ML		 3640 unsigned int port = ap->port_no;
3641 unsigned int hardport = mv_hardport_from_port(port);
1cfd19ae 3642 void __iomem *hc_mmio = mv_hc_base_from_port(hpriv->base, port);
bdd4ddde 3643 void __iomem *port_mmio = mv_ap_base(ap);
c4de573b 3644 u32 hc_irq_cause;
bdd4ddde 3645
bdd4ddde 3646 /* clear EDMA errors on this port */
cae5a29d 3647 writel(0, port_mmio + EDMA_ERR_IRQ_CAUSE);
bdd4ddde
JG		 3648
3649 /* clear pending irq events */
cae6edc3 3650 hc_irq_cause = ~((DEV_IRQ | DMA_IRQ) << hardport);
cae5a29d 3651 writelfl(hc_irq_cause, hc_mmio + HC_IRQ_CAUSE);
bdd4ddde 3652
88e675e1 3653 mv_enable_port_irqs(ap, ERR_IRQ);
31961943
BR		 3654}
3655
05b308e1
BR		 3656/**
3657 * mv_port_init - Perform some early initialization on a single port.
3658 * @port: libata data structure storing shadow register addresses
3659 * @port_mmio: base address of the port
3660 *
3661 * Initialize shadow register mmio addresses, clear outstanding
3662 * interrupts on the port, and unmask interrupts for the future
3663 * start of the port.
3664 *
3665 * LOCKING:
3666 * Inherited from caller.
3667 */
31961943 3668static void mv_port_init(struct ata_ioports *port, void __iomem *port_mmio)
20f733e7 3669{
cae5a29d 3670 void __iomem *serr, *shd_base = port_mmio + SHD_BLK;
31961943 3671
8b260248 3672 /* PIO related setup
31961943
BR		 3673 */
3674 port->data_addr = shd_base + (sizeof(u32) * ATA_REG_DATA);
8b260248 3675 port->error_addr =
31961943
BR		 3676 port->feature_addr = shd_base + (sizeof(u32) * ATA_REG_ERR);
3677 port->nsect_addr = shd_base + (sizeof(u32) * ATA_REG_NSECT);
3678 port->lbal_addr = shd_base + (sizeof(u32) * ATA_REG_LBAL);
3679 port->lbam_addr = shd_base + (sizeof(u32) * ATA_REG_LBAM);
3680 port->lbah_addr = shd_base + (sizeof(u32) * ATA_REG_LBAH);
3681 port->device_addr = shd_base + (sizeof(u32) * ATA_REG_DEVICE);
8b260248 3682 port->status_addr =
31961943
BR		 3683 port->command_addr = shd_base + (sizeof(u32) * ATA_REG_STATUS);
3684 /* special case: control/altstatus doesn't have ATA_REG_ address */
cae5a29d 3685 port->altstatus_addr = port->ctl_addr = shd_base + SHD_CTL_AST;
31961943 3686
31961943 3687 /* Clear any currently outstanding port interrupt conditions */
cae5a29d
ML		 3688 serr = port_mmio + mv_scr_offset(SCR_ERROR);
3689 writelfl(readl(serr), serr);
3690 writelfl(0, port_mmio + EDMA_ERR_IRQ_CAUSE);
31961943 3691
646a4da5 3692 /* unmask all non-transient EDMA error interrupts */
cae5a29d 3693 writelfl(~EDMA_ERR_IRQ_TRANSIENT, port_mmio + EDMA_ERR_IRQ_MASK);
20f733e7 3694
8b260248 3695 VPRINTK("EDMA cfg=0x%08x EDMA IRQ err cause/mask=0x%08x/0x%08x\n",
cae5a29d
ML		 3696 readl(port_mmio + EDMA_CFG),
3697 readl(port_mmio + EDMA_ERR_IRQ_CAUSE),
3698 readl(port_mmio + EDMA_ERR_IRQ_MASK));
20f733e7
BR		 3699}
3700
616d4a98
ML		 3701static unsigned int mv_in_pcix_mode(struct ata_host *host)
3702{
3703 struct mv_host_priv *hpriv = host->private_data;
3704 void __iomem *mmio = hpriv->base;
3705 u32 reg;
3706
1f398472 3707 if (IS_SOC(hpriv) || !IS_PCIE(hpriv))
616d4a98 3708 return 0; /* not PCI-X capable */
cae5a29d 3709 reg = readl(mmio + MV_PCI_MODE);
616d4a98
ML		 3710 if ((reg & MV_PCI_MODE_MASK) == 0)
3711 return 0; /* conventional PCI mode */
3712 return 1; /* chip is in PCI-X mode */
3713}
3714
3715static int mv_pci_cut_through_okay(struct ata_host *host)
3716{
3717 struct mv_host_priv *hpriv = host->private_data;
3718 void __iomem *mmio = hpriv->base;
3719 u32 reg;
3720
3721 if (!mv_in_pcix_mode(host)) {
cae5a29d
ML		 3722 reg = readl(mmio + MV_PCI_COMMAND);
3723 if (reg & MV_PCI_COMMAND_MRDTRIG)
616d4a98
ML		 3724 return 0; /* not okay */
3725 }
3726 return 1; /* okay */
3727}
3728
65ad7fef
ML		 3729static void mv_60x1b2_errata_pci7(struct ata_host *host)
3730{
3731 struct mv_host_priv *hpriv = host->private_data;
3732 void __iomem *mmio = hpriv->base;
3733
3734 /* workaround for 60x1-B2 errata PCI#7 */
3735 if (mv_in_pcix_mode(host)) {
cae5a29d
ML		 3736 u32 reg = readl(mmio + MV_PCI_COMMAND);
3737 writelfl(reg & ~MV_PCI_COMMAND_MWRCOM, mmio + MV_PCI_COMMAND);
65ad7fef
ML		 3738 }
3739}
3740
4447d351 3741static int mv_chip_id(struct ata_host *host, unsigned int board_idx)
bca1c4eb 3742{
4447d351
TH		 3743 struct pci_dev *pdev = to_pci_dev(host->dev);
3744 struct mv_host_priv *hpriv = host->private_data;
bca1c4eb
JG		 3745 u32 hp_flags = hpriv->hp_flags;
3746
5796d1c4 3747 switch (board_idx) {
47c2b677
JG		 3748 case chip_5080:
3749 hpriv->ops = &mv5xxx_ops;
ee9ccdf7 3750 hp_flags |= MV_HP_GEN_I;
47c2b677 3751
44c10138 3752 switch (pdev->revision) {
47c2b677
JG		 3753 case 0x1:
3754 hp_flags |= MV_HP_ERRATA_50XXB0;
3755 break;
3756 case 0x3:
3757 hp_flags |= MV_HP_ERRATA_50XXB2;
3758 break;
3759 default:
a44fec1f
JP		 3760 dev_warn(&pdev->dev,
3761 "Applying 50XXB2 workarounds to unknown rev\n");
47c2b677
JG		 3762 hp_flags |= MV_HP_ERRATA_50XXB2;
3763 break;
3764 }
3765 break;
3766
bca1c4eb
JG		 3767 case chip_504x:
3768 case chip_508x:
47c2b677 3769 hpriv->ops = &mv5xxx_ops;
ee9ccdf7 3770 hp_flags |= MV_HP_GEN_I;
bca1c4eb 3771
44c10138 3772 switch (pdev->revision) {
47c2b677
JG		 3773 case 0x0:
3774 hp_flags |= MV_HP_ERRATA_50XXB0;
3775 break;
3776 case 0x3:
3777 hp_flags |= MV_HP_ERRATA_50XXB2;
3778 break;
3779 default:
a44fec1f
JP		 3780 dev_warn(&pdev->dev,
3781 "Applying B2 workarounds to unknown rev\n");
47c2b677
JG		 3782 hp_flags |= MV_HP_ERRATA_50XXB2;
3783 break;
bca1c4eb
JG		 3784 }
3785 break;
3786
3787 case chip_604x:
3788 case chip_608x:
47c2b677 3789 hpriv->ops = &mv6xxx_ops;
ee9ccdf7 3790 hp_flags |= MV_HP_GEN_II;
47c2b677 3791
44c10138 3792 switch (pdev->revision) {
47c2b677 3793 case 0x7:
65ad7fef 3794 mv_60x1b2_errata_pci7(host);
47c2b677
JG		 3795 hp_flags |= MV_HP_ERRATA_60X1B2;
3796 break;
3797 case 0x9:
3798 hp_flags |= MV_HP_ERRATA_60X1C0;
bca1c4eb
JG		 3799 break;
3800 default:
a44fec1f
JP		 3801 dev_warn(&pdev->dev,
3802 "Applying B2 workarounds to unknown rev\n");
47c2b677 3803 hp_flags |= MV_HP_ERRATA_60X1B2;
bca1c4eb
JG		 3804 break;
3805 }
3806 break;
3807
e4e7b892 3808 case chip_7042:
616d4a98 3809 hp_flags |= MV_HP_PCIE | MV_HP_CUT_THROUGH;
306b30f7
ML		 3810 if (pdev->vendor == PCI_VENDOR_ID_TTI &&
3811 (pdev->device == 0x2300 || pdev->device == 0x2310))
3812 {
4e520033
ML		 3813 /*
3814 * Highpoint RocketRAID PCIe 23xx series cards:
3815 *
3816 * Unconfigured drives are treated as "Legacy"
3817 * by the BIOS, and it overwrites sector 8 with
3818 * a "Lgcy" metadata block prior to Linux boot.
3819 *
3820 * Configured drives (RAID or JBOD) leave sector 8
3821 * alone, but instead overwrite a high numbered
3822 * sector for the RAID metadata. This sector can
3823 * be determined exactly, by truncating the physical
3824 * drive capacity to a nice even GB value.
3825 *
3826 * RAID metadata is at: (dev->n_sectors & ~0xfffff)
3827 *
3828 * Warn the user, lest they think we're just buggy.
3829 */
3830 printk(KERN_WARNING DRV_NAME ": Highpoint RocketRAID"
3831 " BIOS CORRUPTS DATA on all attached drives,"
3832 " regardless of if/how they are configured."
3833 " BEWARE!\n");
3834 printk(KERN_WARNING DRV_NAME ": For data safety, do not"
3835 " use sectors 8-9 on \"Legacy\" drives,"
3836 " and avoid the final two gigabytes on"
3837 " all RocketRAID BIOS initialized drives.\n");
306b30f7 3838 }
8e7decdb 3839 /* drop through */
e4e7b892
JG		 3840 case chip_6042:
3841 hpriv->ops = &mv6xxx_ops;
e4e7b892 3842 hp_flags |= MV_HP_GEN_IIE;
616d4a98
ML		 3843 if (board_idx == chip_6042 && mv_pci_cut_through_okay(host))
3844 hp_flags |= MV_HP_CUT_THROUGH;
e4e7b892 3845
44c10138 3846 switch (pdev->revision) {
5cf73bfb 3847 case 0x2: /* Rev.B0: the first/only public release */
e4e7b892
JG		 3848 hp_flags |= MV_HP_ERRATA_60X1C0;
3849 break;
3850 default:
a44fec1f
JP		 3851 dev_warn(&pdev->dev,
3852 "Applying 60X1C0 workarounds to unknown rev\n");
e4e7b892
JG		 3853 hp_flags |= MV_HP_ERRATA_60X1C0;
3854 break;
3855 }
3856 break;
f351b2d6 3857 case chip_soc:
29b7e43c
MM		 3858 if (soc_is_65n(hpriv))
3859 hpriv->ops = &mv_soc_65n_ops;
3860 else
3861 hpriv->ops = &mv_soc_ops;
eb3a55a9
SB		 3862 hp_flags |= MV_HP_FLAG_SOC | MV_HP_GEN_IIE |
3863 MV_HP_ERRATA_60X1C0;
f351b2d6 3864 break;
e4e7b892 3865
bca1c4eb 3866 default:
a44fec1f 3867 dev_err(host->dev, "BUG: invalid board index %u\n", board_idx);
bca1c4eb
JG		 3868 return 1;
3869 }
3870
3871 hpriv->hp_flags = hp_flags;
02a121da 3872 if (hp_flags & MV_HP_PCIE) {
cae5a29d
ML		 3873 hpriv->irq_cause_offset = PCIE_IRQ_CAUSE;
3874 hpriv->irq_mask_offset = PCIE_IRQ_MASK;
02a121da
ML		 3875 hpriv->unmask_all_irqs = PCIE_UNMASK_ALL_IRQS;
3876 } else {
cae5a29d
ML		 3877 hpriv->irq_cause_offset = PCI_IRQ_CAUSE;
3878 hpriv->irq_mask_offset = PCI_IRQ_MASK;
02a121da
ML		 3879 hpriv->unmask_all_irqs = PCI_UNMASK_ALL_IRQS;
3880 }
bca1c4eb
JG		 3881
3882 return 0;
3883}
3884
05b308e1 3885/**
47c2b677 3886 * mv_init_host - Perform some early initialization of the host.
4447d351 3887 * @host: ATA host to initialize
05b308e1
BR		 3888 *
3889 * If possible, do an early global reset of the host. Then do
3890 * our port init and clear/unmask all/relevant host interrupts.
3891 *
3892 * LOCKING:
3893 * Inherited from caller.
3894 */
1bfeff03 3895static int mv_init_host(struct ata_host *host)
20f733e7
BR		 3896{
3897 int rc = 0, n_hc, port, hc;
4447d351 3898 struct mv_host_priv *hpriv = host->private_data;
f351b2d6 3899 void __iomem *mmio = hpriv->base;
47c2b677 3900
1bfeff03 3901 rc = mv_chip_id(host, hpriv->board_idx);
bca1c4eb 3902 if (rc)
352fab70 3903 goto done;
f351b2d6 3904
1f398472 3905 if (IS_SOC(hpriv)) {
cae5a29d
ML		 3906 hpriv->main_irq_cause_addr = mmio + SOC_HC_MAIN_IRQ_CAUSE;
3907 hpriv->main_irq_mask_addr = mmio + SOC_HC_MAIN_IRQ_MASK;
1f398472 3908 } else {
cae5a29d
ML		 3909 hpriv->main_irq_cause_addr = mmio + PCI_HC_MAIN_IRQ_CAUSE;
3910 hpriv->main_irq_mask_addr = mmio + PCI_HC_MAIN_IRQ_MASK;
f351b2d6 3911 }
352fab70 3912
5d0fb2e7
TR		 3913 /* initialize shadow irq mask with register's value */
3914 hpriv->main_irq_mask = readl(hpriv->main_irq_mask_addr);
3915
352fab70 3916 /* global interrupt mask: 0 == mask everything */
c4de573b 3917 mv_set_main_irq_mask(host, ~0, 0);
bca1c4eb 3918
4447d351 3919 n_hc = mv_get_hc_count(host->ports[0]->flags);
bca1c4eb 3920
4447d351 3921 for (port = 0; port < host->n_ports; port++)
29b7e43c
MM		 3922 if (hpriv->ops->read_preamp)
3923 hpriv->ops->read_preamp(hpriv, port, mmio);
20f733e7 3924
c9d39130 3925 rc = hpriv->ops->reset_hc(hpriv, mmio, n_hc);
47c2b677 3926 if (rc)
20f733e7 3927 goto done;
20f733e7 3928
522479fb 3929 hpriv->ops->reset_flash(hpriv, mmio);
7bb3c529 3930 hpriv->ops->reset_bus(host, mmio);
47c2b677 3931 hpriv->ops->enable_leds(hpriv, mmio);
20f733e7 3932
4447d351 3933 for (port = 0; port < host->n_ports; port++) {
cbcdd875 3934 struct ata_port *ap = host->ports[port];
2a47ce06 3935 void __iomem *port_mmio = mv_port_base(mmio, port);
cbcdd875
TH		 3936
3937 mv_port_init(&ap->ioaddr, port_mmio);
20f733e7
BR		 3938 }
3939
3940 for (hc = 0; hc < n_hc; hc++) {
31961943
BR		 3941 void __iomem *hc_mmio = mv_hc_base(mmio, hc);
3942
3943 VPRINTK("HC%i: HC config=0x%08x HC IRQ cause "
3944 "(before clear)=0x%08x\n", hc,
cae5a29d
ML		 3945 readl(hc_mmio + HC_CFG),
3946 readl(hc_mmio + HC_IRQ_CAUSE));
31961943
BR		 3947
3948 /* Clear any currently outstanding hc interrupt conditions */
cae5a29d 3949 writelfl(0, hc_mmio + HC_IRQ_CAUSE);
20f733e7
BR		 3950 }
3951
44c65d16
ML		 3952 if (!IS_SOC(hpriv)) {
3953 /* Clear any currently outstanding host interrupt conditions */
cae5a29d 3954 writelfl(0, mmio + hpriv->irq_cause_offset);
31961943 3955
44c65d16 3956 /* and unmask interrupt generation for host regs */
cae5a29d 3957 writelfl(hpriv->unmask_all_irqs, mmio + hpriv->irq_mask_offset);
44c65d16 3958 }
51de32d2 3959
6be96ac1
ML		 3960 /*
3961 * enable only global host interrupts for now.
3962 * The per-port interrupts get done later as ports are set up.
3963 */
3964 mv_set_main_irq_mask(host, 0, PCI_ERR);
2b748a0a
ML		 3965 mv_set_irq_coalescing(host, irq_coalescing_io_count,
3966 irq_coalescing_usecs);
f351b2d6
SB		 3967done:
3968 return rc;
3969}
fb621e2f 3970
fbf14e2f
BB		 3971static int mv_create_dma_pools(struct mv_host_priv *hpriv, struct device *dev)
3972{
3973 hpriv->crqb_pool = dmam_pool_create("crqb_q", dev, MV_CRQB_Q_SZ,
3974 MV_CRQB_Q_SZ, 0);
3975 if (!hpriv->crqb_pool)
3976 return -ENOMEM;
3977
3978 hpriv->crpb_pool = dmam_pool_create("crpb_q", dev, MV_CRPB_Q_SZ,
3979 MV_CRPB_Q_SZ, 0);
3980 if (!hpriv->crpb_pool)
3981 return -ENOMEM;
3982
3983 hpriv->sg_tbl_pool = dmam_pool_create("sg_tbl", dev, MV_SG_TBL_SZ,
3984 MV_SG_TBL_SZ, 0);
3985 if (!hpriv->sg_tbl_pool)
3986 return -ENOMEM;
3987
3988 return 0;
3989}
3990
15a32632 3991static void mv_conf_mbus_windows(struct mv_host_priv *hpriv,
63a9332b 3992 const struct mbus_dram_target_info *dram)
15a32632
LB		 3993{
3994 int i;
3995
3996 for (i = 0; i < 4; i++) {
3997 writel(0, hpriv->base + WINDOW_CTRL(i));
3998 writel(0, hpriv->base + WINDOW_BASE(i));
3999 }
4000
4001 for (i = 0; i < dram->num_cs; i++) {
63a9332b 4002 const struct mbus_dram_window *cs = dram->cs + i;
15a32632
LB		 4003
4004 writel(((cs->size - 1) & 0xffff0000) |
4005 (cs->mbus_attr << 8) |
4006 (dram->mbus_dram_target_id << 4) | 1,
4007 hpriv->base + WINDOW_CTRL(i));
4008 writel(cs->base, hpriv->base + WINDOW_BASE(i));
4009 }
4010}
4011
f351b2d6
SB		 4012/**
4013 * mv_platform_probe - handle a positive probe of an soc Marvell
4014 * host
4015 * @pdev: platform device found
4016 *
4017 * LOCKING:
4018 * Inherited from caller.
4019 */
4020static int mv_platform_probe(struct platform_device *pdev)
4021{
f351b2d6 4022 const struct mv_sata_platform_data *mv_platform_data;
63a9332b 4023 const struct mbus_dram_target_info *dram;
f351b2d6
SB		 4024 const struct ata_port_info *ppi[] =
4025 { &mv_port_info[chip_soc], NULL };
4026 struct ata_host *host;
4027 struct mv_host_priv *hpriv;
4028 struct resource *res;
99b80e97
DC		 4029 int n_ports = 0;
4030 int rc;
eee98990
AL		 4031#if defined(CONFIG_HAVE_CLK)
4032 int port;
4033#endif
20f733e7 4034
06296a1e 4035 ata_print_version_once(&pdev->dev, DRV_VERSION);
bca1c4eb 4036
f351b2d6
SB		 4037 /*
4038 * Simple resource validation ..
4039 */
4040 if (unlikely(pdev->num_resources != 2)) {
4041 dev_err(&pdev->dev, "invalid number of resources\n");
4042 return -EINVAL;
4043 }
4044
4045 /*
4046 * Get the register base first
4047 */
4048 res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
4049 if (res == NULL)
4050 return -EINVAL;
4051
4052 /* allocate host */
4053 mv_platform_data = pdev->dev.platform_data;
4054 n_ports = mv_platform_data->n_ports;
4055
4056 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
4057 hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL);
4058
4059 if (!host || !hpriv)
4060 return -ENOMEM;
eee98990
AL		 4061#if defined(CONFIG_HAVE_CLK)
4062 hpriv->port_clks = devm_kzalloc(&pdev->dev,
4063 sizeof(struct clk *) * n_ports,
4064 GFP_KERNEL);
4065 if (!hpriv->port_clks)
4066 return -ENOMEM;
4067#endif
f351b2d6
SB		 4068 host->private_data = hpriv;
4069 hpriv->n_ports = n_ports;
1bfeff03 4070 hpriv->board_idx = chip_soc;
f351b2d6
SB		 4071
4072 host->iomap = NULL;
f1cb0ea1 4073 hpriv->base = devm_ioremap(&pdev->dev, res->start,
041b5eac 4074 resource_size(res));
cae5a29d 4075 hpriv->base -= SATAHC0_REG_BASE;
f351b2d6 4076
c77a2f4e
SB		 4077#if defined(CONFIG_HAVE_CLK)
4078 hpriv->clk = clk_get(&pdev->dev, NULL);
4079 if (IS_ERR(hpriv->clk))
eee98990 4080 dev_notice(&pdev->dev, "cannot get optional clkdev\n");
c77a2f4e 4081 else
eee98990
AL		 4082 clk_prepare_enable(hpriv->clk);
4083
4084 for (port = 0; port < n_ports; port++) {
4085 char port_number[16];
4086 sprintf(port_number, "%d", port);
4087 hpriv->port_clks[port] = clk_get(&pdev->dev, port_number);
4088 if (!IS_ERR(hpriv->port_clks[port]))
4089 clk_prepare_enable(hpriv->port_clks[port]);
4090 }
c77a2f4e
SB		 4091#endif
4092
15a32632
LB		 4093 /*
4094 * (Re-)program MBUS remapping windows if we are asked to.
4095 */
63a9332b
AL		 4096 dram = mv_mbus_dram_info();
4097 if (dram)
4098 mv_conf_mbus_windows(hpriv, dram);
15a32632 4099
fbf14e2f
BB		 4100 rc = mv_create_dma_pools(hpriv, &pdev->dev);
4101 if (rc)
c77a2f4e 4102 goto err;
fbf14e2f 4103
f351b2d6 4104 /* initialize adapter */
1bfeff03 4105 rc = mv_init_host(host);
f351b2d6 4106 if (rc)
c77a2f4e 4107 goto err;
f351b2d6 4108
a44fec1f
JP		 4109 dev_info(&pdev->dev, "slots %u ports %d\n",
4110 (unsigned)MV_MAX_Q_DEPTH, host->n_ports);
f351b2d6 4111
c00a4c9d
SS		 4112 rc = ata_host_activate(host, platform_get_irq(pdev, 0), mv_interrupt,
4113 IRQF_SHARED, &mv6_sht);
4114 if (!rc)
4115 return 0;
4116
c77a2f4e
SB		 4117err:
4118#if defined(CONFIG_HAVE_CLK)
4119 if (!IS_ERR(hpriv->clk)) {
eee98990 4120 clk_disable_unprepare(hpriv->clk);
c77a2f4e
SB		 4121 clk_put(hpriv->clk);
4122 }
eee98990
AL		 4123 for (port = 0; port < n_ports; port++) {
4124 if (!IS_ERR(hpriv->port_clks[port])) {
4125 clk_disable_unprepare(hpriv->port_clks[port]);
4126 clk_put(hpriv->port_clks[port]);
4127 }
4128 }
c77a2f4e
SB		 4129#endif
4130
4131 return rc;
f351b2d6
SB		 4132}
4133
4134/*
4135 *
4136 * mv_platform_remove - unplug a platform interface
4137 * @pdev: platform device
4138 *
4139 * A platform bus SATA device has been unplugged. Perform the needed
4140 * cleanup. Also called on module unload for any active devices.
4141 */
4142static int __devexit mv_platform_remove(struct platform_device *pdev)
4143{
d8661921 4144 struct ata_host *host = platform_get_drvdata(pdev);
c77a2f4e
SB		 4145#if defined(CONFIG_HAVE_CLK)
4146 struct mv_host_priv *hpriv = host->private_data;
eee98990 4147 int port;
c77a2f4e 4148#endif
f351b2d6 4149 ata_host_detach(host);
c77a2f4e
SB		 4150
4151#if defined(CONFIG_HAVE_CLK)
4152 if (!IS_ERR(hpriv->clk)) {
eee98990 4153 clk_disable_unprepare(hpriv->clk);
c77a2f4e
SB		 4154 clk_put(hpriv->clk);
4155 }
eee98990
AL		 4156 for (port = 0; port < host->n_ports; port++) {
4157 if (!IS_ERR(hpriv->port_clks[port])) {
4158 clk_disable_unprepare(hpriv->port_clks[port]);
4159 clk_put(hpriv->port_clks[port]);
4160 }
4161 }
c77a2f4e 4162#endif
f351b2d6 4163 return 0;
20f733e7
BR		 4164}
4165
6481f2b5
SB		 4166#ifdef CONFIG_PM
4167static int mv_platform_suspend(struct platform_device *pdev, pm_message_t state)
4168{
d8661921 4169 struct ata_host *host = platform_get_drvdata(pdev);
6481f2b5
SB		 4170 if (host)
4171 return ata_host_suspend(host, state);
4172 else
4173 return 0;
4174}
4175
4176static int mv_platform_resume(struct platform_device *pdev)
4177{
d8661921 4178 struct ata_host *host = platform_get_drvdata(pdev);
63a9332b 4179 const struct mbus_dram_target_info *dram;
6481f2b5
SB		 4180 int ret;
4181
4182 if (host) {
4183 struct mv_host_priv *hpriv = host->private_data;
63a9332b 4184
6481f2b5
SB		 4185 /*
4186 * (Re-)program MBUS remapping windows if we are asked to.
4187 */
63a9332b
AL		 4188 dram = mv_mbus_dram_info();
4189 if (dram)
4190 mv_conf_mbus_windows(hpriv, dram);
6481f2b5
SB		 4191
4192 /* initialize adapter */
1bfeff03 4193 ret = mv_init_host(host);
6481f2b5
SB		 4194 if (ret) {
4195 printk(KERN_ERR DRV_NAME ": Error during HW init\n");
4196 return ret;
4197 }
4198 ata_host_resume(host);
4199 }
4200
4201 return 0;
4202}
4203#else
4204#define mv_platform_suspend NULL
4205#define mv_platform_resume NULL
4206#endif
4207
f351b2d6
SB		 4208static struct platform_driver mv_platform_driver = {
4209 .probe = mv_platform_probe,
4210 .remove = __devexit_p(mv_platform_remove),
6481f2b5
SB		 4211 .suspend = mv_platform_suspend,
4212 .resume = mv_platform_resume,
f351b2d6
SB		 4213 .driver = {
4214 .name = DRV_NAME,
4215 .owner = THIS_MODULE,
4216 },
4217};
4218
4219
7bb3c529 4220#ifdef CONFIG_PCI
f351b2d6
SB		 4221static int mv_pci_init_one(struct pci_dev *pdev,
4222 const struct pci_device_id *ent);
b2dec48c
SB		 4223#ifdef CONFIG_PM
4224static int mv_pci_device_resume(struct pci_dev *pdev);
4225#endif
f351b2d6 4226
7bb3c529
SB		 4227
4228static struct pci_driver mv_pci_driver = {
4229 .name = DRV_NAME,
4230 .id_table = mv_pci_tbl,
f351b2d6 4231 .probe = mv_pci_init_one,
7bb3c529 4232 .remove = ata_pci_remove_one,
b2dec48c
SB		 4233#ifdef CONFIG_PM
4234 .suspend = ata_pci_device_suspend,
4235 .resume = mv_pci_device_resume,
4236#endif
4237
7bb3c529
SB		 4238};
4239
7bb3c529
SB		 4240/* move to PCI layer or libata core? */
4241static int pci_go_64(struct pci_dev *pdev)
4242{
4243 int rc;
4244
6a35528a
YH		 4245 if (!pci_set_dma_mask(pdev, DMA_BIT_MASK(64))) {
4246 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(64));
7bb3c529 4247 if (rc) {
284901a9 4248 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
7bb3c529 4249 if (rc) {
a44fec1f
JP		 4250 dev_err(&pdev->dev,
4251 "64-bit DMA enable failed\n");
7bb3c529
SB		 4252 return rc;
4253 }
4254 }
4255 } else {
284901a9 4256 rc = pci_set_dma_mask(pdev, DMA_BIT_MASK(32));
7bb3c529 4257 if (rc) {
a44fec1f 4258 dev_err(&pdev->dev, "32-bit DMA enable failed\n");
7bb3c529
SB		 4259 return rc;
4260 }
284901a9 4261 rc = pci_set_consistent_dma_mask(pdev, DMA_BIT_MASK(32));
7bb3c529 4262 if (rc) {
a44fec1f
JP		 4263 dev_err(&pdev->dev,
4264 "32-bit consistent DMA enable failed\n");
7bb3c529
SB		 4265 return rc;
4266 }
4267 }
4268
4269 return rc;
4270}
4271
05b308e1
BR		 4272/**
4273 * mv_print_info - Dump key info to kernel log for perusal.
4447d351 4274 * @host: ATA host to print info about
05b308e1
BR		 4275 *
4276 * FIXME: complete this.
4277 *
4278 * LOCKING:
4279 * Inherited from caller.
4280 */
4447d351 4281static void mv_print_info(struct ata_host *host)
31961943 4282{
4447d351
TH		 4283 struct pci_dev *pdev = to_pci_dev(host->dev);
4284 struct mv_host_priv *hpriv = host->private_data;
44c10138 4285 u8 scc;
c1e4fe71 4286 const char *scc_s, *gen;
31961943
BR		 4287
4288 /* Use this to determine the HW stepping of the chip so we know
4289 * what errata to workaround
4290 */
31961943
BR		 4291 pci_read_config_byte(pdev, PCI_CLASS_DEVICE, &scc);
4292 if (scc == 0)
4293 scc_s = "SCSI";
4294 else if (scc == 0x01)
4295 scc_s = "RAID";
4296 else
c1e4fe71
JG		 4297 scc_s = "?";
4298
4299 if (IS_GEN_I(hpriv))
4300 gen = "I";
4301 else if (IS_GEN_II(hpriv))
4302 gen = "II";
4303 else if (IS_GEN_IIE(hpriv))
4304 gen = "IIE";
4305 else
4306 gen = "?";
31961943 4307
a44fec1f
JP		 4308 dev_info(&pdev->dev, "Gen-%s %u slots %u ports %s mode IRQ via %s\n",
4309 gen, (unsigned)MV_MAX_Q_DEPTH, host->n_ports,
4310 scc_s, (MV_HP_FLAG_MSI & hpriv->hp_flags) ? "MSI" : "INTx");
31961943
BR		 4311}
4312
05b308e1 4313/**
f351b2d6 4314 * mv_pci_init_one - handle a positive probe of a PCI Marvell host
05b308e1
BR		 4315 * @pdev: PCI device found
4316 * @ent: PCI device ID entry for the matched host
4317 *
4318 * LOCKING:
4319 * Inherited from caller.
4320 */
f351b2d6
SB		 4321static int mv_pci_init_one(struct pci_dev *pdev,
4322 const struct pci_device_id *ent)
20f733e7 4323{
20f733e7 4324 unsigned int board_idx = (unsigned int)ent->driver_data;
4447d351
TH		 4325 const struct ata_port_info *ppi[] = { &mv_port_info[board_idx], NULL };
4326 struct ata_host *host;
4327 struct mv_host_priv *hpriv;
c4bc7d73 4328 int n_ports, port, rc;
20f733e7 4329
06296a1e 4330 ata_print_version_once(&pdev->dev, DRV_VERSION);
20f733e7 4331
4447d351
TH		 4332 /* allocate host */
4333 n_ports = mv_get_hc_count(ppi[0]->flags) * MV_PORTS_PER_HC;
4334
4335 host = ata_host_alloc_pinfo(&pdev->dev, ppi, n_ports);
4336 hpriv = devm_kzalloc(&pdev->dev, sizeof(*hpriv), GFP_KERNEL);
4337 if (!host || !hpriv)
4338 return -ENOMEM;
4339 host->private_data = hpriv;
f351b2d6 4340 hpriv->n_ports = n_ports;
1bfeff03 4341 hpriv->board_idx = board_idx;
4447d351
TH		 4342
4343 /* acquire resources */
24dc5f33
TH		 4344 rc = pcim_enable_device(pdev);
4345 if (rc)
20f733e7 4346 return rc;
20f733e7 4347
0d5ff566
TH		 4348 rc = pcim_iomap_regions(pdev, 1 << MV_PRIMARY_BAR, DRV_NAME);
4349 if (rc == -EBUSY)
24dc5f33 4350 pcim_pin_device(pdev);
0d5ff566 4351 if (rc)
24dc5f33 4352 return rc;
4447d351 4353 host->iomap = pcim_iomap_table(pdev);
f351b2d6 4354 hpriv->base = host->iomap[MV_PRIMARY_BAR];
20f733e7 4355
d88184fb
JG		 4356 rc = pci_go_64(pdev);
4357 if (rc)
4358 return rc;
4359
da2fa9ba
ML		 4360 rc = mv_create_dma_pools(hpriv, &pdev->dev);
4361 if (rc)
4362 return rc;
4363
c4bc7d73
SB		 4364 for (port = 0; port < host->n_ports; port++) {
4365 struct ata_port *ap = host->ports[port];
4366 void __iomem *port_mmio = mv_port_base(hpriv->base, port);
4367 unsigned int offset = port_mmio - hpriv->base;
4368
4369 ata_port_pbar_desc(ap, MV_PRIMARY_BAR, -1, "mmio");
4370 ata_port_pbar_desc(ap, MV_PRIMARY_BAR, offset, "port");
4371 }
4372
20f733e7 4373 /* initialize adapter */
1bfeff03 4374 rc = mv_init_host(host);
24dc5f33
TH		 4375 if (rc)
4376 return rc;
20f733e7 4377
6d3c30ef
ML		 4378 /* Enable message-switched interrupts, if requested */
4379 if (msi && pci_enable_msi(pdev) == 0)
4380 hpriv->hp_flags |= MV_HP_FLAG_MSI;
20f733e7 4381
31961943 4382 mv_dump_pci_cfg(pdev, 0x68);
4447d351 4383 mv_print_info(host);
20f733e7 4384
4447d351 4385 pci_set_master(pdev);
ea8b4db9 4386 pci_try_set_mwi(pdev);
4447d351 4387 return ata_host_activate(host, pdev->irq, mv_interrupt, IRQF_SHARED,
c5d3e45a 4388 IS_GEN_I(hpriv) ? &mv5_sht : &mv6_sht);
20f733e7 4389}
b2dec48c
SB		 4390
4391#ifdef CONFIG_PM
4392static int mv_pci_device_resume(struct pci_dev *pdev)
4393{
d8661921 4394 struct ata_host *host = pci_get_drvdata(pdev);
b2dec48c
SB		 4395 int rc;
4396
4397 rc = ata_pci_device_do_resume(pdev);
4398 if (rc)
4399 return rc;
4400
4401 /* initialize adapter */
4402 rc = mv_init_host(host);
4403 if (rc)
4404 return rc;
4405
4406 ata_host_resume(host);
4407
4408 return 0;
4409}
4410#endif
7bb3c529 4411#endif
20f733e7 4412
f351b2d6
SB		 4413static int mv_platform_probe(struct platform_device *pdev);
4414static int __devexit mv_platform_remove(struct platform_device *pdev);
4415
20f733e7
BR		 4416static int __init mv_init(void)
4417{
7bb3c529
SB		 4418 int rc = -ENODEV;
4419#ifdef CONFIG_PCI
4420 rc = pci_register_driver(&mv_pci_driver);
f351b2d6
SB		 4421 if (rc < 0)
4422 return rc;
4423#endif
4424 rc = platform_driver_register(&mv_platform_driver);
4425
4426#ifdef CONFIG_PCI
4427 if (rc < 0)
4428 pci_unregister_driver(&mv_pci_driver);
7bb3c529
SB		 4429#endif
4430 return rc;
20f733e7
BR		 4431}
4432
4433static void __exit mv_exit(void)
4434{
7bb3c529 4435#ifdef CONFIG_PCI
20f733e7 4436 pci_unregister_driver(&mv_pci_driver);
7bb3c529 4437#endif
f351b2d6 4438 platform_driver_unregister(&mv_platform_driver);
20f733e7
BR		 4439}
4440
4441MODULE_AUTHOR("Brett Russ");
4442MODULE_DESCRIPTION("SCSI low-level driver for Marvell SATA controllers");
4443MODULE_LICENSE("GPL");
4444MODULE_DEVICE_TABLE(pci, mv_pci_tbl);
4445MODULE_VERSION(DRV_VERSION);
17c5aab5 4446MODULE_ALIAS("platform:" DRV_NAME);
20f733e7
BR		 4447
4448module_init(mv_init);
4449module_exit(mv_exit);
Linux 6.x block layer and io_uring tree(s)