[linux-2.6-block.git] / drivers / ata / sata_highbank.c

/*
 * Calxeda Highbank AHCI SATA platform driver
 * Copyright 2012 Calxeda, Inc.
 *
 * based on the AHCI SATA platform driver by Jeff Garzik and Anton Vorontsov
 *
 * This program is free software; you can redistribute it and/or modify it
 * under the terms and conditions of the GNU General Public License,
 * version 2, as published by the Free Software Foundation.
 *
 * This program is distributed in the hope it will be useful, but WITHOUT
 * ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
 * FITNESS FOR A PARTICULAR PURPOSE.  See the GNU General Public License for
 * more details.
 *
 * You should have received a copy of the GNU General Public License along with
 * this program.  If not, see <http://www.gnu.org/licenses/>.
 */
#include <linux/kernel.h>
#include <linux/gfp.h>
#include <linux/module.h>
#include <linux/types.h>
#include <linux/err.h>
#include <linux/io.h>
#include <linux/spinlock.h>
#include <linux/device.h>
#include <linux/of_device.h>
#include <linux/of_address.h>
#include <linux/platform_device.h>
#include <linux/libata.h>
#include <linux/interrupt.h>
#include <linux/delay.h>
#include <linux/export.h>
#include <linux/gpio/consumer.h>

#include "ahci.h"

#define CPHY_MAP(dev, addr) ((((dev) & 0x1f) << 7) | (((addr) >> 9) & 0x7f))
#define CPHY_ADDR(addr) (((addr) & 0x1ff) << 2)
#define SERDES_CR_CTL			0x80a0
#define SERDES_CR_ADDR			0x80a1
#define SERDES_CR_DATA			0x80a2
#define CR_BUSY				0x0001
#define CR_START			0x0001
#define CR_WR_RDN			0x0002
#define CPHY_TX_INPUT_STS		0x2001
#define CPHY_RX_INPUT_STS		0x2002
#define CPHY_SATA_TX_OVERRIDE		0x8000
#define CPHY_SATA_RX_OVERRIDE	 	0x4000
#define CPHY_TX_OVERRIDE		0x2004
#define CPHY_RX_OVERRIDE		0x2005
#define SPHY_LANE			0x100
#define SPHY_HALF_RATE			0x0001
#define CPHY_SATA_DPLL_MODE		0x0700
#define CPHY_SATA_DPLL_SHIFT		8
#define CPHY_SATA_DPLL_RESET		(1 << 11)
#define CPHY_SATA_TX_ATTEN		0x1c00
#define CPHY_SATA_TX_ATTEN_SHIFT	10
#define CPHY_PHY_COUNT			6
#define CPHY_LANE_COUNT			4
#define CPHY_PORT_COUNT			(CPHY_PHY_COUNT * CPHY_LANE_COUNT)

static DEFINE_SPINLOCK(cphy_lock);
/* Each of the 6 phys can have up to 4 sata ports attached to i. Map 0-based
 * sata ports to their phys and then to their lanes within the phys
 */
struct phy_lane_info {
	void __iomem *phy_base;
	u8 lane_mapping;
	u8 phy_devs;
	u8 tx_atten;
};
static struct phy_lane_info port_data[CPHY_PORT_COUNT];

static DEFINE_SPINLOCK(sgpio_lock);
#define SCLOCK				0
#define SLOAD				1
#define SDATA				2
#define SGPIO_PINS			3
#define SGPIO_PORTS			8

struct ecx_plat_data {
	u32		n_ports;
	/* number of extra clocks that the SGPIO PIC controller expects */
	u32		pre_clocks;
	u32		post_clocks;
	struct gpio_desc *sgpio_gpiod[SGPIO_PINS];
	u32		sgpio_pattern;
	u32		port_to_sgpio[SGPIO_PORTS];
};

#define SGPIO_SIGNALS			3
#define ECX_ACTIVITY_BITS		0x300000
#define ECX_ACTIVITY_SHIFT		0
#define ECX_LOCATE_BITS			0x80000
#define ECX_LOCATE_SHIFT		1
#define ECX_FAULT_BITS			0x400000
#define ECX_FAULT_SHIFT			2
static inline int sgpio_bit_shift(struct ecx_plat_data *pdata, u32 port,
				u32 shift)
{
	return 1 << (3 * pdata->port_to_sgpio[port] + shift);
}

static void ecx_parse_sgpio(struct ecx_plat_data *pdata, u32 port, u32 state)
{
	if (state & ECX_ACTIVITY_BITS)
		pdata->sgpio_pattern |= sgpio_bit_shift(pdata, port,
						ECX_ACTIVITY_SHIFT);
	else
		pdata->sgpio_pattern &= ~sgpio_bit_shift(pdata, port,
						ECX_ACTIVITY_SHIFT);
	if (state & ECX_LOCATE_BITS)
		pdata->sgpio_pattern |= sgpio_bit_shift(pdata, port,
						ECX_LOCATE_SHIFT);
	else
		pdata->sgpio_pattern &= ~sgpio_bit_shift(pdata, port,
						ECX_LOCATE_SHIFT);
	if (state & ECX_FAULT_BITS)
		pdata->sgpio_pattern |= sgpio_bit_shift(pdata, port,
						ECX_FAULT_SHIFT);
	else
		pdata->sgpio_pattern &= ~sgpio_bit_shift(pdata, port,
						ECX_FAULT_SHIFT);
}

/*
 * Tell the LED controller that the signal has changed by raising the clock
 * line for 50 uS and then lowering it for 50 uS.
 */
static void ecx_led_cycle_clock(struct ecx_plat_data *pdata)
{
	gpiod_set_value(pdata->sgpio_gpiod[SCLOCK], 1);
	udelay(50);
	gpiod_set_value(pdata->sgpio_gpiod[SCLOCK], 0);
	udelay(50);
}

static ssize_t ecx_transmit_led_message(struct ata_port *ap, u32 state,
					ssize_t size)
{
	struct ahci_host_priv *hpriv =  ap->host->private_data;
	struct ecx_plat_data *pdata = hpriv->plat_data;
	struct ahci_port_priv *pp = ap->private_data;
	unsigned long flags;
	int pmp, i;
	struct ahci_em_priv *emp;
	u32 sgpio_out;

	/* get the slot number from the message */
	pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8;
	if (pmp < EM_MAX_SLOTS)
		emp = &pp->em_priv[pmp];
	else
		return -EINVAL;

	if (!(hpriv->em_msg_type & EM_MSG_TYPE_LED))
		return size;

	spin_lock_irqsave(&sgpio_lock, flags);
	ecx_parse_sgpio(pdata, ap->port_no, state);
	sgpio_out = pdata->sgpio_pattern;
	for (i = 0; i < pdata->pre_clocks; i++)
		ecx_led_cycle_clock(pdata);

	gpiod_set_value(pdata->sgpio_gpiod[SLOAD], 1);
	ecx_led_cycle_clock(pdata);
	gpiod_set_value(pdata->sgpio_gpiod[SLOAD], 0);
	/*
	 * bit-bang out the SGPIO pattern, by consuming a bit and then
	 * clocking it out.
	 */
	for (i = 0; i < (SGPIO_SIGNALS * pdata->n_ports); i++) {
		gpiod_set_value(pdata->sgpio_gpiod[SDATA], sgpio_out & 1);
		sgpio_out >>= 1;
		ecx_led_cycle_clock(pdata);
	}
	for (i = 0; i < pdata->post_clocks; i++)
		ecx_led_cycle_clock(pdata);

	/* save off new led state for port/slot */
	emp->led_state = state;

	spin_unlock_irqrestore(&sgpio_lock, flags);
	return size;
}

static void highbank_set_em_messages(struct device *dev,
					struct ahci_host_priv *hpriv,
					struct ata_port_info *pi)
{
	struct device_node *np = dev->of_node;
	struct ecx_plat_data *pdata = hpriv->plat_data;
	int i;

	for (i = 0; i < SGPIO_PINS; i++) {
		struct gpio_desc *gpiod;

		gpiod = devm_gpiod_get_index(dev, "calxeda,sgpio", i,
					     GPIOD_OUT_HIGH);
		if (IS_ERR(gpiod)) {
			dev_err(dev, "failed to get GPIO %d\n", i);
			continue;
		}
		gpiod_set_consumer_name(gpiod, "CX SGPIO");

		pdata->sgpio_gpiod[i] = gpiod;
	}
	of_property_read_u32_array(np, "calxeda,led-order",
						pdata->port_to_sgpio,
						pdata->n_ports);
	if (of_property_read_u32(np, "calxeda,pre-clocks", &pdata->pre_clocks))
		pdata->pre_clocks = 0;
	if (of_property_read_u32(np, "calxeda,post-clocks",
				&pdata->post_clocks))
		pdata->post_clocks = 0;

	/* store em_loc */
	hpriv->em_loc = 0;
	hpriv->em_buf_sz = 4;
	hpriv->em_msg_type = EM_MSG_TYPE_LED;
	pi->flags |= ATA_FLAG_EM | ATA_FLAG_SW_ACTIVITY;
}

static u32 __combo_phy_reg_read(u8 sata_port, u32 addr)
{
	u32 data;
	u8 dev = port_data[sata_port].phy_devs;
	spin_lock(&cphy_lock);
	writel(CPHY_MAP(dev, addr), port_data[sata_port].phy_base + 0x800);
	data = readl(port_data[sata_port].phy_base + CPHY_ADDR(addr));
	spin_unlock(&cphy_lock);
	return data;
}

static void __combo_phy_reg_write(u8 sata_port, u32 addr, u32 data)
{
	u8 dev = port_data[sata_port].phy_devs;
	spin_lock(&cphy_lock);
	writel(CPHY_MAP(dev, addr), port_data[sata_port].phy_base + 0x800);
	writel(data, port_data[sata_port].phy_base + CPHY_ADDR(addr));
	spin_unlock(&cphy_lock);
}

static void combo_phy_wait_for_ready(u8 sata_port)
{
	while (__combo_phy_reg_read(sata_port, SERDES_CR_CTL) & CR_BUSY)
		udelay(5);
}

static u32 combo_phy_read(u8 sata_port, u32 addr)
{
	combo_phy_wait_for_ready(sata_port);
	__combo_phy_reg_write(sata_port, SERDES_CR_ADDR, addr);
	__combo_phy_reg_write(sata_port, SERDES_CR_CTL, CR_START);
	combo_phy_wait_for_ready(sata_port);
	return __combo_phy_reg_read(sata_port, SERDES_CR_DATA);
}

static void combo_phy_write(u8 sata_port, u32 addr, u32 data)
{
	combo_phy_wait_for_ready(sata_port);
	__combo_phy_reg_write(sata_port, SERDES_CR_ADDR, addr);
	__combo_phy_reg_write(sata_port, SERDES_CR_DATA, data);
	__combo_phy_reg_write(sata_port, SERDES_CR_CTL, CR_WR_RDN | CR_START);
}

static void highbank_cphy_disable_overrides(u8 sata_port)
{
	u8 lane = port_data[sata_port].lane_mapping;
	u32 tmp;
	if (unlikely(port_data[sata_port].phy_base == NULL))
		return;
	tmp = combo_phy_read(sata_port, CPHY_RX_INPUT_STS + lane * SPHY_LANE);
	tmp &= ~CPHY_SATA_RX_OVERRIDE;
	combo_phy_write(sata_port, CPHY_RX_OVERRIDE + lane * SPHY_LANE, tmp);
}

static void cphy_override_tx_attenuation(u8 sata_port, u32 val)
{
	u8 lane = port_data[sata_port].lane_mapping;
	u32 tmp;

	if (val & 0x8)
		return;

	tmp = combo_phy_read(sata_port, CPHY_TX_INPUT_STS + lane * SPHY_LANE);
	tmp &= ~CPHY_SATA_TX_OVERRIDE;
	combo_phy_write(sata_port, CPHY_TX_OVERRIDE + lane * SPHY_LANE, tmp);

	tmp |= CPHY_SATA_TX_OVERRIDE;
	combo_phy_write(sata_port, CPHY_TX_OVERRIDE + lane * SPHY_LANE, tmp);

	tmp |= (val << CPHY_SATA_TX_ATTEN_SHIFT) & CPHY_SATA_TX_ATTEN;
	combo_phy_write(sata_port, CPHY_TX_OVERRIDE + lane * SPHY_LANE, tmp);
}

static void cphy_override_rx_mode(u8 sata_port, u32 val)
{
	u8 lane = port_data[sata_port].lane_mapping;
	u32 tmp;
	tmp = combo_phy_read(sata_port, CPHY_RX_INPUT_STS + lane * SPHY_LANE);
	tmp &= ~CPHY_SATA_RX_OVERRIDE;
	combo_phy_write(sata_port, CPHY_RX_OVERRIDE + lane * SPHY_LANE, tmp);

	tmp |= CPHY_SATA_RX_OVERRIDE;
	combo_phy_write(sata_port, CPHY_RX_OVERRIDE + lane * SPHY_LANE, tmp);

	tmp &= ~CPHY_SATA_DPLL_MODE;
	tmp |= val << CPHY_SATA_DPLL_SHIFT;
	combo_phy_write(sata_port, CPHY_RX_OVERRIDE + lane * SPHY_LANE, tmp);

	tmp |= CPHY_SATA_DPLL_RESET;
	combo_phy_write(sata_port, CPHY_RX_OVERRIDE + lane * SPHY_LANE, tmp);

	tmp &= ~CPHY_SATA_DPLL_RESET;
	combo_phy_write(sata_port, CPHY_RX_OVERRIDE + lane * SPHY_LANE, tmp);

	msleep(15);
}

static void highbank_cphy_override_lane(u8 sata_port)
{
	u8 lane = port_data[sata_port].lane_mapping;
	u32 tmp, k = 0;

	if (unlikely(port_data[sata_port].phy_base == NULL))
		return;
	do {
		tmp = combo_phy_read(sata_port, CPHY_RX_INPUT_STS +
						lane * SPHY_LANE);
	} while ((tmp & SPHY_HALF_RATE) && (k++ < 1000));
	cphy_override_rx_mode(sata_port, 3);
	cphy_override_tx_attenuation(sata_port, port_data[sata_port].tx_atten);
}

static int highbank_initialize_phys(struct device *dev, void __iomem *addr)
{
	struct device_node *sata_node = dev->of_node;
	int phy_count = 0, phy, port = 0, i;
	void __iomem *cphy_base[CPHY_PHY_COUNT] = {};
	struct device_node *phy_nodes[CPHY_PHY_COUNT] = {};
	u32 tx_atten[CPHY_PORT_COUNT] = {};

	memset(port_data, 0, sizeof(struct phy_lane_info) * CPHY_PORT_COUNT);

	do {
		u32 tmp;
		struct of_phandle_args phy_data;
		if (of_parse_phandle_with_args(sata_node,
				"calxeda,port-phys", "#phy-cells",
				port, &phy_data))
			break;
		for (phy = 0; phy < phy_count; phy++) {
			if (phy_nodes[phy] == phy_data.np)
				break;
		}
		if (phy_nodes[phy] == NULL) {
			phy_nodes[phy] = phy_data.np;
			cphy_base[phy] = of_iomap(phy_nodes[phy], 0);
			if (cphy_base[phy] == NULL) {
				return 0;
			}
			phy_count += 1;
		}
		port_data[port].lane_mapping = phy_data.args[0];
		of_property_read_u32(phy_nodes[phy], "phydev", &tmp);
		port_data[port].phy_devs = tmp;
		port_data[port].phy_base = cphy_base[phy];
		of_node_put(phy_data.np);
		port += 1;
	} while (port < CPHY_PORT_COUNT);
	of_property_read_u32_array(sata_node, "calxeda,tx-atten",
				tx_atten, port);
	for (i = 0; i < port; i++)
		port_data[i].tx_atten = (u8) tx_atten[i];
	return 0;
}

/*
 * The Calxeda SATA phy intermittently fails to bring up a link with Gen3
 * Retrying the phy hard reset can work around the issue, but the drive
 * may fail again. In less than 150 out of 15000 test runs, it took more
 * than 10 tries for the link to be established (but never more than 35).
 * Triple the maximum observed retry count to provide plenty of margin for
 * rare events and to guarantee that the link is established.
 *
 * Also, the default 2 second time-out on a failed drive is too long in
 * this situation. The uboot implementation of the same driver function
 * uses a much shorter time-out period and never experiences a time out
 * issue. Reducing the time-out to 500ms improves the responsiveness.
 * The other timing constants were kept the same as the stock AHCI driver.
 * This change was also tested 15000 times on 24 drives and none of them
 * experienced a time out.
 */
static int ahci_highbank_hardreset(struct ata_link *link, unsigned int *class,
				unsigned long deadline)
{
	static const unsigned long timing[] = { 5, 100, 500};
	struct ata_port *ap = link->ap;
	struct ahci_port_priv *pp = ap->private_data;
	struct ahci_host_priv *hpriv = ap->host->private_data;
	u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
	struct ata_taskfile tf;
	bool online;
	u32 sstatus;
	int rc;
	int retry = 100;

	hpriv->stop_engine(ap);

	/* clear D2H reception area to properly wait for D2H FIS */
	ata_tf_init(link->device, &tf);
	tf.command = ATA_BUSY;
	ata_tf_to_fis(&tf, 0, 0, d2h_fis);

	do {
		highbank_cphy_disable_overrides(link->ap->port_no);
		rc = sata_link_hardreset(link, timing, deadline, &online, NULL);
		highbank_cphy_override_lane(link->ap->port_no);

		/* If the status is 1, we are connected, but the link did not
		 * come up. So retry resetting the link again.
		 */
		if (sata_scr_read(link, SCR_STATUS, &sstatus))
			break;
		if (!(sstatus & 0x3))
			break;
	} while (!online && retry--);

	hpriv->start_engine(ap);

	if (online)
		*class = ahci_dev_classify(ap);

	return rc;
}

static struct ata_port_operations ahci_highbank_ops = {
	.inherits		= &ahci_ops,
	.hardreset		= ahci_highbank_hardreset,
	.transmit_led_message   = ecx_transmit_led_message,
};

static const struct ata_port_info ahci_highbank_port_info = {
	.flags          = AHCI_FLAG_COMMON,
	.pio_mask       = ATA_PIO4,
	.udma_mask      = ATA_UDMA6,
	.port_ops       = &ahci_highbank_ops,
};

static struct scsi_host_template ahci_highbank_platform_sht = {
	AHCI_SHT("sata_highbank"),
};

static const struct of_device_id ahci_of_match[] = {
	{ .compatible = "calxeda,hb-ahci" },
	{},
};
MODULE_DEVICE_TABLE(of, ahci_of_match);

static int ahci_highbank_probe(struct platform_device *pdev)
{
	struct device *dev = &pdev->dev;
	struct ahci_host_priv *hpriv;
	struct ecx_plat_data *pdata;
	struct ata_host *host;
	struct resource *mem;
	int irq;
	int i;
	int rc;
	u32 n_ports;
	struct ata_port_info pi = ahci_highbank_port_info;
	const struct ata_port_info *ppi[] = { &pi, NULL };

	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (!mem) {
		dev_err(dev, "no mmio space\n");
		return -EINVAL;
	}

	irq = platform_get_irq(pdev, 0);
	if (irq <= 0) {
		dev_err(dev, "no irq\n");
		return -EINVAL;
	}

	hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
	if (!hpriv) {
		dev_err(dev, "can't alloc ahci_host_priv\n");
		return -ENOMEM;
	}
	pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
	if (!pdata) {
		dev_err(dev, "can't alloc ecx_plat_data\n");
		return -ENOMEM;
	}

	hpriv->irq = irq;
	hpriv->flags |= (unsigned long)pi.private_data;

	hpriv->mmio = devm_ioremap(dev, mem->start, resource_size(mem));
	if (!hpriv->mmio) {
		dev_err(dev, "can't map %pR\n", mem);
		return -ENOMEM;
	}

	rc = highbank_initialize_phys(dev, hpriv->mmio);
	if (rc)
		return rc;


	ahci_save_initial_config(dev, hpriv);

	/* prepare host */
	if (hpriv->cap & HOST_CAP_NCQ)
		pi.flags |= ATA_FLAG_NCQ;

	if (hpriv->cap & HOST_CAP_PMP)
		pi.flags |= ATA_FLAG_PMP;

	if (hpriv->cap & HOST_CAP_64)
		dma_set_coherent_mask(dev, DMA_BIT_MASK(64));

	/* CAP.NP sometimes indicate the index of the last enabled
	 * port, at other times, that of the last possible port, so
	 * determining the maximum port number requires looking at
	 * both CAP.NP and port_map.
	 */
	n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));

	pdata->n_ports = n_ports;
	hpriv->plat_data = pdata;
	highbank_set_em_messages(dev, hpriv, &pi);

	host = ata_host_alloc_pinfo(dev, ppi, n_ports);
	if (!host) {
		rc = -ENOMEM;
		goto err0;
	}

	host->private_data = hpriv;

	if (!(hpriv->cap & HOST_CAP_SSS) || ahci_ignore_sss)
		host->flags |= ATA_HOST_PARALLEL_SCAN;

	for (i = 0; i < host->n_ports; i++) {
		struct ata_port *ap = host->ports[i];

		ata_port_desc(ap, "mmio %pR", mem);
		ata_port_desc(ap, "port 0x%x", 0x100 + ap->port_no * 0x80);

		/* set enclosure management message type */
		if (ap->flags & ATA_FLAG_EM)
			ap->em_message_type = hpriv->em_msg_type;

		/* disabled/not-implemented port */
		if (!(hpriv->port_map & (1 << i)))
			ap->ops = &ata_dummy_port_ops;
	}

	rc = ahci_reset_controller(host);
	if (rc)
		goto err0;

	ahci_init_controller(host);
	ahci_print_info(host, "platform");

	rc = ahci_host_activate(host, &ahci_highbank_platform_sht);
	if (rc)
		goto err0;

	return 0;
err0:
	return rc;
}

#ifdef CONFIG_PM_SLEEP
static int ahci_highbank_suspend(struct device *dev)
{
	struct ata_host *host = dev_get_drvdata(dev);
	struct ahci_host_priv *hpriv = host->private_data;
	void __iomem *mmio = hpriv->mmio;
	u32 ctl;
	int rc;

	if (hpriv->flags & AHCI_HFLAG_NO_SUSPEND) {
		dev_err(dev, "firmware update required for suspend/resume\n");
		return -EIO;
	}

	/*
	 * AHCI spec rev1.1 section 8.3.3:
	 * Software must disable interrupts prior to requesting a
	 * transition of the HBA to D3 state.
	 */
	ctl = readl(mmio + HOST_CTL);
	ctl &= ~HOST_IRQ_EN;
	writel(ctl, mmio + HOST_CTL);
	readl(mmio + HOST_CTL); /* flush */

	rc = ata_host_suspend(host, PMSG_SUSPEND);
	if (rc)
		return rc;

	return 0;
}

static int ahci_highbank_resume(struct device *dev)
{
	struct ata_host *host = dev_get_drvdata(dev);
	int rc;

	if (dev->power.power_state.event == PM_EVENT_SUSPEND) {
		rc = ahci_reset_controller(host);
		if (rc)
			return rc;

		ahci_init_controller(host);
	}

	ata_host_resume(host);

	return 0;
}
#endif

static SIMPLE_DEV_PM_OPS(ahci_highbank_pm_ops,
		  ahci_highbank_suspend, ahci_highbank_resume);

static struct platform_driver ahci_highbank_driver = {
	.remove = ata_platform_remove_one,
        .driver = {
                .name = "highbank-ahci",
                .of_match_table = ahci_of_match,
                .pm = &ahci_highbank_pm_ops,
        },
	.probe = ahci_highbank_probe,
};

module_platform_driver(ahci_highbank_driver);

MODULE_DESCRIPTION("Calxeda Highbank AHCI SATA platform driver");
MODULE_AUTHOR("Mark Langsdorf <mark.langsdorf@calxeda.com>");
MODULE_LICENSE("GPL");
MODULE_ALIAS("sata:highbank");
Commit	Line	Data
8996b89d ML	1	/*
	2	* Calxeda Highbank AHCI SATA platform driver
	3	* Copyright 2012 Calxeda, Inc.
	4	*
	5	* based on the AHCI SATA platform driver by Jeff Garzik and Anton Vorontsov
	6	*
	7	* This program is free software; you can redistribute it and/or modify it
	8	* under the terms and conditions of the GNU General Public License,
	9	* version 2, as published by the Free Software Foundation.
	10	*
	11	* This program is distributed in the hope it will be useful, but WITHOUT
	12	* ANY WARRANTY; without even the implied warranty of MERCHANTABILITY or
	13	* FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public License for
	14	* more details.
	15	*
	16	* You should have received a copy of the GNU General Public License along with
	17	* this program. If not, see <http://www.gnu.org/licenses/>.
	18	*/
	19	#include <linux/kernel.h>
	20	#include <linux/gfp.h>
	21	#include <linux/module.h>
8996b89d ML	22	#include <linux/types.h>
	23	#include <linux/err.h>
	24	#include <linux/io.h>
	25	#include <linux/spinlock.h>
	26	#include <linux/device.h>
	27	#include <linux/of_device.h>
	28	#include <linux/of_address.h>
	29	#include <linux/platform_device.h>
	30	#include <linux/libata.h>
8996b89d ML	31	#include <linux/interrupt.h>
	32	#include <linux/delay.h>
	33	#include <linux/export.h>
83a7faac	34	#include <linux/gpio/consumer.h>
d50b110f	35
8996b89d ML	36	#include "ahci.h"
	37
	38	#define CPHY_MAP(dev, addr) ((((dev) & 0x1f) << 7) \| (((addr) >> 9) & 0x7f))
	39	#define CPHY_ADDR(addr) (((addr) & 0x1ff) << 2)
	40	#define SERDES_CR_CTL 0x80a0
	41	#define SERDES_CR_ADDR 0x80a1
	42	#define SERDES_CR_DATA 0x80a2
	43	#define CR_BUSY 0x0001
	44	#define CR_START 0x0001
	45	#define CR_WR_RDN 0x0002
b2e4c7b9	46	#define CPHY_TX_INPUT_STS 0x2001
8996b89d	47	#define CPHY_RX_INPUT_STS 0x2002
b2e4c7b9 ML	48	#define CPHY_SATA_TX_OVERRIDE 0x8000
	49	#define CPHY_SATA_RX_OVERRIDE 0x4000
	50	#define CPHY_TX_OVERRIDE 0x2004
	51	#define CPHY_RX_OVERRIDE 0x2005
8996b89d ML	52	#define SPHY_LANE 0x100
	53	#define SPHY_HALF_RATE 0x0001
	54	#define CPHY_SATA_DPLL_MODE 0x0700
	55	#define CPHY_SATA_DPLL_SHIFT 8
	56	#define CPHY_SATA_DPLL_RESET (1 << 11)
b2e4c7b9 ML	57	#define CPHY_SATA_TX_ATTEN 0x1c00
b2e4c7b9 ML	58	#define CPHY_SATA_TX_ATTEN_SHIFT 10
8996b89d ML	59	#define CPHY_PHY_COUNT 6
	60	#define CPHY_LANE_COUNT 4
	61	#define CPHY_PORT_COUNT (CPHY_PHY_COUNT * CPHY_LANE_COUNT)
	62
	63	static DEFINE_SPINLOCK(cphy_lock);
	64	/* Each of the 6 phys can have up to 4 sata ports attached to i. Map 0-based
	65	* sata ports to their phys and then to their lanes within the phys
	66	*/
	67	struct phy_lane_info {
	68	void __iomem *phy_base;
	69	u8 lane_mapping;
	70	u8 phy_devs;
b2e4c7b9	71	u8 tx_atten;
8996b89d ML	72	};
	73	static struct phy_lane_info port_data[CPHY_PORT_COUNT];
	74
d50b110f ML	75	static DEFINE_SPINLOCK(sgpio_lock);
	76	#define SCLOCK 0
	77	#define SLOAD 1
	78	#define SDATA 2
	79	#define SGPIO_PINS 3
	80	#define SGPIO_PORTS 8
	81
d50b110f ML	82	struct ecx_plat_data {
d50b110f ML	83	u32 n_ports;
2b79c56f ML	84	/* number of extra clocks that the SGPIO PIC controller expects */
	85	u32 pre_clocks;
	86	u32 post_clocks;
83a7faac	87	struct gpio_desc *sgpio_gpiod[SGPIO_PINS];
d50b110f ML	88	u32 sgpio_pattern;
	89	u32 port_to_sgpio[SGPIO_PORTS];
	90	};
	91
	92	#define SGPIO_SIGNALS 3
	93	#define ECX_ACTIVITY_BITS 0x300000
8c427f06	94	#define ECX_ACTIVITY_SHIFT 0
d50b110f ML	95	#define ECX_LOCATE_BITS 0x80000
	96	#define ECX_LOCATE_SHIFT 1
	97	#define ECX_FAULT_BITS 0x400000
8c427f06	98	#define ECX_FAULT_SHIFT 2
d50b110f ML	99	static inline int sgpio_bit_shift(struct ecx_plat_data *pdata, u32 port,
	100	u32 shift)
	101	{
	102	return 1 << (3 * pdata->port_to_sgpio[port] + shift);
	103	}
	104
	105	static void ecx_parse_sgpio(struct ecx_plat_data *pdata, u32 port, u32 state)
	106	{
	107	if (state & ECX_ACTIVITY_BITS)
	108	pdata->sgpio_pattern \|= sgpio_bit_shift(pdata, port,
	109	ECX_ACTIVITY_SHIFT);
	110	else
	111	pdata->sgpio_pattern &= ~sgpio_bit_shift(pdata, port,
	112	ECX_ACTIVITY_SHIFT);
	113	if (state & ECX_LOCATE_BITS)
	114	pdata->sgpio_pattern \|= sgpio_bit_shift(pdata, port,
	115	ECX_LOCATE_SHIFT);
	116	else
	117	pdata->sgpio_pattern &= ~sgpio_bit_shift(pdata, port,
	118	ECX_LOCATE_SHIFT);
	119	if (state & ECX_FAULT_BITS)
	120	pdata->sgpio_pattern \|= sgpio_bit_shift(pdata, port,
	121	ECX_FAULT_SHIFT);
	122	else
	123	pdata->sgpio_pattern &= ~sgpio_bit_shift(pdata, port,
	124	ECX_FAULT_SHIFT);
	125	}
	126
	127	/*
	128	* Tell the LED controller that the signal has changed by raising the clock
	129	* line for 50 uS and then lowering it for 50 uS.
	130	*/
	131	static void ecx_led_cycle_clock(struct ecx_plat_data *pdata)
	132	{
83a7faac	133	gpiod_set_value(pdata->sgpio_gpiod[SCLOCK], 1);
d50b110f	134	udelay(50);
83a7faac	135	gpiod_set_value(pdata->sgpio_gpiod[SCLOCK], 0);
d50b110f ML	136	udelay(50);
	137	}
	138
	139	static ssize_t ecx_transmit_led_message(struct ata_port *ap, u32 state,
	140	ssize_t size)
	141	{
	142	struct ahci_host_priv *hpriv = ap->host->private_data;
a498e316	143	struct ecx_plat_data *pdata = hpriv->plat_data;
d50b110f ML	144	struct ahci_port_priv *pp = ap->private_data;
	145	unsigned long flags;
	146	int pmp, i;
	147	struct ahci_em_priv *emp;
	148	u32 sgpio_out;
	149
	150	/* get the slot number from the message */
	151	pmp = (state & EM_MSG_LED_PMP_SLOT) >> 8;
	152	if (pmp < EM_MAX_SLOTS)
	153	emp = &pp->em_priv[pmp];
	154	else
	155	return -EINVAL;
	156
	157	if (!(hpriv->em_msg_type & EM_MSG_TYPE_LED))
	158	return size;
	159
	160	spin_lock_irqsave(&sgpio_lock, flags);
	161	ecx_parse_sgpio(pdata, ap->port_no, state);
	162	sgpio_out = pdata->sgpio_pattern;
2b79c56f ML	163	for (i = 0; i < pdata->pre_clocks; i++)
	164	ecx_led_cycle_clock(pdata);
	165
83a7faac	166	gpiod_set_value(pdata->sgpio_gpiod[SLOAD], 1);
d50b110f	167	ecx_led_cycle_clock(pdata);
83a7faac	168	gpiod_set_value(pdata->sgpio_gpiod[SLOAD], 0);
d50b110f ML	169	/*
	170	* bit-bang out the SGPIO pattern, by consuming a bit and then
	171	* clocking it out.
	172	*/
	173	for (i = 0; i < (SGPIO_SIGNALS * pdata->n_ports); i++) {
83a7faac	174	gpiod_set_value(pdata->sgpio_gpiod[SDATA], sgpio_out & 1);
d50b110f ML	175	sgpio_out >>= 1;
	176	ecx_led_cycle_clock(pdata);
	177	}
2b79c56f ML	178	for (i = 0; i < pdata->post_clocks; i++)
2b79c56f ML	179	ecx_led_cycle_clock(pdata);
d50b110f ML	180
	181	/* save off new led state for port/slot */
	182	emp->led_state = state;
	183
	184	spin_unlock_irqrestore(&sgpio_lock, flags);
	185	return size;
	186	}
	187
	188	static void highbank_set_em_messages(struct device *dev,
	189	struct ahci_host_priv *hpriv,
	190	struct ata_port_info *pi)
	191	{
	192	struct device_node *np = dev->of_node;
	193	struct ecx_plat_data *pdata = hpriv->plat_data;
	194	int i;
d50b110f ML	195
d50b110f ML	196	for (i = 0; i < SGPIO_PINS; i++) {
83a7faac LW	197	struct gpio_desc *gpiod;
	198
	199	gpiod = devm_gpiod_get_index(dev, "calxeda,sgpio", i,
	200	GPIOD_OUT_HIGH);
	201	if (IS_ERR(gpiod)) {
	202	dev_err(dev, "failed to get GPIO %d\n", i);
	203	continue;
d50b110f	204	}
83a7faac LW	205	gpiod_set_consumer_name(gpiod, "CX SGPIO");
	206
	207	pdata->sgpio_gpiod[i] = gpiod;
d50b110f ML	208	}
	209	of_property_read_u32_array(np, "calxeda,led-order",
	210	pdata->port_to_sgpio,
	211	pdata->n_ports);
2b79c56f ML	212	if (of_property_read_u32(np, "calxeda,pre-clocks", &pdata->pre_clocks))
	213	pdata->pre_clocks = 0;
	214	if (of_property_read_u32(np, "calxeda,post-clocks",
	215	&pdata->post_clocks))
	216	pdata->post_clocks = 0;
d50b110f ML	217
	218	/* store em_loc */
	219	hpriv->em_loc = 0;
	220	hpriv->em_buf_sz = 4;
	221	hpriv->em_msg_type = EM_MSG_TYPE_LED;
	222	pi->flags \|= ATA_FLAG_EM \| ATA_FLAG_SW_ACTIVITY;
	223	}
	224
8996b89d ML	225	static u32 __combo_phy_reg_read(u8 sata_port, u32 addr)
	226	{
	227	u32 data;
	228	u8 dev = port_data[sata_port].phy_devs;
	229	spin_lock(&cphy_lock);
	230	writel(CPHY_MAP(dev, addr), port_data[sata_port].phy_base + 0x800);
	231	data = readl(port_data[sata_port].phy_base + CPHY_ADDR(addr));
	232	spin_unlock(&cphy_lock);
	233	return data;
	234	}
	235
	236	static void __combo_phy_reg_write(u8 sata_port, u32 addr, u32 data)
	237	{
	238	u8 dev = port_data[sata_port].phy_devs;
	239	spin_lock(&cphy_lock);
	240	writel(CPHY_MAP(dev, addr), port_data[sata_port].phy_base + 0x800);
	241	writel(data, port_data[sata_port].phy_base + CPHY_ADDR(addr));
	242	spin_unlock(&cphy_lock);
	243	}
	244
	245	static void combo_phy_wait_for_ready(u8 sata_port)
	246	{
	247	while (__combo_phy_reg_read(sata_port, SERDES_CR_CTL) & CR_BUSY)
	248	udelay(5);
	249	}
	250
	251	static u32 combo_phy_read(u8 sata_port, u32 addr)
	252	{
	253	combo_phy_wait_for_ready(sata_port);
	254	__combo_phy_reg_write(sata_port, SERDES_CR_ADDR, addr);
	255	__combo_phy_reg_write(sata_port, SERDES_CR_CTL, CR_START);
	256	combo_phy_wait_for_ready(sata_port);
	257	return __combo_phy_reg_read(sata_port, SERDES_CR_DATA);
	258	}
	259
	260	static void combo_phy_write(u8 sata_port, u32 addr, u32 data)
	261	{
	262	combo_phy_wait_for_ready(sata_port);
	263	__combo_phy_reg_write(sata_port, SERDES_CR_ADDR, addr);
	264	__combo_phy_reg_write(sata_port, SERDES_CR_DATA, data);
	265	__combo_phy_reg_write(sata_port, SERDES_CR_CTL, CR_WR_RDN \| CR_START);
	266	}
	267
	268	static void highbank_cphy_disable_overrides(u8 sata_port)
	269	{
	270	u8 lane = port_data[sata_port].lane_mapping;
	271	u32 tmp;
	272	if (unlikely(port_data[sata_port].phy_base == NULL))
	273	return;
	274	tmp = combo_phy_read(sata_port, CPHY_RX_INPUT_STS + lane * SPHY_LANE);
b2e4c7b9 ML	275	tmp &= ~CPHY_SATA_RX_OVERRIDE;
	276	combo_phy_write(sata_port, CPHY_RX_OVERRIDE + lane * SPHY_LANE, tmp);
	277	}
	278
	279	static void cphy_override_tx_attenuation(u8 sata_port, u32 val)
	280	{
	281	u8 lane = port_data[sata_port].lane_mapping;
	282	u32 tmp;
	283
	284	if (val & 0x8)
	285	return;
	286
	287	tmp = combo_phy_read(sata_port, CPHY_TX_INPUT_STS + lane * SPHY_LANE);
	288	tmp &= ~CPHY_SATA_TX_OVERRIDE;
	289	combo_phy_write(sata_port, CPHY_TX_OVERRIDE + lane * SPHY_LANE, tmp);
	290
	291	tmp \|= CPHY_SATA_TX_OVERRIDE;
	292	combo_phy_write(sata_port, CPHY_TX_OVERRIDE + lane * SPHY_LANE, tmp);
	293
	294	tmp \|= (val << CPHY_SATA_TX_ATTEN_SHIFT) & CPHY_SATA_TX_ATTEN;
	295	combo_phy_write(sata_port, CPHY_TX_OVERRIDE + lane * SPHY_LANE, tmp);
8996b89d ML	296	}
	297
	298	static void cphy_override_rx_mode(u8 sata_port, u32 val)
	299	{
	300	u8 lane = port_data[sata_port].lane_mapping;
	301	u32 tmp;
	302	tmp = combo_phy_read(sata_port, CPHY_RX_INPUT_STS + lane * SPHY_LANE);
b2e4c7b9 ML	303	tmp &= ~CPHY_SATA_RX_OVERRIDE;
b2e4c7b9 ML	304	combo_phy_write(sata_port, CPHY_RX_OVERRIDE + lane * SPHY_LANE, tmp);
8996b89d	305
b2e4c7b9 ML	306	tmp \|= CPHY_SATA_RX_OVERRIDE;
b2e4c7b9 ML	307	combo_phy_write(sata_port, CPHY_RX_OVERRIDE + lane * SPHY_LANE, tmp);
8996b89d ML	308
	309	tmp &= ~CPHY_SATA_DPLL_MODE;
	310	tmp \|= val << CPHY_SATA_DPLL_SHIFT;
b2e4c7b9	311	combo_phy_write(sata_port, CPHY_RX_OVERRIDE + lane * SPHY_LANE, tmp);
8996b89d ML	312
8996b89d ML	313	tmp \|= CPHY_SATA_DPLL_RESET;
b2e4c7b9	314	combo_phy_write(sata_port, CPHY_RX_OVERRIDE + lane * SPHY_LANE, tmp);
8996b89d ML	315
8996b89d ML	316	tmp &= ~CPHY_SATA_DPLL_RESET;
b2e4c7b9	317	combo_phy_write(sata_port, CPHY_RX_OVERRIDE + lane * SPHY_LANE, tmp);
8996b89d ML	318
	319	msleep(15);
	320	}
	321
	322	static void highbank_cphy_override_lane(u8 sata_port)
	323	{
	324	u8 lane = port_data[sata_port].lane_mapping;
	325	u32 tmp, k = 0;
	326
	327	if (unlikely(port_data[sata_port].phy_base == NULL))
	328	return;
	329	do {
	330	tmp = combo_phy_read(sata_port, CPHY_RX_INPUT_STS +
	331	lane * SPHY_LANE);
	332	} while ((tmp & SPHY_HALF_RATE) && (k++ < 1000));
	333	cphy_override_rx_mode(sata_port, 3);
b2e4c7b9	334	cphy_override_tx_attenuation(sata_port, port_data[sata_port].tx_atten);
8996b89d ML	335	}
	336
	337	static int highbank_initialize_phys(struct device dev, void __iomem addr)
	338	{
	339	struct device_node *sata_node = dev->of_node;
b2e4c7b9	340	int phy_count = 0, phy, port = 0, i;
225f1eae DC	341	void __iomem *cphy_base[CPHY_PHY_COUNT] = {};
	342	struct device_node *phy_nodes[CPHY_PHY_COUNT] = {};
	343	u32 tx_atten[CPHY_PORT_COUNT] = {};
b2e4c7b9	344
8996b89d	345	memset(port_data, 0, sizeof(struct phy_lane_info) * CPHY_PORT_COUNT);
8996b89d ML	346
	347	do {
	348	u32 tmp;
	349	struct of_phandle_args phy_data;
	350	if (of_parse_phandle_with_args(sata_node,
	351	"calxeda,port-phys", "#phy-cells",
	352	port, &phy_data))
	353	break;
	354	for (phy = 0; phy < phy_count; phy++) {
	355	if (phy_nodes[phy] == phy_data.np)
	356	break;
	357	}
	358	if (phy_nodes[phy] == NULL) {
	359	phy_nodes[phy] = phy_data.np;
	360	cphy_base[phy] = of_iomap(phy_nodes[phy], 0);
	361	if (cphy_base[phy] == NULL) {
	362	return 0;
	363	}
	364	phy_count += 1;
	365	}
	366	port_data[port].lane_mapping = phy_data.args[0];
	367	of_property_read_u32(phy_nodes[phy], "phydev", &tmp);
	368	port_data[port].phy_devs = tmp;
	369	port_data[port].phy_base = cphy_base[phy];
	370	of_node_put(phy_data.np);
	371	port += 1;
	372	} while (port < CPHY_PORT_COUNT);
b2e4c7b9 ML	373	of_property_read_u32_array(sata_node, "calxeda,tx-atten",
	374	tx_atten, port);
	375	for (i = 0; i < port; i++)
	376	port_data[i].tx_atten = (u8) tx_atten[i];
8996b89d ML	377	return 0;
	378	}
	379
ddfef5de ML	380	/*
	381	* The Calxeda SATA phy intermittently fails to bring up a link with Gen3
	382	* Retrying the phy hard reset can work around the issue, but the drive
	383	* may fail again. In less than 150 out of 15000 test runs, it took more
	384	* than 10 tries for the link to be established (but never more than 35).
	385	* Triple the maximum observed retry count to provide plenty of margin for
	386	* rare events and to guarantee that the link is established.
	387	*
	388	* Also, the default 2 second time-out on a failed drive is too long in
	389	* this situation. The uboot implementation of the same driver function
	390	* uses a much shorter time-out period and never experiences a time out
	391	* issue. Reducing the time-out to 500ms improves the responsiveness.
	392	* The other timing constants were kept the same as the stock AHCI driver.
	393	* This change was also tested 15000 times on 24 drives and none of them
	394	* experienced a time out.
	395	*/
8996b89d ML	396	static int ahci_highbank_hardreset(struct ata_link link, unsigned int class,
	397	unsigned long deadline)
	398	{
ddfef5de	399	static const unsigned long timing[] = { 5, 100, 500};
8996b89d ML	400	struct ata_port *ap = link->ap;
8996b89d ML	401	struct ahci_port_priv *pp = ap->private_data;
039ece38	402	struct ahci_host_priv *hpriv = ap->host->private_data;
8996b89d ML	403	u8 *d2h_fis = pp->rx_fis + RX_FIS_D2H_REG;
	404	struct ata_taskfile tf;
	405	bool online;
	406	u32 sstatus;
	407	int rc;
ddfef5de	408	int retry = 100;
8996b89d	409
fa89f53b	410	hpriv->stop_engine(ap);
8996b89d ML	411
	412	/* clear D2H reception area to properly wait for D2H FIS */
	413	ata_tf_init(link->device, &tf);
121650a5	414	tf.command = ATA_BUSY;
8996b89d ML	415	ata_tf_to_fis(&tf, 0, 0, d2h_fis);
	416
	417	do {
	418	highbank_cphy_disable_overrides(link->ap->port_no);
	419	rc = sata_link_hardreset(link, timing, deadline, &online, NULL);
	420	highbank_cphy_override_lane(link->ap->port_no);
	421
	422	/* If the status is 1, we are connected, but the link did not
	423	* come up. So retry resetting the link again.
	424	*/
	425	if (sata_scr_read(link, SCR_STATUS, &sstatus))
	426	break;
	427	if (!(sstatus & 0x3))
	428	break;
	429	} while (!online && retry--);
	430
039ece38	431	hpriv->start_engine(ap);
8996b89d ML	432
	433	if (online)
	434	*class = ahci_dev_classify(ap);
	435
	436	return rc;
	437	}
	438
	439	static struct ata_port_operations ahci_highbank_ops = {
	440	.inherits = &ahci_ops,
	441	.hardreset = ahci_highbank_hardreset,
d50b110f	442	.transmit_led_message = ecx_transmit_led_message,
8996b89d ML	443	};
	444
	445	static const struct ata_port_info ahci_highbank_port_info = {
	446	.flags = AHCI_FLAG_COMMON,
	447	.pio_mask = ATA_PIO4,
	448	.udma_mask = ATA_UDMA6,
	449	.port_ops = &ahci_highbank_ops,
	450	};
	451
	452	static struct scsi_host_template ahci_highbank_platform_sht = {
2cc1144a	453	AHCI_SHT("sata_highbank"),
8996b89d ML	454	};
	455
	456	static const struct of_device_id ahci_of_match[] = {
	457	{ .compatible = "calxeda,hb-ahci" },
	458	{},
	459	};
	460	MODULE_DEVICE_TABLE(of, ahci_of_match);
	461
0ec24914	462	static int ahci_highbank_probe(struct platform_device *pdev)
8996b89d ML	463	{
	464	struct device *dev = &pdev->dev;
	465	struct ahci_host_priv *hpriv;
d50b110f	466	struct ecx_plat_data *pdata;
8996b89d ML	467	struct ata_host *host;
	468	struct resource *mem;
	469	int irq;
8996b89d ML	470	int i;
8996b89d ML	471	int rc;
d50b110f	472	u32 n_ports;
8996b89d ML	473	struct ata_port_info pi = ahci_highbank_port_info;
	474	const struct ata_port_info *ppi[] = { &pi, NULL };
	475
	476	mem = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	477	if (!mem) {
	478	dev_err(dev, "no mmio space\n");
	479	return -EINVAL;
	480	}
	481
	482	irq = platform_get_irq(pdev, 0);
	483	if (irq <= 0) {
	484	dev_err(dev, "no irq\n");
	485	return -EINVAL;
	486	}
	487
	488	hpriv = devm_kzalloc(dev, sizeof(*hpriv), GFP_KERNEL);
	489	if (!hpriv) {
	490	dev_err(dev, "can't alloc ahci_host_priv\n");
	491	return -ENOMEM;
	492	}
d50b110f ML	493	pdata = devm_kzalloc(dev, sizeof(*pdata), GFP_KERNEL);
	494	if (!pdata) {
	495	dev_err(dev, "can't alloc ecx_plat_data\n");
	496	return -ENOMEM;
	497	}
8996b89d	498
21bfd1aa	499	hpriv->irq = irq;
8996b89d ML	500	hpriv->flags \|= (unsigned long)pi.private_data;
	501
	502	hpriv->mmio = devm_ioremap(dev, mem->start, resource_size(mem));
	503	if (!hpriv->mmio) {
	504	dev_err(dev, "can't map %pR\n", mem);
	505	return -ENOMEM;
	506	}
	507
	508	rc = highbank_initialize_phys(dev, hpriv->mmio);
	509	if (rc)
	510	return rc;
	511
	512
725c7b57	513	ahci_save_initial_config(dev, hpriv);
8996b89d ML	514
	515	/* prepare host */
	516	if (hpriv->cap & HOST_CAP_NCQ)
	517	pi.flags \|= ATA_FLAG_NCQ;
	518
	519	if (hpriv->cap & HOST_CAP_PMP)
	520	pi.flags \|= ATA_FLAG_PMP;
	521
404eafe1 RH	522	if (hpriv->cap & HOST_CAP_64)
	523	dma_set_coherent_mask(dev, DMA_BIT_MASK(64));
	524
8996b89d ML	525	/* CAP.NP sometimes indicate the index of the last enabled
	526	* port, at other times, that of the last possible port, so
	527	* determining the maximum port number requires looking at
	528	* both CAP.NP and port_map.
	529	*/
	530	n_ports = max(ahci_nr_ports(hpriv->cap), fls(hpriv->port_map));
	531
d50b110f ML	532	pdata->n_ports = n_ports;
	533	hpriv->plat_data = pdata;
	534	highbank_set_em_messages(dev, hpriv, &pi);
	535
8996b89d ML	536	host = ata_host_alloc_pinfo(dev, ppi, n_ports);
	537	if (!host) {
	538	rc = -ENOMEM;
	539	goto err0;
	540	}
	541
	542	host->private_data = hpriv;
	543
	544	if (!(hpriv->cap & HOST_CAP_SSS) \|\| ahci_ignore_sss)
	545	host->flags \|= ATA_HOST_PARALLEL_SCAN;
	546
8996b89d ML	547	for (i = 0; i < host->n_ports; i++) {
	548	struct ata_port *ap = host->ports[i];
	549
	550	ata_port_desc(ap, "mmio %pR", mem);
	551	ata_port_desc(ap, "port 0x%x", 0x100 + ap->port_no * 0x80);
	552
	553	/* set enclosure management message type */
	554	if (ap->flags & ATA_FLAG_EM)
	555	ap->em_message_type = hpriv->em_msg_type;
	556
	557	/* disabled/not-implemented port */
	558	if (!(hpriv->port_map & (1 << i)))
	559	ap->ops = &ata_dummy_port_ops;
	560	}
	561
	562	rc = ahci_reset_controller(host);
	563	if (rc)
	564	goto err0;
	565
	566	ahci_init_controller(host);
	567	ahci_print_info(host, "platform");
	568
21bfd1aa	569	rc = ahci_host_activate(host, &ahci_highbank_platform_sht);
8996b89d ML	570	if (rc)
	571	goto err0;
	572
	573	return 0;
	574	err0:
	575	return rc;
	576	}
	577
29448ec1	578	#ifdef CONFIG_PM_SLEEP
8996b89d ML	579	static int ahci_highbank_suspend(struct device *dev)
	580	{
	581	struct ata_host *host = dev_get_drvdata(dev);
	582	struct ahci_host_priv *hpriv = host->private_data;
	583	void __iomem *mmio = hpriv->mmio;
	584	u32 ctl;
	585	int rc;
	586
	587	if (hpriv->flags & AHCI_HFLAG_NO_SUSPEND) {
	588	dev_err(dev, "firmware update required for suspend/resume\n");
	589	return -EIO;
	590	}
	591
	592	/*
	593	* AHCI spec rev1.1 section 8.3.3:
	594	* Software must disable interrupts prior to requesting a
	595	* transition of the HBA to D3 state.
	596	*/
	597	ctl = readl(mmio + HOST_CTL);
	598	ctl &= ~HOST_IRQ_EN;
	599	writel(ctl, mmio + HOST_CTL);
	600	readl(mmio + HOST_CTL); /* flush */
	601
	602	rc = ata_host_suspend(host, PMSG_SUSPEND);
	603	if (rc)
	604	return rc;
	605
	606	return 0;
	607	}
	608
	609	static int ahci_highbank_resume(struct device *dev)
	610	{
	611	struct ata_host *host = dev_get_drvdata(dev);
	612	int rc;
	613
	614	if (dev->power.power_state.event == PM_EVENT_SUSPEND) {
	615	rc = ahci_reset_controller(host);
	616	if (rc)
	617	return rc;
	618
	619	ahci_init_controller(host);
	620	}
	621
	622	ata_host_resume(host);
	623
	624	return 0;
	625	}
	626	#endif
	627
b1a72d60	628	static SIMPLE_DEV_PM_OPS(ahci_highbank_pm_ops,
8996b89d ML	629	ahci_highbank_suspend, ahci_highbank_resume);
	630
	631	static struct platform_driver ahci_highbank_driver = {
e2ec1817	632	.remove = ata_platform_remove_one,
8996b89d ML	633	.driver = {
8996b89d ML	634	.name = "highbank-ahci",
8996b89d ML	635	.of_match_table = ahci_of_match,
	636	.pm = &ahci_highbank_pm_ops,
	637	},
	638	.probe = ahci_highbank_probe,
	639	};
	640
	641	module_platform_driver(ahci_highbank_driver);
	642
	643	MODULE_DESCRIPTION("Calxeda Highbank AHCI SATA platform driver");
	644	MODULE_AUTHOR("Mark Langsdorf <mark.langsdorf@calxeda.com>");
	645	MODULE_LICENSE("GPL");
	646	MODULE_ALIAS("sata:highbank");