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2874c5fd | 1 | // SPDX-License-Identifier: GPL-2.0-or-later |
faf0b2e5 LY |
2 | /* |
3 | * drivers/ata/sata_fsl.c | |
4 | * | |
5 | * Freescale 3.0Gbps SATA device driver | |
6 | * | |
7 | * Author: Ashish Kalra <ashish.kalra@freescale.com> | |
8 | * Li Yang <leoli@freescale.com> | |
9 | * | |
6b4b8fc8 | 10 | * Copyright (c) 2006-2007, 2011-2012 Freescale Semiconductor, Inc. |
faf0b2e5 LY |
11 | */ |
12 | ||
13 | #include <linux/kernel.h> | |
14 | #include <linux/module.h> | |
15 | #include <linux/platform_device.h> | |
5a0e3ad6 | 16 | #include <linux/slab.h> |
faf0b2e5 LY |
17 | |
18 | #include <scsi/scsi_host.h> | |
19 | #include <scsi/scsi_cmnd.h> | |
20 | #include <linux/libata.h> | |
21 | #include <asm/io.h> | |
5af50730 RH |
22 | #include <linux/of_address.h> |
23 | #include <linux/of_irq.h> | |
faf0b2e5 LY |
24 | #include <linux/of_platform.h> |
25 | ||
6b4b8fc8 QL |
26 | static unsigned int intr_coalescing_count; |
27 | module_param(intr_coalescing_count, int, S_IRUGO); | |
28 | MODULE_PARM_DESC(intr_coalescing_count, | |
29 | "INT coalescing count threshold (1..31)"); | |
30 | ||
31 | static unsigned int intr_coalescing_ticks; | |
32 | module_param(intr_coalescing_ticks, int, S_IRUGO); | |
33 | MODULE_PARM_DESC(intr_coalescing_ticks, | |
34 | "INT coalescing timer threshold in AHB ticks"); | |
faf0b2e5 LY |
35 | /* Controller information */ |
36 | enum { | |
37 | SATA_FSL_QUEUE_DEPTH = 16, | |
38 | SATA_FSL_MAX_PRD = 63, | |
39 | SATA_FSL_MAX_PRD_USABLE = SATA_FSL_MAX_PRD - 1, | |
40 | SATA_FSL_MAX_PRD_DIRECT = 16, /* Direct PRDT entries */ | |
41 | ||
9cbe056f | 42 | SATA_FSL_HOST_FLAGS = (ATA_FLAG_SATA | ATA_FLAG_PIO_DMA | |
4f2568f5 AW |
43 | ATA_FLAG_PMP | ATA_FLAG_NCQ | |
44 | ATA_FLAG_AN | ATA_FLAG_NO_LOG_PAGE), | |
faf0b2e5 LY |
45 | |
46 | SATA_FSL_MAX_CMDS = SATA_FSL_QUEUE_DEPTH, | |
47 | SATA_FSL_CMD_HDR_SIZE = 16, /* 4 DWORDS */ | |
48 | SATA_FSL_CMD_SLOT_SIZE = (SATA_FSL_MAX_CMDS * SATA_FSL_CMD_HDR_SIZE), | |
49 | ||
50 | /* | |
51 | * SATA-FSL host controller supports a max. of (15+1) direct PRDEs, and | |
25985edc | 52 | * chained indirect PRDEs up to a max count of 63. |
af901ca1 | 53 | * We are allocating an array of 63 PRDEs contiguously, but PRDE#15 will |
faf0b2e5 | 54 | * be setup as an indirect descriptor, pointing to it's next |
af901ca1 | 55 | * (contiguous) PRDE. Though chained indirect PRDE arrays are |
faf0b2e5 LY |
56 | * supported,it will be more efficient to use a direct PRDT and |
57 | * a single chain/link to indirect PRDE array/PRDT. | |
58 | */ | |
59 | ||
60 | SATA_FSL_CMD_DESC_CFIS_SZ = 32, | |
61 | SATA_FSL_CMD_DESC_SFIS_SZ = 32, | |
62 | SATA_FSL_CMD_DESC_ACMD_SZ = 16, | |
63 | SATA_FSL_CMD_DESC_RSRVD = 16, | |
64 | ||
65 | SATA_FSL_CMD_DESC_SIZE = (SATA_FSL_CMD_DESC_CFIS_SZ + | |
66 | SATA_FSL_CMD_DESC_SFIS_SZ + | |
67 | SATA_FSL_CMD_DESC_ACMD_SZ + | |
68 | SATA_FSL_CMD_DESC_RSRVD + | |
69 | SATA_FSL_MAX_PRD * 16), | |
70 | ||
71 | SATA_FSL_CMD_DESC_OFFSET_TO_PRDT = | |
72 | (SATA_FSL_CMD_DESC_CFIS_SZ + | |
73 | SATA_FSL_CMD_DESC_SFIS_SZ + | |
74 | SATA_FSL_CMD_DESC_ACMD_SZ + | |
75 | SATA_FSL_CMD_DESC_RSRVD), | |
76 | ||
77 | SATA_FSL_CMD_DESC_AR_SZ = (SATA_FSL_CMD_DESC_SIZE * SATA_FSL_MAX_CMDS), | |
78 | SATA_FSL_PORT_PRIV_DMA_SZ = (SATA_FSL_CMD_SLOT_SIZE + | |
79 | SATA_FSL_CMD_DESC_AR_SZ), | |
80 | ||
81 | /* | |
82 | * MPC8315 has two SATA controllers, SATA1 & SATA2 | |
83 | * (one port per controller) | |
84 | * MPC837x has 2/4 controllers, one port per controller | |
85 | */ | |
86 | ||
87 | SATA_FSL_MAX_PORTS = 1, | |
88 | ||
89 | SATA_FSL_IRQ_FLAG = IRQF_SHARED, | |
90 | }; | |
91 | ||
6b4b8fc8 QL |
92 | /* |
93 | * Interrupt Coalescing Control Register bitdefs */ | |
94 | enum { | |
95 | ICC_MIN_INT_COUNT_THRESHOLD = 1, | |
96 | ICC_MAX_INT_COUNT_THRESHOLD = ((1 << 5) - 1), | |
97 | ICC_MIN_INT_TICKS_THRESHOLD = 0, | |
98 | ICC_MAX_INT_TICKS_THRESHOLD = ((1 << 19) - 1), | |
99 | ICC_SAFE_INT_TICKS = 1, | |
100 | }; | |
101 | ||
faf0b2e5 LY |
102 | /* |
103 | * Host Controller command register set - per port | |
104 | */ | |
105 | enum { | |
106 | CQ = 0, | |
107 | CA = 8, | |
108 | CC = 0x10, | |
109 | CE = 0x18, | |
110 | DE = 0x20, | |
111 | CHBA = 0x24, | |
112 | HSTATUS = 0x28, | |
113 | HCONTROL = 0x2C, | |
114 | CQPMP = 0x30, | |
115 | SIGNATURE = 0x34, | |
116 | ICC = 0x38, | |
117 | ||
118 | /* | |
119 | * Host Status Register (HStatus) bitdefs | |
120 | */ | |
121 | ONLINE = (1 << 31), | |
122 | GOING_OFFLINE = (1 << 30), | |
123 | BIST_ERR = (1 << 29), | |
100f586b | 124 | CLEAR_ERROR = (1 << 27), |
faf0b2e5 LY |
125 | |
126 | FATAL_ERR_HC_MASTER_ERR = (1 << 18), | |
127 | FATAL_ERR_PARITY_ERR_TX = (1 << 17), | |
128 | FATAL_ERR_PARITY_ERR_RX = (1 << 16), | |
129 | FATAL_ERR_DATA_UNDERRUN = (1 << 13), | |
130 | FATAL_ERR_DATA_OVERRUN = (1 << 12), | |
131 | FATAL_ERR_CRC_ERR_TX = (1 << 11), | |
132 | FATAL_ERR_CRC_ERR_RX = (1 << 10), | |
133 | FATAL_ERR_FIFO_OVRFL_TX = (1 << 9), | |
134 | FATAL_ERR_FIFO_OVRFL_RX = (1 << 8), | |
135 | ||
136 | FATAL_ERROR_DECODE = FATAL_ERR_HC_MASTER_ERR | | |
137 | FATAL_ERR_PARITY_ERR_TX | | |
138 | FATAL_ERR_PARITY_ERR_RX | | |
139 | FATAL_ERR_DATA_UNDERRUN | | |
140 | FATAL_ERR_DATA_OVERRUN | | |
141 | FATAL_ERR_CRC_ERR_TX | | |
142 | FATAL_ERR_CRC_ERR_RX | | |
143 | FATAL_ERR_FIFO_OVRFL_TX | FATAL_ERR_FIFO_OVRFL_RX, | |
144 | ||
100f586b | 145 | INT_ON_DATA_LENGTH_MISMATCH = (1 << 12), |
faf0b2e5 LY |
146 | INT_ON_FATAL_ERR = (1 << 5), |
147 | INT_ON_PHYRDY_CHG = (1 << 4), | |
148 | ||
149 | INT_ON_SIGNATURE_UPDATE = (1 << 3), | |
150 | INT_ON_SNOTIFY_UPDATE = (1 << 2), | |
151 | INT_ON_SINGL_DEVICE_ERR = (1 << 1), | |
152 | INT_ON_CMD_COMPLETE = 1, | |
153 | ||
fd6c29e3 | 154 | INT_ON_ERROR = INT_ON_FATAL_ERR | INT_ON_SNOTIFY_UPDATE | |
faf0b2e5 LY |
155 | INT_ON_PHYRDY_CHG | INT_ON_SINGL_DEVICE_ERR, |
156 | ||
157 | /* | |
158 | * Host Control Register (HControl) bitdefs | |
159 | */ | |
160 | HCONTROL_ONLINE_PHY_RST = (1 << 31), | |
161 | HCONTROL_FORCE_OFFLINE = (1 << 30), | |
93272b13 | 162 | HCONTROL_LEGACY = (1 << 28), |
faf0b2e5 LY |
163 | HCONTROL_PARITY_PROT_MOD = (1 << 14), |
164 | HCONTROL_DPATH_PARITY = (1 << 12), | |
165 | HCONTROL_SNOOP_ENABLE = (1 << 10), | |
166 | HCONTROL_PMP_ATTACHED = (1 << 9), | |
167 | HCONTROL_COPYOUT_STATFIS = (1 << 8), | |
168 | IE_ON_FATAL_ERR = (1 << 5), | |
169 | IE_ON_PHYRDY_CHG = (1 << 4), | |
170 | IE_ON_SIGNATURE_UPDATE = (1 << 3), | |
171 | IE_ON_SNOTIFY_UPDATE = (1 << 2), | |
172 | IE_ON_SINGL_DEVICE_ERR = (1 << 1), | |
173 | IE_ON_CMD_COMPLETE = 1, | |
174 | ||
175 | DEFAULT_PORT_IRQ_ENABLE_MASK = IE_ON_FATAL_ERR | IE_ON_PHYRDY_CHG | | |
fd6c29e3 | 176 | IE_ON_SIGNATURE_UPDATE | IE_ON_SNOTIFY_UPDATE | |
faf0b2e5 LY |
177 | IE_ON_SINGL_DEVICE_ERR | IE_ON_CMD_COMPLETE, |
178 | ||
179 | EXT_INDIRECT_SEG_PRD_FLAG = (1 << 31), | |
2f957fc9 X |
180 | DATA_SNOOP_ENABLE_V1 = (1 << 22), |
181 | DATA_SNOOP_ENABLE_V2 = (1 << 28), | |
faf0b2e5 LY |
182 | }; |
183 | ||
184 | /* | |
185 | * SATA Superset Registers | |
186 | */ | |
187 | enum { | |
188 | SSTATUS = 0, | |
189 | SERROR = 4, | |
190 | SCONTROL = 8, | |
191 | SNOTIFY = 0xC, | |
192 | }; | |
193 | ||
194 | /* | |
195 | * Control Status Register Set | |
196 | */ | |
197 | enum { | |
198 | TRANSCFG = 0, | |
199 | TRANSSTATUS = 4, | |
200 | LINKCFG = 8, | |
201 | LINKCFG1 = 0xC, | |
202 | LINKCFG2 = 0x10, | |
203 | LINKSTATUS = 0x14, | |
204 | LINKSTATUS1 = 0x18, | |
205 | PHYCTRLCFG = 0x1C, | |
206 | COMMANDSTAT = 0x20, | |
207 | }; | |
208 | ||
578ca87c PK |
209 | /* TRANSCFG (transport-layer) configuration control */ |
210 | enum { | |
211 | TRANSCFG_RX_WATER_MARK = (1 << 4), | |
212 | }; | |
213 | ||
faf0b2e5 LY |
214 | /* PHY (link-layer) configuration control */ |
215 | enum { | |
216 | PHY_BIST_ENABLE = 0x01, | |
217 | }; | |
218 | ||
219 | /* | |
220 | * Command Header Table entry, i.e, command slot | |
221 | * 4 Dwords per command slot, command header size == 64 Dwords. | |
222 | */ | |
223 | struct cmdhdr_tbl_entry { | |
224 | u32 cda; | |
225 | u32 prde_fis_len; | |
226 | u32 ttl; | |
227 | u32 desc_info; | |
228 | }; | |
229 | ||
230 | /* | |
231 | * Description information bitdefs | |
232 | */ | |
233 | enum { | |
d3587243 | 234 | CMD_DESC_RES = (1 << 11), |
faf0b2e5 LY |
235 | VENDOR_SPECIFIC_BIST = (1 << 10), |
236 | CMD_DESC_SNOOP_ENABLE = (1 << 9), | |
237 | FPDMA_QUEUED_CMD = (1 << 8), | |
238 | SRST_CMD = (1 << 7), | |
239 | BIST = (1 << 6), | |
240 | ATAPI_CMD = (1 << 5), | |
241 | }; | |
242 | ||
243 | /* | |
244 | * Command Descriptor | |
245 | */ | |
246 | struct command_desc { | |
247 | u8 cfis[8 * 4]; | |
248 | u8 sfis[8 * 4]; | |
23c72ffe KC |
249 | struct_group(cdb, |
250 | u8 acmd[4 * 4]; | |
251 | u8 fill[4 * 4]; | |
252 | ); | |
faf0b2e5 LY |
253 | u32 prdt[SATA_FSL_MAX_PRD_DIRECT * 4]; |
254 | u32 prdt_indirect[(SATA_FSL_MAX_PRD - SATA_FSL_MAX_PRD_DIRECT) * 4]; | |
255 | }; | |
256 | ||
257 | /* | |
258 | * Physical region table descriptor(PRD) | |
259 | */ | |
260 | ||
261 | struct prde { | |
262 | u32 dba; | |
263 | u8 fill[2 * 4]; | |
264 | u32 ddc_and_ext; | |
265 | }; | |
266 | ||
267 | /* | |
268 | * ata_port private data | |
269 | * This is our per-port instance data. | |
270 | */ | |
271 | struct sata_fsl_port_priv { | |
272 | struct cmdhdr_tbl_entry *cmdslot; | |
273 | dma_addr_t cmdslot_paddr; | |
274 | struct command_desc *cmdentry; | |
275 | dma_addr_t cmdentry_paddr; | |
faf0b2e5 LY |
276 | }; |
277 | ||
278 | /* | |
279 | * ata_port->host_set private data | |
280 | */ | |
281 | struct sata_fsl_host_priv { | |
282 | void __iomem *hcr_base; | |
283 | void __iomem *ssr_base; | |
284 | void __iomem *csr_base; | |
79b3edc9 | 285 | int irq; |
2f957fc9 | 286 | int data_snoop; |
6b4b8fc8 | 287 | struct device_attribute intr_coalescing; |
7551c40d | 288 | struct device_attribute rx_watermark; |
faf0b2e5 LY |
289 | }; |
290 | ||
6b4b8fc8 QL |
291 | static void fsl_sata_set_irq_coalescing(struct ata_host *host, |
292 | unsigned int count, unsigned int ticks) | |
293 | { | |
294 | struct sata_fsl_host_priv *host_priv = host->private_data; | |
295 | void __iomem *hcr_base = host_priv->hcr_base; | |
99bbdfa6 | 296 | unsigned long flags; |
6b4b8fc8 QL |
297 | |
298 | if (count > ICC_MAX_INT_COUNT_THRESHOLD) | |
299 | count = ICC_MAX_INT_COUNT_THRESHOLD; | |
300 | else if (count < ICC_MIN_INT_COUNT_THRESHOLD) | |
301 | count = ICC_MIN_INT_COUNT_THRESHOLD; | |
302 | ||
303 | if (ticks > ICC_MAX_INT_TICKS_THRESHOLD) | |
304 | ticks = ICC_MAX_INT_TICKS_THRESHOLD; | |
305 | else if ((ICC_MIN_INT_TICKS_THRESHOLD == ticks) && | |
306 | (count > ICC_MIN_INT_COUNT_THRESHOLD)) | |
307 | ticks = ICC_SAFE_INT_TICKS; | |
308 | ||
99bbdfa6 | 309 | spin_lock_irqsave(&host->lock, flags); |
6b4b8fc8 QL |
310 | iowrite32((count << 24 | ticks), hcr_base + ICC); |
311 | ||
312 | intr_coalescing_count = count; | |
313 | intr_coalescing_ticks = ticks; | |
99bbdfa6 | 314 | spin_unlock_irqrestore(&host->lock, flags); |
6b4b8fc8 | 315 | |
07f42258 | 316 | DPRINTK("interrupt coalescing, count = 0x%x, ticks = %x\n", |
6b4b8fc8 | 317 | intr_coalescing_count, intr_coalescing_ticks); |
c9efa492 | 318 | DPRINTK("ICC register status: (hcr base: %p) = 0x%x\n", |
6b4b8fc8 QL |
319 | hcr_base, ioread32(hcr_base + ICC)); |
320 | } | |
321 | ||
322 | static ssize_t fsl_sata_intr_coalescing_show(struct device *dev, | |
323 | struct device_attribute *attr, char *buf) | |
324 | { | |
ab0efc06 | 325 | return sysfs_emit(buf, "%d %d\n", |
6b4b8fc8 QL |
326 | intr_coalescing_count, intr_coalescing_ticks); |
327 | } | |
328 | ||
329 | static ssize_t fsl_sata_intr_coalescing_store(struct device *dev, | |
330 | struct device_attribute *attr, | |
331 | const char *buf, size_t count) | |
332 | { | |
333 | unsigned int coalescing_count, coalescing_ticks; | |
334 | ||
335 | if (sscanf(buf, "%d%d", | |
336 | &coalescing_count, | |
337 | &coalescing_ticks) != 2) { | |
338 | printk(KERN_ERR "fsl-sata: wrong parameter format.\n"); | |
339 | return -EINVAL; | |
340 | } | |
341 | ||
342 | fsl_sata_set_irq_coalescing(dev_get_drvdata(dev), | |
343 | coalescing_count, coalescing_ticks); | |
344 | ||
345 | return strlen(buf); | |
346 | } | |
347 | ||
7551c40d QL |
348 | static ssize_t fsl_sata_rx_watermark_show(struct device *dev, |
349 | struct device_attribute *attr, char *buf) | |
350 | { | |
351 | unsigned int rx_watermark; | |
352 | unsigned long flags; | |
353 | struct ata_host *host = dev_get_drvdata(dev); | |
354 | struct sata_fsl_host_priv *host_priv = host->private_data; | |
355 | void __iomem *csr_base = host_priv->csr_base; | |
356 | ||
357 | spin_lock_irqsave(&host->lock, flags); | |
358 | rx_watermark = ioread32(csr_base + TRANSCFG); | |
359 | rx_watermark &= 0x1f; | |
7551c40d | 360 | spin_unlock_irqrestore(&host->lock, flags); |
ab0efc06 DLM |
361 | |
362 | return sysfs_emit(buf, "%d\n", rx_watermark); | |
7551c40d QL |
363 | } |
364 | ||
365 | static ssize_t fsl_sata_rx_watermark_store(struct device *dev, | |
366 | struct device_attribute *attr, | |
367 | const char *buf, size_t count) | |
368 | { | |
369 | unsigned int rx_watermark; | |
370 | unsigned long flags; | |
371 | struct ata_host *host = dev_get_drvdata(dev); | |
372 | struct sata_fsl_host_priv *host_priv = host->private_data; | |
373 | void __iomem *csr_base = host_priv->csr_base; | |
374 | u32 temp; | |
375 | ||
376 | if (sscanf(buf, "%d", &rx_watermark) != 1) { | |
377 | printk(KERN_ERR "fsl-sata: wrong parameter format.\n"); | |
378 | return -EINVAL; | |
379 | } | |
380 | ||
381 | spin_lock_irqsave(&host->lock, flags); | |
382 | temp = ioread32(csr_base + TRANSCFG); | |
383 | temp &= 0xffffffe0; | |
384 | iowrite32(temp | rx_watermark, csr_base + TRANSCFG); | |
385 | ||
386 | spin_unlock_irqrestore(&host->lock, flags); | |
387 | return strlen(buf); | |
388 | } | |
389 | ||
faf0b2e5 | 390 | static inline unsigned int sata_fsl_tag(unsigned int tag, |
520d3a1a | 391 | void __iomem *hcr_base) |
faf0b2e5 LY |
392 | { |
393 | /* We let libATA core do actual (queue) tag allocation */ | |
394 | ||
faf0b2e5 LY |
395 | if (unlikely(tag >= SATA_FSL_QUEUE_DEPTH)) { |
396 | DPRINTK("tag %d invalid : out of range\n", tag); | |
397 | return 0; | |
398 | } | |
399 | ||
400 | if (unlikely((ioread32(hcr_base + CQ)) & (1 << tag))) { | |
401 | DPRINTK("tag %d invalid : in use!!\n", tag); | |
402 | return 0; | |
403 | } | |
404 | ||
405 | return tag; | |
406 | } | |
407 | ||
408 | static void sata_fsl_setup_cmd_hdr_entry(struct sata_fsl_port_priv *pp, | |
409 | unsigned int tag, u32 desc_info, | |
410 | u32 data_xfer_len, u8 num_prde, | |
411 | u8 fis_len) | |
412 | { | |
413 | dma_addr_t cmd_descriptor_address; | |
414 | ||
415 | cmd_descriptor_address = pp->cmdentry_paddr + | |
416 | tag * SATA_FSL_CMD_DESC_SIZE; | |
417 | ||
418 | /* NOTE: both data_xfer_len & fis_len are Dword counts */ | |
419 | ||
420 | pp->cmdslot[tag].cda = cpu_to_le32(cmd_descriptor_address); | |
421 | pp->cmdslot[tag].prde_fis_len = | |
422 | cpu_to_le32((num_prde << 16) | (fis_len << 2)); | |
423 | pp->cmdslot[tag].ttl = cpu_to_le32(data_xfer_len & ~0x03); | |
520d3a1a | 424 | pp->cmdslot[tag].desc_info = cpu_to_le32(desc_info | (tag & 0x1F)); |
faf0b2e5 LY |
425 | |
426 | VPRINTK("cda=0x%x, prde_fis_len=0x%x, ttl=0x%x, di=0x%x\n", | |
427 | pp->cmdslot[tag].cda, | |
428 | pp->cmdslot[tag].prde_fis_len, | |
429 | pp->cmdslot[tag].ttl, pp->cmdslot[tag].desc_info); | |
430 | ||
431 | } | |
432 | ||
433 | static unsigned int sata_fsl_fill_sg(struct ata_queued_cmd *qc, void *cmd_desc, | |
2f957fc9 X |
434 | u32 *ttl, dma_addr_t cmd_desc_paddr, |
435 | int data_snoop) | |
faf0b2e5 LY |
436 | { |
437 | struct scatterlist *sg; | |
438 | unsigned int num_prde = 0; | |
439 | u32 ttl_dwords = 0; | |
440 | ||
441 | /* | |
af901ca1 | 442 | * NOTE : direct & indirect prdt's are contiguously allocated |
faf0b2e5 LY |
443 | */ |
444 | struct prde *prd = (struct prde *)&((struct command_desc *) | |
445 | cmd_desc)->prdt; | |
446 | ||
447 | struct prde *prd_ptr_to_indirect_ext = NULL; | |
448 | unsigned indirect_ext_segment_sz = 0; | |
449 | dma_addr_t indirect_ext_segment_paddr; | |
ff2aeb1e | 450 | unsigned int si; |
faf0b2e5 | 451 | |
b1f5dc48 | 452 | VPRINTK("SATA FSL : cd = 0x%p, prd = 0x%p\n", cmd_desc, prd); |
faf0b2e5 LY |
453 | |
454 | indirect_ext_segment_paddr = cmd_desc_paddr + | |
455 | SATA_FSL_CMD_DESC_OFFSET_TO_PRDT + SATA_FSL_MAX_PRD_DIRECT * 16; | |
456 | ||
ff2aeb1e | 457 | for_each_sg(qc->sg, sg, qc->n_elem, si) { |
faf0b2e5 LY |
458 | dma_addr_t sg_addr = sg_dma_address(sg); |
459 | u32 sg_len = sg_dma_len(sg); | |
460 | ||
f48c019f KG |
461 | VPRINTK("SATA FSL : fill_sg, sg_addr = 0x%llx, sg_len = %d\n", |
462 | (unsigned long long)sg_addr, sg_len); | |
faf0b2e5 LY |
463 | |
464 | /* warn if each s/g element is not dword aligned */ | |
6b4b8fc8 | 465 | if (unlikely(sg_addr & 0x03)) |
a9a79dfe JP |
466 | ata_port_err(qc->ap, "s/g addr unaligned : 0x%llx\n", |
467 | (unsigned long long)sg_addr); | |
6b4b8fc8 | 468 | if (unlikely(sg_len & 0x03)) |
a9a79dfe JP |
469 | ata_port_err(qc->ap, "s/g len unaligned : 0x%x\n", |
470 | sg_len); | |
faf0b2e5 | 471 | |
37198e30 JB |
472 | if (num_prde == (SATA_FSL_MAX_PRD_DIRECT - 1) && |
473 | sg_next(sg) != NULL) { | |
faf0b2e5 LY |
474 | VPRINTK("setting indirect prde\n"); |
475 | prd_ptr_to_indirect_ext = prd; | |
476 | prd->dba = cpu_to_le32(indirect_ext_segment_paddr); | |
477 | indirect_ext_segment_sz = 0; | |
478 | ++prd; | |
479 | ++num_prde; | |
480 | } | |
481 | ||
482 | ttl_dwords += sg_len; | |
483 | prd->dba = cpu_to_le32(sg_addr); | |
2f957fc9 | 484 | prd->ddc_and_ext = cpu_to_le32(data_snoop | (sg_len & ~0x03)); |
faf0b2e5 LY |
485 | |
486 | VPRINTK("sg_fill, ttl=%d, dba=0x%x, ddc=0x%x\n", | |
487 | ttl_dwords, prd->dba, prd->ddc_and_ext); | |
488 | ||
489 | ++num_prde; | |
490 | ++prd; | |
491 | if (prd_ptr_to_indirect_ext) | |
492 | indirect_ext_segment_sz += sg_len; | |
493 | } | |
494 | ||
495 | if (prd_ptr_to_indirect_ext) { | |
496 | /* set indirect extension flag along with indirect ext. size */ | |
497 | prd_ptr_to_indirect_ext->ddc_and_ext = | |
498 | cpu_to_le32((EXT_INDIRECT_SEG_PRD_FLAG | | |
2f957fc9 | 499 | data_snoop | |
faf0b2e5 LY |
500 | (indirect_ext_segment_sz & ~0x03))); |
501 | } | |
502 | ||
503 | *ttl = ttl_dwords; | |
504 | return num_prde; | |
505 | } | |
506 | ||
95364f36 | 507 | static enum ata_completion_errors sata_fsl_qc_prep(struct ata_queued_cmd *qc) |
faf0b2e5 LY |
508 | { |
509 | struct ata_port *ap = qc->ap; | |
510 | struct sata_fsl_port_priv *pp = ap->private_data; | |
511 | struct sata_fsl_host_priv *host_priv = ap->host->private_data; | |
512 | void __iomem *hcr_base = host_priv->hcr_base; | |
4e5b6260 | 513 | unsigned int tag = sata_fsl_tag(qc->hw_tag, hcr_base); |
faf0b2e5 | 514 | struct command_desc *cd; |
d3587243 | 515 | u32 desc_info = CMD_DESC_RES | CMD_DESC_SNOOP_ENABLE; |
faf0b2e5 LY |
516 | u32 num_prde = 0; |
517 | u32 ttl_dwords = 0; | |
518 | dma_addr_t cd_paddr; | |
519 | ||
520 | cd = (struct command_desc *)pp->cmdentry + tag; | |
521 | cd_paddr = pp->cmdentry_paddr + tag * SATA_FSL_CMD_DESC_SIZE; | |
522 | ||
034d8e8f | 523 | ata_tf_to_fis(&qc->tf, qc->dev->link->pmp, 1, (u8 *) &cd->cfis); |
faf0b2e5 LY |
524 | |
525 | VPRINTK("Dumping cfis : 0x%x, 0x%x, 0x%x\n", | |
526 | cd->cfis[0], cd->cfis[1], cd->cfis[2]); | |
527 | ||
528 | if (qc->tf.protocol == ATA_PROT_NCQ) { | |
529 | VPRINTK("FPDMA xfer,Sctor cnt[0:7],[8:15] = %d,%d\n", | |
530 | cd->cfis[3], cd->cfis[11]); | |
531 | } | |
532 | ||
533 | /* setup "ACMD - atapi command" in cmd. desc. if this is ATAPI cmd */ | |
405e66b3 | 534 | if (ata_is_atapi(qc->tf.protocol)) { |
faf0b2e5 | 535 | desc_info |= ATAPI_CMD; |
23c72ffe KC |
536 | memset(&cd->cdb, 0, sizeof(cd->cdb)); |
537 | memcpy(&cd->cdb, qc->cdb, qc->dev->cdb_len); | |
faf0b2e5 LY |
538 | } |
539 | ||
540 | if (qc->flags & ATA_QCFLAG_DMAMAP) | |
541 | num_prde = sata_fsl_fill_sg(qc, (void *)cd, | |
2f957fc9 X |
542 | &ttl_dwords, cd_paddr, |
543 | host_priv->data_snoop); | |
faf0b2e5 LY |
544 | |
545 | if (qc->tf.protocol == ATA_PROT_NCQ) | |
546 | desc_info |= FPDMA_QUEUED_CMD; | |
547 | ||
548 | sata_fsl_setup_cmd_hdr_entry(pp, tag, desc_info, ttl_dwords, | |
549 | num_prde, 5); | |
550 | ||
551 | VPRINTK("SATA FSL : xx_qc_prep, di = 0x%x, ttl = %d, num_prde = %d\n", | |
552 | desc_info, ttl_dwords, num_prde); | |
95364f36 JS |
553 | |
554 | return AC_ERR_OK; | |
faf0b2e5 LY |
555 | } |
556 | ||
557 | static unsigned int sata_fsl_qc_issue(struct ata_queued_cmd *qc) | |
558 | { | |
559 | struct ata_port *ap = qc->ap; | |
560 | struct sata_fsl_host_priv *host_priv = ap->host->private_data; | |
561 | void __iomem *hcr_base = host_priv->hcr_base; | |
4e5b6260 | 562 | unsigned int tag = sata_fsl_tag(qc->hw_tag, hcr_base); |
faf0b2e5 LY |
563 | |
564 | VPRINTK("xx_qc_issue called,CQ=0x%x,CA=0x%x,CE=0x%x,CC=0x%x\n", | |
565 | ioread32(CQ + hcr_base), | |
566 | ioread32(CA + hcr_base), | |
567 | ioread32(CE + hcr_base), ioread32(CC + hcr_base)); | |
568 | ||
034d8e8f AK |
569 | iowrite32(qc->dev->link->pmp, CQPMP + hcr_base); |
570 | ||
faf0b2e5 LY |
571 | /* Simply queue command to the controller/device */ |
572 | iowrite32(1 << tag, CQ + hcr_base); | |
573 | ||
574 | VPRINTK("xx_qc_issue called, tag=%d, CQ=0x%x, CA=0x%x\n", | |
575 | tag, ioread32(CQ + hcr_base), ioread32(CA + hcr_base)); | |
576 | ||
577 | VPRINTK("CE=0x%x, DE=0x%x, CC=0x%x, CmdStat = 0x%x\n", | |
578 | ioread32(CE + hcr_base), | |
579 | ioread32(DE + hcr_base), | |
b1f5dc48 AV |
580 | ioread32(CC + hcr_base), |
581 | ioread32(COMMANDSTAT + host_priv->csr_base)); | |
faf0b2e5 LY |
582 | |
583 | return 0; | |
584 | } | |
585 | ||
4c9bf4e7 TH |
586 | static bool sata_fsl_qc_fill_rtf(struct ata_queued_cmd *qc) |
587 | { | |
588 | struct sata_fsl_port_priv *pp = qc->ap->private_data; | |
589 | struct sata_fsl_host_priv *host_priv = qc->ap->host->private_data; | |
590 | void __iomem *hcr_base = host_priv->hcr_base; | |
4e5b6260 | 591 | unsigned int tag = sata_fsl_tag(qc->hw_tag, hcr_base); |
4c9bf4e7 TH |
592 | struct command_desc *cd; |
593 | ||
594 | cd = pp->cmdentry + tag; | |
595 | ||
596 | ata_tf_from_fis(cd->sfis, &qc->result_tf); | |
597 | return true; | |
598 | } | |
599 | ||
82ef04fb TH |
600 | static int sata_fsl_scr_write(struct ata_link *link, |
601 | unsigned int sc_reg_in, u32 val) | |
faf0b2e5 | 602 | { |
82ef04fb | 603 | struct sata_fsl_host_priv *host_priv = link->ap->host->private_data; |
faf0b2e5 LY |
604 | void __iomem *ssr_base = host_priv->ssr_base; |
605 | unsigned int sc_reg; | |
606 | ||
607 | switch (sc_reg_in) { | |
608 | case SCR_STATUS: | |
faf0b2e5 | 609 | case SCR_ERROR: |
faf0b2e5 | 610 | case SCR_CONTROL: |
faf0b2e5 | 611 | case SCR_ACTIVE: |
9465d532 | 612 | sc_reg = sc_reg_in; |
faf0b2e5 LY |
613 | break; |
614 | default: | |
615 | return -EINVAL; | |
616 | } | |
617 | ||
618 | VPRINTK("xx_scr_write, reg_in = %d\n", sc_reg); | |
619 | ||
2a52e8d4 | 620 | iowrite32(val, ssr_base + (sc_reg * 4)); |
faf0b2e5 LY |
621 | return 0; |
622 | } | |
623 | ||
82ef04fb TH |
624 | static int sata_fsl_scr_read(struct ata_link *link, |
625 | unsigned int sc_reg_in, u32 *val) | |
faf0b2e5 | 626 | { |
82ef04fb | 627 | struct sata_fsl_host_priv *host_priv = link->ap->host->private_data; |
faf0b2e5 LY |
628 | void __iomem *ssr_base = host_priv->ssr_base; |
629 | unsigned int sc_reg; | |
630 | ||
631 | switch (sc_reg_in) { | |
632 | case SCR_STATUS: | |
faf0b2e5 | 633 | case SCR_ERROR: |
faf0b2e5 | 634 | case SCR_CONTROL: |
faf0b2e5 | 635 | case SCR_ACTIVE: |
9465d532 | 636 | sc_reg = sc_reg_in; |
faf0b2e5 LY |
637 | break; |
638 | default: | |
639 | return -EINVAL; | |
640 | } | |
641 | ||
642 | VPRINTK("xx_scr_read, reg_in = %d\n", sc_reg); | |
643 | ||
2a52e8d4 | 644 | *val = ioread32(ssr_base + (sc_reg * 4)); |
faf0b2e5 LY |
645 | return 0; |
646 | } | |
647 | ||
648 | static void sata_fsl_freeze(struct ata_port *ap) | |
649 | { | |
650 | struct sata_fsl_host_priv *host_priv = ap->host->private_data; | |
651 | void __iomem *hcr_base = host_priv->hcr_base; | |
652 | u32 temp; | |
653 | ||
654 | VPRINTK("xx_freeze, CQ=0x%x, CA=0x%x, CE=0x%x, DE=0x%x\n", | |
655 | ioread32(CQ + hcr_base), | |
656 | ioread32(CA + hcr_base), | |
657 | ioread32(CE + hcr_base), ioread32(DE + hcr_base)); | |
b1f5dc48 AV |
658 | VPRINTK("CmdStat = 0x%x\n", |
659 | ioread32(host_priv->csr_base + COMMANDSTAT)); | |
faf0b2e5 LY |
660 | |
661 | /* disable interrupts on the controller/port */ | |
662 | temp = ioread32(hcr_base + HCONTROL); | |
663 | iowrite32((temp & ~0x3F), hcr_base + HCONTROL); | |
664 | ||
665 | VPRINTK("in xx_freeze : HControl = 0x%x, HStatus = 0x%x\n", | |
666 | ioread32(hcr_base + HCONTROL), ioread32(hcr_base + HSTATUS)); | |
667 | } | |
668 | ||
669 | static void sata_fsl_thaw(struct ata_port *ap) | |
670 | { | |
671 | struct sata_fsl_host_priv *host_priv = ap->host->private_data; | |
672 | void __iomem *hcr_base = host_priv->hcr_base; | |
673 | u32 temp; | |
674 | ||
675 | /* ack. any pending IRQs for this controller/port */ | |
676 | temp = ioread32(hcr_base + HSTATUS); | |
677 | ||
678 | VPRINTK("xx_thaw, pending IRQs = 0x%x\n", (temp & 0x3F)); | |
679 | ||
680 | if (temp & 0x3F) | |
681 | iowrite32((temp & 0x3F), hcr_base + HSTATUS); | |
682 | ||
683 | /* enable interrupts on the controller/port */ | |
684 | temp = ioread32(hcr_base + HCONTROL); | |
685 | iowrite32((temp | DEFAULT_PORT_IRQ_ENABLE_MASK), hcr_base + HCONTROL); | |
686 | ||
687 | VPRINTK("xx_thaw : HControl = 0x%x, HStatus = 0x%x\n", | |
688 | ioread32(hcr_base + HCONTROL), ioread32(hcr_base + HSTATUS)); | |
689 | } | |
690 | ||
034d8e8f AK |
691 | static void sata_fsl_pmp_attach(struct ata_port *ap) |
692 | { | |
693 | struct sata_fsl_host_priv *host_priv = ap->host->private_data; | |
694 | void __iomem *hcr_base = host_priv->hcr_base; | |
695 | u32 temp; | |
696 | ||
697 | temp = ioread32(hcr_base + HCONTROL); | |
698 | iowrite32((temp | HCONTROL_PMP_ATTACHED), hcr_base + HCONTROL); | |
699 | } | |
700 | ||
701 | static void sata_fsl_pmp_detach(struct ata_port *ap) | |
702 | { | |
703 | struct sata_fsl_host_priv *host_priv = ap->host->private_data; | |
704 | void __iomem *hcr_base = host_priv->hcr_base; | |
705 | u32 temp; | |
706 | ||
707 | temp = ioread32(hcr_base + HCONTROL); | |
708 | temp &= ~HCONTROL_PMP_ATTACHED; | |
709 | iowrite32(temp, hcr_base + HCONTROL); | |
710 | ||
711 | /* enable interrupts on the controller/port */ | |
712 | temp = ioread32(hcr_base + HCONTROL); | |
713 | iowrite32((temp | DEFAULT_PORT_IRQ_ENABLE_MASK), hcr_base + HCONTROL); | |
714 | ||
715 | } | |
716 | ||
faf0b2e5 LY |
717 | static int sata_fsl_port_start(struct ata_port *ap) |
718 | { | |
719 | struct device *dev = ap->host->dev; | |
720 | struct sata_fsl_port_priv *pp; | |
faf0b2e5 LY |
721 | void *mem; |
722 | dma_addr_t mem_dma; | |
723 | struct sata_fsl_host_priv *host_priv = ap->host->private_data; | |
724 | void __iomem *hcr_base = host_priv->hcr_base; | |
725 | u32 temp; | |
726 | ||
727 | pp = kzalloc(sizeof(*pp), GFP_KERNEL); | |
728 | if (!pp) | |
729 | return -ENOMEM; | |
730 | ||
750afb08 LC |
731 | mem = dma_alloc_coherent(dev, SATA_FSL_PORT_PRIV_DMA_SZ, &mem_dma, |
732 | GFP_KERNEL); | |
faf0b2e5 | 733 | if (!mem) { |
faf0b2e5 LY |
734 | kfree(pp); |
735 | return -ENOMEM; | |
736 | } | |
faf0b2e5 LY |
737 | |
738 | pp->cmdslot = mem; | |
739 | pp->cmdslot_paddr = mem_dma; | |
740 | ||
741 | mem += SATA_FSL_CMD_SLOT_SIZE; | |
742 | mem_dma += SATA_FSL_CMD_SLOT_SIZE; | |
743 | ||
744 | pp->cmdentry = mem; | |
745 | pp->cmdentry_paddr = mem_dma; | |
746 | ||
747 | ap->private_data = pp; | |
748 | ||
749 | VPRINTK("CHBA = 0x%x, cmdentry_phys = 0x%x\n", | |
750 | pp->cmdslot_paddr, pp->cmdentry_paddr); | |
751 | ||
752 | /* Now, update the CHBA register in host controller cmd register set */ | |
753 | iowrite32(pp->cmdslot_paddr & 0xffffffff, hcr_base + CHBA); | |
754 | ||
755 | /* | |
756 | * Now, we can bring the controller on-line & also initiate | |
757 | * the COMINIT sequence, we simply return here and the boot-probing | |
758 | * & device discovery process is re-initiated by libATA using a | |
759 | * Softreset EH (dummy) session. Hence, boot probing and device | |
760 | * discovey will be part of sata_fsl_softreset() callback. | |
761 | */ | |
762 | ||
763 | temp = ioread32(hcr_base + HCONTROL); | |
764 | iowrite32((temp | HCONTROL_ONLINE_PHY_RST), hcr_base + HCONTROL); | |
765 | ||
766 | VPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS)); | |
767 | VPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL)); | |
768 | VPRINTK("CHBA = 0x%x\n", ioread32(hcr_base + CHBA)); | |
769 | ||
faf0b2e5 LY |
770 | return 0; |
771 | } | |
772 | ||
773 | static void sata_fsl_port_stop(struct ata_port *ap) | |
774 | { | |
775 | struct device *dev = ap->host->dev; | |
776 | struct sata_fsl_port_priv *pp = ap->private_data; | |
777 | struct sata_fsl_host_priv *host_priv = ap->host->private_data; | |
778 | void __iomem *hcr_base = host_priv->hcr_base; | |
779 | u32 temp; | |
780 | ||
781 | /* | |
782 | * Force host controller to go off-line, aborting current operations | |
783 | */ | |
784 | temp = ioread32(hcr_base + HCONTROL); | |
785 | temp &= ~HCONTROL_ONLINE_PHY_RST; | |
786 | temp |= HCONTROL_FORCE_OFFLINE; | |
787 | iowrite32(temp, hcr_base + HCONTROL); | |
788 | ||
789 | /* Poll for controller to go offline - should happen immediately */ | |
97750ceb | 790 | ata_wait_register(ap, hcr_base + HSTATUS, ONLINE, ONLINE, 1, 1); |
faf0b2e5 LY |
791 | |
792 | ap->private_data = NULL; | |
793 | dma_free_coherent(dev, SATA_FSL_PORT_PRIV_DMA_SZ, | |
794 | pp->cmdslot, pp->cmdslot_paddr); | |
795 | ||
faf0b2e5 LY |
796 | kfree(pp); |
797 | } | |
798 | ||
799 | static unsigned int sata_fsl_dev_classify(struct ata_port *ap) | |
800 | { | |
801 | struct sata_fsl_host_priv *host_priv = ap->host->private_data; | |
802 | void __iomem *hcr_base = host_priv->hcr_base; | |
803 | struct ata_taskfile tf; | |
804 | u32 temp; | |
805 | ||
806 | temp = ioread32(hcr_base + SIGNATURE); | |
807 | ||
808 | VPRINTK("raw sig = 0x%x\n", temp); | |
809 | VPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS)); | |
810 | VPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL)); | |
811 | ||
812 | tf.lbah = (temp >> 24) & 0xff; | |
813 | tf.lbam = (temp >> 16) & 0xff; | |
814 | tf.lbal = (temp >> 8) & 0xff; | |
815 | tf.nsect = temp & 0xff; | |
816 | ||
817 | return ata_dev_classify(&tf); | |
818 | } | |
819 | ||
a0a74d1e | 820 | static int sata_fsl_hardreset(struct ata_link *link, unsigned int *class, |
034d8e8f | 821 | unsigned long deadline) |
faf0b2e5 | 822 | { |
1bf617b7 | 823 | struct ata_port *ap = link->ap; |
faf0b2e5 LY |
824 | struct sata_fsl_host_priv *host_priv = ap->host->private_data; |
825 | void __iomem *hcr_base = host_priv->hcr_base; | |
826 | u32 temp; | |
faf0b2e5 | 827 | int i = 0; |
faf0b2e5 LY |
828 | unsigned long start_jiffies; |
829 | ||
a0a74d1e | 830 | DPRINTK("in xx_hardreset\n"); |
034d8e8f | 831 | |
faf0b2e5 LY |
832 | try_offline_again: |
833 | /* | |
834 | * Force host controller to go off-line, aborting current operations | |
835 | */ | |
836 | temp = ioread32(hcr_base + HCONTROL); | |
837 | temp &= ~HCONTROL_ONLINE_PHY_RST; | |
838 | iowrite32(temp, hcr_base + HCONTROL); | |
839 | ||
840 | /* Poll for controller to go offline */ | |
97750ceb TH |
841 | temp = ata_wait_register(ap, hcr_base + HSTATUS, ONLINE, ONLINE, |
842 | 1, 500); | |
faf0b2e5 LY |
843 | |
844 | if (temp & ONLINE) { | |
a9a79dfe | 845 | ata_port_err(ap, "Hardreset failed, not off-lined %d\n", i); |
faf0b2e5 LY |
846 | |
847 | /* | |
848 | * Try to offline controller atleast twice | |
849 | */ | |
850 | i++; | |
851 | if (i == 2) | |
852 | goto err; | |
853 | else | |
854 | goto try_offline_again; | |
855 | } | |
856 | ||
a0a74d1e | 857 | DPRINTK("hardreset, controller off-lined\n"); |
faf0b2e5 LY |
858 | VPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS)); |
859 | VPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL)); | |
860 | ||
861 | /* | |
862 | * PHY reset should remain asserted for atleast 1ms | |
863 | */ | |
97750ceb | 864 | ata_msleep(ap, 1); |
faf0b2e5 | 865 | |
29200f12 MH |
866 | sata_set_spd(link); |
867 | ||
faf0b2e5 LY |
868 | /* |
869 | * Now, bring the host controller online again, this can take time | |
870 | * as PHY reset and communication establishment, 1st D2H FIS and | |
871 | * device signature update is done, on safe side assume 500ms | |
872 | * NOTE : Host online status may be indicated immediately!! | |
873 | */ | |
874 | ||
875 | temp = ioread32(hcr_base + HCONTROL); | |
876 | temp |= (HCONTROL_ONLINE_PHY_RST | HCONTROL_SNOOP_ENABLE); | |
034d8e8f | 877 | temp |= HCONTROL_PMP_ATTACHED; |
faf0b2e5 LY |
878 | iowrite32(temp, hcr_base + HCONTROL); |
879 | ||
97750ceb | 880 | temp = ata_wait_register(ap, hcr_base + HSTATUS, ONLINE, 0, 1, 500); |
faf0b2e5 LY |
881 | |
882 | if (!(temp & ONLINE)) { | |
a9a79dfe | 883 | ata_port_err(ap, "Hardreset failed, not on-lined\n"); |
faf0b2e5 LY |
884 | goto err; |
885 | } | |
886 | ||
a0a74d1e | 887 | DPRINTK("hardreset, controller off-lined & on-lined\n"); |
faf0b2e5 LY |
888 | VPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS)); |
889 | VPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL)); | |
890 | ||
891 | /* | |
892 | * First, wait for the PHYRDY change to occur before waiting for | |
893 | * the signature, and also verify if SStatus indicates device | |
894 | * presence | |
895 | */ | |
896 | ||
97750ceb | 897 | temp = ata_wait_register(ap, hcr_base + HSTATUS, 0xFF, 0, 1, 500); |
1bf617b7 | 898 | if ((!(temp & 0x10)) || ata_link_offline(link)) { |
a9a79dfe JP |
899 | ata_port_warn(ap, "No Device OR PHYRDY change,Hstatus = 0x%x\n", |
900 | ioread32(hcr_base + HSTATUS)); | |
034d8e8f | 901 | *class = ATA_DEV_NONE; |
a0a74d1e | 902 | return 0; |
faf0b2e5 LY |
903 | } |
904 | ||
905 | /* | |
906 | * Wait for the first D2H from device,i.e,signature update notification | |
907 | */ | |
908 | start_jiffies = jiffies; | |
97750ceb | 909 | temp = ata_wait_register(ap, hcr_base + HSTATUS, 0xFF, 0x10, |
faf0b2e5 LY |
910 | 500, jiffies_to_msecs(deadline - start_jiffies)); |
911 | ||
912 | if ((temp & 0xFF) != 0x18) { | |
a9a79dfe | 913 | ata_port_warn(ap, "No Signature Update\n"); |
034d8e8f | 914 | *class = ATA_DEV_NONE; |
a0a74d1e | 915 | goto do_followup_srst; |
faf0b2e5 | 916 | } else { |
a9a79dfe JP |
917 | ata_port_info(ap, "Signature Update detected @ %d msecs\n", |
918 | jiffies_to_msecs(jiffies - start_jiffies)); | |
a0a74d1e JY |
919 | *class = sata_fsl_dev_classify(ap); |
920 | return 0; | |
921 | } | |
922 | ||
923 | do_followup_srst: | |
924 | /* | |
925 | * request libATA to perform follow-up softreset | |
926 | */ | |
927 | return -EAGAIN; | |
928 | ||
929 | err: | |
930 | return -EIO; | |
931 | } | |
932 | ||
933 | static int sata_fsl_softreset(struct ata_link *link, unsigned int *class, | |
934 | unsigned long deadline) | |
935 | { | |
936 | struct ata_port *ap = link->ap; | |
937 | struct sata_fsl_port_priv *pp = ap->private_data; | |
938 | struct sata_fsl_host_priv *host_priv = ap->host->private_data; | |
939 | void __iomem *hcr_base = host_priv->hcr_base; | |
940 | int pmp = sata_srst_pmp(link); | |
941 | u32 temp; | |
942 | struct ata_taskfile tf; | |
943 | u8 *cfis; | |
944 | u32 Serror; | |
945 | ||
946 | DPRINTK("in xx_softreset\n"); | |
947 | ||
948 | if (ata_link_offline(link)) { | |
949 | DPRINTK("PHY reports no device\n"); | |
950 | *class = ATA_DEV_NONE; | |
951 | return 0; | |
faf0b2e5 LY |
952 | } |
953 | ||
954 | /* | |
955 | * Send a device reset (SRST) explicitly on command slot #0 | |
956 | * Check : will the command queue (reg) be cleared during offlining ?? | |
957 | * Also we will be online only if Phy commn. has been established | |
958 | * and device presence has been detected, therefore if we have | |
959 | * reached here, we can send a command to the target device | |
960 | */ | |
961 | ||
faf0b2e5 LY |
962 | DPRINTK("Sending SRST/device reset\n"); |
963 | ||
1bf617b7 | 964 | ata_tf_init(link->device, &tf); |
520d3a1a | 965 | cfis = (u8 *) &pp->cmdentry->cfis; |
faf0b2e5 LY |
966 | |
967 | /* device reset/SRST is a control register update FIS, uses tag0 */ | |
968 | sata_fsl_setup_cmd_hdr_entry(pp, 0, | |
d3587243 | 969 | SRST_CMD | CMD_DESC_RES | CMD_DESC_SNOOP_ENABLE, 0, 0, 5); |
faf0b2e5 LY |
970 | |
971 | tf.ctl |= ATA_SRST; /* setup SRST bit in taskfile control reg */ | |
034d8e8f | 972 | ata_tf_to_fis(&tf, pmp, 0, cfis); |
faf0b2e5 LY |
973 | |
974 | DPRINTK("Dumping cfis : 0x%x, 0x%x, 0x%x, 0x%x\n", | |
975 | cfis[0], cfis[1], cfis[2], cfis[3]); | |
976 | ||
977 | /* | |
978 | * Queue SRST command to the controller/device, ensure that no | |
979 | * other commands are active on the controller/device | |
980 | */ | |
981 | ||
982 | DPRINTK("@Softreset, CQ = 0x%x, CA = 0x%x, CC = 0x%x\n", | |
983 | ioread32(CQ + hcr_base), | |
984 | ioread32(CA + hcr_base), ioread32(CC + hcr_base)); | |
985 | ||
986 | iowrite32(0xFFFF, CC + hcr_base); | |
a0a74d1e JY |
987 | if (pmp != SATA_PMP_CTRL_PORT) |
988 | iowrite32(pmp, CQPMP + hcr_base); | |
faf0b2e5 LY |
989 | iowrite32(1, CQ + hcr_base); |
990 | ||
97750ceb | 991 | temp = ata_wait_register(ap, CQ + hcr_base, 0x1, 0x1, 1, 5000); |
faf0b2e5 | 992 | if (temp & 0x1) { |
a9a79dfe | 993 | ata_port_warn(ap, "ATA_SRST issue failed\n"); |
faf0b2e5 LY |
994 | |
995 | DPRINTK("Softreset@5000,CQ=0x%x,CA=0x%x,CC=0x%x\n", | |
996 | ioread32(CQ + hcr_base), | |
997 | ioread32(CA + hcr_base), ioread32(CC + hcr_base)); | |
998 | ||
82ef04fb | 999 | sata_fsl_scr_read(&ap->link, SCR_ERROR, &Serror); |
faf0b2e5 LY |
1000 | |
1001 | DPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS)); | |
1002 | DPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL)); | |
1003 | DPRINTK("Serror = 0x%x\n", Serror); | |
1004 | goto err; | |
1005 | } | |
1006 | ||
97750ceb | 1007 | ata_msleep(ap, 1); |
faf0b2e5 LY |
1008 | |
1009 | /* | |
25985edc | 1010 | * SATA device enters reset state after receiving a Control register |
faf0b2e5 LY |
1011 | * FIS with SRST bit asserted and it awaits another H2D Control reg. |
1012 | * FIS with SRST bit cleared, then the device does internal diags & | |
1013 | * initialization, followed by indicating it's initialization status | |
1014 | * using ATA signature D2H register FIS to the host controller. | |
1015 | */ | |
1016 | ||
d3587243 DL |
1017 | sata_fsl_setup_cmd_hdr_entry(pp, 0, CMD_DESC_RES | CMD_DESC_SNOOP_ENABLE, |
1018 | 0, 0, 5); | |
faf0b2e5 LY |
1019 | |
1020 | tf.ctl &= ~ATA_SRST; /* 2nd H2D Ctl. register FIS */ | |
034d8e8f | 1021 | ata_tf_to_fis(&tf, pmp, 0, cfis); |
faf0b2e5 | 1022 | |
034d8e8f AK |
1023 | if (pmp != SATA_PMP_CTRL_PORT) |
1024 | iowrite32(pmp, CQPMP + hcr_base); | |
faf0b2e5 | 1025 | iowrite32(1, CQ + hcr_base); |
97750ceb | 1026 | ata_msleep(ap, 150); /* ?? */ |
faf0b2e5 LY |
1027 | |
1028 | /* | |
1029 | * The above command would have signalled an interrupt on command | |
1030 | * complete, which needs special handling, by clearing the Nth | |
1031 | * command bit of the CCreg | |
1032 | */ | |
1033 | iowrite32(0x01, CC + hcr_base); /* We know it will be cmd#0 always */ | |
faf0b2e5 LY |
1034 | |
1035 | DPRINTK("SATA FSL : Now checking device signature\n"); | |
1036 | ||
1037 | *class = ATA_DEV_NONE; | |
1038 | ||
1039 | /* Verify if SStatus indicates device presence */ | |
1bf617b7 | 1040 | if (ata_link_online(link)) { |
faf0b2e5 LY |
1041 | /* |
1042 | * if we are here, device presence has been detected, | |
1043 | * 1st D2H FIS would have been received, but sfis in | |
1044 | * command desc. is not updated, but signature register | |
1045 | * would have been updated | |
1046 | */ | |
1047 | ||
1048 | *class = sata_fsl_dev_classify(ap); | |
1049 | ||
1050 | DPRINTK("class = %d\n", *class); | |
1051 | VPRINTK("ccreg = 0x%x\n", ioread32(hcr_base + CC)); | |
1052 | VPRINTK("cereg = 0x%x\n", ioread32(hcr_base + CE)); | |
1053 | } | |
1054 | ||
1055 | return 0; | |
1056 | ||
1057 | err: | |
1058 | return -EIO; | |
1059 | } | |
1060 | ||
034d8e8f AK |
1061 | static void sata_fsl_error_handler(struct ata_port *ap) |
1062 | { | |
1063 | ||
1064 | DPRINTK("in xx_error_handler\n"); | |
1065 | sata_pmp_error_handler(ap); | |
1066 | ||
1067 | } | |
1068 | ||
faf0b2e5 LY |
1069 | static void sata_fsl_post_internal_cmd(struct ata_queued_cmd *qc) |
1070 | { | |
1071 | if (qc->flags & ATA_QCFLAG_FAILED) | |
1072 | qc->err_mask |= AC_ERR_OTHER; | |
1073 | ||
1074 | if (qc->err_mask) { | |
1075 | /* make DMA engine forget about the failed command */ | |
1076 | ||
1077 | } | |
1078 | } | |
1079 | ||
faf0b2e5 LY |
1080 | static void sata_fsl_error_intr(struct ata_port *ap) |
1081 | { | |
faf0b2e5 LY |
1082 | struct sata_fsl_host_priv *host_priv = ap->host->private_data; |
1083 | void __iomem *hcr_base = host_priv->hcr_base; | |
034d8e8f | 1084 | u32 hstatus, dereg=0, cereg = 0, SError = 0; |
faf0b2e5 | 1085 | unsigned int err_mask = 0, action = 0; |
034d8e8f AK |
1086 | int freeze = 0, abort=0; |
1087 | struct ata_link *link = NULL; | |
1088 | struct ata_queued_cmd *qc = NULL; | |
1089 | struct ata_eh_info *ehi; | |
faf0b2e5 LY |
1090 | |
1091 | hstatus = ioread32(hcr_base + HSTATUS); | |
1092 | cereg = ioread32(hcr_base + CE); | |
1093 | ||
034d8e8f AK |
1094 | /* first, analyze and record host port events */ |
1095 | link = &ap->link; | |
1096 | ehi = &link->eh_info; | |
faf0b2e5 LY |
1097 | ata_ehi_clear_desc(ehi); |
1098 | ||
1099 | /* | |
1100 | * Handle & Clear SError | |
1101 | */ | |
1102 | ||
82ef04fb | 1103 | sata_fsl_scr_read(&ap->link, SCR_ERROR, &SError); |
fd6c29e3 | 1104 | if (unlikely(SError & 0xFFFF0000)) |
82ef04fb | 1105 | sata_fsl_scr_write(&ap->link, SCR_ERROR, SError); |
faf0b2e5 LY |
1106 | |
1107 | DPRINTK("error_intr,hStat=0x%x,CE=0x%x,DE =0x%x,SErr=0x%x\n", | |
1108 | hstatus, cereg, ioread32(hcr_base + DE), SError); | |
1109 | ||
034d8e8f AK |
1110 | /* handle fatal errors */ |
1111 | if (hstatus & FATAL_ERROR_DECODE) { | |
1112 | ehi->err_mask |= AC_ERR_ATA_BUS; | |
1113 | ehi->action |= ATA_EH_SOFTRESET; | |
faf0b2e5 | 1114 | |
faf0b2e5 LY |
1115 | freeze = 1; |
1116 | } | |
1117 | ||
fd6c29e3 | 1118 | /* Handle SDB FIS receive & notify update */ |
1119 | if (hstatus & INT_ON_SNOTIFY_UPDATE) | |
1120 | sata_async_notification(ap); | |
1121 | ||
faf0b2e5 LY |
1122 | /* Handle PHYRDY change notification */ |
1123 | if (hstatus & INT_ON_PHYRDY_CHG) { | |
1124 | DPRINTK("SATA FSL: PHYRDY change indication\n"); | |
1125 | ||
1126 | /* Setup a soft-reset EH action */ | |
1127 | ata_ehi_hotplugged(ehi); | |
034d8e8f | 1128 | ata_ehi_push_desc(ehi, "%s", "PHY RDY changed"); |
faf0b2e5 LY |
1129 | freeze = 1; |
1130 | } | |
1131 | ||
034d8e8f AK |
1132 | /* handle single device errors */ |
1133 | if (cereg) { | |
1134 | /* | |
1135 | * clear the command error, also clears queue to the device | |
1136 | * in error, and we can (re)issue commands to this device. | |
1137 | * When a device is in error all commands queued into the | |
1138 | * host controller and at the device are considered aborted | |
1139 | * and the queue for that device is stopped. Now, after | |
1140 | * clearing the device error, we can issue commands to the | |
1141 | * device to interrogate it to find the source of the error. | |
1142 | */ | |
1143 | abort = 1; | |
1144 | ||
1145 | DPRINTK("single device error, CE=0x%x, DE=0x%x\n", | |
1146 | ioread32(hcr_base + CE), ioread32(hcr_base + DE)); | |
faf0b2e5 | 1147 | |
034d8e8f AK |
1148 | /* find out the offending link and qc */ |
1149 | if (ap->nr_pmp_links) { | |
4ac7534a PK |
1150 | unsigned int dev_num; |
1151 | ||
034d8e8f AK |
1152 | dereg = ioread32(hcr_base + DE); |
1153 | iowrite32(dereg, hcr_base + DE); | |
1154 | iowrite32(cereg, hcr_base + CE); | |
1155 | ||
4ac7534a PK |
1156 | dev_num = ffs(dereg) - 1; |
1157 | if (dev_num < ap->nr_pmp_links && dereg != 0) { | |
1158 | link = &ap->pmp_link[dev_num]; | |
034d8e8f AK |
1159 | ehi = &link->eh_info; |
1160 | qc = ata_qc_from_tag(ap, link->active_tag); | |
1161 | /* | |
1162 | * We should consider this as non fatal error, | |
1163 | * and TF must be updated as done below. | |
1164 | */ | |
1165 | ||
1166 | err_mask |= AC_ERR_DEV; | |
1167 | ||
1168 | } else { | |
1169 | err_mask |= AC_ERR_HSM; | |
1170 | action |= ATA_EH_HARDRESET; | |
1171 | freeze = 1; | |
1172 | } | |
1173 | } else { | |
1174 | dereg = ioread32(hcr_base + DE); | |
1175 | iowrite32(dereg, hcr_base + DE); | |
1176 | iowrite32(cereg, hcr_base + CE); | |
1177 | ||
1178 | qc = ata_qc_from_tag(ap, link->active_tag); | |
1179 | /* | |
1180 | * We should consider this as non fatal error, | |
1181 | * and TF must be updated as done below. | |
1182 | */ | |
1183 | err_mask |= AC_ERR_DEV; | |
1184 | } | |
1185 | } | |
1186 | ||
1187 | /* record error info */ | |
fd6c29e3 | 1188 | if (qc) |
faf0b2e5 | 1189 | qc->err_mask |= err_mask; |
fd6c29e3 | 1190 | else |
faf0b2e5 LY |
1191 | ehi->err_mask |= err_mask; |
1192 | ||
1193 | ehi->action |= action; | |
faf0b2e5 LY |
1194 | |
1195 | /* freeze or abort */ | |
1196 | if (freeze) | |
1197 | ata_port_freeze(ap); | |
034d8e8f AK |
1198 | else if (abort) { |
1199 | if (qc) | |
1200 | ata_link_abort(qc->dev->link); | |
1201 | else | |
1202 | ata_port_abort(ap); | |
1203 | } | |
faf0b2e5 LY |
1204 | } |
1205 | ||
faf0b2e5 LY |
1206 | static void sata_fsl_host_intr(struct ata_port *ap) |
1207 | { | |
1208 | struct sata_fsl_host_priv *host_priv = ap->host->private_data; | |
1209 | void __iomem *hcr_base = host_priv->hcr_base; | |
752e386c | 1210 | u32 hstatus, done_mask = 0; |
faf0b2e5 LY |
1211 | struct ata_queued_cmd *qc; |
1212 | u32 SError; | |
100f586b SX |
1213 | u32 tag; |
1214 | u32 status_mask = INT_ON_ERROR; | |
faf0b2e5 LY |
1215 | |
1216 | hstatus = ioread32(hcr_base + HSTATUS); | |
1217 | ||
82ef04fb | 1218 | sata_fsl_scr_read(&ap->link, SCR_ERROR, &SError); |
faf0b2e5 | 1219 | |
100f586b SX |
1220 | /* Read command completed register */ |
1221 | done_mask = ioread32(hcr_base + CC); | |
1222 | ||
1223 | /* Workaround for data length mismatch errata */ | |
1224 | if (unlikely(hstatus & INT_ON_DATA_LENGTH_MISMATCH)) { | |
d3543b4d | 1225 | ata_qc_for_each_with_internal(ap, qc, tag) { |
100f586b SX |
1226 | if (qc && ata_is_atapi(qc->tf.protocol)) { |
1227 | u32 hcontrol; | |
1228 | /* Set HControl[27] to clear error registers */ | |
1229 | hcontrol = ioread32(hcr_base + HCONTROL); | |
1230 | iowrite32(hcontrol | CLEAR_ERROR, | |
1231 | hcr_base + HCONTROL); | |
1232 | ||
1233 | /* Clear HControl[27] */ | |
1234 | iowrite32(hcontrol & ~CLEAR_ERROR, | |
1235 | hcr_base + HCONTROL); | |
1236 | ||
1237 | /* Clear SError[E] bit */ | |
1238 | sata_fsl_scr_write(&ap->link, SCR_ERROR, | |
1239 | SError); | |
1240 | ||
1241 | /* Ignore fatal error and device error */ | |
1242 | status_mask &= ~(INT_ON_SINGL_DEVICE_ERR | |
1243 | | INT_ON_FATAL_ERR); | |
1244 | break; | |
1245 | } | |
1246 | } | |
1247 | } | |
1248 | ||
faf0b2e5 LY |
1249 | if (unlikely(SError & 0xFFFF0000)) { |
1250 | DPRINTK("serror @host_intr : 0x%x\n", SError); | |
1251 | sata_fsl_error_intr(ap); | |
faf0b2e5 LY |
1252 | } |
1253 | ||
100f586b | 1254 | if (unlikely(hstatus & status_mask)) { |
faf0b2e5 LY |
1255 | DPRINTK("error interrupt!!\n"); |
1256 | sata_fsl_error_intr(ap); | |
1257 | return; | |
1258 | } | |
1259 | ||
034d8e8f | 1260 | VPRINTK("Status of all queues :\n"); |
e3ed8939 | 1261 | VPRINTK("done_mask/CC = 0x%x, CA = 0x%x, CE=0x%x,CQ=0x%x,apqa=0x%llx\n", |
752e386c | 1262 | done_mask, |
034d8e8f AK |
1263 | ioread32(hcr_base + CA), |
1264 | ioread32(hcr_base + CE), | |
1265 | ioread32(hcr_base + CQ), | |
1266 | ap->qc_active); | |
1267 | ||
752e386c | 1268 | if (done_mask & ap->qc_active) { |
faf0b2e5 | 1269 | int i; |
faf0b2e5 | 1270 | /* clear CC bit, this will also complete the interrupt */ |
752e386c | 1271 | iowrite32(done_mask, hcr_base + CC); |
faf0b2e5 LY |
1272 | |
1273 | DPRINTK("Status of all queues :\n"); | |
752e386c TH |
1274 | DPRINTK("done_mask/CC = 0x%x, CA = 0x%x, CE=0x%x\n", |
1275 | done_mask, ioread32(hcr_base + CA), | |
faf0b2e5 LY |
1276 | ioread32(hcr_base + CE)); |
1277 | ||
1278 | for (i = 0; i < SATA_FSL_QUEUE_DEPTH; i++) { | |
1aadf5c3 | 1279 | if (done_mask & (1 << i)) |
faf0b2e5 LY |
1280 | DPRINTK |
1281 | ("completing ncq cmd,tag=%d,CC=0x%x,CA=0x%x\n", | |
1282 | i, ioread32(hcr_base + CC), | |
1283 | ioread32(hcr_base + CA)); | |
faf0b2e5 | 1284 | } |
8385d756 | 1285 | ata_qc_complete_multiple(ap, ata_qc_get_active(ap) ^ done_mask); |
faf0b2e5 LY |
1286 | return; |
1287 | ||
88e10092 | 1288 | } else if ((ap->qc_active & (1ULL << ATA_TAG_INTERNAL))) { |
faf0b2e5 | 1289 | iowrite32(1, hcr_base + CC); |
034d8e8f | 1290 | qc = ata_qc_from_tag(ap, ATA_TAG_INTERNAL); |
faf0b2e5 | 1291 | |
034d8e8f AK |
1292 | DPRINTK("completing non-ncq cmd, CC=0x%x\n", |
1293 | ioread32(hcr_base + CC)); | |
faf0b2e5 | 1294 | |
034d8e8f | 1295 | if (qc) { |
faf0b2e5 | 1296 | ata_qc_complete(qc); |
034d8e8f | 1297 | } |
faf0b2e5 LY |
1298 | } else { |
1299 | /* Spurious Interrupt!! */ | |
1300 | DPRINTK("spurious interrupt!!, CC = 0x%x\n", | |
1301 | ioread32(hcr_base + CC)); | |
752e386c | 1302 | iowrite32(done_mask, hcr_base + CC); |
faf0b2e5 LY |
1303 | return; |
1304 | } | |
1305 | } | |
1306 | ||
1307 | static irqreturn_t sata_fsl_interrupt(int irq, void *dev_instance) | |
1308 | { | |
1309 | struct ata_host *host = dev_instance; | |
1310 | struct sata_fsl_host_priv *host_priv = host->private_data; | |
1311 | void __iomem *hcr_base = host_priv->hcr_base; | |
1312 | u32 interrupt_enables; | |
1313 | unsigned handled = 0; | |
1314 | struct ata_port *ap; | |
1315 | ||
1316 | /* ack. any pending IRQs for this controller/port */ | |
1317 | interrupt_enables = ioread32(hcr_base + HSTATUS); | |
1318 | interrupt_enables &= 0x3F; | |
1319 | ||
1320 | DPRINTK("interrupt status 0x%x\n", interrupt_enables); | |
1321 | ||
1322 | if (!interrupt_enables) | |
1323 | return IRQ_NONE; | |
1324 | ||
1325 | spin_lock(&host->lock); | |
1326 | ||
1327 | /* Assuming one port per host controller */ | |
1328 | ||
1329 | ap = host->ports[0]; | |
1330 | if (ap) { | |
1331 | sata_fsl_host_intr(ap); | |
1332 | } else { | |
a44fec1f | 1333 | dev_warn(host->dev, "interrupt on disabled port 0\n"); |
faf0b2e5 LY |
1334 | } |
1335 | ||
1336 | iowrite32(interrupt_enables, hcr_base + HSTATUS); | |
1337 | handled = 1; | |
1338 | ||
1339 | spin_unlock(&host->lock); | |
1340 | ||
1341 | return IRQ_RETVAL(handled); | |
1342 | } | |
1343 | ||
1344 | /* | |
1345 | * Multiple ports are represented by multiple SATA controllers with | |
1346 | * one port per controller | |
1347 | */ | |
1348 | static int sata_fsl_init_controller(struct ata_host *host) | |
1349 | { | |
1350 | struct sata_fsl_host_priv *host_priv = host->private_data; | |
1351 | void __iomem *hcr_base = host_priv->hcr_base; | |
1352 | u32 temp; | |
1353 | ||
1354 | /* | |
1355 | * NOTE : We cannot bring the controller online before setting | |
1356 | * the CHBA, hence main controller initialization is done as | |
1357 | * part of the port_start() callback | |
1358 | */ | |
1359 | ||
93272b13 JH |
1360 | /* sata controller to operate in enterprise mode */ |
1361 | temp = ioread32(hcr_base + HCONTROL); | |
1362 | iowrite32(temp & ~HCONTROL_LEGACY, hcr_base + HCONTROL); | |
1363 | ||
faf0b2e5 LY |
1364 | /* ack. any pending IRQs for this controller/port */ |
1365 | temp = ioread32(hcr_base + HSTATUS); | |
1366 | if (temp & 0x3F) | |
1367 | iowrite32((temp & 0x3F), hcr_base + HSTATUS); | |
1368 | ||
1369 | /* Keep interrupts disabled on the controller */ | |
1370 | temp = ioread32(hcr_base + HCONTROL); | |
1371 | iowrite32((temp & ~0x3F), hcr_base + HCONTROL); | |
1372 | ||
1373 | /* Disable interrupt coalescing control(icc), for the moment */ | |
1374 | DPRINTK("icc = 0x%x\n", ioread32(hcr_base + ICC)); | |
1375 | iowrite32(0x01000000, hcr_base + ICC); | |
1376 | ||
1377 | /* clear error registers, SError is cleared by libATA */ | |
1378 | iowrite32(0x00000FFFF, hcr_base + CE); | |
1379 | iowrite32(0x00000FFFF, hcr_base + DE); | |
1380 | ||
6b4b8fc8 QL |
1381 | /* |
1382 | * reset the number of command complete bits which will cause the | |
1383 | * interrupt to be signaled | |
1384 | */ | |
1385 | fsl_sata_set_irq_coalescing(host, intr_coalescing_count, | |
1386 | intr_coalescing_ticks); | |
1387 | ||
faf0b2e5 LY |
1388 | /* |
1389 | * host controller will be brought on-line, during xx_port_start() | |
1390 | * callback, that should also initiate the OOB, COMINIT sequence | |
1391 | */ | |
1392 | ||
1393 | DPRINTK("HStatus = 0x%x\n", ioread32(hcr_base + HSTATUS)); | |
1394 | DPRINTK("HControl = 0x%x\n", ioread32(hcr_base + HCONTROL)); | |
1395 | ||
1396 | return 0; | |
1397 | } | |
1398 | ||
6c8ad7e8 BL |
1399 | static void sata_fsl_host_stop(struct ata_host *host) |
1400 | { | |
1401 | struct sata_fsl_host_priv *host_priv = host->private_data; | |
1402 | ||
1403 | iounmap(host_priv->hcr_base); | |
1404 | kfree(host_priv); | |
1405 | } | |
1406 | ||
faf0b2e5 LY |
1407 | /* |
1408 | * scsi mid-layer and libata interface structures | |
1409 | */ | |
1410 | static struct scsi_host_template sata_fsl_sht = { | |
68d1d07b | 1411 | ATA_NCQ_SHT("sata_fsl"), |
faf0b2e5 | 1412 | .can_queue = SATA_FSL_QUEUE_DEPTH, |
faf0b2e5 | 1413 | .sg_tablesize = SATA_FSL_MAX_PRD_USABLE, |
faf0b2e5 | 1414 | .dma_boundary = ATA_DMA_BOUNDARY, |
faf0b2e5 LY |
1415 | }; |
1416 | ||
034d8e8f AK |
1417 | static struct ata_port_operations sata_fsl_ops = { |
1418 | .inherits = &sata_pmp_port_ops, | |
029cfd6b | 1419 | |
f90f613c | 1420 | .qc_defer = ata_std_qc_defer, |
faf0b2e5 LY |
1421 | .qc_prep = sata_fsl_qc_prep, |
1422 | .qc_issue = sata_fsl_qc_issue, | |
4c9bf4e7 | 1423 | .qc_fill_rtf = sata_fsl_qc_fill_rtf, |
faf0b2e5 LY |
1424 | |
1425 | .scr_read = sata_fsl_scr_read, | |
1426 | .scr_write = sata_fsl_scr_write, | |
1427 | ||
1428 | .freeze = sata_fsl_freeze, | |
1429 | .thaw = sata_fsl_thaw, | |
a1efdaba | 1430 | .softreset = sata_fsl_softreset, |
a0a74d1e | 1431 | .hardreset = sata_fsl_hardreset, |
034d8e8f AK |
1432 | .pmp_softreset = sata_fsl_softreset, |
1433 | .error_handler = sata_fsl_error_handler, | |
faf0b2e5 LY |
1434 | .post_internal_cmd = sata_fsl_post_internal_cmd, |
1435 | ||
1436 | .port_start = sata_fsl_port_start, | |
1437 | .port_stop = sata_fsl_port_stop, | |
034d8e8f | 1438 | |
6c8ad7e8 BL |
1439 | .host_stop = sata_fsl_host_stop, |
1440 | ||
034d8e8f AK |
1441 | .pmp_attach = sata_fsl_pmp_attach, |
1442 | .pmp_detach = sata_fsl_pmp_detach, | |
faf0b2e5 LY |
1443 | }; |
1444 | ||
1445 | static const struct ata_port_info sata_fsl_port_info[] = { | |
1446 | { | |
1447 | .flags = SATA_FSL_HOST_FLAGS, | |
14bdef98 EIB |
1448 | .pio_mask = ATA_PIO4, |
1449 | .udma_mask = ATA_UDMA6, | |
faf0b2e5 LY |
1450 | .port_ops = &sata_fsl_ops, |
1451 | }, | |
1452 | }; | |
1453 | ||
1c48a5c9 | 1454 | static int sata_fsl_probe(struct platform_device *ofdev) |
faf0b2e5 | 1455 | { |
e4ac522b | 1456 | int retval = -ENXIO; |
faf0b2e5 LY |
1457 | void __iomem *hcr_base = NULL; |
1458 | void __iomem *ssr_base = NULL; | |
1459 | void __iomem *csr_base = NULL; | |
1460 | struct sata_fsl_host_priv *host_priv = NULL; | |
faf0b2e5 | 1461 | int irq; |
6b4b8fc8 | 1462 | struct ata_host *host = NULL; |
578ca87c | 1463 | u32 temp; |
faf0b2e5 LY |
1464 | |
1465 | struct ata_port_info pi = sata_fsl_port_info[0]; | |
1466 | const struct ata_port_info *ppi[] = { &pi, NULL }; | |
1467 | ||
a44fec1f | 1468 | dev_info(&ofdev->dev, "Sata FSL Platform/CSB Driver init\n"); |
faf0b2e5 | 1469 | |
61c7a080 | 1470 | hcr_base = of_iomap(ofdev->dev.of_node, 0); |
faf0b2e5 LY |
1471 | if (!hcr_base) |
1472 | goto error_exit_with_cleanup; | |
1473 | ||
1474 | ssr_base = hcr_base + 0x100; | |
1475 | csr_base = hcr_base + 0x140; | |
1476 | ||
578ca87c PK |
1477 | if (!of_device_is_compatible(ofdev->dev.of_node, "fsl,mpc8315-sata")) { |
1478 | temp = ioread32(csr_base + TRANSCFG); | |
1479 | temp = temp & 0xffffffe0; | |
1480 | iowrite32(temp | TRANSCFG_RX_WATER_MARK, csr_base + TRANSCFG); | |
1481 | } | |
1482 | ||
faf0b2e5 LY |
1483 | DPRINTK("@reset i/o = 0x%x\n", ioread32(csr_base + TRANSCFG)); |
1484 | DPRINTK("sizeof(cmd_desc) = %d\n", sizeof(struct command_desc)); | |
1485 | DPRINTK("sizeof(#define cmd_desc) = %d\n", SATA_FSL_CMD_DESC_SIZE); | |
1486 | ||
1487 | host_priv = kzalloc(sizeof(struct sata_fsl_host_priv), GFP_KERNEL); | |
1488 | if (!host_priv) | |
1489 | goto error_exit_with_cleanup; | |
1490 | ||
1491 | host_priv->hcr_base = hcr_base; | |
1492 | host_priv->ssr_base = ssr_base; | |
1493 | host_priv->csr_base = csr_base; | |
1494 | ||
6f48394c BL |
1495 | irq = platform_get_irq(ofdev, 0); |
1496 | if (irq < 0) { | |
1497 | retval = irq; | |
faf0b2e5 LY |
1498 | goto error_exit_with_cleanup; |
1499 | } | |
79b3edc9 | 1500 | host_priv->irq = irq; |
faf0b2e5 | 1501 | |
2f957fc9 X |
1502 | if (of_device_is_compatible(ofdev->dev.of_node, "fsl,pq-sata-v2")) |
1503 | host_priv->data_snoop = DATA_SNOOP_ENABLE_V2; | |
1504 | else | |
1505 | host_priv->data_snoop = DATA_SNOOP_ENABLE_V1; | |
1506 | ||
faf0b2e5 LY |
1507 | /* allocate host structure */ |
1508 | host = ata_host_alloc_pinfo(&ofdev->dev, ppi, SATA_FSL_MAX_PORTS); | |
6b4b8fc8 QL |
1509 | if (!host) { |
1510 | retval = -ENOMEM; | |
1511 | goto error_exit_with_cleanup; | |
1512 | } | |
faf0b2e5 LY |
1513 | |
1514 | /* host->iomap is not used currently */ | |
1515 | host->private_data = host_priv; | |
1516 | ||
faf0b2e5 LY |
1517 | /* initialize host controller */ |
1518 | sata_fsl_init_controller(host); | |
1519 | ||
1520 | /* | |
1521 | * Now, register with libATA core, this will also initiate the | |
1522 | * device discovery process, invoking our port_start() handler & | |
1523 | * error_handler() to execute a dummy Softreset EH session | |
1524 | */ | |
1525 | ata_host_activate(host, irq, sata_fsl_interrupt, SATA_FSL_IRQ_FLAG, | |
1526 | &sata_fsl_sht); | |
1527 | ||
6b4b8fc8 QL |
1528 | host_priv->intr_coalescing.show = fsl_sata_intr_coalescing_show; |
1529 | host_priv->intr_coalescing.store = fsl_sata_intr_coalescing_store; | |
1530 | sysfs_attr_init(&host_priv->intr_coalescing.attr); | |
1531 | host_priv->intr_coalescing.attr.name = "intr_coalescing"; | |
1532 | host_priv->intr_coalescing.attr.mode = S_IRUGO | S_IWUSR; | |
1533 | retval = device_create_file(host->dev, &host_priv->intr_coalescing); | |
1534 | if (retval) | |
1535 | goto error_exit_with_cleanup; | |
1536 | ||
7551c40d QL |
1537 | host_priv->rx_watermark.show = fsl_sata_rx_watermark_show; |
1538 | host_priv->rx_watermark.store = fsl_sata_rx_watermark_store; | |
1539 | sysfs_attr_init(&host_priv->rx_watermark.attr); | |
1540 | host_priv->rx_watermark.attr.name = "rx_watermark"; | |
1541 | host_priv->rx_watermark.attr.mode = S_IRUGO | S_IWUSR; | |
1542 | retval = device_create_file(host->dev, &host_priv->rx_watermark); | |
1543 | if (retval) { | |
1544 | device_remove_file(&ofdev->dev, &host_priv->intr_coalescing); | |
1545 | goto error_exit_with_cleanup; | |
1546 | } | |
1547 | ||
faf0b2e5 LY |
1548 | return 0; |
1549 | ||
1550 | error_exit_with_cleanup: | |
1551 | ||
d89995db | 1552 | if (host) |
6b4b8fc8 | 1553 | ata_host_detach(host); |
6b4b8fc8 | 1554 | |
faf0b2e5 LY |
1555 | if (hcr_base) |
1556 | iounmap(hcr_base); | |
c99cc9a2 | 1557 | kfree(host_priv); |
faf0b2e5 LY |
1558 | |
1559 | return retval; | |
1560 | } | |
1561 | ||
2dc11581 | 1562 | static int sata_fsl_remove(struct platform_device *ofdev) |
faf0b2e5 | 1563 | { |
d89995db | 1564 | struct ata_host *host = platform_get_drvdata(ofdev); |
faf0b2e5 LY |
1565 | struct sata_fsl_host_priv *host_priv = host->private_data; |
1566 | ||
6b4b8fc8 | 1567 | device_remove_file(&ofdev->dev, &host_priv->intr_coalescing); |
7551c40d | 1568 | device_remove_file(&ofdev->dev, &host_priv->rx_watermark); |
6b4b8fc8 | 1569 | |
faf0b2e5 LY |
1570 | ata_host_detach(host); |
1571 | ||
faf0b2e5 LY |
1572 | return 0; |
1573 | } | |
1574 | ||
58eb8cd5 | 1575 | #ifdef CONFIG_PM_SLEEP |
2dc11581 | 1576 | static int sata_fsl_suspend(struct platform_device *op, pm_message_t state) |
dc77ad4c | 1577 | { |
d89995db | 1578 | struct ata_host *host = platform_get_drvdata(op); |
dc77ad4c DL |
1579 | return ata_host_suspend(host, state); |
1580 | } | |
1581 | ||
2dc11581 | 1582 | static int sata_fsl_resume(struct platform_device *op) |
dc77ad4c | 1583 | { |
d89995db | 1584 | struct ata_host *host = platform_get_drvdata(op); |
dc77ad4c DL |
1585 | struct sata_fsl_host_priv *host_priv = host->private_data; |
1586 | int ret; | |
1587 | void __iomem *hcr_base = host_priv->hcr_base; | |
1588 | struct ata_port *ap = host->ports[0]; | |
1589 | struct sata_fsl_port_priv *pp = ap->private_data; | |
1590 | ||
1591 | ret = sata_fsl_init_controller(host); | |
1592 | if (ret) { | |
a44fec1f | 1593 | dev_err(&op->dev, "Error initializing hardware\n"); |
dc77ad4c DL |
1594 | return ret; |
1595 | } | |
1596 | ||
1597 | /* Recovery the CHBA register in host controller cmd register set */ | |
1598 | iowrite32(pp->cmdslot_paddr & 0xffffffff, hcr_base + CHBA); | |
1599 | ||
93272b13 JH |
1600 | iowrite32((ioread32(hcr_base + HCONTROL) |
1601 | | HCONTROL_ONLINE_PHY_RST | |
1602 | | HCONTROL_SNOOP_ENABLE | |
1603 | | HCONTROL_PMP_ATTACHED), | |
1604 | hcr_base + HCONTROL); | |
1605 | ||
dc77ad4c DL |
1606 | ata_host_resume(host); |
1607 | return 0; | |
1608 | } | |
1609 | #endif | |
1610 | ||
e3779f6a | 1611 | static const struct of_device_id fsl_sata_match[] = { |
faf0b2e5 | 1612 | { |
96ce1b6d | 1613 | .compatible = "fsl,pq-sata", |
faf0b2e5 | 1614 | }, |
2f957fc9 X |
1615 | { |
1616 | .compatible = "fsl,pq-sata-v2", | |
1617 | }, | |
faf0b2e5 LY |
1618 | {}, |
1619 | }; | |
1620 | ||
1621 | MODULE_DEVICE_TABLE(of, fsl_sata_match); | |
1622 | ||
1c48a5c9 | 1623 | static struct platform_driver fsl_sata_driver = { |
4018294b GL |
1624 | .driver = { |
1625 | .name = "fsl-sata", | |
4018294b GL |
1626 | .of_match_table = fsl_sata_match, |
1627 | }, | |
faf0b2e5 LY |
1628 | .probe = sata_fsl_probe, |
1629 | .remove = sata_fsl_remove, | |
58eb8cd5 | 1630 | #ifdef CONFIG_PM_SLEEP |
dc77ad4c DL |
1631 | .suspend = sata_fsl_suspend, |
1632 | .resume = sata_fsl_resume, | |
1633 | #endif | |
faf0b2e5 LY |
1634 | }; |
1635 | ||
99c8ea3e | 1636 | module_platform_driver(fsl_sata_driver); |
faf0b2e5 LY |
1637 | |
1638 | MODULE_LICENSE("GPL"); | |
1639 | MODULE_AUTHOR("Ashish Kalra, Freescale Semiconductor"); | |
1640 | MODULE_DESCRIPTION("Freescale 3.0Gbps SATA controller low level driver"); | |
1641 | MODULE_VERSION("1.10"); |