Commit | Line | Data |
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669a5db4 JG |
1 | /* |
2 | * pata_via.c - VIA PATA for new ATA layer | |
3 | * (C) 2005-2006 Red Hat Inc | |
4 | * Alan Cox <alan@redhat.com> | |
5 | * | |
6 | * Documentation | |
7 | * Most chipset documentation available under NDA only | |
8 | * | |
9 | * VIA version guide | |
10 | * VIA VT82C561 - early design, uses ata_generic currently | |
11 | * VIA VT82C576 - MWDMA, 33Mhz | |
12 | * VIA VT82C586 - MWDMA, 33Mhz | |
13 | * VIA VT82C586a - Added UDMA to 33Mhz | |
14 | * VIA VT82C586b - UDMA33 | |
15 | * VIA VT82C596a - Nonfunctional UDMA66 | |
16 | * VIA VT82C596b - Working UDMA66 | |
17 | * VIA VT82C686 - Nonfunctional UDMA66 | |
18 | * VIA VT82C686a - Working UDMA66 | |
19 | * VIA VT82C686b - Updated to UDMA100 | |
20 | * VIA VT8231 - UDMA100 | |
21 | * VIA VT8233 - UDMA100 | |
22 | * VIA VT8233a - UDMA133 | |
23 | * VIA VT8233c - UDMA100 | |
24 | * VIA VT8235 - UDMA133 | |
25 | * VIA VT8237 - UDMA133 | |
75f609d2 | 26 | * VIA VT8251 - UDMA133 |
669a5db4 JG |
27 | * |
28 | * Most registers remain compatible across chips. Others start reserved | |
29 | * and acquire sensible semantics if set to 1 (eg cable detect). A few | |
30 | * exceptions exist, notably around the FIFO settings. | |
31 | * | |
32 | * One additional quirk of the VIA design is that like ALi they use few | |
33 | * PCI IDs for a lot of chips. | |
34 | * | |
35 | * Based heavily on: | |
36 | * | |
37 | * Version 3.38 | |
38 | * | |
39 | * VIA IDE driver for Linux. Supported southbridges: | |
40 | * | |
41 | * vt82c576, vt82c586, vt82c586a, vt82c586b, vt82c596a, vt82c596b, | |
42 | * vt82c686, vt82c686a, vt82c686b, vt8231, vt8233, vt8233c, vt8233a, | |
43 | * vt8235, vt8237 | |
44 | * | |
45 | * Copyright (c) 2000-2002 Vojtech Pavlik | |
46 | * | |
47 | * Based on the work of: | |
48 | * Michel Aubry | |
49 | * Jeff Garzik | |
50 | * Andre Hedrick | |
51 | ||
52 | */ | |
53 | ||
54 | #include <linux/kernel.h> | |
55 | #include <linux/module.h> | |
56 | #include <linux/pci.h> | |
57 | #include <linux/init.h> | |
58 | #include <linux/blkdev.h> | |
59 | #include <linux/delay.h> | |
60 | #include <scsi/scsi_host.h> | |
61 | #include <linux/libata.h> | |
62 | ||
63 | #define DRV_NAME "pata_via" | |
627d2d32 | 64 | #define DRV_VERSION "0.2.0" |
669a5db4 JG |
65 | |
66 | /* | |
67 | * The following comes directly from Vojtech Pavlik's ide/pci/via82cxxx | |
68 | * driver. | |
69 | */ | |
70 | ||
71 | enum { | |
72 | VIA_UDMA = 0x007, | |
73 | VIA_UDMA_NONE = 0x000, | |
74 | VIA_UDMA_33 = 0x001, | |
75 | VIA_UDMA_66 = 0x002, | |
76 | VIA_UDMA_100 = 0x003, | |
77 | VIA_UDMA_133 = 0x004, | |
78 | VIA_BAD_PREQ = 0x010, /* Crashes if PREQ# till DDACK# set */ | |
79 | VIA_BAD_CLK66 = 0x020, /* 66 MHz clock doesn't work correctly */ | |
80 | VIA_SET_FIFO = 0x040, /* Needs to have FIFO split set */ | |
81 | VIA_NO_UNMASK = 0x080, /* Doesn't work with IRQ unmasking on */ | |
82 | VIA_BAD_ID = 0x100, /* Has wrong vendor ID (0x1107) */ | |
83 | VIA_BAD_AST = 0x200, /* Don't touch Address Setup Timing */ | |
84 | VIA_NO_ENABLES = 0x400, /* Has no enablebits */ | |
85 | }; | |
86 | ||
87 | /* | |
88 | * VIA SouthBridge chips. | |
89 | */ | |
90 | ||
91 | static const struct via_isa_bridge { | |
92 | const char *name; | |
93 | u16 id; | |
94 | u8 rev_min; | |
95 | u8 rev_max; | |
96 | u16 flags; | |
97 | } via_isa_bridges[] = { | |
75f609d2 | 98 | { "vt8251", PCI_DEVICE_ID_VIA_8251, 0x00, 0x2f, VIA_UDMA_133 | VIA_BAD_AST }, |
669a5db4 JG |
99 | { "cx700", PCI_DEVICE_ID_VIA_CX700, 0x00, 0x2f, VIA_UDMA_133 | VIA_BAD_AST }, |
100 | { "vt6410", PCI_DEVICE_ID_VIA_6410, 0x00, 0x2f, VIA_UDMA_133 | VIA_BAD_AST | VIA_NO_ENABLES}, | |
101 | { "vt8237a", PCI_DEVICE_ID_VIA_8237A, 0x00, 0x2f, VIA_UDMA_133 | VIA_BAD_AST }, | |
102 | { "vt8237", PCI_DEVICE_ID_VIA_8237, 0x00, 0x2f, VIA_UDMA_133 | VIA_BAD_AST }, | |
103 | { "vt8235", PCI_DEVICE_ID_VIA_8235, 0x00, 0x2f, VIA_UDMA_133 | VIA_BAD_AST }, | |
104 | { "vt8233a", PCI_DEVICE_ID_VIA_8233A, 0x00, 0x2f, VIA_UDMA_133 | VIA_BAD_AST }, | |
105 | { "vt8233c", PCI_DEVICE_ID_VIA_8233C_0, 0x00, 0x2f, VIA_UDMA_100 }, | |
106 | { "vt8233", PCI_DEVICE_ID_VIA_8233_0, 0x00, 0x2f, VIA_UDMA_100 }, | |
107 | { "vt8231", PCI_DEVICE_ID_VIA_8231, 0x00, 0x2f, VIA_UDMA_100 }, | |
108 | { "vt82c686b", PCI_DEVICE_ID_VIA_82C686, 0x40, 0x4f, VIA_UDMA_100 }, | |
109 | { "vt82c686a", PCI_DEVICE_ID_VIA_82C686, 0x10, 0x2f, VIA_UDMA_66 }, | |
110 | { "vt82c686", PCI_DEVICE_ID_VIA_82C686, 0x00, 0x0f, VIA_UDMA_33 | VIA_BAD_CLK66 }, | |
111 | { "vt82c596b", PCI_DEVICE_ID_VIA_82C596, 0x10, 0x2f, VIA_UDMA_66 }, | |
112 | { "vt82c596a", PCI_DEVICE_ID_VIA_82C596, 0x00, 0x0f, VIA_UDMA_33 | VIA_BAD_CLK66 }, | |
113 | { "vt82c586b", PCI_DEVICE_ID_VIA_82C586_0, 0x47, 0x4f, VIA_UDMA_33 | VIA_SET_FIFO }, | |
114 | { "vt82c586b", PCI_DEVICE_ID_VIA_82C586_0, 0x40, 0x46, VIA_UDMA_33 | VIA_SET_FIFO | VIA_BAD_PREQ }, | |
115 | { "vt82c586b", PCI_DEVICE_ID_VIA_82C586_0, 0x30, 0x3f, VIA_UDMA_33 | VIA_SET_FIFO }, | |
116 | { "vt82c586a", PCI_DEVICE_ID_VIA_82C586_0, 0x20, 0x2f, VIA_UDMA_33 | VIA_SET_FIFO }, | |
117 | { "vt82c586", PCI_DEVICE_ID_VIA_82C586_0, 0x00, 0x0f, VIA_UDMA_NONE | VIA_SET_FIFO }, | |
118 | { "vt82c576", PCI_DEVICE_ID_VIA_82C576, 0x00, 0x2f, VIA_UDMA_NONE | VIA_SET_FIFO | VIA_NO_UNMASK }, | |
119 | { "vt82c576", PCI_DEVICE_ID_VIA_82C576, 0x00, 0x2f, VIA_UDMA_NONE | VIA_SET_FIFO | VIA_NO_UNMASK | VIA_BAD_ID }, | |
120 | { NULL } | |
121 | }; | |
122 | ||
123 | /** | |
124 | * via_cable_detect - cable detection | |
125 | * @ap: ATA port | |
126 | * | |
127 | * Perform cable detection. Actually for the VIA case the BIOS | |
128 | * already did this for us. We read the values provided by the | |
129 | * BIOS. If you are using an 8235 in a non-PC configuration you | |
130 | * may need to update this code. | |
131 | * | |
132 | * Hotplug also impacts on this. | |
133 | */ | |
134 | ||
135 | static int via_cable_detect(struct ata_port *ap) { | |
136 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); | |
137 | u32 ata66; | |
138 | ||
139 | pci_read_config_dword(pdev, 0x50, &ata66); | |
140 | /* Check both the drive cable reporting bits, we might not have | |
141 | two drives */ | |
142 | if (ata66 & (0x10100000 >> (16 * ap->port_no))) | |
143 | return ATA_CBL_PATA80; | |
144 | else | |
145 | return ATA_CBL_PATA40; | |
146 | } | |
147 | ||
148 | static int via_pre_reset(struct ata_port *ap) | |
149 | { | |
150 | const struct via_isa_bridge *config = ap->host->private_data; | |
151 | ||
152 | if (!(config->flags & VIA_NO_ENABLES)) { | |
153 | static const struct pci_bits via_enable_bits[] = { | |
154 | { 0x40, 1, 0x02, 0x02 }, | |
155 | { 0x40, 1, 0x01, 0x01 } | |
156 | }; | |
157 | ||
158 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); | |
85cd7251 | 159 | |
c961922b AC |
160 | if (!pci_test_config_bits(pdev, &via_enable_bits[ap->port_no])) |
161 | return -ENOENT; | |
669a5db4 JG |
162 | } |
163 | ||
5c9a7611 | 164 | if ((config->flags & VIA_UDMA) >= VIA_UDMA_100) |
669a5db4 | 165 | ap->cbl = via_cable_detect(ap); |
5c9a7611 A |
166 | /* The UDMA66 series has no cable detect so do drive side detect */ |
167 | else if ((config->flags & VIA_UDMA) < VIA_UDMA_66) | |
669a5db4 | 168 | ap->cbl = ATA_CBL_PATA40; |
5c9a7611 A |
169 | else |
170 | ap->cbl = ATA_CBL_PATA_UNK; | |
171 | ||
172 | ||
669a5db4 JG |
173 | return ata_std_prereset(ap); |
174 | } | |
175 | ||
176 | ||
177 | /** | |
178 | * via_error_handler - reset for VIA chips | |
179 | * @ap: ATA port | |
180 | * | |
181 | * Handle the reset callback for the later chips with cable detect | |
182 | */ | |
183 | ||
184 | static void via_error_handler(struct ata_port *ap) | |
185 | { | |
186 | ata_bmdma_drive_eh(ap, via_pre_reset, ata_std_softreset, NULL, ata_std_postreset); | |
187 | } | |
188 | ||
189 | /** | |
190 | * via_do_set_mode - set initial PIO mode data | |
191 | * @ap: ATA interface | |
192 | * @adev: ATA device | |
193 | * @mode: ATA mode being programmed | |
194 | * @tdiv: Clocks per PCI clock | |
195 | * @set_ast: Set to program address setup | |
196 | * @udma_type: UDMA mode/format of registers | |
197 | * | |
198 | * Program the VIA registers for DMA and PIO modes. Uses the ata timing | |
199 | * support in order to compute modes. | |
200 | * | |
201 | * FIXME: Hotplug will require we serialize multiple mode changes | |
202 | * on the two channels. | |
203 | */ | |
204 | ||
205 | static void via_do_set_mode(struct ata_port *ap, struct ata_device *adev, int mode, int tdiv, int set_ast, int udma_type) | |
206 | { | |
207 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); | |
208 | struct ata_device *peer = ata_dev_pair(adev); | |
209 | struct ata_timing t, p; | |
210 | static int via_clock = 33333; /* Bus clock in kHZ - ought to be tunable one day */ | |
211 | unsigned long T = 1000000000 / via_clock; | |
212 | unsigned long UT = T/tdiv; | |
213 | int ut; | |
214 | int offset = 3 - (2*ap->port_no) - adev->devno; | |
215 | ||
216 | ||
217 | /* Calculate the timing values we require */ | |
218 | ata_timing_compute(adev, mode, &t, T, UT); | |
219 | ||
220 | /* We share 8bit timing so we must merge the constraints */ | |
221 | if (peer) { | |
222 | if (peer->pio_mode) { | |
223 | ata_timing_compute(peer, peer->pio_mode, &p, T, UT); | |
224 | ata_timing_merge(&p, &t, &t, ATA_TIMING_8BIT); | |
225 | } | |
226 | } | |
227 | ||
228 | /* Address setup is programmable but breaks on UDMA133 setups */ | |
229 | if (set_ast) { | |
230 | u8 setup; /* 2 bits per drive */ | |
231 | int shift = 2 * offset; | |
232 | ||
233 | pci_read_config_byte(pdev, 0x4C, &setup); | |
234 | setup &= ~(3 << shift); | |
235 | setup |= FIT(t.setup, 1, 4) << shift; /* 1,4 or 1,4 - 1 FIXME */ | |
236 | pci_write_config_byte(pdev, 0x4C, setup); | |
237 | } | |
238 | ||
239 | /* Load the PIO mode bits */ | |
240 | pci_write_config_byte(pdev, 0x4F - ap->port_no, | |
241 | ((FIT(t.act8b, 1, 16) - 1) << 4) | (FIT(t.rec8b, 1, 16) - 1)); | |
242 | pci_write_config_byte(pdev, 0x48 + offset, | |
243 | ((FIT(t.active, 1, 16) - 1) << 4) | (FIT(t.recover, 1, 16) - 1)); | |
244 | ||
245 | /* Load the UDMA bits according to type */ | |
246 | switch(udma_type) { | |
247 | default: | |
248 | /* BUG() ? */ | |
249 | /* fall through */ | |
250 | case 33: | |
251 | ut = t.udma ? (0xe0 | (FIT(t.udma, 2, 5) - 2)) : 0x03; | |
252 | break; | |
253 | case 66: | |
254 | ut = t.udma ? (0xe8 | (FIT(t.udma, 2, 9) - 2)) : 0x0f; | |
255 | break; | |
256 | case 100: | |
257 | ut = t.udma ? (0xe0 | (FIT(t.udma, 2, 9) - 2)) : 0x07; | |
258 | break; | |
259 | case 133: | |
260 | ut = t.udma ? (0xe0 | (FIT(t.udma, 2, 9) - 2)) : 0x07; | |
261 | break; | |
262 | } | |
263 | /* Set UDMA unless device is not UDMA capable */ | |
264 | if (udma_type) | |
265 | pci_write_config_byte(pdev, 0x50 + offset, ut); | |
266 | } | |
267 | ||
268 | static void via_set_piomode(struct ata_port *ap, struct ata_device *adev) | |
269 | { | |
270 | const struct via_isa_bridge *config = ap->host->private_data; | |
271 | int set_ast = (config->flags & VIA_BAD_AST) ? 0 : 1; | |
272 | int mode = config->flags & VIA_UDMA; | |
273 | static u8 tclock[5] = { 1, 1, 2, 3, 4 }; | |
274 | static u8 udma[5] = { 0, 33, 66, 100, 133 }; | |
275 | ||
276 | via_do_set_mode(ap, adev, adev->pio_mode, tclock[mode], set_ast, udma[mode]); | |
277 | } | |
278 | ||
279 | static void via_set_dmamode(struct ata_port *ap, struct ata_device *adev) | |
280 | { | |
281 | const struct via_isa_bridge *config = ap->host->private_data; | |
282 | int set_ast = (config->flags & VIA_BAD_AST) ? 0 : 1; | |
283 | int mode = config->flags & VIA_UDMA; | |
284 | static u8 tclock[5] = { 1, 1, 2, 3, 4 }; | |
285 | static u8 udma[5] = { 0, 33, 66, 100, 133 }; | |
286 | ||
287 | via_do_set_mode(ap, adev, adev->dma_mode, tclock[mode], set_ast, udma[mode]); | |
288 | } | |
289 | ||
290 | static struct scsi_host_template via_sht = { | |
291 | .module = THIS_MODULE, | |
292 | .name = DRV_NAME, | |
293 | .ioctl = ata_scsi_ioctl, | |
294 | .queuecommand = ata_scsi_queuecmd, | |
295 | .can_queue = ATA_DEF_QUEUE, | |
296 | .this_id = ATA_SHT_THIS_ID, | |
297 | .sg_tablesize = LIBATA_MAX_PRD, | |
669a5db4 JG |
298 | .cmd_per_lun = ATA_SHT_CMD_PER_LUN, |
299 | .emulated = ATA_SHT_EMULATED, | |
300 | .use_clustering = ATA_SHT_USE_CLUSTERING, | |
301 | .proc_name = DRV_NAME, | |
302 | .dma_boundary = ATA_DMA_BOUNDARY, | |
303 | .slave_configure = ata_scsi_slave_config, | |
afdfe899 | 304 | .slave_destroy = ata_scsi_slave_destroy, |
669a5db4 | 305 | .bios_param = ata_std_bios_param, |
627d2d32 A |
306 | .resume = ata_scsi_device_resume, |
307 | .suspend = ata_scsi_device_suspend, | |
669a5db4 JG |
308 | }; |
309 | ||
310 | static struct ata_port_operations via_port_ops = { | |
311 | .port_disable = ata_port_disable, | |
312 | .set_piomode = via_set_piomode, | |
313 | .set_dmamode = via_set_dmamode, | |
314 | .mode_filter = ata_pci_default_filter, | |
315 | ||
316 | .tf_load = ata_tf_load, | |
317 | .tf_read = ata_tf_read, | |
318 | .check_status = ata_check_status, | |
319 | .exec_command = ata_exec_command, | |
320 | .dev_select = ata_std_dev_select, | |
321 | ||
322 | .freeze = ata_bmdma_freeze, | |
323 | .thaw = ata_bmdma_thaw, | |
324 | .error_handler = via_error_handler, | |
325 | .post_internal_cmd = ata_bmdma_post_internal_cmd, | |
326 | ||
327 | .bmdma_setup = ata_bmdma_setup, | |
328 | .bmdma_start = ata_bmdma_start, | |
329 | .bmdma_stop = ata_bmdma_stop, | |
330 | .bmdma_status = ata_bmdma_status, | |
331 | ||
332 | .qc_prep = ata_qc_prep, | |
333 | .qc_issue = ata_qc_issue_prot, | |
bda30288 | 334 | |
669a5db4 JG |
335 | .data_xfer = ata_pio_data_xfer, |
336 | ||
337 | .irq_handler = ata_interrupt, | |
338 | .irq_clear = ata_bmdma_irq_clear, | |
339 | ||
340 | .port_start = ata_port_start, | |
341 | .port_stop = ata_port_stop, | |
342 | .host_stop = ata_host_stop | |
343 | }; | |
344 | ||
345 | static struct ata_port_operations via_port_ops_noirq = { | |
346 | .port_disable = ata_port_disable, | |
347 | .set_piomode = via_set_piomode, | |
348 | .set_dmamode = via_set_dmamode, | |
349 | .mode_filter = ata_pci_default_filter, | |
350 | ||
351 | .tf_load = ata_tf_load, | |
352 | .tf_read = ata_tf_read, | |
353 | .check_status = ata_check_status, | |
354 | .exec_command = ata_exec_command, | |
355 | .dev_select = ata_std_dev_select, | |
356 | ||
357 | .freeze = ata_bmdma_freeze, | |
358 | .thaw = ata_bmdma_thaw, | |
359 | .error_handler = via_error_handler, | |
360 | .post_internal_cmd = ata_bmdma_post_internal_cmd, | |
361 | ||
362 | .bmdma_setup = ata_bmdma_setup, | |
363 | .bmdma_start = ata_bmdma_start, | |
364 | .bmdma_stop = ata_bmdma_stop, | |
365 | .bmdma_status = ata_bmdma_status, | |
366 | ||
367 | .qc_prep = ata_qc_prep, | |
368 | .qc_issue = ata_qc_issue_prot, | |
bda30288 | 369 | |
669a5db4 JG |
370 | .data_xfer = ata_pio_data_xfer_noirq, |
371 | ||
372 | .irq_handler = ata_interrupt, | |
373 | .irq_clear = ata_bmdma_irq_clear, | |
374 | ||
375 | .port_start = ata_port_start, | |
376 | .port_stop = ata_port_stop, | |
377 | .host_stop = ata_host_stop | |
378 | }; | |
379 | ||
627d2d32 A |
380 | /** |
381 | * via_config_fifo - set up the FIFO | |
382 | * @pdev: PCI device | |
383 | * @flags: configuration flags | |
384 | * | |
385 | * Set the FIFO properties for this device if neccessary. Used both on | |
386 | * set up and on and the resume path | |
387 | */ | |
388 | ||
389 | static void via_config_fifo(struct pci_dev *pdev, unsigned int flags) | |
390 | { | |
391 | u8 enable; | |
392 | ||
393 | /* 0x40 low bits indicate enabled channels */ | |
394 | pci_read_config_byte(pdev, 0x40 , &enable); | |
395 | enable &= 3; | |
396 | ||
397 | if (flags & VIA_SET_FIFO) { | |
398 | u8 fifo_setting[4] = {0x00, 0x60, 0x00, 0x20}; | |
399 | u8 fifo; | |
400 | ||
401 | pci_read_config_byte(pdev, 0x43, &fifo); | |
402 | ||
403 | /* Clear PREQ# until DDACK# for errata */ | |
404 | if (flags & VIA_BAD_PREQ) | |
405 | fifo &= 0x7F; | |
406 | else | |
407 | fifo &= 0x9f; | |
408 | /* Turn on FIFO for enabled channels */ | |
409 | fifo |= fifo_setting[enable]; | |
410 | pci_write_config_byte(pdev, 0x43, fifo); | |
411 | } | |
412 | } | |
413 | ||
669a5db4 JG |
414 | /** |
415 | * via_init_one - discovery callback | |
627d2d32 | 416 | * @pdev: PCI device |
669a5db4 JG |
417 | * @id: PCI table info |
418 | * | |
419 | * A VIA IDE interface has been discovered. Figure out what revision | |
420 | * and perform configuration work before handing it to the ATA layer | |
421 | */ | |
422 | ||
423 | static int via_init_one(struct pci_dev *pdev, const struct pci_device_id *id) | |
424 | { | |
425 | /* Early VIA without UDMA support */ | |
426 | static struct ata_port_info via_mwdma_info = { | |
427 | .sht = &via_sht, | |
3d3cca37 | 428 | .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SETXFER_POLLING, |
669a5db4 JG |
429 | .pio_mask = 0x1f, |
430 | .mwdma_mask = 0x07, | |
431 | .port_ops = &via_port_ops | |
432 | }; | |
433 | /* Ditto with IRQ masking required */ | |
434 | static struct ata_port_info via_mwdma_info_borked = { | |
435 | .sht = &via_sht, | |
3d3cca37 | 436 | .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SETXFER_POLLING, |
669a5db4 JG |
437 | .pio_mask = 0x1f, |
438 | .mwdma_mask = 0x07, | |
439 | .port_ops = &via_port_ops_noirq, | |
440 | }; | |
441 | /* VIA UDMA 33 devices (and borked 66) */ | |
442 | static struct ata_port_info via_udma33_info = { | |
443 | .sht = &via_sht, | |
3d3cca37 | 444 | .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SETXFER_POLLING, |
669a5db4 JG |
445 | .pio_mask = 0x1f, |
446 | .mwdma_mask = 0x07, | |
447 | .udma_mask = 0x7, | |
448 | .port_ops = &via_port_ops | |
449 | }; | |
450 | /* VIA UDMA 66 devices */ | |
451 | static struct ata_port_info via_udma66_info = { | |
452 | .sht = &via_sht, | |
3d3cca37 | 453 | .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SETXFER_POLLING, |
669a5db4 JG |
454 | .pio_mask = 0x1f, |
455 | .mwdma_mask = 0x07, | |
456 | .udma_mask = 0x1f, | |
457 | .port_ops = &via_port_ops | |
458 | }; | |
459 | /* VIA UDMA 100 devices */ | |
460 | static struct ata_port_info via_udma100_info = { | |
461 | .sht = &via_sht, | |
3d3cca37 | 462 | .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SETXFER_POLLING, |
669a5db4 JG |
463 | .pio_mask = 0x1f, |
464 | .mwdma_mask = 0x07, | |
465 | .udma_mask = 0x3f, | |
466 | .port_ops = &via_port_ops | |
467 | }; | |
468 | /* UDMA133 with bad AST (All current 133) */ | |
469 | static struct ata_port_info via_udma133_info = { | |
470 | .sht = &via_sht, | |
3d3cca37 | 471 | .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SETXFER_POLLING, |
669a5db4 JG |
472 | .pio_mask = 0x1f, |
473 | .mwdma_mask = 0x07, | |
474 | .udma_mask = 0x7f, /* FIXME: should check north bridge */ | |
475 | .port_ops = &via_port_ops | |
476 | }; | |
477 | struct ata_port_info *port_info[2], *type; | |
478 | struct pci_dev *isa = NULL; | |
479 | const struct via_isa_bridge *config; | |
480 | static int printed_version; | |
481 | u8 t; | |
482 | u8 enable; | |
483 | u32 timing; | |
484 | ||
485 | if (!printed_version++) | |
486 | dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n"); | |
487 | ||
488 | /* To find out how the IDE will behave and what features we | |
489 | actually have to look at the bridge not the IDE controller */ | |
490 | for (config = via_isa_bridges; config->id; config++) | |
491 | if ((isa = pci_get_device(PCI_VENDOR_ID_VIA + | |
492 | !!(config->flags & VIA_BAD_ID), | |
493 | config->id, NULL))) { | |
494 | ||
495 | pci_read_config_byte(isa, PCI_REVISION_ID, &t); | |
496 | if (t >= config->rev_min && | |
497 | t <= config->rev_max) | |
498 | break; | |
499 | pci_dev_put(isa); | |
500 | } | |
501 | ||
502 | if (!config->id) { | |
503 | printk(KERN_WARNING "via: Unknown VIA SouthBridge, disabling.\n"); | |
504 | return -ENODEV; | |
505 | } | |
506 | pci_dev_put(isa); | |
507 | ||
508 | /* 0x40 low bits indicate enabled channels */ | |
509 | pci_read_config_byte(pdev, 0x40 , &enable); | |
510 | enable &= 3; | |
511 | if (enable == 0) { | |
512 | return -ENODEV; | |
513 | } | |
514 | ||
515 | /* Initialise the FIFO for the enabled channels. */ | |
627d2d32 A |
516 | via_config_fifo(pdev, config->flags); |
517 | ||
669a5db4 JG |
518 | /* Clock set up */ |
519 | switch(config->flags & VIA_UDMA) { | |
520 | case VIA_UDMA_NONE: | |
521 | if (config->flags & VIA_NO_UNMASK) | |
522 | type = &via_mwdma_info_borked; | |
523 | else | |
524 | type = &via_mwdma_info; | |
525 | break; | |
526 | case VIA_UDMA_33: | |
527 | type = &via_udma33_info; | |
528 | break; | |
529 | case VIA_UDMA_66: | |
530 | type = &via_udma66_info; | |
531 | /* The 66 MHz devices require we enable the clock */ | |
532 | pci_read_config_dword(pdev, 0x50, &timing); | |
533 | timing |= 0x80008; | |
534 | pci_write_config_dword(pdev, 0x50, timing); | |
535 | break; | |
536 | case VIA_UDMA_100: | |
537 | type = &via_udma100_info; | |
538 | break; | |
539 | case VIA_UDMA_133: | |
540 | type = &via_udma133_info; | |
541 | break; | |
542 | default: | |
543 | WARN_ON(1); | |
544 | return -ENODEV; | |
545 | } | |
546 | ||
547 | if (config->flags & VIA_BAD_CLK66) { | |
548 | /* Disable the 66MHz clock on problem devices */ | |
549 | pci_read_config_dword(pdev, 0x50, &timing); | |
550 | timing &= ~0x80008; | |
551 | pci_write_config_dword(pdev, 0x50, timing); | |
552 | } | |
553 | ||
554 | /* We have established the device type, now fire it up */ | |
555 | type->private_data = (void *)config; | |
556 | ||
557 | port_info[0] = port_info[1] = type; | |
558 | return ata_pci_init_one(pdev, port_info, 2); | |
559 | } | |
560 | ||
627d2d32 A |
561 | /** |
562 | * via_reinit_one - reinit after resume | |
563 | * @pdev; PCI device | |
564 | * | |
565 | * Called when the VIA PATA device is resumed. We must then | |
566 | * reconfigure the fifo and other setup we may have altered. In | |
567 | * addition the kernel needs to have the resume methods on PCI | |
568 | * quirk supported. | |
569 | */ | |
570 | ||
571 | static int via_reinit_one(struct pci_dev *pdev) | |
572 | { | |
573 | u32 timing; | |
574 | struct ata_host *host = dev_get_drvdata(&pdev->dev); | |
575 | const struct via_isa_bridge *config = host->private_data; | |
576 | ||
577 | via_config_fifo(pdev, config->flags); | |
578 | ||
579 | if ((config->flags & VIA_UDMA) == VIA_UDMA_66) { | |
580 | /* The 66 MHz devices require we enable the clock */ | |
581 | pci_read_config_dword(pdev, 0x50, &timing); | |
582 | timing |= 0x80008; | |
583 | pci_write_config_dword(pdev, 0x50, timing); | |
584 | } | |
585 | if (config->flags & VIA_BAD_CLK66) { | |
586 | /* Disable the 66MHz clock on problem devices */ | |
587 | pci_read_config_dword(pdev, 0x50, &timing); | |
588 | timing &= ~0x80008; | |
589 | pci_write_config_dword(pdev, 0x50, timing); | |
590 | } | |
591 | return ata_pci_device_resume(pdev); | |
592 | } | |
593 | ||
669a5db4 | 594 | static const struct pci_device_id via[] = { |
2d2744fc JG |
595 | { PCI_VDEVICE(VIA, PCI_DEVICE_ID_VIA_82C576_1), }, |
596 | { PCI_VDEVICE(VIA, PCI_DEVICE_ID_VIA_82C586_1), }, | |
597 | { PCI_VDEVICE(VIA, PCI_DEVICE_ID_VIA_6410), }, | |
598 | { PCI_VDEVICE(VIA, PCI_DEVICE_ID_VIA_SATA_EIDE), }, | |
599 | ||
600 | { }, | |
669a5db4 JG |
601 | }; |
602 | ||
603 | static struct pci_driver via_pci_driver = { | |
2d2744fc | 604 | .name = DRV_NAME, |
669a5db4 JG |
605 | .id_table = via, |
606 | .probe = via_init_one, | |
627d2d32 A |
607 | .remove = ata_pci_remove_one, |
608 | .suspend = ata_pci_device_suspend, | |
609 | .resume = via_reinit_one, | |
669a5db4 JG |
610 | }; |
611 | ||
612 | static int __init via_init(void) | |
613 | { | |
614 | return pci_register_driver(&via_pci_driver); | |
615 | } | |
616 | ||
669a5db4 JG |
617 | static void __exit via_exit(void) |
618 | { | |
619 | pci_unregister_driver(&via_pci_driver); | |
620 | } | |
621 | ||
669a5db4 JG |
622 | MODULE_AUTHOR("Alan Cox"); |
623 | MODULE_DESCRIPTION("low-level driver for VIA PATA"); | |
624 | MODULE_LICENSE("GPL"); | |
625 | MODULE_DEVICE_TABLE(pci, via); | |
626 | MODULE_VERSION(DRV_VERSION); | |
627 | ||
628 | module_init(via_init); | |
629 | module_exit(via_exit); |