Commit | Line | Data |
---|---|---|
669a5db4 JG |
1 | /* |
2 | * pata_via.c - VIA PATA for new ATA layer | |
3 | * (C) 2005-2006 Red Hat Inc | |
669a5db4 JG |
4 | * |
5 | * Documentation | |
6 | * Most chipset documentation available under NDA only | |
7 | * | |
8 | * VIA version guide | |
9 | * VIA VT82C561 - early design, uses ata_generic currently | |
10 | * VIA VT82C576 - MWDMA, 33Mhz | |
11 | * VIA VT82C586 - MWDMA, 33Mhz | |
12 | * VIA VT82C586a - Added UDMA to 33Mhz | |
13 | * VIA VT82C586b - UDMA33 | |
14 | * VIA VT82C596a - Nonfunctional UDMA66 | |
15 | * VIA VT82C596b - Working UDMA66 | |
16 | * VIA VT82C686 - Nonfunctional UDMA66 | |
17 | * VIA VT82C686a - Working UDMA66 | |
18 | * VIA VT82C686b - Updated to UDMA100 | |
19 | * VIA VT8231 - UDMA100 | |
20 | * VIA VT8233 - UDMA100 | |
21 | * VIA VT8233a - UDMA133 | |
22 | * VIA VT8233c - UDMA100 | |
23 | * VIA VT8235 - UDMA133 | |
24 | * VIA VT8237 - UDMA133 | |
05c39e50 | 25 | * VIA VT8237S - UDMA133 |
75f609d2 | 26 | * VIA VT8251 - UDMA133 |
669a5db4 JG |
27 | * |
28 | * Most registers remain compatible across chips. Others start reserved | |
29 | * and acquire sensible semantics if set to 1 (eg cable detect). A few | |
30 | * exceptions exist, notably around the FIFO settings. | |
31 | * | |
32 | * One additional quirk of the VIA design is that like ALi they use few | |
33 | * PCI IDs for a lot of chips. | |
34 | * | |
35 | * Based heavily on: | |
36 | * | |
37 | * Version 3.38 | |
38 | * | |
39 | * VIA IDE driver for Linux. Supported southbridges: | |
40 | * | |
41 | * vt82c576, vt82c586, vt82c586a, vt82c586b, vt82c596a, vt82c596b, | |
42 | * vt82c686, vt82c686a, vt82c686b, vt8231, vt8233, vt8233c, vt8233a, | |
43 | * vt8235, vt8237 | |
44 | * | |
45 | * Copyright (c) 2000-2002 Vojtech Pavlik | |
46 | * | |
47 | * Based on the work of: | |
48 | * Michel Aubry | |
49 | * Jeff Garzik | |
50 | * Andre Hedrick | |
51 | ||
52 | */ | |
53 | ||
54 | #include <linux/kernel.h> | |
55 | #include <linux/module.h> | |
56 | #include <linux/pci.h> | |
57 | #include <linux/init.h> | |
58 | #include <linux/blkdev.h> | |
59 | #include <linux/delay.h> | |
60 | #include <scsi/scsi_host.h> | |
61 | #include <linux/libata.h> | |
cf5792d2 | 62 | #include <linux/dmi.h> |
669a5db4 JG |
63 | |
64 | #define DRV_NAME "pata_via" | |
b4746ed7 | 65 | #define DRV_VERSION "0.3.4" |
669a5db4 JG |
66 | |
67 | /* | |
68 | * The following comes directly from Vojtech Pavlik's ide/pci/via82cxxx | |
69 | * driver. | |
70 | */ | |
71 | ||
72 | enum { | |
73 | VIA_UDMA = 0x007, | |
74 | VIA_UDMA_NONE = 0x000, | |
75 | VIA_UDMA_33 = 0x001, | |
76 | VIA_UDMA_66 = 0x002, | |
77 | VIA_UDMA_100 = 0x003, | |
78 | VIA_UDMA_133 = 0x004, | |
79 | VIA_BAD_PREQ = 0x010, /* Crashes if PREQ# till DDACK# set */ | |
80 | VIA_BAD_CLK66 = 0x020, /* 66 MHz clock doesn't work correctly */ | |
81 | VIA_SET_FIFO = 0x040, /* Needs to have FIFO split set */ | |
82 | VIA_NO_UNMASK = 0x080, /* Doesn't work with IRQ unmasking on */ | |
83 | VIA_BAD_ID = 0x100, /* Has wrong vendor ID (0x1107) */ | |
84 | VIA_BAD_AST = 0x200, /* Don't touch Address Setup Timing */ | |
85 | VIA_NO_ENABLES = 0x400, /* Has no enablebits */ | |
7585eb1b | 86 | VIA_SATA_PATA = 0x800, /* SATA/PATA combined configuration */ |
669a5db4 JG |
87 | }; |
88 | ||
e4d866cd J |
89 | enum { |
90 | VIA_IDFLAG_SINGLE = (1 << 0), /* single channel controller) */ | |
91 | }; | |
92 | ||
669a5db4 JG |
93 | /* |
94 | * VIA SouthBridge chips. | |
95 | */ | |
96 | ||
97 | static const struct via_isa_bridge { | |
98 | const char *name; | |
99 | u16 id; | |
100 | u8 rev_min; | |
101 | u8 rev_max; | |
102 | u16 flags; | |
103 | } via_isa_bridges[] = { | |
e4d866cd J |
104 | { "vx855", PCI_DEVICE_ID_VIA_VX855, 0x00, 0x2f, |
105 | VIA_UDMA_133 | VIA_BAD_AST | VIA_SATA_PATA }, | |
bfce5e01 J |
106 | { "vx800", PCI_DEVICE_ID_VIA_VX800, 0x00, 0x2f, VIA_UDMA_133 | |
107 | VIA_BAD_AST | VIA_SATA_PATA }, | |
e4d866cd J |
108 | { "vt8261", PCI_DEVICE_ID_VIA_8261, 0x00, 0x2f, |
109 | VIA_UDMA_133 | VIA_BAD_AST }, | |
e0b874df | 110 | { "vt8237s", PCI_DEVICE_ID_VIA_8237S, 0x00, 0x2f, VIA_UDMA_133 | VIA_BAD_AST }, |
75f609d2 | 111 | { "vt8251", PCI_DEVICE_ID_VIA_8251, 0x00, 0x2f, VIA_UDMA_133 | VIA_BAD_AST }, |
7585eb1b | 112 | { "cx700", PCI_DEVICE_ID_VIA_CX700, 0x00, 0x2f, VIA_UDMA_133 | VIA_BAD_AST | VIA_SATA_PATA }, |
5955c7a2 | 113 | { "vt6410", PCI_DEVICE_ID_VIA_6410, 0x00, 0x2f, VIA_UDMA_133 | VIA_BAD_AST | VIA_NO_ENABLES }, |
7d948b11 | 114 | { "vt6415", PCI_DEVICE_ID_VIA_6415, 0x00, 0xff, VIA_UDMA_133 | VIA_BAD_AST | VIA_NO_ENABLES }, |
669a5db4 JG |
115 | { "vt8237a", PCI_DEVICE_ID_VIA_8237A, 0x00, 0x2f, VIA_UDMA_133 | VIA_BAD_AST }, |
116 | { "vt8237", PCI_DEVICE_ID_VIA_8237, 0x00, 0x2f, VIA_UDMA_133 | VIA_BAD_AST }, | |
117 | { "vt8235", PCI_DEVICE_ID_VIA_8235, 0x00, 0x2f, VIA_UDMA_133 | VIA_BAD_AST }, | |
118 | { "vt8233a", PCI_DEVICE_ID_VIA_8233A, 0x00, 0x2f, VIA_UDMA_133 | VIA_BAD_AST }, | |
119 | { "vt8233c", PCI_DEVICE_ID_VIA_8233C_0, 0x00, 0x2f, VIA_UDMA_100 }, | |
120 | { "vt8233", PCI_DEVICE_ID_VIA_8233_0, 0x00, 0x2f, VIA_UDMA_100 }, | |
121 | { "vt8231", PCI_DEVICE_ID_VIA_8231, 0x00, 0x2f, VIA_UDMA_100 }, | |
122 | { "vt82c686b", PCI_DEVICE_ID_VIA_82C686, 0x40, 0x4f, VIA_UDMA_100 }, | |
123 | { "vt82c686a", PCI_DEVICE_ID_VIA_82C686, 0x10, 0x2f, VIA_UDMA_66 }, | |
124 | { "vt82c686", PCI_DEVICE_ID_VIA_82C686, 0x00, 0x0f, VIA_UDMA_33 | VIA_BAD_CLK66 }, | |
125 | { "vt82c596b", PCI_DEVICE_ID_VIA_82C596, 0x10, 0x2f, VIA_UDMA_66 }, | |
126 | { "vt82c596a", PCI_DEVICE_ID_VIA_82C596, 0x00, 0x0f, VIA_UDMA_33 | VIA_BAD_CLK66 }, | |
127 | { "vt82c586b", PCI_DEVICE_ID_VIA_82C586_0, 0x47, 0x4f, VIA_UDMA_33 | VIA_SET_FIFO }, | |
128 | { "vt82c586b", PCI_DEVICE_ID_VIA_82C586_0, 0x40, 0x46, VIA_UDMA_33 | VIA_SET_FIFO | VIA_BAD_PREQ }, | |
129 | { "vt82c586b", PCI_DEVICE_ID_VIA_82C586_0, 0x30, 0x3f, VIA_UDMA_33 | VIA_SET_FIFO }, | |
130 | { "vt82c586a", PCI_DEVICE_ID_VIA_82C586_0, 0x20, 0x2f, VIA_UDMA_33 | VIA_SET_FIFO }, | |
131 | { "vt82c586", PCI_DEVICE_ID_VIA_82C586_0, 0x00, 0x0f, VIA_UDMA_NONE | VIA_SET_FIFO }, | |
132 | { "vt82c576", PCI_DEVICE_ID_VIA_82C576, 0x00, 0x2f, VIA_UDMA_NONE | VIA_SET_FIFO | VIA_NO_UNMASK }, | |
133 | { "vt82c576", PCI_DEVICE_ID_VIA_82C576, 0x00, 0x2f, VIA_UDMA_NONE | VIA_SET_FIFO | VIA_NO_UNMASK | VIA_BAD_ID }, | |
e4d866cd J |
134 | { "vtxxxx", PCI_DEVICE_ID_VIA_ANON, 0x00, 0x2f, |
135 | VIA_UDMA_133 | VIA_BAD_AST }, | |
669a5db4 JG |
136 | { NULL } |
137 | }; | |
138 | ||
b4746ed7 AC |
139 | struct via_port { |
140 | u8 cached_device; | |
141 | }; | |
cf5792d2 AC |
142 | |
143 | /* | |
144 | * Cable special cases | |
145 | */ | |
146 | ||
1855256c | 147 | static const struct dmi_system_id cable_dmi_table[] = { |
cf5792d2 AC |
148 | { |
149 | .ident = "Acer Ferrari 3400", | |
150 | .matches = { | |
151 | DMI_MATCH(DMI_BOARD_VENDOR, "Acer,Inc."), | |
152 | DMI_MATCH(DMI_BOARD_NAME, "Ferrari 3400"), | |
153 | }, | |
154 | }, | |
155 | { } | |
156 | }; | |
157 | ||
158 | static int via_cable_override(struct pci_dev *pdev) | |
159 | { | |
160 | /* Systems by DMI */ | |
161 | if (dmi_check_system(cable_dmi_table)) | |
162 | return 1; | |
9edbdbea AC |
163 | /* Arima W730-K8/Targa Visionary 811/... */ |
164 | if (pdev->subsystem_vendor == 0x161F && pdev->subsystem_device == 0x2032) | |
165 | return 1; | |
cf5792d2 AC |
166 | return 0; |
167 | } | |
168 | ||
169 | ||
669a5db4 JG |
170 | /** |
171 | * via_cable_detect - cable detection | |
172 | * @ap: ATA port | |
173 | * | |
174 | * Perform cable detection. Actually for the VIA case the BIOS | |
175 | * already did this for us. We read the values provided by the | |
176 | * BIOS. If you are using an 8235 in a non-PC configuration you | |
177 | * may need to update this code. | |
178 | * | |
179 | * Hotplug also impacts on this. | |
180 | */ | |
181 | ||
182 | static int via_cable_detect(struct ata_port *ap) { | |
97cb81c3 | 183 | const struct via_isa_bridge *config = ap->host->private_data; |
669a5db4 JG |
184 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); |
185 | u32 ata66; | |
186 | ||
cf5792d2 AC |
187 | if (via_cable_override(pdev)) |
188 | return ATA_CBL_PATA40_SHORT; | |
189 | ||
7585eb1b TH |
190 | if ((config->flags & VIA_SATA_PATA) && ap->port_no == 0) |
191 | return ATA_CBL_SATA; | |
192 | ||
97cb81c3 AC |
193 | /* Early chips are 40 wire */ |
194 | if ((config->flags & VIA_UDMA) < VIA_UDMA_66) | |
195 | return ATA_CBL_PATA40; | |
196 | /* UDMA 66 chips have only drive side logic */ | |
b447916e | 197 | else if ((config->flags & VIA_UDMA) < VIA_UDMA_100) |
97cb81c3 AC |
198 | return ATA_CBL_PATA_UNK; |
199 | /* UDMA 100 or later */ | |
669a5db4 JG |
200 | pci_read_config_dword(pdev, 0x50, &ata66); |
201 | /* Check both the drive cable reporting bits, we might not have | |
202 | two drives */ | |
203 | if (ata66 & (0x10100000 >> (16 * ap->port_no))) | |
204 | return ATA_CBL_PATA80; | |
7d73a363 | 205 | /* Check with ACPI so we can spot BIOS reported SATA bridges */ |
021ee9a6 TH |
206 | if (ata_acpi_init_gtm(ap) && |
207 | ata_acpi_cbl_80wire(ap, ata_acpi_init_gtm(ap))) | |
7d73a363 | 208 | return ATA_CBL_PATA80; |
97cb81c3 | 209 | return ATA_CBL_PATA40; |
669a5db4 JG |
210 | } |
211 | ||
cc0680a5 | 212 | static int via_pre_reset(struct ata_link *link, unsigned long deadline) |
669a5db4 | 213 | { |
cc0680a5 | 214 | struct ata_port *ap = link->ap; |
669a5db4 JG |
215 | const struct via_isa_bridge *config = ap->host->private_data; |
216 | ||
217 | if (!(config->flags & VIA_NO_ENABLES)) { | |
218 | static const struct pci_bits via_enable_bits[] = { | |
219 | { 0x40, 1, 0x02, 0x02 }, | |
220 | { 0x40, 1, 0x01, 0x01 } | |
221 | }; | |
669a5db4 | 222 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); |
c961922b AC |
223 | if (!pci_test_config_bits(pdev, &via_enable_bits[ap->port_no])) |
224 | return -ENOENT; | |
669a5db4 | 225 | } |
d4b2bab4 | 226 | |
9363c382 | 227 | return ata_sff_prereset(link, deadline); |
669a5db4 JG |
228 | } |
229 | ||
230 | ||
669a5db4 JG |
231 | /** |
232 | * via_do_set_mode - set initial PIO mode data | |
233 | * @ap: ATA interface | |
234 | * @adev: ATA device | |
235 | * @mode: ATA mode being programmed | |
236 | * @tdiv: Clocks per PCI clock | |
237 | * @set_ast: Set to program address setup | |
238 | * @udma_type: UDMA mode/format of registers | |
239 | * | |
240 | * Program the VIA registers for DMA and PIO modes. Uses the ata timing | |
241 | * support in order to compute modes. | |
242 | * | |
243 | * FIXME: Hotplug will require we serialize multiple mode changes | |
244 | * on the two channels. | |
245 | */ | |
246 | ||
247 | static void via_do_set_mode(struct ata_port *ap, struct ata_device *adev, int mode, int tdiv, int set_ast, int udma_type) | |
248 | { | |
249 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); | |
250 | struct ata_device *peer = ata_dev_pair(adev); | |
251 | struct ata_timing t, p; | |
252 | static int via_clock = 33333; /* Bus clock in kHZ - ought to be tunable one day */ | |
253 | unsigned long T = 1000000000 / via_clock; | |
254 | unsigned long UT = T/tdiv; | |
255 | int ut; | |
256 | int offset = 3 - (2*ap->port_no) - adev->devno; | |
257 | ||
669a5db4 JG |
258 | /* Calculate the timing values we require */ |
259 | ata_timing_compute(adev, mode, &t, T, UT); | |
260 | ||
261 | /* We share 8bit timing so we must merge the constraints */ | |
262 | if (peer) { | |
263 | if (peer->pio_mode) { | |
264 | ata_timing_compute(peer, peer->pio_mode, &p, T, UT); | |
265 | ata_timing_merge(&p, &t, &t, ATA_TIMING_8BIT); | |
266 | } | |
267 | } | |
268 | ||
269 | /* Address setup is programmable but breaks on UDMA133 setups */ | |
270 | if (set_ast) { | |
271 | u8 setup; /* 2 bits per drive */ | |
272 | int shift = 2 * offset; | |
273 | ||
274 | pci_read_config_byte(pdev, 0x4C, &setup); | |
275 | setup &= ~(3 << shift); | |
07633b5d | 276 | setup |= clamp_val(t.setup, 1, 4) << shift; /* 1,4 or 1,4 - 1 FIXME */ |
669a5db4 JG |
277 | pci_write_config_byte(pdev, 0x4C, setup); |
278 | } | |
279 | ||
280 | /* Load the PIO mode bits */ | |
281 | pci_write_config_byte(pdev, 0x4F - ap->port_no, | |
07633b5d | 282 | ((clamp_val(t.act8b, 1, 16) - 1) << 4) | (clamp_val(t.rec8b, 1, 16) - 1)); |
669a5db4 | 283 | pci_write_config_byte(pdev, 0x48 + offset, |
07633b5d | 284 | ((clamp_val(t.active, 1, 16) - 1) << 4) | (clamp_val(t.recover, 1, 16) - 1)); |
669a5db4 JG |
285 | |
286 | /* Load the UDMA bits according to type */ | |
287 | switch(udma_type) { | |
288 | default: | |
289 | /* BUG() ? */ | |
290 | /* fall through */ | |
291 | case 33: | |
07633b5d | 292 | ut = t.udma ? (0xe0 | (clamp_val(t.udma, 2, 5) - 2)) : 0x03; |
669a5db4 JG |
293 | break; |
294 | case 66: | |
07633b5d | 295 | ut = t.udma ? (0xe8 | (clamp_val(t.udma, 2, 9) - 2)) : 0x0f; |
669a5db4 JG |
296 | break; |
297 | case 100: | |
07633b5d | 298 | ut = t.udma ? (0xe0 | (clamp_val(t.udma, 2, 9) - 2)) : 0x07; |
669a5db4 JG |
299 | break; |
300 | case 133: | |
07633b5d | 301 | ut = t.udma ? (0xe0 | (clamp_val(t.udma, 2, 9) - 2)) : 0x07; |
669a5db4 JG |
302 | break; |
303 | } | |
08ebd43d | 304 | |
669a5db4 | 305 | /* Set UDMA unless device is not UDMA capable */ |
943547ab | 306 | if (udma_type && t.udma) { |
08ebd43d LR |
307 | u8 cable80_status; |
308 | ||
309 | /* Get 80-wire cable detection bit */ | |
310 | pci_read_config_byte(pdev, 0x50 + offset, &cable80_status); | |
311 | cable80_status &= 0x10; | |
312 | ||
313 | pci_write_config_byte(pdev, 0x50 + offset, ut | cable80_status); | |
314 | } | |
669a5db4 JG |
315 | } |
316 | ||
317 | static void via_set_piomode(struct ata_port *ap, struct ata_device *adev) | |
318 | { | |
319 | const struct via_isa_bridge *config = ap->host->private_data; | |
320 | int set_ast = (config->flags & VIA_BAD_AST) ? 0 : 1; | |
321 | int mode = config->flags & VIA_UDMA; | |
322 | static u8 tclock[5] = { 1, 1, 2, 3, 4 }; | |
323 | static u8 udma[5] = { 0, 33, 66, 100, 133 }; | |
324 | ||
325 | via_do_set_mode(ap, adev, adev->pio_mode, tclock[mode], set_ast, udma[mode]); | |
326 | } | |
327 | ||
328 | static void via_set_dmamode(struct ata_port *ap, struct ata_device *adev) | |
329 | { | |
330 | const struct via_isa_bridge *config = ap->host->private_data; | |
331 | int set_ast = (config->flags & VIA_BAD_AST) ? 0 : 1; | |
332 | int mode = config->flags & VIA_UDMA; | |
333 | static u8 tclock[5] = { 1, 1, 2, 3, 4 }; | |
334 | static u8 udma[5] = { 0, 33, 66, 100, 133 }; | |
335 | ||
336 | via_do_set_mode(ap, adev, adev->dma_mode, tclock[mode], set_ast, udma[mode]); | |
337 | } | |
338 | ||
bfce5e01 | 339 | /** |
ff04715b | 340 | * via_tf_load - send taskfile registers to host controller |
bfce5e01 J |
341 | * @ap: Port to which output is sent |
342 | * @tf: ATA taskfile register set | |
343 | * | |
344 | * Outputs ATA taskfile to standard ATA host controller. | |
345 | * | |
346 | * Note: This is to fix the internal bug of via chipsets, which | |
ff04715b TH |
347 | * will reset the device register after changing the IEN bit on |
348 | * ctl register | |
bfce5e01 | 349 | */ |
ff04715b | 350 | static void via_tf_load(struct ata_port *ap, const struct ata_taskfile *tf) |
bfce5e01 | 351 | { |
b4746ed7 AC |
352 | struct ata_ioports *ioaddr = &ap->ioaddr; |
353 | struct via_port *vp = ap->private_data; | |
354 | unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR; | |
355 | int newctl = 0; | |
356 | ||
357 | if (tf->ctl != ap->last_ctl) { | |
358 | iowrite8(tf->ctl, ioaddr->ctl_addr); | |
359 | ap->last_ctl = tf->ctl; | |
360 | ata_wait_idle(ap); | |
361 | newctl = 1; | |
362 | } | |
363 | ||
364 | if (tf->flags & ATA_TFLAG_DEVICE) { | |
365 | iowrite8(tf->device, ioaddr->device_addr); | |
366 | vp->cached_device = tf->device; | |
367 | } else if (newctl) | |
368 | iowrite8(vp->cached_device, ioaddr->device_addr); | |
369 | ||
370 | if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) { | |
371 | WARN_ON_ONCE(!ioaddr->ctl_addr); | |
372 | iowrite8(tf->hob_feature, ioaddr->feature_addr); | |
373 | iowrite8(tf->hob_nsect, ioaddr->nsect_addr); | |
374 | iowrite8(tf->hob_lbal, ioaddr->lbal_addr); | |
375 | iowrite8(tf->hob_lbam, ioaddr->lbam_addr); | |
376 | iowrite8(tf->hob_lbah, ioaddr->lbah_addr); | |
377 | VPRINTK("hob: feat 0x%X nsect 0x%X, lba 0x%X 0x%X 0x%X\n", | |
378 | tf->hob_feature, | |
379 | tf->hob_nsect, | |
380 | tf->hob_lbal, | |
381 | tf->hob_lbam, | |
382 | tf->hob_lbah); | |
383 | } | |
bfce5e01 | 384 | |
b4746ed7 AC |
385 | if (is_addr) { |
386 | iowrite8(tf->feature, ioaddr->feature_addr); | |
387 | iowrite8(tf->nsect, ioaddr->nsect_addr); | |
388 | iowrite8(tf->lbal, ioaddr->lbal_addr); | |
389 | iowrite8(tf->lbam, ioaddr->lbam_addr); | |
390 | iowrite8(tf->lbah, ioaddr->lbah_addr); | |
391 | VPRINTK("feat 0x%X nsect 0x%X lba 0x%X 0x%X 0x%X\n", | |
392 | tf->feature, | |
393 | tf->nsect, | |
394 | tf->lbal, | |
395 | tf->lbam, | |
396 | tf->lbah); | |
bfce5e01 | 397 | } |
b4746ed7 AC |
398 | |
399 | ata_wait_idle(ap); | |
400 | } | |
401 | ||
402 | static int via_port_start(struct ata_port *ap) | |
403 | { | |
404 | struct via_port *vp; | |
405 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); | |
406 | ||
407 | int ret = ata_sff_port_start(ap); | |
408 | if (ret < 0) | |
409 | return ret; | |
410 | ||
411 | vp = devm_kzalloc(&pdev->dev, sizeof(struct via_port), GFP_KERNEL); | |
412 | if (vp == NULL) | |
413 | return -ENOMEM; | |
414 | ap->private_data = vp; | |
415 | return 0; | |
bfce5e01 J |
416 | } |
417 | ||
669a5db4 | 418 | static struct scsi_host_template via_sht = { |
68d1d07b | 419 | ATA_BMDMA_SHT(DRV_NAME), |
669a5db4 JG |
420 | }; |
421 | ||
422 | static struct ata_port_operations via_port_ops = { | |
029cfd6b TH |
423 | .inherits = &ata_bmdma_port_ops, |
424 | .cable_detect = via_cable_detect, | |
669a5db4 JG |
425 | .set_piomode = via_set_piomode, |
426 | .set_dmamode = via_set_dmamode, | |
a1efdaba | 427 | .prereset = via_pre_reset, |
ff04715b | 428 | .sff_tf_load = via_tf_load, |
b4746ed7 | 429 | .port_start = via_port_start, |
669a5db4 JG |
430 | }; |
431 | ||
432 | static struct ata_port_operations via_port_ops_noirq = { | |
029cfd6b | 433 | .inherits = &via_port_ops, |
5682ed33 | 434 | .sff_data_xfer = ata_sff_data_xfer_noirq, |
669a5db4 JG |
435 | }; |
436 | ||
627d2d32 A |
437 | /** |
438 | * via_config_fifo - set up the FIFO | |
439 | * @pdev: PCI device | |
440 | * @flags: configuration flags | |
441 | * | |
3a4fa0a2 | 442 | * Set the FIFO properties for this device if necessary. Used both on |
627d2d32 A |
443 | * set up and on and the resume path |
444 | */ | |
445 | ||
446 | static void via_config_fifo(struct pci_dev *pdev, unsigned int flags) | |
447 | { | |
448 | u8 enable; | |
f20b16ff | 449 | |
627d2d32 A |
450 | /* 0x40 low bits indicate enabled channels */ |
451 | pci_read_config_byte(pdev, 0x40 , &enable); | |
452 | enable &= 3; | |
f20b16ff | 453 | |
627d2d32 | 454 | if (flags & VIA_SET_FIFO) { |
73720861 | 455 | static const u8 fifo_setting[4] = {0x00, 0x60, 0x00, 0x20}; |
627d2d32 A |
456 | u8 fifo; |
457 | ||
458 | pci_read_config_byte(pdev, 0x43, &fifo); | |
459 | ||
460 | /* Clear PREQ# until DDACK# for errata */ | |
461 | if (flags & VIA_BAD_PREQ) | |
462 | fifo &= 0x7F; | |
463 | else | |
464 | fifo &= 0x9f; | |
465 | /* Turn on FIFO for enabled channels */ | |
466 | fifo |= fifo_setting[enable]; | |
467 | pci_write_config_byte(pdev, 0x43, fifo); | |
468 | } | |
469 | } | |
470 | ||
669a5db4 JG |
471 | /** |
472 | * via_init_one - discovery callback | |
627d2d32 | 473 | * @pdev: PCI device |
669a5db4 JG |
474 | * @id: PCI table info |
475 | * | |
476 | * A VIA IDE interface has been discovered. Figure out what revision | |
477 | * and perform configuration work before handing it to the ATA layer | |
478 | */ | |
479 | ||
480 | static int via_init_one(struct pci_dev *pdev, const struct pci_device_id *id) | |
481 | { | |
482 | /* Early VIA without UDMA support */ | |
1626aeb8 | 483 | static const struct ata_port_info via_mwdma_info = { |
464cf177 | 484 | .flags = ATA_FLAG_SLAVE_POSS, |
14bdef98 EIB |
485 | .pio_mask = ATA_PIO4, |
486 | .mwdma_mask = ATA_MWDMA2, | |
669a5db4 JG |
487 | .port_ops = &via_port_ops |
488 | }; | |
489 | /* Ditto with IRQ masking required */ | |
1626aeb8 | 490 | static const struct ata_port_info via_mwdma_info_borked = { |
464cf177 | 491 | .flags = ATA_FLAG_SLAVE_POSS, |
14bdef98 EIB |
492 | .pio_mask = ATA_PIO4, |
493 | .mwdma_mask = ATA_MWDMA2, | |
669a5db4 JG |
494 | .port_ops = &via_port_ops_noirq, |
495 | }; | |
496 | /* VIA UDMA 33 devices (and borked 66) */ | |
1626aeb8 | 497 | static const struct ata_port_info via_udma33_info = { |
464cf177 | 498 | .flags = ATA_FLAG_SLAVE_POSS, |
14bdef98 EIB |
499 | .pio_mask = ATA_PIO4, |
500 | .mwdma_mask = ATA_MWDMA2, | |
bf6263a8 | 501 | .udma_mask = ATA_UDMA2, |
669a5db4 JG |
502 | .port_ops = &via_port_ops |
503 | }; | |
504 | /* VIA UDMA 66 devices */ | |
1626aeb8 | 505 | static const struct ata_port_info via_udma66_info = { |
464cf177 | 506 | .flags = ATA_FLAG_SLAVE_POSS, |
14bdef98 EIB |
507 | .pio_mask = ATA_PIO4, |
508 | .mwdma_mask = ATA_MWDMA2, | |
bf6263a8 | 509 | .udma_mask = ATA_UDMA4, |
669a5db4 JG |
510 | .port_ops = &via_port_ops |
511 | }; | |
512 | /* VIA UDMA 100 devices */ | |
1626aeb8 | 513 | static const struct ata_port_info via_udma100_info = { |
464cf177 | 514 | .flags = ATA_FLAG_SLAVE_POSS, |
14bdef98 EIB |
515 | .pio_mask = ATA_PIO4, |
516 | .mwdma_mask = ATA_MWDMA2, | |
bf6263a8 | 517 | .udma_mask = ATA_UDMA5, |
669a5db4 JG |
518 | .port_ops = &via_port_ops |
519 | }; | |
520 | /* UDMA133 with bad AST (All current 133) */ | |
1626aeb8 | 521 | static const struct ata_port_info via_udma133_info = { |
464cf177 | 522 | .flags = ATA_FLAG_SLAVE_POSS, |
14bdef98 EIB |
523 | .pio_mask = ATA_PIO4, |
524 | .mwdma_mask = ATA_MWDMA2, | |
bf6263a8 | 525 | .udma_mask = ATA_UDMA6, /* FIXME: should check north bridge */ |
669a5db4 JG |
526 | .port_ops = &via_port_ops |
527 | }; | |
887125e3 | 528 | const struct ata_port_info *ppi[] = { NULL, NULL }; |
669a5db4 JG |
529 | struct pci_dev *isa = NULL; |
530 | const struct via_isa_bridge *config; | |
531 | static int printed_version; | |
669a5db4 JG |
532 | u8 enable; |
533 | u32 timing; | |
e4d866cd | 534 | unsigned long flags = id->driver_data; |
f08048e9 | 535 | int rc; |
669a5db4 JG |
536 | |
537 | if (!printed_version++) | |
538 | dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n"); | |
539 | ||
f08048e9 TH |
540 | rc = pcim_enable_device(pdev); |
541 | if (rc) | |
542 | return rc; | |
543 | ||
e4d866cd J |
544 | if (flags & VIA_IDFLAG_SINGLE) |
545 | ppi[1] = &ata_dummy_port_info; | |
546 | ||
669a5db4 JG |
547 | /* To find out how the IDE will behave and what features we |
548 | actually have to look at the bridge not the IDE controller */ | |
e4d866cd J |
549 | for (config = via_isa_bridges; config->id != PCI_DEVICE_ID_VIA_ANON; |
550 | config++) | |
669a5db4 JG |
551 | if ((isa = pci_get_device(PCI_VENDOR_ID_VIA + |
552 | !!(config->flags & VIA_BAD_ID), | |
553 | config->id, NULL))) { | |
554 | ||
44c10138 AK |
555 | if (isa->revision >= config->rev_min && |
556 | isa->revision <= config->rev_max) | |
669a5db4 JG |
557 | break; |
558 | pci_dev_put(isa); | |
559 | } | |
560 | ||
669a5db4 JG |
561 | pci_dev_put(isa); |
562 | ||
11f6400e AC |
563 | if (!(config->flags & VIA_NO_ENABLES)) { |
564 | /* 0x40 low bits indicate enabled channels */ | |
565 | pci_read_config_byte(pdev, 0x40 , &enable); | |
566 | enable &= 3; | |
567 | if (enable == 0) | |
568 | return -ENODEV; | |
669a5db4 JG |
569 | } |
570 | ||
571 | /* Initialise the FIFO for the enabled channels. */ | |
627d2d32 | 572 | via_config_fifo(pdev, config->flags); |
f20b16ff | 573 | |
669a5db4 JG |
574 | /* Clock set up */ |
575 | switch(config->flags & VIA_UDMA) { | |
576 | case VIA_UDMA_NONE: | |
577 | if (config->flags & VIA_NO_UNMASK) | |
887125e3 | 578 | ppi[0] = &via_mwdma_info_borked; |
669a5db4 | 579 | else |
887125e3 | 580 | ppi[0] = &via_mwdma_info; |
669a5db4 JG |
581 | break; |
582 | case VIA_UDMA_33: | |
887125e3 | 583 | ppi[0] = &via_udma33_info; |
669a5db4 JG |
584 | break; |
585 | case VIA_UDMA_66: | |
887125e3 | 586 | ppi[0] = &via_udma66_info; |
669a5db4 JG |
587 | /* The 66 MHz devices require we enable the clock */ |
588 | pci_read_config_dword(pdev, 0x50, &timing); | |
589 | timing |= 0x80008; | |
590 | pci_write_config_dword(pdev, 0x50, timing); | |
591 | break; | |
592 | case VIA_UDMA_100: | |
887125e3 | 593 | ppi[0] = &via_udma100_info; |
669a5db4 JG |
594 | break; |
595 | case VIA_UDMA_133: | |
887125e3 | 596 | ppi[0] = &via_udma133_info; |
669a5db4 JG |
597 | break; |
598 | default: | |
599 | WARN_ON(1); | |
600 | return -ENODEV; | |
601 | } | |
602 | ||
603 | if (config->flags & VIA_BAD_CLK66) { | |
604 | /* Disable the 66MHz clock on problem devices */ | |
605 | pci_read_config_dword(pdev, 0x50, &timing); | |
606 | timing &= ~0x80008; | |
607 | pci_write_config_dword(pdev, 0x50, timing); | |
608 | } | |
609 | ||
610 | /* We have established the device type, now fire it up */ | |
9363c382 | 611 | return ata_pci_sff_init_one(pdev, ppi, &via_sht, (void *)config); |
669a5db4 JG |
612 | } |
613 | ||
438ac6d5 | 614 | #ifdef CONFIG_PM |
627d2d32 A |
615 | /** |
616 | * via_reinit_one - reinit after resume | |
617 | * @pdev; PCI device | |
618 | * | |
619 | * Called when the VIA PATA device is resumed. We must then | |
620 | * reconfigure the fifo and other setup we may have altered. In | |
621 | * addition the kernel needs to have the resume methods on PCI | |
622 | * quirk supported. | |
623 | */ | |
624 | ||
625 | static int via_reinit_one(struct pci_dev *pdev) | |
626 | { | |
627 | u32 timing; | |
628 | struct ata_host *host = dev_get_drvdata(&pdev->dev); | |
629 | const struct via_isa_bridge *config = host->private_data; | |
f08048e9 TH |
630 | int rc; |
631 | ||
632 | rc = ata_pci_device_do_resume(pdev); | |
633 | if (rc) | |
634 | return rc; | |
f20b16ff | 635 | |
627d2d32 A |
636 | via_config_fifo(pdev, config->flags); |
637 | ||
638 | if ((config->flags & VIA_UDMA) == VIA_UDMA_66) { | |
639 | /* The 66 MHz devices require we enable the clock */ | |
640 | pci_read_config_dword(pdev, 0x50, &timing); | |
641 | timing |= 0x80008; | |
642 | pci_write_config_dword(pdev, 0x50, timing); | |
643 | } | |
644 | if (config->flags & VIA_BAD_CLK66) { | |
645 | /* Disable the 66MHz clock on problem devices */ | |
646 | pci_read_config_dword(pdev, 0x50, &timing); | |
647 | timing &= ~0x80008; | |
648 | pci_write_config_dword(pdev, 0x50, timing); | |
649 | } | |
f08048e9 TH |
650 | |
651 | ata_host_resume(host); | |
652 | return 0; | |
627d2d32 | 653 | } |
438ac6d5 | 654 | #endif |
627d2d32 | 655 | |
669a5db4 | 656 | static const struct pci_device_id via[] = { |
5955c7a2 | 657 | { PCI_VDEVICE(VIA, 0x0415), }, |
52df0ee0 JG |
658 | { PCI_VDEVICE(VIA, 0x0571), }, |
659 | { PCI_VDEVICE(VIA, 0x0581), }, | |
660 | { PCI_VDEVICE(VIA, 0x1571), }, | |
661 | { PCI_VDEVICE(VIA, 0x3164), }, | |
662 | { PCI_VDEVICE(VIA, 0x5324), }, | |
e4d866cd | 663 | { PCI_VDEVICE(VIA, 0xC409), VIA_IDFLAG_SINGLE }, |
2d2744fc JG |
664 | |
665 | { }, | |
669a5db4 JG |
666 | }; |
667 | ||
668 | static struct pci_driver via_pci_driver = { | |
2d2744fc | 669 | .name = DRV_NAME, |
669a5db4 JG |
670 | .id_table = via, |
671 | .probe = via_init_one, | |
627d2d32 | 672 | .remove = ata_pci_remove_one, |
438ac6d5 | 673 | #ifdef CONFIG_PM |
627d2d32 A |
674 | .suspend = ata_pci_device_suspend, |
675 | .resume = via_reinit_one, | |
438ac6d5 | 676 | #endif |
669a5db4 JG |
677 | }; |
678 | ||
679 | static int __init via_init(void) | |
680 | { | |
681 | return pci_register_driver(&via_pci_driver); | |
682 | } | |
683 | ||
669a5db4 JG |
684 | static void __exit via_exit(void) |
685 | { | |
686 | pci_unregister_driver(&via_pci_driver); | |
687 | } | |
688 | ||
669a5db4 JG |
689 | MODULE_AUTHOR("Alan Cox"); |
690 | MODULE_DESCRIPTION("low-level driver for VIA PATA"); | |
691 | MODULE_LICENSE("GPL"); | |
692 | MODULE_DEVICE_TABLE(pci, via); | |
693 | MODULE_VERSION(DRV_VERSION); | |
694 | ||
695 | module_init(via_init); | |
696 | module_exit(via_exit); |