Commit | Line | Data |
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669a5db4 JG |
1 | /* |
2 | * pata_sis.c - SiS ATA driver | |
3 | * | |
ab771630 | 4 | * (C) 2005 Red Hat |
750c7136 | 5 | * (C) 2007,2009 Bartlomiej Zolnierkiewicz |
669a5db4 JG |
6 | * |
7 | * Based upon linux/drivers/ide/pci/sis5513.c | |
8 | * Copyright (C) 1999-2000 Andre Hedrick <andre@linux-ide.org> | |
9 | * Copyright (C) 2002 Lionel Bouton <Lionel.Bouton@inet6.fr>, Maintainer | |
10 | * Copyright (C) 2003 Vojtech Pavlik <vojtech@suse.cz> | |
11 | * SiS Taiwan : for direct support and hardware. | |
12 | * Daniela Engert : for initial ATA100 advices and numerous others. | |
13 | * John Fremlin, Manfred Spraul, Dave Morgan, Peter Kjellerstedt : | |
14 | * for checking code correctness, providing patches. | |
15 | * Original tests and design on the SiS620 chipset. | |
16 | * ATA100 tests and design on the SiS735 chipset. | |
17 | * ATA16/33 support from specs | |
18 | * ATA133 support for SiS961/962 by L.C. Chang <lcchang@sis.com.tw> | |
19 | * | |
20 | * | |
21 | * TODO | |
22 | * Check MWDMA on drives that don't support MWDMA speed pio cycles ? | |
23 | * More Testing | |
24 | */ | |
25 | ||
26 | #include <linux/kernel.h> | |
27 | #include <linux/module.h> | |
28 | #include <linux/pci.h> | |
29 | #include <linux/init.h> | |
30 | #include <linux/blkdev.h> | |
31 | #include <linux/delay.h> | |
32 | #include <linux/device.h> | |
33 | #include <scsi/scsi_host.h> | |
34 | #include <linux/libata.h> | |
35 | #include <linux/ata.h> | |
4bb64fb9 | 36 | #include "sis.h" |
669a5db4 JG |
37 | |
38 | #define DRV_NAME "pata_sis" | |
4761c06c | 39 | #define DRV_VERSION "0.5.2" |
669a5db4 JG |
40 | |
41 | struct sis_chipset { | |
1626aeb8 TH |
42 | u16 device; /* PCI host ID */ |
43 | const struct ata_port_info *info; /* Info block */ | |
669a5db4 JG |
44 | /* Probably add family, cable detect type etc here to clean |
45 | up code later */ | |
46 | }; | |
47 | ||
7dcbc1f2 JJ |
48 | struct sis_laptop { |
49 | u16 device; | |
50 | u16 subvendor; | |
51 | u16 subdevice; | |
52 | }; | |
53 | ||
54 | static const struct sis_laptop sis_laptop[] = { | |
55 | /* devid, subvendor, subdev */ | |
56 | { 0x5513, 0x1043, 0x1107 }, /* ASUS A6K */ | |
4f2d47cf | 57 | { 0x5513, 0x1734, 0x105F }, /* FSC Amilo A1630 */ |
1f71d067 | 58 | { 0x5513, 0x1071, 0x8640 }, /* EasyNote K5305 */ |
7dcbc1f2 JJ |
59 | /* end marker */ |
60 | { 0, } | |
61 | }; | |
62 | ||
63 | static int sis_short_ata40(struct pci_dev *dev) | |
64 | { | |
65 | const struct sis_laptop *lap = &sis_laptop[0]; | |
66 | ||
67 | while (lap->device) { | |
68 | if (lap->device == dev->device && | |
69 | lap->subvendor == dev->subsystem_vendor && | |
70 | lap->subdevice == dev->subsystem_device) | |
71 | return 1; | |
72 | lap++; | |
73 | } | |
74 | ||
75 | return 0; | |
76 | } | |
77 | ||
669a5db4 | 78 | /** |
dd668d15 | 79 | * sis_old_port_base - return PCI configuration base for dev |
669a5db4 JG |
80 | * @adev: device |
81 | * | |
82 | * Returns the base of the PCI configuration registers for this port | |
83 | * number. | |
84 | */ | |
85 | ||
dd668d15 | 86 | static int sis_old_port_base(struct ata_device *adev) |
669a5db4 | 87 | { |
9af5c9c9 | 88 | return 0x40 + (4 * adev->link->ap->port_no) + (2 * adev->devno); |
669a5db4 JG |
89 | } |
90 | ||
91 | /** | |
2e413f51 | 92 | * sis_133_cable_detect - check for 40/80 pin |
669a5db4 | 93 | * @ap: Port |
d4b2bab4 | 94 | * @deadline: deadline jiffies for the operation |
669a5db4 JG |
95 | * |
96 | * Perform cable detection for the later UDMA133 capable | |
97 | * SiS chipset. | |
98 | */ | |
99 | ||
2e413f51 | 100 | static int sis_133_cable_detect(struct ata_port *ap) |
669a5db4 | 101 | { |
669a5db4 JG |
102 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); |
103 | u16 tmp; | |
104 | ||
669a5db4 JG |
105 | /* The top bit of this register is the cable detect bit */ |
106 | pci_read_config_word(pdev, 0x50 + 2 * ap->port_no, &tmp); | |
7dcbc1f2 | 107 | if ((tmp & 0x8000) && !sis_short_ata40(pdev)) |
2e413f51 AC |
108 | return ATA_CBL_PATA40; |
109 | return ATA_CBL_PATA80; | |
669a5db4 JG |
110 | } |
111 | ||
112 | /** | |
2e413f51 | 113 | * sis_66_cable_detect - check for 40/80 pin |
669a5db4 JG |
114 | * @ap: Port |
115 | * | |
116 | * Perform cable detection on the UDMA66, UDMA100 and early UDMA133 | |
117 | * SiS IDE controllers. | |
118 | */ | |
119 | ||
2e413f51 | 120 | static int sis_66_cable_detect(struct ata_port *ap) |
669a5db4 | 121 | { |
669a5db4 JG |
122 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); |
123 | u8 tmp; | |
124 | ||
669a5db4 JG |
125 | /* Older chips keep cable detect in bits 4/5 of reg 0x48 */ |
126 | pci_read_config_byte(pdev, 0x48, &tmp); | |
127 | tmp >>= ap->port_no; | |
7dcbc1f2 | 128 | if ((tmp & 0x10) && !sis_short_ata40(pdev)) |
2e413f51 AC |
129 | return ATA_CBL_PATA40; |
130 | return ATA_CBL_PATA80; | |
669a5db4 JG |
131 | } |
132 | ||
669a5db4 JG |
133 | |
134 | /** | |
2e413f51 | 135 | * sis_pre_reset - probe begin |
cc0680a5 | 136 | * @link: ATA link |
d4b2bab4 | 137 | * @deadline: deadline jiffies for the operation |
669a5db4 JG |
138 | * |
139 | * Set up cable type and use generic probe init | |
140 | */ | |
141 | ||
cc0680a5 | 142 | static int sis_pre_reset(struct ata_link *link, unsigned long deadline) |
669a5db4 JG |
143 | { |
144 | static const struct pci_bits sis_enable_bits[] = { | |
145 | { 0x4aU, 1U, 0x02UL, 0x02UL }, /* port 0 */ | |
146 | { 0x4aU, 1U, 0x04UL, 0x04UL }, /* port 1 */ | |
147 | }; | |
85cd7251 | 148 | |
cc0680a5 | 149 | struct ata_port *ap = link->ap; |
669a5db4 JG |
150 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); |
151 | ||
2e413f51 AC |
152 | if (!pci_test_config_bits(pdev, &sis_enable_bits[ap->port_no])) |
153 | return -ENOENT; | |
d4b2bab4 | 154 | |
15ce0943 AC |
155 | /* Clear the FIFO settings. We can't enable the FIFO until |
156 | we know we are poking at a disk */ | |
157 | pci_write_config_byte(pdev, 0x4B, 0); | |
9363c382 | 158 | return ata_sff_prereset(link, deadline); |
669a5db4 JG |
159 | } |
160 | ||
161 | ||
669a5db4 JG |
162 | /** |
163 | * sis_set_fifo - Set RWP fifo bits for this device | |
164 | * @ap: Port | |
165 | * @adev: Device | |
166 | * | |
167 | * SIS chipsets implement prefetch/postwrite bits for each device | |
168 | * on both channels. This functionality is not ATAPI compatible and | |
169 | * must be configured according to the class of device present | |
170 | */ | |
171 | ||
172 | static void sis_set_fifo(struct ata_port *ap, struct ata_device *adev) | |
173 | { | |
174 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); | |
175 | u8 fifoctrl; | |
176 | u8 mask = 0x11; | |
177 | ||
178 | mask <<= (2 * ap->port_no); | |
179 | mask <<= adev->devno; | |
180 | ||
181 | /* This holds various bits including the FIFO control */ | |
182 | pci_read_config_byte(pdev, 0x4B, &fifoctrl); | |
183 | fifoctrl &= ~mask; | |
184 | ||
185 | /* Enable for ATA (disk) only */ | |
186 | if (adev->class == ATA_DEV_ATA) | |
187 | fifoctrl |= mask; | |
188 | pci_write_config_byte(pdev, 0x4B, fifoctrl); | |
189 | } | |
190 | ||
191 | /** | |
192 | * sis_old_set_piomode - Initialize host controller PATA PIO timings | |
193 | * @ap: Port whose timings we are configuring | |
194 | * @adev: Device we are configuring for. | |
195 | * | |
196 | * Set PIO mode for device, in host controller PCI config space. This | |
197 | * function handles PIO set up for all chips that are pre ATA100 and | |
198 | * also early ATA100 devices. | |
199 | * | |
200 | * LOCKING: | |
201 | * None (inherited from caller). | |
202 | */ | |
203 | ||
204 | static void sis_old_set_piomode (struct ata_port *ap, struct ata_device *adev) | |
205 | { | |
206 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); | |
dd668d15 | 207 | int port = sis_old_port_base(adev); |
669a5db4 JG |
208 | u8 t1, t2; |
209 | int speed = adev->pio_mode - XFER_PIO_0; | |
210 | ||
211 | const u8 active[] = { 0x00, 0x07, 0x04, 0x03, 0x01 }; | |
212 | const u8 recovery[] = { 0x00, 0x06, 0x04, 0x03, 0x03 }; | |
213 | ||
214 | sis_set_fifo(ap, adev); | |
215 | ||
216 | pci_read_config_byte(pdev, port, &t1); | |
217 | pci_read_config_byte(pdev, port + 1, &t2); | |
218 | ||
219 | t1 &= ~0x0F; /* Clear active/recovery timings */ | |
220 | t2 &= ~0x07; | |
221 | ||
222 | t1 |= active[speed]; | |
223 | t2 |= recovery[speed]; | |
224 | ||
225 | pci_write_config_byte(pdev, port, t1); | |
226 | pci_write_config_byte(pdev, port + 1, t2); | |
227 | } | |
228 | ||
229 | /** | |
4761c06c | 230 | * sis_100_set_piomode - Initialize host controller PATA PIO timings |
669a5db4 JG |
231 | * @ap: Port whose timings we are configuring |
232 | * @adev: Device we are configuring for. | |
233 | * | |
234 | * Set PIO mode for device, in host controller PCI config space. This | |
235 | * function handles PIO set up for ATA100 devices and early ATA133. | |
236 | * | |
237 | * LOCKING: | |
238 | * None (inherited from caller). | |
239 | */ | |
240 | ||
241 | static void sis_100_set_piomode (struct ata_port *ap, struct ata_device *adev) | |
242 | { | |
243 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); | |
dd668d15 | 244 | int port = sis_old_port_base(adev); |
669a5db4 JG |
245 | int speed = adev->pio_mode - XFER_PIO_0; |
246 | ||
247 | const u8 actrec[] = { 0x00, 0x67, 0x44, 0x33, 0x31 }; | |
248 | ||
249 | sis_set_fifo(ap, adev); | |
250 | ||
251 | pci_write_config_byte(pdev, port, actrec[speed]); | |
252 | } | |
253 | ||
254 | /** | |
f20941f3 | 255 | * sis_133_do_piomode - Initialize host controller PATA PIO/DMA timings |
669a5db4 JG |
256 | * @ap: Port whose timings we are configuring |
257 | * @adev: Device we are configuring for. | |
258 | * | |
259 | * Set PIO mode for device, in host controller PCI config space. This | |
f20941f3 AC |
260 | * function handles PIO set up for the later ATA133 devices. The same |
261 | * timings are used for MWDMA. | |
669a5db4 JG |
262 | * |
263 | * LOCKING: | |
264 | * None (inherited from caller). | |
265 | */ | |
266 | ||
f20941f3 AC |
267 | static void sis_133_do_piomode(struct ata_port *ap, struct ata_device *adev, |
268 | int speed) | |
669a5db4 JG |
269 | { |
270 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); | |
271 | int port = 0x40; | |
272 | u32 t1; | |
273 | u32 reg54; | |
669a5db4 JG |
274 | |
275 | const u32 timing133[] = { | |
276 | 0x28269000, /* Recovery << 24 | Act << 16 | Ini << 12 */ | |
277 | 0x0C266000, | |
278 | 0x04263000, | |
279 | 0x0C0A3000, | |
280 | 0x05093000 | |
281 | }; | |
282 | const u32 timing100[] = { | |
283 | 0x1E1C6000, /* Recovery << 24 | Act << 16 | Ini << 12 */ | |
284 | 0x091C4000, | |
285 | 0x031C2000, | |
286 | 0x09072000, | |
287 | 0x04062000 | |
288 | }; | |
289 | ||
290 | sis_set_fifo(ap, adev); | |
291 | ||
292 | /* If bit 14 is set then the registers are mapped at 0x70 not 0x40 */ | |
293 | pci_read_config_dword(pdev, 0x54, ®54); | |
294 | if (reg54 & 0x40000000) | |
295 | port = 0x70; | |
296 | port += 8 * ap->port_no + 4 * adev->devno; | |
297 | ||
298 | pci_read_config_dword(pdev, port, &t1); | |
299 | t1 &= 0xC0C00FFF; /* Mask out timing */ | |
300 | ||
301 | if (t1 & 0x08) /* 100 or 133 ? */ | |
302 | t1 |= timing133[speed]; | |
303 | else | |
304 | t1 |= timing100[speed]; | |
305 | pci_write_config_byte(pdev, port, t1); | |
306 | } | |
307 | ||
f20941f3 AC |
308 | /** |
309 | * sis_133_set_piomode - Initialize host controller PATA PIO timings | |
310 | * @ap: Port whose timings we are configuring | |
311 | * @adev: Device we are configuring for. | |
312 | * | |
313 | * Set PIO mode for device, in host controller PCI config space. This | |
314 | * function handles PIO set up for the later ATA133 devices. | |
315 | * | |
316 | * LOCKING: | |
317 | * None (inherited from caller). | |
318 | */ | |
319 | ||
320 | static void sis_133_set_piomode (struct ata_port *ap, struct ata_device *adev) | |
321 | { | |
322 | ||
323 | sis_133_do_piomode(ap, adev, adev->pio_mode - XFER_PIO_0); | |
324 | } | |
325 | ||
326 | /** | |
327 | * mwdma_clip_to_pio - clip MWDMA mode | |
328 | * @adev: device | |
329 | * | |
330 | * As the SiS shared MWDMA and PIO timings we must program the equivalent | |
331 | * PIO timing for the MWDMA mode but we must not program one higher than | |
332 | * the permitted PIO timing of the device. | |
333 | */ | |
334 | ||
335 | static int mwdma_clip_to_pio(struct ata_device *adev) | |
336 | { | |
337 | const int mwdma_to_pio[3] = { | |
338 | XFER_PIO_0, XFER_PIO_3, XFER_PIO_4 | |
339 | }; | |
340 | return min(mwdma_to_pio[adev->dma_mode - XFER_MW_DMA_0], | |
341 | adev->pio_mode - XFER_PIO_0); | |
342 | } | |
343 | ||
669a5db4 JG |
344 | /** |
345 | * sis_old_set_dmamode - Initialize host controller PATA DMA timings | |
346 | * @ap: Port whose timings we are configuring | |
347 | * @adev: Device to program | |
348 | * | |
349 | * Set UDMA/MWDMA mode for device, in host controller PCI config space. | |
350 | * Handles pre UDMA and UDMA33 devices. Supports MWDMA as well unlike | |
351 | * the old ide/pci driver. | |
352 | * | |
353 | * LOCKING: | |
354 | * None (inherited from caller). | |
355 | */ | |
356 | ||
357 | static void sis_old_set_dmamode (struct ata_port *ap, struct ata_device *adev) | |
358 | { | |
359 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); | |
360 | int speed = adev->dma_mode - XFER_MW_DMA_0; | |
dd668d15 | 361 | int drive_pci = sis_old_port_base(adev); |
669a5db4 JG |
362 | u16 timing; |
363 | ||
4761c06c | 364 | const u16 mwdma_bits[] = { 0x008, 0x302, 0x301 }; |
669a5db4 JG |
365 | const u16 udma_bits[] = { 0xE000, 0xC000, 0xA000 }; |
366 | ||
367 | pci_read_config_word(pdev, drive_pci, &timing); | |
368 | ||
369 | if (adev->dma_mode < XFER_UDMA_0) { | |
370 | /* bits 3-0 hold recovery timing bits 8-10 active timing and | |
1967b7ff | 371 | the higher bits are dependant on the device */ |
f20941f3 | 372 | speed = mwdma_clip_to_pio(adev); |
4761c06c | 373 | timing &= ~0x870F; |
669a5db4 | 374 | timing |= mwdma_bits[speed]; |
669a5db4 JG |
375 | } else { |
376 | /* Bit 15 is UDMA on/off, bit 13-14 are cycle time */ | |
377 | speed = adev->dma_mode - XFER_UDMA_0; | |
378 | timing &= ~0x6000; | |
379 | timing |= udma_bits[speed]; | |
380 | } | |
4761c06c | 381 | pci_write_config_word(pdev, drive_pci, timing); |
669a5db4 JG |
382 | } |
383 | ||
384 | /** | |
385 | * sis_66_set_dmamode - Initialize host controller PATA DMA timings | |
386 | * @ap: Port whose timings we are configuring | |
387 | * @adev: Device to program | |
388 | * | |
389 | * Set UDMA/MWDMA mode for device, in host controller PCI config space. | |
390 | * Handles UDMA66 and early UDMA100 devices. Supports MWDMA as well unlike | |
391 | * the old ide/pci driver. | |
392 | * | |
393 | * LOCKING: | |
394 | * None (inherited from caller). | |
395 | */ | |
396 | ||
397 | static void sis_66_set_dmamode (struct ata_port *ap, struct ata_device *adev) | |
398 | { | |
399 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); | |
400 | int speed = adev->dma_mode - XFER_MW_DMA_0; | |
dd668d15 | 401 | int drive_pci = sis_old_port_base(adev); |
669a5db4 JG |
402 | u16 timing; |
403 | ||
edeb614c | 404 | /* MWDMA 0-2 and UDMA 0-5 */ |
4761c06c | 405 | const u16 mwdma_bits[] = { 0x008, 0x302, 0x301 }; |
edeb614c | 406 | const u16 udma_bits[] = { 0xF000, 0xD000, 0xB000, 0xA000, 0x9000, 0x8000 }; |
669a5db4 JG |
407 | |
408 | pci_read_config_word(pdev, drive_pci, &timing); | |
409 | ||
410 | if (adev->dma_mode < XFER_UDMA_0) { | |
411 | /* bits 3-0 hold recovery timing bits 8-10 active timing and | |
1967b7ff | 412 | the higher bits are dependant on the device, bit 15 udma */ |
f20941f3 | 413 | speed = mwdma_clip_to_pio(adev); |
dd668d15 | 414 | timing &= ~0x870F; |
669a5db4 JG |
415 | timing |= mwdma_bits[speed]; |
416 | } else { | |
417 | /* Bit 15 is UDMA on/off, bit 12-14 are cycle time */ | |
418 | speed = adev->dma_mode - XFER_UDMA_0; | |
dd668d15 | 419 | timing &= ~0xF000; |
669a5db4 JG |
420 | timing |= udma_bits[speed]; |
421 | } | |
422 | pci_write_config_word(pdev, drive_pci, timing); | |
423 | } | |
424 | ||
425 | /** | |
426 | * sis_100_set_dmamode - Initialize host controller PATA DMA timings | |
427 | * @ap: Port whose timings we are configuring | |
428 | * @adev: Device to program | |
429 | * | |
430 | * Set UDMA/MWDMA mode for device, in host controller PCI config space. | |
f20941f3 | 431 | * Handles later UDMA100 devices. |
669a5db4 JG |
432 | * |
433 | * LOCKING: | |
434 | * None (inherited from caller). | |
435 | */ | |
436 | ||
437 | static void sis_100_set_dmamode (struct ata_port *ap, struct ata_device *adev) | |
438 | { | |
439 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); | |
440 | int speed = adev->dma_mode - XFER_MW_DMA_0; | |
dd668d15 | 441 | int drive_pci = sis_old_port_base(adev); |
f20941f3 | 442 | u16 timing; |
669a5db4 | 443 | |
f20941f3 AC |
444 | const u16 udma_bits[] = { |
445 | 0x8B00, 0x8700, 0x8500, 0x8300, 0x8200, 0x8100}; | |
446 | const u8 mwdma_bits[] = { 0x08, 0x32, 0x31 }; | |
669a5db4 | 447 | |
f20941f3 | 448 | pci_read_config_word(pdev, drive_pci, &timing); |
669a5db4 JG |
449 | |
450 | if (adev->dma_mode < XFER_UDMA_0) { | |
f20941f3 AC |
451 | speed = mwdma_clip_to_pio(adev); |
452 | timing &= ~0x80FF; | |
453 | timing |= mwdma_bits[speed]; | |
669a5db4 | 454 | } else { |
dd668d15 | 455 | /* Bit 7 is UDMA on/off, bit 0-3 are cycle time */ |
669a5db4 | 456 | speed = adev->dma_mode - XFER_UDMA_0; |
f20941f3 | 457 | timing &= ~0x8F00; |
669a5db4 JG |
458 | timing |= udma_bits[speed]; |
459 | } | |
f20941f3 | 460 | pci_write_config_word(pdev, drive_pci, timing); |
669a5db4 JG |
461 | } |
462 | ||
463 | /** | |
464 | * sis_133_early_set_dmamode - Initialize host controller PATA DMA timings | |
465 | * @ap: Port whose timings we are configuring | |
466 | * @adev: Device to program | |
467 | * | |
468 | * Set UDMA/MWDMA mode for device, in host controller PCI config space. | |
4761c06c | 469 | * Handles early SiS 961 bridges. |
669a5db4 JG |
470 | * |
471 | * LOCKING: | |
472 | * None (inherited from caller). | |
473 | */ | |
474 | ||
475 | static void sis_133_early_set_dmamode (struct ata_port *ap, struct ata_device *adev) | |
476 | { | |
477 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); | |
478 | int speed = adev->dma_mode - XFER_MW_DMA_0; | |
dd668d15 | 479 | int drive_pci = sis_old_port_base(adev); |
f20941f3 AC |
480 | u16 timing; |
481 | /* Bits 15-12 are timing */ | |
482 | static const u16 udma_bits[] = { | |
483 | 0x8F00, 0x8A00, 0x8700, 0x8500, 0x8300, 0x8200, 0x8100 | |
484 | }; | |
485 | static const u8 mwdma_bits[] = { 0x08, 0x32, 0x31 }; | |
669a5db4 | 486 | |
f20941f3 | 487 | pci_read_config_word(pdev, drive_pci, &timing); |
669a5db4 JG |
488 | |
489 | if (adev->dma_mode < XFER_UDMA_0) { | |
f20941f3 AC |
490 | speed = mwdma_clip_to_pio(adev); |
491 | timing &= ~0x80FF; | |
492 | timing = mwdma_bits[speed]; | |
669a5db4 | 493 | } else { |
dd668d15 | 494 | /* Bit 7 is UDMA on/off, bit 0-3 are cycle time */ |
669a5db4 | 495 | speed = adev->dma_mode - XFER_UDMA_0; |
f20941f3 | 496 | timing &= ~0x8F00; |
669a5db4 JG |
497 | timing |= udma_bits[speed]; |
498 | } | |
f20941f3 | 499 | pci_write_config_word(pdev, drive_pci, timing); |
669a5db4 JG |
500 | } |
501 | ||
502 | /** | |
503 | * sis_133_set_dmamode - Initialize host controller PATA DMA timings | |
504 | * @ap: Port whose timings we are configuring | |
505 | * @adev: Device to program | |
506 | * | |
507 | * Set UDMA/MWDMA mode for device, in host controller PCI config space. | |
669a5db4 JG |
508 | * |
509 | * LOCKING: | |
510 | * None (inherited from caller). | |
511 | */ | |
512 | ||
513 | static void sis_133_set_dmamode (struct ata_port *ap, struct ata_device *adev) | |
514 | { | |
515 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); | |
516 | int speed = adev->dma_mode - XFER_MW_DMA_0; | |
517 | int port = 0x40; | |
518 | u32 t1; | |
519 | u32 reg54; | |
520 | ||
521 | /* bits 4- cycle time 8 - cvs time */ | |
2e413f51 AC |
522 | static const u32 timing_u100[] = { 0x6B0, 0x470, 0x350, 0x140, 0x120, 0x110, 0x000 }; |
523 | static const u32 timing_u133[] = { 0x9F0, 0x6A0, 0x470, 0x250, 0x230, 0x220, 0x210 }; | |
669a5db4 JG |
524 | |
525 | /* If bit 14 is set then the registers are mapped at 0x70 not 0x40 */ | |
526 | pci_read_config_dword(pdev, 0x54, ®54); | |
527 | if (reg54 & 0x40000000) | |
528 | port = 0x70; | |
529 | port += (8 * ap->port_no) + (4 * adev->devno); | |
669a5db4 JG |
530 | pci_read_config_dword(pdev, port, &t1); |
531 | ||
532 | if (adev->dma_mode < XFER_UDMA_0) { | |
f20941f3 AC |
533 | speed = mwdma_clip_to_pio(adev); |
534 | sis_133_do_piomode(ap, adev, speed); | |
535 | t1 &= ~4; /* UDMA off */ | |
669a5db4 JG |
536 | } else { |
537 | speed = adev->dma_mode - XFER_UDMA_0; | |
538 | /* if & 8 no UDMA133 - need info for ... */ | |
539 | t1 &= ~0x00000FF0; | |
540 | t1 |= 0x00000004; | |
541 | if (t1 & 0x08) | |
542 | t1 |= timing_u133[speed]; | |
543 | else | |
544 | t1 |= timing_u100[speed]; | |
545 | } | |
546 | pci_write_config_dword(pdev, port, t1); | |
547 | } | |
548 | ||
549 | static struct scsi_host_template sis_sht = { | |
68d1d07b | 550 | ATA_BMDMA_SHT(DRV_NAME), |
669a5db4 JG |
551 | }; |
552 | ||
029cfd6b TH |
553 | static struct ata_port_operations sis_133_for_sata_ops = { |
554 | .inherits = &ata_bmdma_port_ops, | |
669a5db4 JG |
555 | .set_piomode = sis_133_set_piomode, |
556 | .set_dmamode = sis_133_set_dmamode, | |
2e413f51 | 557 | .cable_detect = sis_133_cable_detect, |
029cfd6b | 558 | }; |
669a5db4 | 559 | |
029cfd6b TH |
560 | static struct ata_port_operations sis_base_ops = { |
561 | .inherits = &ata_bmdma_port_ops, | |
a1efdaba | 562 | .prereset = sis_pre_reset, |
669a5db4 JG |
563 | }; |
564 | ||
029cfd6b TH |
565 | static struct ata_port_operations sis_133_ops = { |
566 | .inherits = &sis_base_ops, | |
a3cabb27 UK |
567 | .set_piomode = sis_133_set_piomode, |
568 | .set_dmamode = sis_133_set_dmamode, | |
a3cabb27 | 569 | .cable_detect = sis_133_cable_detect, |
a3cabb27 UK |
570 | }; |
571 | ||
029cfd6b TH |
572 | static struct ata_port_operations sis_133_early_ops = { |
573 | .inherits = &sis_base_ops, | |
669a5db4 JG |
574 | .set_piomode = sis_100_set_piomode, |
575 | .set_dmamode = sis_133_early_set_dmamode, | |
2e413f51 | 576 | .cable_detect = sis_66_cable_detect, |
669a5db4 JG |
577 | }; |
578 | ||
029cfd6b TH |
579 | static struct ata_port_operations sis_100_ops = { |
580 | .inherits = &sis_base_ops, | |
669a5db4 JG |
581 | .set_piomode = sis_100_set_piomode, |
582 | .set_dmamode = sis_100_set_dmamode, | |
2e413f51 | 583 | .cable_detect = sis_66_cable_detect, |
669a5db4 JG |
584 | }; |
585 | ||
029cfd6b TH |
586 | static struct ata_port_operations sis_66_ops = { |
587 | .inherits = &sis_base_ops, | |
669a5db4 JG |
588 | .set_piomode = sis_old_set_piomode, |
589 | .set_dmamode = sis_66_set_dmamode, | |
2e413f51 | 590 | .cable_detect = sis_66_cable_detect, |
669a5db4 JG |
591 | }; |
592 | ||
029cfd6b TH |
593 | static struct ata_port_operations sis_old_ops = { |
594 | .inherits = &sis_base_ops, | |
669a5db4 JG |
595 | .set_piomode = sis_old_set_piomode, |
596 | .set_dmamode = sis_old_set_dmamode, | |
2e413f51 | 597 | .cable_detect = ata_cable_40wire, |
669a5db4 JG |
598 | }; |
599 | ||
1626aeb8 | 600 | static const struct ata_port_info sis_info = { |
1d2808fd | 601 | .flags = ATA_FLAG_SLAVE_POSS, |
14bdef98 EIB |
602 | .pio_mask = ATA_PIO4, |
603 | .mwdma_mask = ATA_MWDMA2, | |
604 | /* No UDMA */ | |
669a5db4 JG |
605 | .port_ops = &sis_old_ops, |
606 | }; | |
1626aeb8 | 607 | static const struct ata_port_info sis_info33 = { |
1d2808fd | 608 | .flags = ATA_FLAG_SLAVE_POSS, |
14bdef98 EIB |
609 | .pio_mask = ATA_PIO4, |
610 | .mwdma_mask = ATA_MWDMA2, | |
611 | .udma_mask = ATA_UDMA2, | |
669a5db4 JG |
612 | .port_ops = &sis_old_ops, |
613 | }; | |
1626aeb8 | 614 | static const struct ata_port_info sis_info66 = { |
1d2808fd | 615 | .flags = ATA_FLAG_SLAVE_POSS, |
14bdef98 EIB |
616 | .pio_mask = ATA_PIO4, |
617 | /* No MWDMA */ | |
618 | .udma_mask = ATA_UDMA4, | |
669a5db4 JG |
619 | .port_ops = &sis_66_ops, |
620 | }; | |
1626aeb8 | 621 | static const struct ata_port_info sis_info100 = { |
1d2808fd | 622 | .flags = ATA_FLAG_SLAVE_POSS, |
14bdef98 EIB |
623 | .pio_mask = ATA_PIO4, |
624 | /* No MWDMA */ | |
669a5db4 JG |
625 | .udma_mask = ATA_UDMA5, |
626 | .port_ops = &sis_100_ops, | |
627 | }; | |
1626aeb8 | 628 | static const struct ata_port_info sis_info100_early = { |
1d2808fd | 629 | .flags = ATA_FLAG_SLAVE_POSS, |
14bdef98 EIB |
630 | .pio_mask = ATA_PIO4, |
631 | /* No MWDMA */ | |
669a5db4 | 632 | .udma_mask = ATA_UDMA5, |
669a5db4 JG |
633 | .port_ops = &sis_66_ops, |
634 | }; | |
a3cabb27 | 635 | static const struct ata_port_info sis_info133 = { |
1d2808fd | 636 | .flags = ATA_FLAG_SLAVE_POSS, |
14bdef98 EIB |
637 | .pio_mask = ATA_PIO4, |
638 | /* No MWDMA */ | |
669a5db4 JG |
639 | .udma_mask = ATA_UDMA6, |
640 | .port_ops = &sis_133_ops, | |
641 | }; | |
a3cabb27 | 642 | const struct ata_port_info sis_info133_for_sata = { |
a3cabb27 | 643 | .flags = ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST, |
14bdef98 EIB |
644 | .pio_mask = ATA_PIO4, |
645 | /* No MWDMA */ | |
a3cabb27 UK |
646 | .udma_mask = ATA_UDMA6, |
647 | .port_ops = &sis_133_for_sata_ops, | |
648 | }; | |
1626aeb8 | 649 | static const struct ata_port_info sis_info133_early = { |
1d2808fd | 650 | .flags = ATA_FLAG_SLAVE_POSS, |
14bdef98 EIB |
651 | .pio_mask = ATA_PIO4, |
652 | /* No MWDMA */ | |
669a5db4 JG |
653 | .udma_mask = ATA_UDMA6, |
654 | .port_ops = &sis_133_early_ops, | |
655 | }; | |
656 | ||
9b14dec5 | 657 | /* Privately shared with the SiS180 SATA driver, not for use elsewhere */ |
a3cabb27 | 658 | EXPORT_SYMBOL_GPL(sis_info133_for_sata); |
669a5db4 JG |
659 | |
660 | static void sis_fixup(struct pci_dev *pdev, struct sis_chipset *sis) | |
661 | { | |
662 | u16 regw; | |
663 | u8 reg; | |
664 | ||
665 | if (sis->info == &sis_info133) { | |
666 | pci_read_config_word(pdev, 0x50, ®w); | |
667 | if (regw & 0x08) | |
668 | pci_write_config_word(pdev, 0x50, regw & ~0x08); | |
669 | pci_read_config_word(pdev, 0x52, ®w); | |
670 | if (regw & 0x08) | |
671 | pci_write_config_word(pdev, 0x52, regw & ~0x08); | |
672 | return; | |
673 | } | |
674 | ||
675 | if (sis->info == &sis_info133_early || sis->info == &sis_info100) { | |
676 | /* Fix up latency */ | |
677 | pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x80); | |
678 | /* Set compatibility bit */ | |
679 | pci_read_config_byte(pdev, 0x49, ®); | |
680 | if (!(reg & 0x01)) | |
681 | pci_write_config_byte(pdev, 0x49, reg | 0x01); | |
682 | return; | |
683 | } | |
684 | ||
685 | if (sis->info == &sis_info66 || sis->info == &sis_info100_early) { | |
686 | /* Fix up latency */ | |
687 | pci_write_config_byte(pdev, PCI_LATENCY_TIMER, 0x80); | |
688 | /* Set compatibility bit */ | |
689 | pci_read_config_byte(pdev, 0x52, ®); | |
690 | if (!(reg & 0x04)) | |
691 | pci_write_config_byte(pdev, 0x52, reg | 0x04); | |
692 | return; | |
693 | } | |
694 | ||
695 | if (sis->info == &sis_info33) { | |
696 | pci_read_config_byte(pdev, PCI_CLASS_PROG, ®); | |
697 | if (( reg & 0x0F ) != 0x00) | |
698 | pci_write_config_byte(pdev, PCI_CLASS_PROG, reg & 0xF0); | |
699 | /* Fall through to ATA16 fixup below */ | |
700 | } | |
701 | ||
702 | if (sis->info == &sis_info || sis->info == &sis_info33) { | |
703 | /* force per drive recovery and active timings | |
704 | needed on ATA_33 and below chips */ | |
705 | pci_read_config_byte(pdev, 0x52, ®); | |
706 | if (!(reg & 0x08)) | |
707 | pci_write_config_byte(pdev, 0x52, reg|0x08); | |
708 | return; | |
709 | } | |
710 | ||
711 | BUG(); | |
712 | } | |
713 | ||
714 | /** | |
715 | * sis_init_one - Register SiS ATA PCI device with kernel services | |
716 | * @pdev: PCI device to register | |
717 | * @ent: Entry in sis_pci_tbl matching with @pdev | |
718 | * | |
719 | * Called from kernel PCI layer. We probe for combined mode (sigh), | |
720 | * and then hand over control to libata, for it to do the rest. | |
721 | * | |
722 | * LOCKING: | |
723 | * Inherited from PCI layer (may sleep). | |
724 | * | |
725 | * RETURNS: | |
726 | * Zero on success, or -ERRNO value. | |
727 | */ | |
728 | ||
729 | static int sis_init_one (struct pci_dev *pdev, const struct pci_device_id *ent) | |
730 | { | |
731 | static int printed_version; | |
887125e3 | 732 | const struct ata_port_info *ppi[] = { NULL, NULL }; |
669a5db4 JG |
733 | struct pci_dev *host = NULL; |
734 | struct sis_chipset *chipset = NULL; | |
f3769e9d | 735 | struct sis_chipset *sets; |
f08048e9 | 736 | int rc; |
669a5db4 JG |
737 | |
738 | static struct sis_chipset sis_chipsets[] = { | |
f20b16ff | 739 | |
af323a2f AC |
740 | { 0x0968, &sis_info133 }, |
741 | { 0x0966, &sis_info133 }, | |
742 | { 0x0965, &sis_info133 }, | |
669a5db4 JG |
743 | { 0x0745, &sis_info100 }, |
744 | { 0x0735, &sis_info100 }, | |
745 | { 0x0733, &sis_info100 }, | |
746 | { 0x0635, &sis_info100 }, | |
747 | { 0x0633, &sis_info100 }, | |
748 | ||
749 | { 0x0730, &sis_info100_early }, /* 100 with ATA 66 layout */ | |
750 | { 0x0550, &sis_info100_early }, /* 100 with ATA 66 layout */ | |
751 | ||
752 | { 0x0640, &sis_info66 }, | |
753 | { 0x0630, &sis_info66 }, | |
754 | { 0x0620, &sis_info66 }, | |
755 | { 0x0540, &sis_info66 }, | |
756 | { 0x0530, &sis_info66 }, | |
757 | ||
758 | { 0x5600, &sis_info33 }, | |
759 | { 0x5598, &sis_info33 }, | |
760 | { 0x5597, &sis_info33 }, | |
761 | { 0x5591, &sis_info33 }, | |
762 | { 0x5582, &sis_info33 }, | |
763 | { 0x5581, &sis_info33 }, | |
764 | ||
765 | { 0x5596, &sis_info }, | |
766 | { 0x5571, &sis_info }, | |
767 | { 0x5517, &sis_info }, | |
768 | { 0x5511, &sis_info }, | |
769 | ||
770 | {0} | |
771 | }; | |
772 | static struct sis_chipset sis133_early = { | |
773 | 0x0, &sis_info133_early | |
774 | }; | |
775 | static struct sis_chipset sis133 = { | |
776 | 0x0, &sis_info133 | |
777 | }; | |
778 | static struct sis_chipset sis100_early = { | |
779 | 0x0, &sis_info100_early | |
780 | }; | |
781 | static struct sis_chipset sis100 = { | |
782 | 0x0, &sis_info100 | |
783 | }; | |
784 | ||
785 | if (!printed_version++) | |
786 | dev_printk(KERN_DEBUG, &pdev->dev, | |
787 | "version " DRV_VERSION "\n"); | |
788 | ||
f08048e9 TH |
789 | rc = pcim_enable_device(pdev); |
790 | if (rc) | |
791 | return rc; | |
669a5db4 | 792 | |
f08048e9 | 793 | /* We have to find the bridge first */ |
f3769e9d AC |
794 | for (sets = &sis_chipsets[0]; sets->device; sets++) { |
795 | host = pci_get_device(PCI_VENDOR_ID_SI, sets->device, NULL); | |
669a5db4 | 796 | if (host != NULL) { |
f3769e9d AC |
797 | chipset = sets; /* Match found */ |
798 | if (sets->device == 0x630) { /* SIS630 */ | |
44c10138 | 799 | if (host->revision >= 0x30) /* 630 ET */ |
669a5db4 JG |
800 | chipset = &sis100_early; |
801 | } | |
802 | break; | |
803 | } | |
804 | } | |
805 | ||
806 | /* Look for concealed bridges */ | |
f3769e9d | 807 | if (chipset == NULL) { |
669a5db4 JG |
808 | /* Second check */ |
809 | u32 idemisc; | |
810 | u16 trueid; | |
811 | ||
812 | /* Disable ID masking and register remapping then | |
813 | see what the real ID is */ | |
814 | ||
815 | pci_read_config_dword(pdev, 0x54, &idemisc); | |
816 | pci_write_config_dword(pdev, 0x54, idemisc & 0x7fffffff); | |
817 | pci_read_config_word(pdev, PCI_DEVICE_ID, &trueid); | |
818 | pci_write_config_dword(pdev, 0x54, idemisc); | |
819 | ||
820 | switch(trueid) { | |
821 | case 0x5518: /* SIS 962/963 */ | |
822 | chipset = &sis133; | |
823 | if ((idemisc & 0x40000000) == 0) { | |
824 | pci_write_config_dword(pdev, 0x54, idemisc | 0x40000000); | |
825 | printk(KERN_INFO "SIS5513: Switching to 5513 register mapping\n"); | |
826 | } | |
827 | break; | |
828 | case 0x0180: /* SIS 965/965L */ | |
829 | chipset = &sis133; | |
830 | break; | |
831 | case 0x1180: /* SIS 966/966L */ | |
832 | chipset = &sis133; | |
833 | break; | |
834 | } | |
835 | } | |
836 | ||
837 | /* Further check */ | |
838 | if (chipset == NULL) { | |
839 | struct pci_dev *lpc_bridge; | |
840 | u16 trueid; | |
841 | u8 prefctl; | |
842 | u8 idecfg; | |
669a5db4 JG |
843 | |
844 | /* Try the second unmasking technique */ | |
845 | pci_read_config_byte(pdev, 0x4a, &idecfg); | |
846 | pci_write_config_byte(pdev, 0x4a, idecfg | 0x10); | |
847 | pci_read_config_word(pdev, PCI_DEVICE_ID, &trueid); | |
848 | pci_write_config_byte(pdev, 0x4a, idecfg); | |
849 | ||
850 | switch(trueid) { | |
851 | case 0x5517: | |
852 | lpc_bridge = pci_get_slot(pdev->bus, 0x10); /* Bus 0 Dev 2 Fn 0 */ | |
853 | if (lpc_bridge == NULL) | |
854 | break; | |
669a5db4 JG |
855 | pci_read_config_byte(pdev, 0x49, &prefctl); |
856 | pci_dev_put(lpc_bridge); | |
857 | ||
44c10138 | 858 | if (lpc_bridge->revision == 0x10 && (prefctl & 0x80)) { |
669a5db4 JG |
859 | chipset = &sis133_early; |
860 | break; | |
861 | } | |
862 | chipset = &sis100; | |
863 | break; | |
864 | } | |
865 | } | |
866 | pci_dev_put(host); | |
867 | ||
868 | /* No chipset info, no support */ | |
869 | if (chipset == NULL) | |
870 | return -ENODEV; | |
871 | ||
887125e3 | 872 | ppi[0] = chipset->info; |
669a5db4 JG |
873 | |
874 | sis_fixup(pdev, chipset); | |
875 | ||
9363c382 | 876 | return ata_pci_sff_init_one(pdev, ppi, &sis_sht, chipset); |
669a5db4 JG |
877 | } |
878 | ||
750c7136 BZ |
879 | #ifdef CONFIG_PM |
880 | static int sis_reinit_one(struct pci_dev *pdev) | |
881 | { | |
882 | struct ata_host *host = dev_get_drvdata(&pdev->dev); | |
883 | int rc; | |
884 | ||
885 | rc = ata_pci_device_do_resume(pdev); | |
886 | if (rc) | |
887 | return rc; | |
888 | ||
889 | sis_fixup(pdev, host->private_data); | |
890 | ||
891 | ata_host_resume(host); | |
892 | return 0; | |
893 | } | |
894 | #endif | |
895 | ||
669a5db4 | 896 | static const struct pci_device_id sis_pci_tbl[] = { |
2d2744fc JG |
897 | { PCI_VDEVICE(SI, 0x5513), }, /* SiS 5513 */ |
898 | { PCI_VDEVICE(SI, 0x5518), }, /* SiS 5518 */ | |
a3cabb27 | 899 | { PCI_VDEVICE(SI, 0x1180), }, /* SiS 1180 */ |
2d2744fc | 900 | |
669a5db4 JG |
901 | { } |
902 | }; | |
903 | ||
904 | static struct pci_driver sis_pci_driver = { | |
905 | .name = DRV_NAME, | |
906 | .id_table = sis_pci_tbl, | |
907 | .probe = sis_init_one, | |
908 | .remove = ata_pci_remove_one, | |
438ac6d5 | 909 | #ifdef CONFIG_PM |
62d64ae0 | 910 | .suspend = ata_pci_device_suspend, |
750c7136 | 911 | .resume = sis_reinit_one, |
438ac6d5 | 912 | #endif |
669a5db4 JG |
913 | }; |
914 | ||
915 | static int __init sis_init(void) | |
916 | { | |
917 | return pci_register_driver(&sis_pci_driver); | |
918 | } | |
919 | ||
920 | static void __exit sis_exit(void) | |
921 | { | |
922 | pci_unregister_driver(&sis_pci_driver); | |
923 | } | |
924 | ||
669a5db4 JG |
925 | module_init(sis_init); |
926 | module_exit(sis_exit); | |
927 | ||
928 | MODULE_AUTHOR("Alan Cox"); | |
929 | MODULE_DESCRIPTION("SCSI low-level driver for SiS ATA"); | |
930 | MODULE_LICENSE("GPL"); | |
931 | MODULE_DEVICE_TABLE(pci, sis_pci_tbl); | |
932 | MODULE_VERSION(DRV_VERSION); | |
933 |