[linux-block.git] / drivers / ata / pata_sil680.c

/*
 * pata_sil680.c 	- SIL680 PATA for new ATA layer
 *			  (C) 2005 Red Hat Inc
 *
 * based upon
 *
 * linux/drivers/ide/pci/siimage.c		Version 1.07	Nov 30, 2003
 *
 * Copyright (C) 2001-2002	Andre Hedrick <andre@linux-ide.org>
 * Copyright (C) 2003		Red Hat <alan@redhat.com>
 *
 *  May be copied or modified under the terms of the GNU General Public License
 *
 *  Documentation publicly available.
 *
 *	If you have strange problems with nVidia chipset systems please
 *	see the SI support documentation and update your system BIOS
 *	if necessary
 *
 * TODO
 *	If we know all our devices are LBA28 (or LBA28 sized)  we could use
 *	the command fifo mode.
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/blkdev.h>
#include <linux/delay.h>
#include <scsi/scsi_host.h>
#include <linux/libata.h>

#define DRV_NAME "pata_sil680"
#define DRV_VERSION "0.4.9"

#define SIL680_MMIO_BAR		5

/**
 *	sil680_selreg		-	return register base
 *	@ap: ATA interface
 *	@r: config offset
 *
 *	Turn a config register offset into the right address in PCI space
 *	to access the control register in question.
 *
 *	Thankfully this is a configuration operation so isn't performance
 *	criticial.
 */

static int sil680_selreg(struct ata_port *ap, int r)
{
	return 0xA0 + (ap->port_no << 4) + r;
}

/**
 *	sil680_seldev		-	return register base
 *	@ap: ATA interface
 *	@adev: ATA device
 *	@r: config offset
 *
 *	Turn a config register offset into the right address in PCI space
 *	to access the control register in question including accounting for
 *	the unit shift.
 */

static int sil680_seldev(struct ata_port *ap, struct ata_device *adev, int r)
{
	return 0xA0 + (ap->port_no << 4) + r + (adev->devno << 1);
}


/**
 *	sil680_cable_detect	-	cable detection
 *	@ap: ATA port
 *
 *	Perform cable detection. The SIL680 stores this in PCI config
 *	space for us.
 */

static int sil680_cable_detect(struct ata_port *ap)
{
	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	int addr = sil680_selreg(ap, 0);
	u8 ata66;

	pci_read_config_byte(pdev, addr, &ata66);
	if (ata66 & 1)
		return ATA_CBL_PATA80;
	else
		return ATA_CBL_PATA40;
}

/**
 *	sil680_set_piomode	-	set PIO mode data
 *	@ap: ATA interface
 *	@adev: ATA device
 *
 *	Program the SIL680 registers for PIO mode. Note that the task speed
 *	registers are shared between the devices so we must pick the lowest
 *	mode for command work.
 */

static void sil680_set_piomode(struct ata_port *ap, struct ata_device *adev)
{
	static const u16 speed_p[5] = {
		0x328A, 0x2283, 0x1104, 0x10C3, 0x10C1
	};
	static const u16 speed_t[5] = {
		0x328A, 0x2283, 0x1281, 0x10C3, 0x10C1
	};

	int tfaddr = sil680_selreg(ap, 0x02);
	int addr = sil680_seldev(ap, adev, 0x04);
	int addr_mask = 0x80 + 4 * ap->port_no;
	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	int pio = adev->pio_mode - XFER_PIO_0;
	int lowest_pio = pio;
	int port_shift = 4 * adev->devno;
	u16 reg;
	u8 mode;

	struct ata_device *pair = ata_dev_pair(adev);

	if (pair != NULL && adev->pio_mode > pair->pio_mode)
		lowest_pio = pair->pio_mode - XFER_PIO_0;

	pci_write_config_word(pdev, addr, speed_p[pio]);
	pci_write_config_word(pdev, tfaddr, speed_t[lowest_pio]);

	pci_read_config_word(pdev, tfaddr-2, &reg);
	pci_read_config_byte(pdev, addr_mask, &mode);

	reg &= ~0x0200;			/* Clear IORDY */
	mode &= ~(3 << port_shift);	/* Clear IORDY and DMA bits */

	if (ata_pio_need_iordy(adev)) {
		reg |= 0x0200;		/* Enable IORDY */
		mode |= 1 << port_shift;
	}
	pci_write_config_word(pdev, tfaddr-2, reg);
	pci_write_config_byte(pdev, addr_mask, mode);
}

/**
 *	sil680_set_dmamode	-	set DMA mode data
 *	@ap: ATA interface
 *	@adev: ATA device
 *
 *	Program the MWDMA/UDMA modes for the sil680 chipset.
 *
 *	The MWDMA mode values are pulled from a lookup table
 *	while the chipset uses mode number for UDMA.
 */

static void sil680_set_dmamode(struct ata_port *ap, struct ata_device *adev)
{
	static const u8 ultra_table[2][7] = {
		{ 0x0C, 0x07, 0x05, 0x04, 0x02, 0x01, 0xFF },	/* 100MHz */
		{ 0x0F, 0x0B, 0x07, 0x05, 0x03, 0x02, 0x01 },	/* 133Mhz */
	};
	static const u16 dma_table[3] = { 0x2208, 0x10C2, 0x10C1 };

	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	int ma = sil680_seldev(ap, adev, 0x08);
	int ua = sil680_seldev(ap, adev, 0x0C);
	int addr_mask = 0x80 + 4 * ap->port_no;
	int port_shift = adev->devno * 4;
	u8 scsc, mode;
	u16 multi, ultra;

	pci_read_config_byte(pdev, 0x8A, &scsc);
	pci_read_config_byte(pdev, addr_mask, &mode);
	pci_read_config_word(pdev, ma, &multi);
	pci_read_config_word(pdev, ua, &ultra);

	/* Mask timing bits */
	ultra &= ~0x3F;
	mode &= ~(0x03 << port_shift);

	/* Extract scsc */
	scsc = (scsc & 0x30) ? 1 : 0;

	if (adev->dma_mode >= XFER_UDMA_0) {
		multi = 0x10C1;
		ultra |= ultra_table[scsc][adev->dma_mode - XFER_UDMA_0];
		mode |= (0x03 << port_shift);
	} else {
		multi = dma_table[adev->dma_mode - XFER_MW_DMA_0];
		mode |= (0x02 << port_shift);
	}
	pci_write_config_byte(pdev, addr_mask, mode);
	pci_write_config_word(pdev, ma, multi);
	pci_write_config_word(pdev, ua, ultra);
}

/**
 *	sil680_sff_exec_command - issue ATA command to host controller
 *	@ap: port to which command is being issued
 *	@tf: ATA taskfile register set
 *
 *	Issues ATA command, with proper synchronization with interrupt
 *	handler / other threads. Use our MMIO space for PCI posting to avoid
 *	a hideously slow cycle all the way to the device.
 *
 *	LOCKING:
 *	spin_lock_irqsave(host lock)
 */
static void sil680_sff_exec_command(struct ata_port *ap,
				    const struct ata_taskfile *tf)
{
	iowrite8(tf->command, ap->ioaddr.command_addr);
	ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
}

static bool sil680_sff_irq_check(struct ata_port *ap)
{
	struct pci_dev *pdev	= to_pci_dev(ap->host->dev);
	int addr		= sil680_selreg(ap, 1);
	u8 val;

	pci_read_config_byte(pdev, addr, &val);

	return val & 0x08;
}

static struct scsi_host_template sil680_sht = {
	ATA_BMDMA_SHT(DRV_NAME),
};


static struct ata_port_operations sil680_port_ops = {
	.inherits		= &ata_bmdma32_port_ops,
	.sff_exec_command	= sil680_sff_exec_command,
	.sff_irq_check		= sil680_sff_irq_check,
	.cable_detect		= sil680_cable_detect,
	.set_piomode		= sil680_set_piomode,
	.set_dmamode		= sil680_set_dmamode,
};

/**
 *	sil680_init_chip		-	chip setup
 *	@pdev: PCI device
 *	@try_mmio: Indicates to caller whether MMIO should be attempted
 *
 *	Perform all the chip setup which must be done both when the device
 *	is powered up on boot and when we resume in case we resumed from RAM.
 *	Returns the final clock settings.
 */

static u8 sil680_init_chip(struct pci_dev *pdev, int *try_mmio)
{
	u8 tmpbyte	= 0;

	/* FIXME: double check */
	pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE,
			      pdev->revision ? 1 : 255);

	pci_write_config_byte(pdev, 0x80, 0x00);
	pci_write_config_byte(pdev, 0x84, 0x00);

	pci_read_config_byte(pdev, 0x8A, &tmpbyte);

	dev_dbg(&pdev->dev, "sil680: BA5_EN = %d clock = %02X\n",
		tmpbyte & 1, tmpbyte & 0x30);

	*try_mmio = 0;
#ifdef CONFIG_PPC
	if (machine_is(cell))
		*try_mmio = (tmpbyte & 1) || pci_resource_start(pdev, 5);
#endif

	switch (tmpbyte & 0x30) {
	case 0x00:
		/* 133 clock attempt to force it on */
		pci_write_config_byte(pdev, 0x8A, tmpbyte|0x10);
		break;
	case 0x30:
		/* if clocking is disabled */
		/* 133 clock attempt to force it on */
		pci_write_config_byte(pdev, 0x8A, tmpbyte & ~0x20);
		break;
	case 0x10:
		/* 133 already */
		break;
	case 0x20:
		/* BIOS set PCI x2 clocking */
		break;
	}

	pci_read_config_byte(pdev,   0x8A, &tmpbyte);
	dev_dbg(&pdev->dev, "sil680: BA5_EN = %d clock = %02X\n",
		tmpbyte & 1, tmpbyte & 0x30);

	pci_write_config_byte(pdev,  0xA1, 0x72);
	pci_write_config_word(pdev,  0xA2, 0x328A);
	pci_write_config_dword(pdev, 0xA4, 0x62DD62DD);
	pci_write_config_dword(pdev, 0xA8, 0x43924392);
	pci_write_config_dword(pdev, 0xAC, 0x40094009);
	pci_write_config_byte(pdev,  0xB1, 0x72);
	pci_write_config_word(pdev,  0xB2, 0x328A);
	pci_write_config_dword(pdev, 0xB4, 0x62DD62DD);
	pci_write_config_dword(pdev, 0xB8, 0x43924392);
	pci_write_config_dword(pdev, 0xBC, 0x40094009);

	switch (tmpbyte & 0x30) {
	case 0x00:
		dev_info(&pdev->dev, "sil680: 100MHz clock.\n");
		break;
	case 0x10:
		dev_info(&pdev->dev, "sil680: 133MHz clock.\n");
		break;
	case 0x20:
		dev_info(&pdev->dev, "sil680: Using PCI clock.\n");
		break;
	/* This last case is _NOT_ ok */
	case 0x30:
		dev_err(&pdev->dev, "sil680: Clock disabled ?\n");
	}
	return tmpbyte & 0x30;
}

static int sil680_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
{
	static const struct ata_port_info info = {
		.flags = ATA_FLAG_SLAVE_POSS,
		.pio_mask = ATA_PIO4,
		.mwdma_mask = ATA_MWDMA2,
		.udma_mask = ATA_UDMA6,
		.port_ops = &sil680_port_ops
	};
	static const struct ata_port_info info_slow = {
		.flags = ATA_FLAG_SLAVE_POSS,
		.pio_mask = ATA_PIO4,
		.mwdma_mask = ATA_MWDMA2,
		.udma_mask = ATA_UDMA5,
		.port_ops = &sil680_port_ops
	};
	const struct ata_port_info *ppi[] = { &info, NULL };
	struct ata_host *host;
	void __iomem *mmio_base;
	int rc, try_mmio;

	ata_print_version_once(&pdev->dev, DRV_VERSION);

	rc = pcim_enable_device(pdev);
	if (rc)
		return rc;

	switch (sil680_init_chip(pdev, &try_mmio)) {
		case 0:
			ppi[0] = &info_slow;
			break;
		case 0x30:
			return -ENODEV;
	}

	if (!try_mmio)
		goto use_ioports;

	/* Try to acquire MMIO resources and fallback to PIO if
	 * that fails
	 */
	rc = pcim_iomap_regions(pdev, 1 << SIL680_MMIO_BAR, DRV_NAME);
	if (rc)
		goto use_ioports;

	/* Allocate host and set it up */
	host = ata_host_alloc_pinfo(&pdev->dev, ppi, 2);
	if (!host)
		return -ENOMEM;
	host->iomap = pcim_iomap_table(pdev);

	/* Setup DMA masks */
	rc = dma_set_mask_and_coherent(&pdev->dev, ATA_DMA_MASK);
	if (rc)
		return rc;
	pci_set_master(pdev);

	/* Get MMIO base and initialize port addresses */
	mmio_base = host->iomap[SIL680_MMIO_BAR];
	host->ports[0]->ioaddr.bmdma_addr = mmio_base + 0x00;
	host->ports[0]->ioaddr.cmd_addr = mmio_base + 0x80;
	host->ports[0]->ioaddr.ctl_addr = mmio_base + 0x8a;
	host->ports[0]->ioaddr.altstatus_addr = mmio_base + 0x8a;
	ata_sff_std_ports(&host->ports[0]->ioaddr);
	host->ports[1]->ioaddr.bmdma_addr = mmio_base + 0x08;
	host->ports[1]->ioaddr.cmd_addr = mmio_base + 0xc0;
	host->ports[1]->ioaddr.ctl_addr = mmio_base + 0xca;
	host->ports[1]->ioaddr.altstatus_addr = mmio_base + 0xca;
	ata_sff_std_ports(&host->ports[1]->ioaddr);

	/* Register & activate */
	return ata_host_activate(host, pdev->irq, ata_bmdma_interrupt,
				 IRQF_SHARED, &sil680_sht);

use_ioports:
	return ata_pci_bmdma_init_one(pdev, ppi, &sil680_sht, NULL, 0);
}

#ifdef CONFIG_PM_SLEEP
static int sil680_reinit_one(struct pci_dev *pdev)
{
	struct ata_host *host = pci_get_drvdata(pdev);
	int try_mmio, rc;

	rc = ata_pci_device_do_resume(pdev);
	if (rc)
		return rc;
	sil680_init_chip(pdev, &try_mmio);
	ata_host_resume(host);
	return 0;
}
#endif

static const struct pci_device_id sil680[] = {
	{ PCI_VDEVICE(CMD, PCI_DEVICE_ID_SII_680), },

	{ },
};

static struct pci_driver sil680_pci_driver = {
	.name 		= DRV_NAME,
	.id_table	= sil680,
	.probe 		= sil680_init_one,
	.remove		= ata_pci_remove_one,
#ifdef CONFIG_PM_SLEEP
	.suspend	= ata_pci_device_suspend,
	.resume		= sil680_reinit_one,
#endif
};

module_pci_driver(sil680_pci_driver);

MODULE_AUTHOR("Alan Cox");
MODULE_DESCRIPTION("low-level driver for SI680 PATA");
MODULE_LICENSE("GPL");
MODULE_DEVICE_TABLE(pci, sil680);
MODULE_VERSION(DRV_VERSION);
Commit	Line	Data
669a5db4 JG	1	/*
	2	* pata_sil680.c - SIL680 PATA for new ATA layer
	3	* (C) 2005 Red Hat Inc
669a5db4 JG	4	*
	5	* based upon
	6	*
	7	* linux/drivers/ide/pci/siimage.c Version 1.07 Nov 30, 2003
	8	*
	9	* Copyright (C) 2001-2002 Andre Hedrick <andre@linux-ide.org>
	10	* Copyright (C) 2003 Red Hat <alan@redhat.com>
	11	*
	12	* May be copied or modified under the terms of the GNU General Public License
	13	*
25985edc	14	* Documentation publicly available.
669a5db4 JG	15	*
	16	* If you have strange problems with nVidia chipset systems please
	17	* see the SI support documentation and update your system BIOS
3a4fa0a2	18	* if necessary
669a5db4 JG	19	*
	20	* TODO
	21	* If we know all our devices are LBA28 (or LBA28 sized) we could use
	22	* the command fifo mode.
	23	*/
	24
	25	#include <linux/kernel.h>
	26	#include <linux/module.h>
	27	#include <linux/pci.h>
669a5db4 JG	28	#include <linux/blkdev.h>
	29	#include <linux/delay.h>
	30	#include <scsi/scsi_host.h>
	31	#include <linux/libata.h>
	32
	33	#define DRV_NAME "pata_sil680"
871af121	34	#define DRV_VERSION "0.4.9"
669a5db4	35
79b0bde1 JG	36	#define SIL680_MMIO_BAR 5
79b0bde1 JG	37
669a5db4 JG	38	/**
669a5db4 JG	39	* sil680_selreg - return register base
6352187e	40	* @ap: ATA interface
669a5db4 JG	41	* @r: config offset
669a5db4 JG	42	*
6352187e BZ	43	* Turn a config register offset into the right address in PCI space
	44	* to access the control register in question.
	45	*
25985edc	46	* Thankfully this is a configuration operation so isn't performance
669a5db4 JG	47	* criticial.
	48	*/
	49
dafbbf5c	50	static int sil680_selreg(struct ata_port *ap, int r)
669a5db4	51	{
dafbbf5c	52	return 0xA0 + (ap->port_no << 4) + r;
669a5db4 JG	53	}
	54
	55	/**
	56	* sil680_seldev - return register base
6352187e	57	* @ap: ATA interface
91c50d8a	58	* @adev: ATA device
669a5db4 JG	59	* @r: config offset
669a5db4 JG	60	*
6352187e BZ	61	* Turn a config register offset into the right address in PCI space
	62	* to access the control register in question including accounting for
	63	* the unit shift.
669a5db4 JG	64	*/
669a5db4 JG	65
dafbbf5c	66	static int sil680_seldev(struct ata_port ap, struct ata_device adev, int r)
669a5db4	67	{
dafbbf5c	68	return 0xA0 + (ap->port_no << 4) + r + (adev->devno << 1);
669a5db4 JG	69	}
	70
	71
	72	/**
	73	* sil680_cable_detect - cable detection
	74	* @ap: ATA port
	75	*
	76	* Perform cable detection. The SIL680 stores this in PCI config
	77	* space for us.
	78	*/
	79
7a113d38 BZ	80	static int sil680_cable_detect(struct ata_port *ap)
7a113d38 BZ	81	{
669a5db4	82	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
dafbbf5c	83	int addr = sil680_selreg(ap, 0);
669a5db4	84	u8 ata66;
dafbbf5c	85
669a5db4 JG	86	pci_read_config_byte(pdev, addr, &ata66);
	87	if (ata66 & 1)
	88	return ATA_CBL_PATA80;
	89	else
	90	return ATA_CBL_PATA40;
	91	}
	92
669a5db4	93	/**
6352187e	94	* sil680_set_piomode - set PIO mode data
669a5db4 JG	95	* @ap: ATA interface
	96	* @adev: ATA device
	97	*
	98	* Program the SIL680 registers for PIO mode. Note that the task speed
	99	* registers are shared between the devices so we must pick the lowest
	100	* mode for command work.
	101	*/
	102
	103	static void sil680_set_piomode(struct ata_port ap, struct ata_device adev)
	104	{
9b8ad4ac BZ	105	static const u16 speed_p[5] = {
	106	0x328A, 0x2283, 0x1104, 0x10C3, 0x10C1
	107	};
	108	static const u16 speed_t[5] = {
	109	0x328A, 0x2283, 0x1281, 0x10C3, 0x10C1
	110	};
669a5db4	111
dafbbf5c SS	112	int tfaddr = sil680_selreg(ap, 0x02);
	113	int addr = sil680_seldev(ap, adev, 0x04);
	114	int addr_mask = 0x80 + 4 * ap->port_no;
669a5db4 JG	115	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	116	int pio = adev->pio_mode - XFER_PIO_0;
	117	int lowest_pio = pio;
cb0e34ba	118	int port_shift = 4 * adev->devno;
669a5db4	119	u16 reg;
cb0e34ba	120	u8 mode;
669a5db4 JG	121
	122	struct ata_device *pair = ata_dev_pair(adev);
	123
	124	if (pair != NULL && adev->pio_mode > pair->pio_mode)
	125	lowest_pio = pair->pio_mode - XFER_PIO_0;
	126
	127	pci_write_config_word(pdev, addr, speed_p[pio]);
	128	pci_write_config_word(pdev, tfaddr, speed_t[lowest_pio]);
	129
	130	pci_read_config_word(pdev, tfaddr-2, &reg);
cb0e34ba	131	pci_read_config_byte(pdev, addr_mask, &mode);
a84471fe	132
669a5db4	133	reg &= ~0x0200; /* Clear IORDY */
cb0e34ba	134	mode &= ~(3 << port_shift); /* Clear IORDY and DMA bits */
a84471fe	135
cb0e34ba	136	if (ata_pio_need_iordy(adev)) {
669a5db4	137	reg \|= 0x0200; /* Enable IORDY */
cb0e34ba A	138	mode \|= 1 << port_shift;
cb0e34ba A	139	}
669a5db4	140	pci_write_config_word(pdev, tfaddr-2, reg);
cb0e34ba	141	pci_write_config_byte(pdev, addr_mask, mode);
669a5db4 JG	142	}
	143
	144	/**
6352187e	145	* sil680_set_dmamode - set DMA mode data
669a5db4 JG	146	* @ap: ATA interface
	147	* @adev: ATA device
	148	*
6352187e BZ	149	* Program the MWDMA/UDMA modes for the sil680 chipset.
	150	*
	151	* The MWDMA mode values are pulled from a lookup table
669a5db4 JG	152	* while the chipset uses mode number for UDMA.
	153	*/
	154
	155	static void sil680_set_dmamode(struct ata_port ap, struct ata_device adev)
	156	{
9b8ad4ac	157	static const u8 ultra_table[2][7] = {
669a5db4 JG	158	{ 0x0C, 0x07, 0x05, 0x04, 0x02, 0x01, 0xFF }, /* 100MHz */
	159	{ 0x0F, 0x0B, 0x07, 0x05, 0x03, 0x02, 0x01 }, /* 133Mhz */
	160	};
9b8ad4ac	161	static const u16 dma_table[3] = { 0x2208, 0x10C2, 0x10C1 };
669a5db4 JG	162
669a5db4 JG	163	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
dafbbf5c SS	164	int ma = sil680_seldev(ap, adev, 0x08);
	165	int ua = sil680_seldev(ap, adev, 0x0C);
	166	int addr_mask = 0x80 + 4 * ap->port_no;
669a5db4 JG	167	int port_shift = adev->devno * 4;
	168	u8 scsc, mode;
	169	u16 multi, ultra;
	170
	171	pci_read_config_byte(pdev, 0x8A, &scsc);
	172	pci_read_config_byte(pdev, addr_mask, &mode);
	173	pci_read_config_word(pdev, ma, &multi);
	174	pci_read_config_word(pdev, ua, &ultra);
	175
	176	/* Mask timing bits */
	177	ultra &= ~0x3F;
	178	mode &= ~(0x03 << port_shift);
	179
	180	/* Extract scsc */
7a113d38	181	scsc = (scsc & 0x30) ? 1 : 0;
669a5db4 JG	182
	183	if (adev->dma_mode >= XFER_UDMA_0) {
	184	multi = 0x10C1;
	185	ultra \|= ultra_table[scsc][adev->dma_mode - XFER_UDMA_0];
	186	mode \|= (0x03 << port_shift);
	187	} else {
	188	multi = dma_table[adev->dma_mode - XFER_MW_DMA_0];
	189	mode \|= (0x02 << port_shift);
	190	}
	191	pci_write_config_byte(pdev, addr_mask, mode);
	192	pci_write_config_word(pdev, ma, multi);
	193	pci_write_config_word(pdev, ua, ultra);
	194	}
	195
c4acf99b AC	196	/**
	197	* sil680_sff_exec_command - issue ATA command to host controller
	198	* @ap: port to which command is being issued
	199	* @tf: ATA taskfile register set
	200	*
	201	* Issues ATA command, with proper synchronization with interrupt
	202	* handler / other threads. Use our MMIO space for PCI posting to avoid
	203	* a hideously slow cycle all the way to the device.
	204	*
	205	* LOCKING:
	206	* spin_lock_irqsave(host lock)
	207	*/
ada5b12e SS	208	static void sil680_sff_exec_command(struct ata_port *ap,
ada5b12e SS	209	const struct ata_taskfile *tf)
c4acf99b	210	{
c4acf99b AC	211	iowrite8(tf->command, ap->ioaddr.command_addr);
	212	ioread8(ap->ioaddr.bmdma_addr + ATA_DMA_CMD);
	213	}
	214
9b980e10 SS	215	static bool sil680_sff_irq_check(struct ata_port *ap)
	216	{
	217	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
dafbbf5c	218	int addr = sil680_selreg(ap, 1);
9b980e10 SS	219	u8 val;
	220
	221	pci_read_config_byte(pdev, addr, &val);
	222
	223	return val & 0x08;
	224	}
	225
669a5db4	226	static struct scsi_host_template sil680_sht = {
68d1d07b	227	ATA_BMDMA_SHT(DRV_NAME),
669a5db4 JG	228	};
669a5db4 JG	229
c4acf99b	230
669a5db4	231	static struct ata_port_operations sil680_port_ops = {
c4acf99b AC	232	.inherits = &ata_bmdma32_port_ops,
c4acf99b AC	233	.sff_exec_command = sil680_sff_exec_command,
9b980e10	234	.sff_irq_check = sil680_sff_irq_check,
c4acf99b AC	235	.cable_detect = sil680_cable_detect,
	236	.set_piomode = sil680_set_piomode,
	237	.set_dmamode = sil680_set_dmamode,
669a5db4 JG	238	};
669a5db4 JG	239
8550c163 A	240	/**
	241	* sil680_init_chip - chip setup
	242	* @pdev: PCI device
91c50d8a	243	* @try_mmio: Indicates to caller whether MMIO should be attempted
8550c163 A	244	*
	245	* Perform all the chip setup which must be done both when the device
	246	* is powered up on boot and when we resume in case we resumed from RAM.
	247	* Returns the final clock settings.
	248	*/
f20b16ff	249
2b9e68f7	250	static u8 sil680_init_chip(struct pci_dev pdev, int try_mmio)
669a5db4	251	{
669a5db4 JG	252	u8 tmpbyte = 0;
669a5db4 JG	253
7a113d38	254	/* FIXME: double check */
89d3b360 SS	255	pci_write_config_byte(pdev, PCI_CACHE_LINE_SIZE,
89d3b360 SS	256	pdev->revision ? 1 : 255);
669a5db4 JG	257
	258	pci_write_config_byte(pdev, 0x80, 0x00);
	259	pci_write_config_byte(pdev, 0x84, 0x00);
	260
	261	pci_read_config_byte(pdev, 0x8A, &tmpbyte);
	262
79b0bde1 JG	263	dev_dbg(&pdev->dev, "sil680: BA5_EN = %d clock = %02X\n",
79b0bde1 JG	264	tmpbyte & 1, tmpbyte & 0x30);
669a5db4	265
0f436eff	266	*try_mmio = 0;
47d692a9	267	#ifdef CONFIG_PPC
0f436eff BH	268	if (machine_is(cell))
	269	*try_mmio = (tmpbyte & 1) \|\| pci_resource_start(pdev, 5);
	270	#endif
2b9e68f7	271
7a113d38 BZ	272	switch (tmpbyte & 0x30) {
	273	case 0x00:
	274	/* 133 clock attempt to force it on */
	275	pci_write_config_byte(pdev, 0x8A, tmpbyte\|0x10);
	276	break;
	277	case 0x30:
	278	/* if clocking is disabled */
	279	/* 133 clock attempt to force it on */
	280	pci_write_config_byte(pdev, 0x8A, tmpbyte & ~0x20);
	281	break;
	282	case 0x10:
	283	/* 133 already */
	284	break;
	285	case 0x20:
	286	/* BIOS set PCI x2 clocking */
	287	break;
669a5db4 JG	288	}
	289
	290	pci_read_config_byte(pdev, 0x8A, &tmpbyte);
79b0bde1 JG	291	dev_dbg(&pdev->dev, "sil680: BA5_EN = %d clock = %02X\n",
79b0bde1 JG	292	tmpbyte & 1, tmpbyte & 0x30);
669a5db4 JG	293
	294	pci_write_config_byte(pdev, 0xA1, 0x72);
	295	pci_write_config_word(pdev, 0xA2, 0x328A);
	296	pci_write_config_dword(pdev, 0xA4, 0x62DD62DD);
	297	pci_write_config_dword(pdev, 0xA8, 0x43924392);
	298	pci_write_config_dword(pdev, 0xAC, 0x40094009);
	299	pci_write_config_byte(pdev, 0xB1, 0x72);
	300	pci_write_config_word(pdev, 0xB2, 0x328A);
	301	pci_write_config_dword(pdev, 0xB4, 0x62DD62DD);
	302	pci_write_config_dword(pdev, 0xB8, 0x43924392);
	303	pci_write_config_dword(pdev, 0xBC, 0x40094009);
	304
7a113d38 BZ	305	switch (tmpbyte & 0x30) {
7a113d38 BZ	306	case 0x00:
3156234b	307	dev_info(&pdev->dev, "sil680: 100MHz clock.\n");
7a113d38 BZ	308	break;
7a113d38 BZ	309	case 0x10:
3156234b	310	dev_info(&pdev->dev, "sil680: 133MHz clock.\n");
7a113d38 BZ	311	break;
7a113d38 BZ	312	case 0x20:
3156234b	313	dev_info(&pdev->dev, "sil680: Using PCI clock.\n");
7a113d38 BZ	314	break;
	315	/* This last case is _NOT_ ok */
	316	case 0x30:
3156234b	317	dev_err(&pdev->dev, "sil680: Clock disabled ?\n");
8550c163 A	318	}
	319	return tmpbyte & 0x30;
	320	}
	321
0ec24914	322	static int sil680_init_one(struct pci_dev pdev, const struct pci_device_id id)
8550c163	323	{
1626aeb8	324	static const struct ata_port_info info = {
1d2808fd	325	.flags = ATA_FLAG_SLAVE_POSS,
14bdef98 EIB	326	.pio_mask = ATA_PIO4,
14bdef98 EIB	327	.mwdma_mask = ATA_MWDMA2,
bf6263a8	328	.udma_mask = ATA_UDMA6,
8550c163 A	329	.port_ops = &sil680_port_ops
8550c163 A	330	};
1626aeb8	331	static const struct ata_port_info info_slow = {
1d2808fd	332	.flags = ATA_FLAG_SLAVE_POSS,
14bdef98 EIB	333	.pio_mask = ATA_PIO4,
14bdef98 EIB	334	.mwdma_mask = ATA_MWDMA2,
bf6263a8	335	.udma_mask = ATA_UDMA5,
8550c163 A	336	.port_ops = &sil680_port_ops
8550c163 A	337	};
1626aeb8	338	const struct ata_port_info *ppi[] = { &info, NULL };
2b9e68f7 BH	339	struct ata_host *host;
	340	void __iomem *mmio_base;
	341	int rc, try_mmio;
8550c163	342
06296a1e	343	ata_print_version_once(&pdev->dev, DRV_VERSION);
8550c163	344
f08048e9 TH	345	rc = pcim_enable_device(pdev);
	346	if (rc)
	347	return rc;
	348
2b9e68f7	349	switch (sil680_init_chip(pdev, &try_mmio)) {
8550c163	350	case 0:
1626aeb8	351	ppi[0] = &info_slow;
8550c163 A	352	break;
	353	case 0x30:
	354	return -ENODEV;
669a5db4	355	}
2b9e68f7 BH	356
	357	if (!try_mmio)
	358	goto use_ioports;
	359
	360	/* Try to acquire MMIO resources and fallback to PIO if
	361	* that fails
	362	*/
2b9e68f7 BH	363	rc = pcim_iomap_regions(pdev, 1 << SIL680_MMIO_BAR, DRV_NAME);
	364	if (rc)
	365	goto use_ioports;
	366
	367	/* Allocate host and set it up */
	368	host = ata_host_alloc_pinfo(&pdev->dev, ppi, 2);
	369	if (!host)
	370	return -ENOMEM;
	371	host->iomap = pcim_iomap_table(pdev);
	372
	373	/* Setup DMA masks */
b5e55556	374	rc = dma_set_mask_and_coherent(&pdev->dev, ATA_DMA_MASK);
2b9e68f7 BH	375	if (rc)
	376	return rc;
	377	pci_set_master(pdev);
	378
	379	/* Get MMIO base and initialize port addresses */
	380	mmio_base = host->iomap[SIL680_MMIO_BAR];
	381	host->ports[0]->ioaddr.bmdma_addr = mmio_base + 0x00;
	382	host->ports[0]->ioaddr.cmd_addr = mmio_base + 0x80;
	383	host->ports[0]->ioaddr.ctl_addr = mmio_base + 0x8a;
	384	host->ports[0]->ioaddr.altstatus_addr = mmio_base + 0x8a;
9363c382	385	ata_sff_std_ports(&host->ports[0]->ioaddr);
2b9e68f7 BH	386	host->ports[1]->ioaddr.bmdma_addr = mmio_base + 0x08;
	387	host->ports[1]->ioaddr.cmd_addr = mmio_base + 0xc0;
	388	host->ports[1]->ioaddr.ctl_addr = mmio_base + 0xca;
	389	host->ports[1]->ioaddr.altstatus_addr = mmio_base + 0xca;
9363c382	390	ata_sff_std_ports(&host->ports[1]->ioaddr);
2b9e68f7 BH	391
2b9e68f7 BH	392	/* Register & activate */
c3b28894	393	return ata_host_activate(host, pdev->irq, ata_bmdma_interrupt,
9363c382	394	IRQF_SHARED, &sil680_sht);
2b9e68f7 BH	395
2b9e68f7 BH	396	use_ioports:
1c5afdf7	397	return ata_pci_bmdma_init_one(pdev, ppi, &sil680_sht, NULL, 0);
669a5db4 JG	398	}
669a5db4 JG	399
58eb8cd5	400	#ifdef CONFIG_PM_SLEEP
8550c163 A	401	static int sil680_reinit_one(struct pci_dev *pdev)
8550c163 A	402	{
0a86e1c8	403	struct ata_host *host = pci_get_drvdata(pdev);
f08048e9	404	int try_mmio, rc;
2b9e68f7	405
f08048e9 TH	406	rc = ata_pci_device_do_resume(pdev);
	407	if (rc)
	408	return rc;
2b9e68f7	409	sil680_init_chip(pdev, &try_mmio);
f08048e9 TH	410	ata_host_resume(host);
f08048e9 TH	411	return 0;
8550c163	412	}
438ac6d5	413	#endif
8550c163	414
669a5db4	415	static const struct pci_device_id sil680[] = {
2d2744fc JG	416	{ PCI_VDEVICE(CMD, PCI_DEVICE_ID_SII_680), },
	417
	418	{ },
669a5db4 JG	419	};
	420
	421	static struct pci_driver sil680_pci_driver = {
2d2744fc	422	.name = DRV_NAME,
669a5db4 JG	423	.id_table = sil680,
669a5db4 JG	424	.probe = sil680_init_one,
8550c163	425	.remove = ata_pci_remove_one,
58eb8cd5	426	#ifdef CONFIG_PM_SLEEP
8550c163 A	427	.suspend = ata_pci_device_suspend,
8550c163 A	428	.resume = sil680_reinit_one,
438ac6d5	429	#endif
669a5db4 JG	430	};
669a5db4 JG	431
2fc75da0	432	module_pci_driver(sil680_pci_driver);
669a5db4	433
669a5db4 JG	434	MODULE_AUTHOR("Alan Cox");
	435	MODULE_DESCRIPTION("low-level driver for SI680 PATA");
	436	MODULE_LICENSE("GPL");
	437	MODULE_DEVICE_TABLE(pci, sil680);
	438	MODULE_VERSION(DRV_VERSION);