[linux-block.git] / drivers / ata / pata_pxa.c

/*
 * Generic PXA PATA driver
 *
 * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
 *
 *  This program is free software; you can redistribute it and/or modify
 *  it under the terms of the GNU General Public License as published by
 *  the Free Software Foundation; either version 2, or (at your option)
 *  any later version.
 *
 *  This program is distributed in the hope that it will be useful,
 *  but WITHOUT ANY WARRANTY; without even the implied warranty of
 *  MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
 *  GNU General Public License for more details.
 *
 *  You should have received a copy of the GNU General Public License
 *  along with this program; see the file COPYING.  If not, write to
 *  the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/blkdev.h>
#include <linux/ata.h>
#include <linux/libata.h>
#include <linux/platform_device.h>
#include <linux/dmaengine.h>
#include <linux/slab.h>
#include <linux/completion.h>

#include <scsi/scsi_host.h>

#include <linux/platform_data/ata-pxa.h>

#define DRV_NAME	"pata_pxa"
#define DRV_VERSION	"0.1"

struct pata_pxa_data {
	struct dma_chan		*dma_chan;
	dma_cookie_t		dma_cookie;
	struct completion	dma_done;
};

/*
 * DMA interrupt handler.
 */
static void pxa_ata_dma_irq(void *d)
{
	struct pata_pxa_data *pd = d;
	enum dma_status status;

	status = dmaengine_tx_status(pd->dma_chan, pd->dma_cookie, NULL);
	if (status == DMA_ERROR || status == DMA_COMPLETE)
		complete(&pd->dma_done);
}

/*
 * Prepare taskfile for submission.
 */
static void pxa_qc_prep(struct ata_queued_cmd *qc)
{
	struct pata_pxa_data *pd = qc->ap->private_data;
	struct dma_async_tx_descriptor *tx;
	enum dma_transfer_direction dir;

	if (!(qc->flags & ATA_QCFLAG_DMAMAP))
		return;

	dir = (qc->dma_dir == DMA_TO_DEVICE ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM);
	tx = dmaengine_prep_slave_sg(pd->dma_chan, qc->sg, qc->n_elem, dir,
				     DMA_PREP_INTERRUPT);
	if (!tx) {
		ata_dev_err(qc->dev, "prep_slave_sg() failed\n");
		return;
	}
	tx->callback = pxa_ata_dma_irq;
	tx->callback_param = pd;
	pd->dma_cookie = dmaengine_submit(tx);
}

/*
 * Configure the DMA controller, load the DMA descriptors, but don't start the
 * DMA controller yet. Only issue the ATA command.
 */
static void pxa_bmdma_setup(struct ata_queued_cmd *qc)
{
	qc->ap->ops->sff_exec_command(qc->ap, &qc->tf);
}

/*
 * Execute the DMA transfer.
 */
static void pxa_bmdma_start(struct ata_queued_cmd *qc)
{
	struct pata_pxa_data *pd = qc->ap->private_data;
	init_completion(&pd->dma_done);
	dma_async_issue_pending(pd->dma_chan);
}

/*
 * Wait until the DMA transfer completes, then stop the DMA controller.
 */
static void pxa_bmdma_stop(struct ata_queued_cmd *qc)
{
	struct pata_pxa_data *pd = qc->ap->private_data;
	enum dma_status status;

	status = dmaengine_tx_status(pd->dma_chan, pd->dma_cookie, NULL);
	if (status != DMA_ERROR && status != DMA_COMPLETE &&
	    wait_for_completion_timeout(&pd->dma_done, HZ))
		ata_dev_err(qc->dev, "Timeout waiting for DMA completion!");

	dmaengine_terminate_all(pd->dma_chan);
}

/*
 * Read DMA status. The bmdma_stop() will take care of properly finishing the
 * DMA transfer so we always have DMA-complete interrupt here.
 */
static unsigned char pxa_bmdma_status(struct ata_port *ap)
{
	struct pata_pxa_data *pd = ap->private_data;
	unsigned char ret = ATA_DMA_INTR;
	struct dma_tx_state state;
	enum dma_status status;

	status = dmaengine_tx_status(pd->dma_chan, pd->dma_cookie, &state);
	if (status != DMA_COMPLETE)
		ret |= ATA_DMA_ERR;

	return ret;
}

/*
 * No IRQ register present so we do nothing.
 */
static void pxa_irq_clear(struct ata_port *ap)
{
}

/*
 * Check for ATAPI DMA. ATAPI DMA is unsupported by this driver. It's still
 * unclear why ATAPI has DMA issues.
 */
static int pxa_check_atapi_dma(struct ata_queued_cmd *qc)
{
	return -EOPNOTSUPP;
}

static struct scsi_host_template pxa_ata_sht = {
	ATA_BMDMA_SHT(DRV_NAME),
};

static struct ata_port_operations pxa_ata_port_ops = {
	.inherits		= &ata_bmdma_port_ops,
	.cable_detect		= ata_cable_40wire,

	.bmdma_setup		= pxa_bmdma_setup,
	.bmdma_start		= pxa_bmdma_start,
	.bmdma_stop		= pxa_bmdma_stop,
	.bmdma_status		= pxa_bmdma_status,

	.check_atapi_dma	= pxa_check_atapi_dma,

	.sff_irq_clear		= pxa_irq_clear,

	.qc_prep		= pxa_qc_prep,
};

static int pxa_ata_probe(struct platform_device *pdev)
{
	struct ata_host *host;
	struct ata_port *ap;
	struct pata_pxa_data *data;
	struct resource *cmd_res;
	struct resource *ctl_res;
	struct resource *dma_res;
	struct resource *irq_res;
	struct pata_pxa_pdata *pdata = dev_get_platdata(&pdev->dev);
	struct dma_slave_config	config;
	int ret = 0;

	/*
	 * Resource validation, three resources are needed:
	 *  - CMD port base address
	 *  - CTL port base address
	 *  - DMA port base address
	 *  - IRQ pin
	 */
	if (pdev->num_resources != 4) {
		dev_err(&pdev->dev, "invalid number of resources\n");
		return -EINVAL;
	}

	/*
	 * CMD port base address
	 */
	cmd_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (unlikely(cmd_res == NULL))
		return -EINVAL;

	/*
	 * CTL port base address
	 */
	ctl_res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
	if (unlikely(ctl_res == NULL))
		return -EINVAL;

	/*
	 * DMA port base address
	 */
	dma_res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
	if (unlikely(dma_res == NULL))
		return -EINVAL;

	/*
	 * IRQ pin
	 */
	irq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
	if (unlikely(irq_res == NULL))
		return -EINVAL;

	/*
	 * Allocate the host
	 */
	host = ata_host_alloc(&pdev->dev, 1);
	if (!host)
		return -ENOMEM;

	ap		= host->ports[0];
	ap->ops		= &pxa_ata_port_ops;
	ap->pio_mask	= ATA_PIO4;
	ap->mwdma_mask	= ATA_MWDMA2;

	ap->ioaddr.cmd_addr	= devm_ioremap(&pdev->dev, cmd_res->start,
						resource_size(cmd_res));
	ap->ioaddr.ctl_addr	= devm_ioremap(&pdev->dev, ctl_res->start,
						resource_size(ctl_res));
	ap->ioaddr.bmdma_addr	= devm_ioremap(&pdev->dev, dma_res->start,
						resource_size(dma_res));

	/*
	 * Adjust register offsets
	 */
	ap->ioaddr.altstatus_addr = ap->ioaddr.ctl_addr;
	ap->ioaddr.data_addr	= ap->ioaddr.cmd_addr +
					(ATA_REG_DATA << pdata->reg_shift);
	ap->ioaddr.error_addr	= ap->ioaddr.cmd_addr +
					(ATA_REG_ERR << pdata->reg_shift);
	ap->ioaddr.feature_addr	= ap->ioaddr.cmd_addr +
					(ATA_REG_FEATURE << pdata->reg_shift);
	ap->ioaddr.nsect_addr	= ap->ioaddr.cmd_addr +
					(ATA_REG_NSECT << pdata->reg_shift);
	ap->ioaddr.lbal_addr	= ap->ioaddr.cmd_addr +
					(ATA_REG_LBAL << pdata->reg_shift);
	ap->ioaddr.lbam_addr	= ap->ioaddr.cmd_addr +
					(ATA_REG_LBAM << pdata->reg_shift);
	ap->ioaddr.lbah_addr	= ap->ioaddr.cmd_addr +
					(ATA_REG_LBAH << pdata->reg_shift);
	ap->ioaddr.device_addr	= ap->ioaddr.cmd_addr +
					(ATA_REG_DEVICE << pdata->reg_shift);
	ap->ioaddr.status_addr	= ap->ioaddr.cmd_addr +
					(ATA_REG_STATUS << pdata->reg_shift);
	ap->ioaddr.command_addr	= ap->ioaddr.cmd_addr +
					(ATA_REG_CMD << pdata->reg_shift);

	/*
	 * Allocate and load driver's internal data structure
	 */
	data = devm_kzalloc(&pdev->dev, sizeof(struct pata_pxa_data),
								GFP_KERNEL);
	if (!data)
		return -ENOMEM;

	ap->private_data = data;

	memset(&config, 0, sizeof(config));
	config.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
	config.dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
	config.src_addr = dma_res->start;
	config.dst_addr = dma_res->start;
	config.src_maxburst = 32;
	config.dst_maxburst = 32;

	/*
	 * Request the DMA channel
	 */
	data->dma_chan =
		dma_request_slave_channel(&pdev->dev, "data");
	if (!data->dma_chan)
		return -EBUSY;
	ret = dmaengine_slave_config(data->dma_chan, &config);
	if (ret < 0) {
		dev_err(&pdev->dev, "dma configuration failed: %d\n", ret);
		return ret;
	}

	/*
	 * Activate the ATA host
	 */
	ret = ata_host_activate(host, irq_res->start, ata_sff_interrupt,
				pdata->irq_flags, &pxa_ata_sht);
	if (ret)
		dma_release_channel(data->dma_chan);

	return ret;
}

static int pxa_ata_remove(struct platform_device *pdev)
{
	struct ata_host *host = platform_get_drvdata(pdev);
	struct pata_pxa_data *data = host->ports[0]->private_data;

	dma_release_channel(data->dma_chan);

	ata_host_detach(host);

	return 0;
}

static struct platform_driver pxa_ata_driver = {
	.probe		= pxa_ata_probe,
	.remove		= pxa_ata_remove,
	.driver		= {
		.name		= DRV_NAME,
	},
};

module_platform_driver(pxa_ata_driver);

MODULE_AUTHOR("Marek Vasut <marek.vasut@gmail.com>");
MODULE_DESCRIPTION("DMA-capable driver for PATA on PXA CPU");
MODULE_LICENSE("GPL");
MODULE_VERSION(DRV_VERSION);
MODULE_ALIAS("platform:" DRV_NAME);
Commit	Line	Data
2dc6c6f1 MV	1	/*
	2	* Generic PXA PATA driver
	3	*
	4	* Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
	5	*
	6	* This program is free software; you can redistribute it and/or modify
	7	* it under the terms of the GNU General Public License as published by
	8	* the Free Software Foundation; either version 2, or (at your option)
	9	* any later version.
	10	*
	11	* This program is distributed in the hope that it will be useful,
	12	* but WITHOUT ANY WARRANTY; without even the implied warranty of
	13	* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
	14	* GNU General Public License for more details.
	15	*
	16	* You should have received a copy of the GNU General Public License
	17	* along with this program; see the file COPYING. If not, write to
	18	* the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA.
	19	*/
	20
	21	#include <linux/kernel.h>
	22	#include <linux/module.h>
2dc6c6f1 MV	23	#include <linux/blkdev.h>
	24	#include <linux/ata.h>
	25	#include <linux/libata.h>
	26	#include <linux/platform_device.h>
88622d80	27	#include <linux/dmaengine.h>
2dc6c6f1 MV	28	#include <linux/slab.h>
	29	#include <linux/completion.h>
	30
	31	#include <scsi/scsi_host.h>
	32
293b2da1	33	#include <linux/platform_data/ata-pxa.h>
2dc6c6f1 MV	34
	35	#define DRV_NAME "pata_pxa"
	36	#define DRV_VERSION "0.1"
	37
	38	struct pata_pxa_data {
88622d80 RJ	39	struct dma_chan *dma_chan;
88622d80 RJ	40	dma_cookie_t dma_cookie;
2dc6c6f1 MV	41	struct completion dma_done;
	42	};
	43
	44	/*
88622d80	45	* DMA interrupt handler.
2dc6c6f1	46	*/
88622d80	47	static void pxa_ata_dma_irq(void *d)
2dc6c6f1	48	{
88622d80 RJ	49	struct pata_pxa_data *pd = d;
88622d80 RJ	50	enum dma_status status;
2dc6c6f1	51
88622d80 RJ	52	status = dmaengine_tx_status(pd->dma_chan, pd->dma_cookie, NULL);
	53	if (status == DMA_ERROR \|\| status == DMA_COMPLETE)
	54	complete(&pd->dma_done);
2dc6c6f1 MV	55	}
	56
	57	/*
	58	* Prepare taskfile for submission.
	59	*/
	60	static void pxa_qc_prep(struct ata_queued_cmd *qc)
	61	{
	62	struct pata_pxa_data *pd = qc->ap->private_data;
88622d80 RJ	63	struct dma_async_tx_descriptor *tx;
88622d80 RJ	64	enum dma_transfer_direction dir;
2dc6c6f1 MV	65
	66	if (!(qc->flags & ATA_QCFLAG_DMAMAP))
	67	return;
	68
88622d80 RJ	69	dir = (qc->dma_dir == DMA_TO_DEVICE ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM);
	70	tx = dmaengine_prep_slave_sg(pd->dma_chan, qc->sg, qc->n_elem, dir,
	71	DMA_PREP_INTERRUPT);
	72	if (!tx) {
	73	ata_dev_err(qc->dev, "prep_slave_sg() failed\n");
	74	return;
	75	}
	76	tx->callback = pxa_ata_dma_irq;
	77	tx->callback_param = pd;
	78	pd->dma_cookie = dmaengine_submit(tx);
2dc6c6f1 MV	79	}
	80
	81	/*
	82	* Configure the DMA controller, load the DMA descriptors, but don't start the
	83	* DMA controller yet. Only issue the ATA command.
	84	*/
	85	static void pxa_bmdma_setup(struct ata_queued_cmd *qc)
	86	{
	87	qc->ap->ops->sff_exec_command(qc->ap, &qc->tf);
	88	}
	89
	90	/*
	91	* Execute the DMA transfer.
	92	*/
	93	static void pxa_bmdma_start(struct ata_queued_cmd *qc)
	94	{
	95	struct pata_pxa_data *pd = qc->ap->private_data;
	96	init_completion(&pd->dma_done);
88622d80	97	dma_async_issue_pending(pd->dma_chan);
2dc6c6f1 MV	98	}
	99
	100	/*
	101	* Wait until the DMA transfer completes, then stop the DMA controller.
	102	*/
	103	static void pxa_bmdma_stop(struct ata_queued_cmd *qc)
	104	{
	105	struct pata_pxa_data *pd = qc->ap->private_data;
88622d80	106	enum dma_status status;
2dc6c6f1	107
88622d80 RJ	108	status = dmaengine_tx_status(pd->dma_chan, pd->dma_cookie, NULL);
	109	if (status != DMA_ERROR && status != DMA_COMPLETE &&
	110	wait_for_completion_timeout(&pd->dma_done, HZ))
	111	ata_dev_err(qc->dev, "Timeout waiting for DMA completion!");
2dc6c6f1	112
88622d80	113	dmaengine_terminate_all(pd->dma_chan);
2dc6c6f1 MV	114	}
	115
	116	/*
	117	* Read DMA status. The bmdma_stop() will take care of properly finishing the
	118	* DMA transfer so we always have DMA-complete interrupt here.
	119	*/
	120	static unsigned char pxa_bmdma_status(struct ata_port *ap)
	121	{
	122	struct pata_pxa_data *pd = ap->private_data;
	123	unsigned char ret = ATA_DMA_INTR;
88622d80 RJ	124	struct dma_tx_state state;
88622d80 RJ	125	enum dma_status status;
2dc6c6f1	126
88622d80 RJ	127	status = dmaengine_tx_status(pd->dma_chan, pd->dma_cookie, &state);
88622d80 RJ	128	if (status != DMA_COMPLETE)
2dc6c6f1 MV	129	ret \|= ATA_DMA_ERR;
	130
	131	return ret;
	132	}
	133
	134	/*
	135	* No IRQ register present so we do nothing.
	136	*/
	137	static void pxa_irq_clear(struct ata_port *ap)
	138	{
	139	}
	140
	141	/*
	142	* Check for ATAPI DMA. ATAPI DMA is unsupported by this driver. It's still
	143	* unclear why ATAPI has DMA issues.
	144	*/
	145	static int pxa_check_atapi_dma(struct ata_queued_cmd *qc)
	146	{
	147	return -EOPNOTSUPP;
	148	}
	149
	150	static struct scsi_host_template pxa_ata_sht = {
	151	ATA_BMDMA_SHT(DRV_NAME),
	152	};
	153
	154	static struct ata_port_operations pxa_ata_port_ops = {
	155	.inherits = &ata_bmdma_port_ops,
	156	.cable_detect = ata_cable_40wire,
	157
	158	.bmdma_setup = pxa_bmdma_setup,
	159	.bmdma_start = pxa_bmdma_start,
	160	.bmdma_stop = pxa_bmdma_stop,
	161	.bmdma_status = pxa_bmdma_status,
	162
	163	.check_atapi_dma = pxa_check_atapi_dma,
	164
	165	.sff_irq_clear = pxa_irq_clear,
	166
	167	.qc_prep = pxa_qc_prep,
	168	};
	169
0ec24914	170	static int pxa_ata_probe(struct platform_device *pdev)
2dc6c6f1 MV	171	{
	172	struct ata_host *host;
	173	struct ata_port *ap;
	174	struct pata_pxa_data *data;
	175	struct resource *cmd_res;
	176	struct resource *ctl_res;
	177	struct resource *dma_res;
	178	struct resource *irq_res;
61b8c345	179	struct pata_pxa_pdata *pdata = dev_get_platdata(&pdev->dev);
88622d80	180	struct dma_slave_config config;
2dc6c6f1 MV	181	int ret = 0;
	182
	183	/*
	184	* Resource validation, three resources are needed:
	185	* - CMD port base address
	186	* - CTL port base address
	187	* - DMA port base address
	188	* - IRQ pin
	189	*/
	190	if (pdev->num_resources != 4) {
	191	dev_err(&pdev->dev, "invalid number of resources\n");
	192	return -EINVAL;
	193	}
	194
	195	/*
	196	* CMD port base address
	197	*/
	198	cmd_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	199	if (unlikely(cmd_res == NULL))
	200	return -EINVAL;
	201
	202	/*
	203	* CTL port base address
	204	*/
	205	ctl_res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
	206	if (unlikely(ctl_res == NULL))
	207	return -EINVAL;
	208
	209	/*
	210	* DMA port base address
	211	*/
	212	dma_res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
	213	if (unlikely(dma_res == NULL))
	214	return -EINVAL;
	215
	216	/*
	217	* IRQ pin
	218	*/
	219	irq_res = platform_get_resource(pdev, IORESOURCE_IRQ, 0);
	220	if (unlikely(irq_res == NULL))
	221	return -EINVAL;
	222
	223	/*
	224	* Allocate the host
	225	*/
	226	host = ata_host_alloc(&pdev->dev, 1);
	227	if (!host)
	228	return -ENOMEM;
	229
	230	ap = host->ports[0];
	231	ap->ops = &pxa_ata_port_ops;
	232	ap->pio_mask = ATA_PIO4;
	233	ap->mwdma_mask = ATA_MWDMA2;
2dc6c6f1 MV	234
	235	ap->ioaddr.cmd_addr = devm_ioremap(&pdev->dev, cmd_res->start,
	236	resource_size(cmd_res));
	237	ap->ioaddr.ctl_addr = devm_ioremap(&pdev->dev, ctl_res->start,
	238	resource_size(ctl_res));
	239	ap->ioaddr.bmdma_addr = devm_ioremap(&pdev->dev, dma_res->start,
	240	resource_size(dma_res));
	241
	242	/*
	243	* Adjust register offsets
	244	*/
	245	ap->ioaddr.altstatus_addr = ap->ioaddr.ctl_addr;
	246	ap->ioaddr.data_addr = ap->ioaddr.cmd_addr +
	247	(ATA_REG_DATA << pdata->reg_shift);
	248	ap->ioaddr.error_addr = ap->ioaddr.cmd_addr +
	249	(ATA_REG_ERR << pdata->reg_shift);
	250	ap->ioaddr.feature_addr = ap->ioaddr.cmd_addr +
	251	(ATA_REG_FEATURE << pdata->reg_shift);
	252	ap->ioaddr.nsect_addr = ap->ioaddr.cmd_addr +
	253	(ATA_REG_NSECT << pdata->reg_shift);
	254	ap->ioaddr.lbal_addr = ap->ioaddr.cmd_addr +
	255	(ATA_REG_LBAL << pdata->reg_shift);
	256	ap->ioaddr.lbam_addr = ap->ioaddr.cmd_addr +
	257	(ATA_REG_LBAM << pdata->reg_shift);
	258	ap->ioaddr.lbah_addr = ap->ioaddr.cmd_addr +
	259	(ATA_REG_LBAH << pdata->reg_shift);
	260	ap->ioaddr.device_addr = ap->ioaddr.cmd_addr +
	261	(ATA_REG_DEVICE << pdata->reg_shift);
	262	ap->ioaddr.status_addr = ap->ioaddr.cmd_addr +
	263	(ATA_REG_STATUS << pdata->reg_shift);
	264	ap->ioaddr.command_addr = ap->ioaddr.cmd_addr +
	265	(ATA_REG_CMD << pdata->reg_shift);
	266
	267	/*
	268	* Allocate and load driver's internal data structure
	269	*/
	270	data = devm_kzalloc(&pdev->dev, sizeof(struct pata_pxa_data),
	271	GFP_KERNEL);
	272	if (!data)
	273	return -ENOMEM;
	274
	275	ap->private_data = data;
2dc6c6f1	276
88622d80 RJ	277	memset(&config, 0, sizeof(config));
	278	config.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
	279	config.dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
	280	config.src_addr = dma_res->start;
	281	config.dst_addr = dma_res->start;
	282	config.src_maxburst = 32;
	283	config.dst_maxburst = 32;
2dc6c6f1 MV	284
	285	/*
	286	* Request the DMA channel
	287	*/
88622d80	288	data->dma_chan =
273340e8	289	dma_request_slave_channel(&pdev->dev, "data");
88622d80	290	if (!data->dma_chan)
2dc6c6f1	291	return -EBUSY;
88622d80 RJ	292	ret = dmaengine_slave_config(data->dma_chan, &config);
	293	if (ret < 0) {
	294	dev_err(&pdev->dev, "dma configuration failed: %d\n", ret);
	295	return ret;
	296	}
2dc6c6f1 MV	297
	298	/*
	299	* Activate the ATA host
	300	*/
	301	ret = ata_host_activate(host, irq_res->start, ata_sff_interrupt,
	302	pdata->irq_flags, &pxa_ata_sht);
	303	if (ret)
88622d80	304	dma_release_channel(data->dma_chan);
2dc6c6f1 MV	305
	306	return ret;
	307	}
	308
0ec24914	309	static int pxa_ata_remove(struct platform_device *pdev)
2dc6c6f1	310	{
d89995db	311	struct ata_host *host = platform_get_drvdata(pdev);
2dc6c6f1 MV	312	struct pata_pxa_data *data = host->ports[0]->private_data;
2dc6c6f1 MV	313
88622d80	314	dma_release_channel(data->dma_chan);
2dc6c6f1 MV	315
	316	ata_host_detach(host);
	317
	318	return 0;
	319	}
	320
	321	static struct platform_driver pxa_ata_driver = {
	322	.probe = pxa_ata_probe,
0ec24914	323	.remove = pxa_ata_remove,
2dc6c6f1 MV	324	.driver = {
2dc6c6f1 MV	325	.name = DRV_NAME,
2dc6c6f1 MV	326	},
	327	};
	328
99c8ea3e	329	module_platform_driver(pxa_ata_driver);
2dc6c6f1 MV	330
	331	MODULE_AUTHOR("Marek Vasut <marek.vasut@gmail.com>");
	332	MODULE_DESCRIPTION("DMA-capable driver for PATA on PXA CPU");
	333	MODULE_LICENSE("GPL");
	334	MODULE_VERSION(DRV_VERSION);
	335	MODULE_ALIAS("platform:" DRV_NAME);