[linux-block.git] / drivers / ata / pata_pxa.c

// SPDX-License-Identifier: GPL-2.0-or-later
/*
 * Generic PXA PATA driver
 *
 * Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/blkdev.h>
#include <linux/ata.h>
#include <linux/libata.h>
#include <linux/platform_device.h>
#include <linux/dmaengine.h>
#include <linux/slab.h>
#include <linux/completion.h>

#include <scsi/scsi_host.h>

#include <linux/platform_data/ata-pxa.h>

#define DRV_NAME	"pata_pxa"
#define DRV_VERSION	"0.1"

struct pata_pxa_data {
	struct dma_chan		*dma_chan;
	dma_cookie_t		dma_cookie;
	struct completion	dma_done;
};

/*
 * DMA interrupt handler.
 */
static void pxa_ata_dma_irq(void *d)
{
	struct pata_pxa_data *pd = d;
	enum dma_status status;

	status = dmaengine_tx_status(pd->dma_chan, pd->dma_cookie, NULL);
	if (status == DMA_ERROR || status == DMA_COMPLETE)
		complete(&pd->dma_done);
}

/*
 * Prepare taskfile for submission.
 */
static enum ata_completion_errors pxa_qc_prep(struct ata_queued_cmd *qc)
{
	struct pata_pxa_data *pd = qc->ap->private_data;
	struct dma_async_tx_descriptor *tx;
	enum dma_transfer_direction dir;

	if (!(qc->flags & ATA_QCFLAG_DMAMAP))
		return AC_ERR_OK;

	dir = (qc->dma_dir == DMA_TO_DEVICE ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM);
	tx = dmaengine_prep_slave_sg(pd->dma_chan, qc->sg, qc->n_elem, dir,
				     DMA_PREP_INTERRUPT);
	if (!tx) {
		ata_dev_err(qc->dev, "prep_slave_sg() failed\n");
		return AC_ERR_OK;
	}
	tx->callback = pxa_ata_dma_irq;
	tx->callback_param = pd;
	pd->dma_cookie = dmaengine_submit(tx);

	return AC_ERR_OK;
}

/*
 * Configure the DMA controller, load the DMA descriptors, but don't start the
 * DMA controller yet. Only issue the ATA command.
 */
static void pxa_bmdma_setup(struct ata_queued_cmd *qc)
{
	qc->ap->ops->sff_exec_command(qc->ap, &qc->tf);
}

/*
 * Execute the DMA transfer.
 */
static void pxa_bmdma_start(struct ata_queued_cmd *qc)
{
	struct pata_pxa_data *pd = qc->ap->private_data;
	init_completion(&pd->dma_done);
	dma_async_issue_pending(pd->dma_chan);
}

/*
 * Wait until the DMA transfer completes, then stop the DMA controller.
 */
static void pxa_bmdma_stop(struct ata_queued_cmd *qc)
{
	struct pata_pxa_data *pd = qc->ap->private_data;
	enum dma_status status;

	status = dmaengine_tx_status(pd->dma_chan, pd->dma_cookie, NULL);
	if (status != DMA_ERROR && status != DMA_COMPLETE &&
	    wait_for_completion_timeout(&pd->dma_done, HZ))
		ata_dev_err(qc->dev, "Timeout waiting for DMA completion!");

	dmaengine_terminate_all(pd->dma_chan);
}

/*
 * Read DMA status. The bmdma_stop() will take care of properly finishing the
 * DMA transfer so we always have DMA-complete interrupt here.
 */
static unsigned char pxa_bmdma_status(struct ata_port *ap)
{
	struct pata_pxa_data *pd = ap->private_data;
	unsigned char ret = ATA_DMA_INTR;
	struct dma_tx_state state;
	enum dma_status status;

	status = dmaengine_tx_status(pd->dma_chan, pd->dma_cookie, &state);
	if (status != DMA_COMPLETE)
		ret |= ATA_DMA_ERR;

	return ret;
}

/*
 * No IRQ register present so we do nothing.
 */
static void pxa_irq_clear(struct ata_port *ap)
{
}

/*
 * Check for ATAPI DMA. ATAPI DMA is unsupported by this driver. It's still
 * unclear why ATAPI has DMA issues.
 */
static int pxa_check_atapi_dma(struct ata_queued_cmd *qc)
{
	return -EOPNOTSUPP;
}

static struct scsi_host_template pxa_ata_sht = {
	ATA_BMDMA_SHT(DRV_NAME),
};

static struct ata_port_operations pxa_ata_port_ops = {
	.inherits		= &ata_bmdma_port_ops,
	.cable_detect		= ata_cable_40wire,

	.bmdma_setup		= pxa_bmdma_setup,
	.bmdma_start		= pxa_bmdma_start,
	.bmdma_stop		= pxa_bmdma_stop,
	.bmdma_status		= pxa_bmdma_status,

	.check_atapi_dma	= pxa_check_atapi_dma,

	.sff_irq_clear		= pxa_irq_clear,

	.qc_prep		= pxa_qc_prep,
};

static int pxa_ata_probe(struct platform_device *pdev)
{
	struct ata_host *host;
	struct ata_port *ap;
	struct pata_pxa_data *data;
	struct resource *cmd_res;
	struct resource *ctl_res;
	struct resource *dma_res;
	struct pata_pxa_pdata *pdata = dev_get_platdata(&pdev->dev);
	struct dma_slave_config	config;
	int ret = 0;
	int irq;

	/*
	 * Resource validation, three resources are needed:
	 *  - CMD port base address
	 *  - CTL port base address
	 *  - DMA port base address
	 *  - IRQ pin
	 */
	if (pdev->num_resources != 4) {
		dev_err(&pdev->dev, "invalid number of resources\n");
		return -EINVAL;
	}

	/*
	 * CMD port base address
	 */
	cmd_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	if (unlikely(cmd_res == NULL))
		return -EINVAL;

	/*
	 * CTL port base address
	 */
	ctl_res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
	if (unlikely(ctl_res == NULL))
		return -EINVAL;

	/*
	 * DMA port base address
	 */
	dma_res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
	if (unlikely(dma_res == NULL))
		return -EINVAL;

	/*
	 * IRQ pin
	 */
	irq = platform_get_irq(pdev, 0);
	if (irq < 0)
		return irq;

	/*
	 * Allocate the host
	 */
	host = ata_host_alloc(&pdev->dev, 1);
	if (!host)
		return -ENOMEM;

	ap		= host->ports[0];
	ap->ops		= &pxa_ata_port_ops;
	ap->pio_mask	= ATA_PIO4;
	ap->mwdma_mask	= ATA_MWDMA2;

	ap->ioaddr.cmd_addr	= devm_ioremap(&pdev->dev, cmd_res->start,
						resource_size(cmd_res));
	ap->ioaddr.ctl_addr	= devm_ioremap(&pdev->dev, ctl_res->start,
						resource_size(ctl_res));
	ap->ioaddr.bmdma_addr	= devm_ioremap(&pdev->dev, dma_res->start,
						resource_size(dma_res));

	/*
	 * Adjust register offsets
	 */
	ap->ioaddr.altstatus_addr = ap->ioaddr.ctl_addr;
	ap->ioaddr.data_addr	= ap->ioaddr.cmd_addr +
					(ATA_REG_DATA << pdata->reg_shift);
	ap->ioaddr.error_addr	= ap->ioaddr.cmd_addr +
					(ATA_REG_ERR << pdata->reg_shift);
	ap->ioaddr.feature_addr	= ap->ioaddr.cmd_addr +
					(ATA_REG_FEATURE << pdata->reg_shift);
	ap->ioaddr.nsect_addr	= ap->ioaddr.cmd_addr +
					(ATA_REG_NSECT << pdata->reg_shift);
	ap->ioaddr.lbal_addr	= ap->ioaddr.cmd_addr +
					(ATA_REG_LBAL << pdata->reg_shift);
	ap->ioaddr.lbam_addr	= ap->ioaddr.cmd_addr +
					(ATA_REG_LBAM << pdata->reg_shift);
	ap->ioaddr.lbah_addr	= ap->ioaddr.cmd_addr +
					(ATA_REG_LBAH << pdata->reg_shift);
	ap->ioaddr.device_addr	= ap->ioaddr.cmd_addr +
					(ATA_REG_DEVICE << pdata->reg_shift);
	ap->ioaddr.status_addr	= ap->ioaddr.cmd_addr +
					(ATA_REG_STATUS << pdata->reg_shift);
	ap->ioaddr.command_addr	= ap->ioaddr.cmd_addr +
					(ATA_REG_CMD << pdata->reg_shift);

	/*
	 * Allocate and load driver's internal data structure
	 */
	data = devm_kzalloc(&pdev->dev, sizeof(struct pata_pxa_data),
								GFP_KERNEL);
	if (!data)
		return -ENOMEM;

	ap->private_data = data;

	memset(&config, 0, sizeof(config));
	config.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
	config.dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
	config.src_addr = dma_res->start;
	config.dst_addr = dma_res->start;
	config.src_maxburst = 32;
	config.dst_maxburst = 32;

	/*
	 * Request the DMA channel
	 */
	data->dma_chan =
		dma_request_slave_channel(&pdev->dev, "data");
	if (!data->dma_chan)
		return -EBUSY;
	ret = dmaengine_slave_config(data->dma_chan, &config);
	if (ret < 0) {
		dev_err(&pdev->dev, "dma configuration failed: %d\n", ret);
		return ret;
	}

	/*
	 * Activate the ATA host
	 */
	ret = ata_host_activate(host, irq, ata_sff_interrupt,
				pdata->irq_flags, &pxa_ata_sht);
	if (ret)
		dma_release_channel(data->dma_chan);

	return ret;
}

static int pxa_ata_remove(struct platform_device *pdev)
{
	struct ata_host *host = platform_get_drvdata(pdev);
	struct pata_pxa_data *data = host->ports[0]->private_data;

	dma_release_channel(data->dma_chan);

	ata_host_detach(host);

	return 0;
}

static struct platform_driver pxa_ata_driver = {
	.probe		= pxa_ata_probe,
	.remove		= pxa_ata_remove,
	.driver		= {
		.name		= DRV_NAME,
	},
};

module_platform_driver(pxa_ata_driver);

MODULE_AUTHOR("Marek Vasut <marek.vasut@gmail.com>");
MODULE_DESCRIPTION("DMA-capable driver for PATA on PXA CPU");
MODULE_LICENSE("GPL");
MODULE_VERSION(DRV_VERSION);
MODULE_ALIAS("platform:" DRV_NAME);
Commit	Line	Data
c82ee6d3	1	// SPDX-License-Identifier: GPL-2.0-or-later
2dc6c6f1 MV	2	/*
	3	* Generic PXA PATA driver
	4	*
	5	* Copyright (C) 2010 Marek Vasut <marek.vasut@gmail.com>
2dc6c6f1 MV	6	*/
	7
	8	#include <linux/kernel.h>
	9	#include <linux/module.h>
2dc6c6f1 MV	10	#include <linux/blkdev.h>
	11	#include <linux/ata.h>
	12	#include <linux/libata.h>
	13	#include <linux/platform_device.h>
88622d80	14	#include <linux/dmaengine.h>
2dc6c6f1 MV	15	#include <linux/slab.h>
	16	#include <linux/completion.h>
	17
	18	#include <scsi/scsi_host.h>
	19
293b2da1	20	#include <linux/platform_data/ata-pxa.h>
2dc6c6f1 MV	21
	22	#define DRV_NAME "pata_pxa"
	23	#define DRV_VERSION "0.1"
	24
	25	struct pata_pxa_data {
88622d80 RJ	26	struct dma_chan *dma_chan;
88622d80 RJ	27	dma_cookie_t dma_cookie;
2dc6c6f1 MV	28	struct completion dma_done;
	29	};
	30
	31	/*
88622d80	32	* DMA interrupt handler.
2dc6c6f1	33	*/
88622d80	34	static void pxa_ata_dma_irq(void *d)
2dc6c6f1	35	{
88622d80 RJ	36	struct pata_pxa_data *pd = d;
88622d80 RJ	37	enum dma_status status;
2dc6c6f1	38
88622d80 RJ	39	status = dmaengine_tx_status(pd->dma_chan, pd->dma_cookie, NULL);
	40	if (status == DMA_ERROR \|\| status == DMA_COMPLETE)
	41	complete(&pd->dma_done);
2dc6c6f1 MV	42	}
	43
	44	/*
	45	* Prepare taskfile for submission.
	46	*/
95364f36	47	static enum ata_completion_errors pxa_qc_prep(struct ata_queued_cmd *qc)
2dc6c6f1 MV	48	{
2dc6c6f1 MV	49	struct pata_pxa_data *pd = qc->ap->private_data;
88622d80 RJ	50	struct dma_async_tx_descriptor *tx;
88622d80 RJ	51	enum dma_transfer_direction dir;
2dc6c6f1 MV	52
2dc6c6f1 MV	53	if (!(qc->flags & ATA_QCFLAG_DMAMAP))
95364f36	54	return AC_ERR_OK;
2dc6c6f1	55
88622d80 RJ	56	dir = (qc->dma_dir == DMA_TO_DEVICE ? DMA_MEM_TO_DEV : DMA_DEV_TO_MEM);
	57	tx = dmaengine_prep_slave_sg(pd->dma_chan, qc->sg, qc->n_elem, dir,
	58	DMA_PREP_INTERRUPT);
	59	if (!tx) {
	60	ata_dev_err(qc->dev, "prep_slave_sg() failed\n");
95364f36	61	return AC_ERR_OK;
88622d80 RJ	62	}
	63	tx->callback = pxa_ata_dma_irq;
	64	tx->callback_param = pd;
	65	pd->dma_cookie = dmaengine_submit(tx);
95364f36 JS	66
95364f36 JS	67	return AC_ERR_OK;
2dc6c6f1 MV	68	}
	69
	70	/*
	71	* Configure the DMA controller, load the DMA descriptors, but don't start the
	72	* DMA controller yet. Only issue the ATA command.
	73	*/
	74	static void pxa_bmdma_setup(struct ata_queued_cmd *qc)
	75	{
	76	qc->ap->ops->sff_exec_command(qc->ap, &qc->tf);
	77	}
	78
	79	/*
	80	* Execute the DMA transfer.
	81	*/
	82	static void pxa_bmdma_start(struct ata_queued_cmd *qc)
	83	{
	84	struct pata_pxa_data *pd = qc->ap->private_data;
	85	init_completion(&pd->dma_done);
88622d80	86	dma_async_issue_pending(pd->dma_chan);
2dc6c6f1 MV	87	}
	88
	89	/*
	90	* Wait until the DMA transfer completes, then stop the DMA controller.
	91	*/
	92	static void pxa_bmdma_stop(struct ata_queued_cmd *qc)
	93	{
	94	struct pata_pxa_data *pd = qc->ap->private_data;
88622d80	95	enum dma_status status;
2dc6c6f1	96
88622d80 RJ	97	status = dmaengine_tx_status(pd->dma_chan, pd->dma_cookie, NULL);
	98	if (status != DMA_ERROR && status != DMA_COMPLETE &&
	99	wait_for_completion_timeout(&pd->dma_done, HZ))
	100	ata_dev_err(qc->dev, "Timeout waiting for DMA completion!");
2dc6c6f1	101
88622d80	102	dmaengine_terminate_all(pd->dma_chan);
2dc6c6f1 MV	103	}
	104
	105	/*
	106	* Read DMA status. The bmdma_stop() will take care of properly finishing the
	107	* DMA transfer so we always have DMA-complete interrupt here.
	108	*/
	109	static unsigned char pxa_bmdma_status(struct ata_port *ap)
	110	{
	111	struct pata_pxa_data *pd = ap->private_data;
	112	unsigned char ret = ATA_DMA_INTR;
88622d80 RJ	113	struct dma_tx_state state;
88622d80 RJ	114	enum dma_status status;
2dc6c6f1	115
88622d80 RJ	116	status = dmaengine_tx_status(pd->dma_chan, pd->dma_cookie, &state);
88622d80 RJ	117	if (status != DMA_COMPLETE)
2dc6c6f1 MV	118	ret \|= ATA_DMA_ERR;
	119
	120	return ret;
	121	}
	122
	123	/*
	124	* No IRQ register present so we do nothing.
	125	*/
	126	static void pxa_irq_clear(struct ata_port *ap)
	127	{
	128	}
	129
	130	/*
	131	* Check for ATAPI DMA. ATAPI DMA is unsupported by this driver. It's still
	132	* unclear why ATAPI has DMA issues.
	133	*/
	134	static int pxa_check_atapi_dma(struct ata_queued_cmd *qc)
	135	{
	136	return -EOPNOTSUPP;
	137	}
	138
	139	static struct scsi_host_template pxa_ata_sht = {
	140	ATA_BMDMA_SHT(DRV_NAME),
	141	};
	142
	143	static struct ata_port_operations pxa_ata_port_ops = {
	144	.inherits = &ata_bmdma_port_ops,
	145	.cable_detect = ata_cable_40wire,
	146
	147	.bmdma_setup = pxa_bmdma_setup,
	148	.bmdma_start = pxa_bmdma_start,
	149	.bmdma_stop = pxa_bmdma_stop,
	150	.bmdma_status = pxa_bmdma_status,
	151
	152	.check_atapi_dma = pxa_check_atapi_dma,
	153
	154	.sff_irq_clear = pxa_irq_clear,
	155
	156	.qc_prep = pxa_qc_prep,
	157	};
	158
0ec24914	159	static int pxa_ata_probe(struct platform_device *pdev)
2dc6c6f1 MV	160	{
	161	struct ata_host *host;
	162	struct ata_port *ap;
	163	struct pata_pxa_data *data;
	164	struct resource *cmd_res;
	165	struct resource *ctl_res;
	166	struct resource *dma_res;
61b8c345	167	struct pata_pxa_pdata *pdata = dev_get_platdata(&pdev->dev);
88622d80	168	struct dma_slave_config config;
2dc6c6f1	169	int ret = 0;
d268afa1	170	int irq;
2dc6c6f1 MV	171
	172	/*
	173	* Resource validation, three resources are needed:
	174	* - CMD port base address
	175	* - CTL port base address
	176	* - DMA port base address
	177	* - IRQ pin
	178	*/
	179	if (pdev->num_resources != 4) {
	180	dev_err(&pdev->dev, "invalid number of resources\n");
	181	return -EINVAL;
	182	}
	183
	184	/*
	185	* CMD port base address
	186	*/
	187	cmd_res = platform_get_resource(pdev, IORESOURCE_MEM, 0);
	188	if (unlikely(cmd_res == NULL))
	189	return -EINVAL;
	190
	191	/*
	192	* CTL port base address
	193	*/
	194	ctl_res = platform_get_resource(pdev, IORESOURCE_MEM, 1);
	195	if (unlikely(ctl_res == NULL))
	196	return -EINVAL;
	197
	198	/*
	199	* DMA port base address
	200	*/
	201	dma_res = platform_get_resource(pdev, IORESOURCE_DMA, 0);
	202	if (unlikely(dma_res == NULL))
	203	return -EINVAL;
	204
	205	/*
	206	* IRQ pin
	207	*/
d268afa1 MC	208	irq = platform_get_irq(pdev, 0);
	209	if (irq < 0)
	210	return irq;
2dc6c6f1 MV	211
	212	/*
	213	* Allocate the host
	214	*/
	215	host = ata_host_alloc(&pdev->dev, 1);
	216	if (!host)
	217	return -ENOMEM;
	218
	219	ap = host->ports[0];
	220	ap->ops = &pxa_ata_port_ops;
	221	ap->pio_mask = ATA_PIO4;
	222	ap->mwdma_mask = ATA_MWDMA2;
2dc6c6f1 MV	223
	224	ap->ioaddr.cmd_addr = devm_ioremap(&pdev->dev, cmd_res->start,
	225	resource_size(cmd_res));
	226	ap->ioaddr.ctl_addr = devm_ioremap(&pdev->dev, ctl_res->start,
	227	resource_size(ctl_res));
	228	ap->ioaddr.bmdma_addr = devm_ioremap(&pdev->dev, dma_res->start,
	229	resource_size(dma_res));
	230
	231	/*
	232	* Adjust register offsets
	233	*/
	234	ap->ioaddr.altstatus_addr = ap->ioaddr.ctl_addr;
	235	ap->ioaddr.data_addr = ap->ioaddr.cmd_addr +
	236	(ATA_REG_DATA << pdata->reg_shift);
	237	ap->ioaddr.error_addr = ap->ioaddr.cmd_addr +
	238	(ATA_REG_ERR << pdata->reg_shift);
	239	ap->ioaddr.feature_addr = ap->ioaddr.cmd_addr +
	240	(ATA_REG_FEATURE << pdata->reg_shift);
	241	ap->ioaddr.nsect_addr = ap->ioaddr.cmd_addr +
	242	(ATA_REG_NSECT << pdata->reg_shift);
	243	ap->ioaddr.lbal_addr = ap->ioaddr.cmd_addr +
	244	(ATA_REG_LBAL << pdata->reg_shift);
	245	ap->ioaddr.lbam_addr = ap->ioaddr.cmd_addr +
	246	(ATA_REG_LBAM << pdata->reg_shift);
	247	ap->ioaddr.lbah_addr = ap->ioaddr.cmd_addr +
	248	(ATA_REG_LBAH << pdata->reg_shift);
	249	ap->ioaddr.device_addr = ap->ioaddr.cmd_addr +
	250	(ATA_REG_DEVICE << pdata->reg_shift);
	251	ap->ioaddr.status_addr = ap->ioaddr.cmd_addr +
	252	(ATA_REG_STATUS << pdata->reg_shift);
	253	ap->ioaddr.command_addr = ap->ioaddr.cmd_addr +
	254	(ATA_REG_CMD << pdata->reg_shift);
	255
	256	/*
	257	* Allocate and load driver's internal data structure
	258	*/
	259	data = devm_kzalloc(&pdev->dev, sizeof(struct pata_pxa_data),
	260	GFP_KERNEL);
	261	if (!data)
	262	return -ENOMEM;
	263
	264	ap->private_data = data;
2dc6c6f1	265
88622d80 RJ	266	memset(&config, 0, sizeof(config));
	267	config.src_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
	268	config.dst_addr_width = DMA_SLAVE_BUSWIDTH_2_BYTES;
	269	config.src_addr = dma_res->start;
	270	config.dst_addr = dma_res->start;
	271	config.src_maxburst = 32;
	272	config.dst_maxburst = 32;
2dc6c6f1 MV	273
	274	/*
	275	* Request the DMA channel
	276	*/
88622d80	277	data->dma_chan =
273340e8	278	dma_request_slave_channel(&pdev->dev, "data");
88622d80	279	if (!data->dma_chan)
2dc6c6f1	280	return -EBUSY;
88622d80 RJ	281	ret = dmaengine_slave_config(data->dma_chan, &config);
	282	if (ret < 0) {
	283	dev_err(&pdev->dev, "dma configuration failed: %d\n", ret);
	284	return ret;
	285	}
2dc6c6f1 MV	286
	287	/*
	288	* Activate the ATA host
	289	*/
d268afa1	290	ret = ata_host_activate(host, irq, ata_sff_interrupt,
2dc6c6f1 MV	291	pdata->irq_flags, &pxa_ata_sht);
2dc6c6f1 MV	292	if (ret)
88622d80	293	dma_release_channel(data->dma_chan);
2dc6c6f1 MV	294
	295	return ret;
	296	}
	297
0ec24914	298	static int pxa_ata_remove(struct platform_device *pdev)
2dc6c6f1	299	{
d89995db	300	struct ata_host *host = platform_get_drvdata(pdev);
2dc6c6f1 MV	301	struct pata_pxa_data *data = host->ports[0]->private_data;
2dc6c6f1 MV	302
88622d80	303	dma_release_channel(data->dma_chan);
2dc6c6f1 MV	304
	305	ata_host_detach(host);
	306
	307	return 0;
	308	}
	309
	310	static struct platform_driver pxa_ata_driver = {
	311	.probe = pxa_ata_probe,
0ec24914	312	.remove = pxa_ata_remove,
2dc6c6f1 MV	313	.driver = {
2dc6c6f1 MV	314	.name = DRV_NAME,
2dc6c6f1 MV	315	},
	316	};
	317
99c8ea3e	318	module_platform_driver(pxa_ata_driver);
2dc6c6f1 MV	319
	320	MODULE_AUTHOR("Marek Vasut <marek.vasut@gmail.com>");
	321	MODULE_DESCRIPTION("DMA-capable driver for PATA on PXA CPU");
	322	MODULE_LICENSE("GPL");
	323	MODULE_VERSION(DRV_VERSION);
	324	MODULE_ALIAS("platform:" DRV_NAME);