[linux-block.git] / drivers / ata / pata_pdc202xx_old.c

// SPDX-License-Identifier: GPL-2.0-only
/*
 * pata_pdc202xx_old.c 	- Promise PDC202xx PATA for new ATA layer
 *			  (C) 2005 Red Hat Inc
 *			  Alan Cox <alan@lxorguk.ukuu.org.uk>
 *			  (C) 2007,2009,2010 Bartlomiej Zolnierkiewicz
 *
 * Based in part on linux/drivers/ide/pci/pdc202xx_old.c
 *
 * First cut with LBA48/ATAPI
 *
 * TODO:
 *	Channel interlock/reset on both required ?
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/blkdev.h>
#include <linux/delay.h>
#include <scsi/scsi_host.h>
#include <linux/libata.h>

#define DRV_NAME "pata_pdc202xx_old"
#define DRV_VERSION "0.4.3"

static int pdc2026x_cable_detect(struct ata_port *ap)
{
	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	u16 cis;

	pci_read_config_word(pdev, 0x50, &cis);
	if (cis & (1 << (10 + ap->port_no)))
		return ATA_CBL_PATA40;
	return ATA_CBL_PATA80;
}

static void pdc202xx_exec_command(struct ata_port *ap,
				  const struct ata_taskfile *tf)
{
	iowrite8(tf->command, ap->ioaddr.command_addr);
	ndelay(400);
}

static bool pdc202xx_irq_check(struct ata_port *ap)
{
	struct pci_dev *pdev	= to_pci_dev(ap->host->dev);
	unsigned long master	= pci_resource_start(pdev, 4);
	u8 sc1d			= inb(master + 0x1d);

	if (ap->port_no) {
		/*
		 * bit 7: error, bit 6: interrupting,
		 * bit 5: FIFO full, bit 4: FIFO empty
		 */
		return sc1d & 0x40;
	} else	{
		/*
		 * bit 3: error, bit 2: interrupting,
		 * bit 1: FIFO full, bit 0: FIFO empty
		 */
		return sc1d & 0x04;
	}
}

/**
 *	pdc202xx_configure_piomode	-	set chip PIO timing
 *	@ap: ATA interface
 *	@adev: ATA device
 *	@pio: PIO mode
 *
 *	Called to do the PIO mode setup. Our timing registers are shared
 *	so a configure_dmamode call will undo any work we do here and vice
 *	versa
 */

static void pdc202xx_configure_piomode(struct ata_port *ap, struct ata_device *adev, int pio)
{
	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	int port = 0x60 + 8 * ap->port_no + 4 * adev->devno;
	static const u16 pio_timing[5] = {
		0x0913, 0x050C , 0x0308, 0x0206, 0x0104
	};
	u8 r_ap, r_bp;

	pci_read_config_byte(pdev, port, &r_ap);
	pci_read_config_byte(pdev, port + 1, &r_bp);
	r_ap &= ~0x3F;	/* Preserve ERRDY_EN, SYNC_IN */
	r_bp &= ~0x1F;
	r_ap |= (pio_timing[pio] >> 8);
	r_bp |= (pio_timing[pio] & 0xFF);

	if (ata_pio_need_iordy(adev))
		r_ap |= 0x20;	/* IORDY enable */
	if (adev->class == ATA_DEV_ATA)
		r_ap |= 0x10;	/* FIFO enable */
	pci_write_config_byte(pdev, port, r_ap);
	pci_write_config_byte(pdev, port + 1, r_bp);
}

/**
 *	pdc202xx_set_piomode	-	set initial PIO mode data
 *	@ap: ATA interface
 *	@adev: ATA device
 *
 *	Called to do the PIO mode setup. Our timing registers are shared
 *	but we want to set the PIO timing by default.
 */

static void pdc202xx_set_piomode(struct ata_port *ap, struct ata_device *adev)
{
	pdc202xx_configure_piomode(ap, adev, adev->pio_mode - XFER_PIO_0);
}

/**
 *	pdc202xx_set_dmamode	-	set DMA mode in chip
 *	@ap: ATA interface
 *	@adev: ATA device
 *
 *	Load DMA cycle times into the chip ready for a DMA transfer
 *	to occur.
 */

static void pdc202xx_set_dmamode(struct ata_port *ap, struct ata_device *adev)
{
	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	int port = 0x60 + 8 * ap->port_no + 4 * adev->devno;
	static u8 udma_timing[6][2] = {
		{ 0x60, 0x03 },	/* 33 Mhz Clock */
		{ 0x40, 0x02 },
		{ 0x20, 0x01 },
		{ 0x40, 0x02 },	/* 66 Mhz Clock */
		{ 0x20, 0x01 },
		{ 0x20, 0x01 }
	};
	static u8 mdma_timing[3][2] = {
		{ 0xe0, 0x0f },
		{ 0x60, 0x04 },
		{ 0x60, 0x03 },
	};
	u8 r_bp, r_cp;

	pci_read_config_byte(pdev, port + 1, &r_bp);
	pci_read_config_byte(pdev, port + 2, &r_cp);

	r_bp &= ~0xE0;
	r_cp &= ~0x0F;

	if (adev->dma_mode >= XFER_UDMA_0) {
		int speed = adev->dma_mode - XFER_UDMA_0;
		r_bp |= udma_timing[speed][0];
		r_cp |= udma_timing[speed][1];

	} else {
		int speed = adev->dma_mode - XFER_MW_DMA_0;
		r_bp |= mdma_timing[speed][0];
		r_cp |= mdma_timing[speed][1];
	}
	pci_write_config_byte(pdev, port + 1, r_bp);
	pci_write_config_byte(pdev, port + 2, r_cp);

}

/**
 *	pdc2026x_bmdma_start		-	DMA engine begin
 *	@qc: ATA command
 *
 *	In UDMA3 or higher we have to clock switch for the duration of the
 *	DMA transfer sequence.
 *
 *	Note: The host lock held by the libata layer protects
 *	us from two channels both trying to set DMA bits at once
 */

static void pdc2026x_bmdma_start(struct ata_queued_cmd *qc)
{
	struct ata_port *ap = qc->ap;
	struct ata_device *adev = qc->dev;
	struct ata_taskfile *tf = &qc->tf;
	int sel66 = ap->port_no ? 0x08: 0x02;

	void __iomem *master = ap->host->ports[0]->ioaddr.bmdma_addr;
	void __iomem *clock = master + 0x11;
	void __iomem *atapi_reg = master + 0x20 + (4 * ap->port_no);

	u32 len;

	/* Check we keep host level locking here */
	if (adev->dma_mode > XFER_UDMA_2)
		iowrite8(ioread8(clock) | sel66, clock);
	else
		iowrite8(ioread8(clock) & ~sel66, clock);

	/* The DMA clocks may have been trashed by a reset. FIXME: make conditional
	   and move to qc_issue ? */
	pdc202xx_set_dmamode(ap, qc->dev);

	/* Cases the state machine will not complete correctly without help */
	if ((tf->flags & ATA_TFLAG_LBA48) ||  tf->protocol == ATAPI_PROT_DMA) {
		len = qc->nbytes / 2;

		if (tf->flags & ATA_TFLAG_WRITE)
			len |= 0x06000000;
		else
			len |= 0x05000000;

		iowrite32(len, atapi_reg);
	}

	/* Activate DMA */
	ata_bmdma_start(qc);
}

/**
 *	pdc2026x_bmdma_stop		-	DMA engine stop
 *	@qc: ATA command
 *
 *	After a DMA completes we need to put the clock back to 33MHz for
 *	PIO timings.
 *
 *	Note: The host lock held by the libata layer protects
 *	us from two channels both trying to set DMA bits at once
 */

static void pdc2026x_bmdma_stop(struct ata_queued_cmd *qc)
{
	struct ata_port *ap = qc->ap;
	struct ata_device *adev = qc->dev;
	struct ata_taskfile *tf = &qc->tf;

	int sel66 = ap->port_no ? 0x08: 0x02;
	/* The clock bits are in the same register for both channels */
	void __iomem *master = ap->host->ports[0]->ioaddr.bmdma_addr;
	void __iomem *clock = master + 0x11;
	void __iomem *atapi_reg = master + 0x20 + (4 * ap->port_no);

	/* Cases the state machine will not complete correctly */
	if (tf->protocol == ATAPI_PROT_DMA || (tf->flags & ATA_TFLAG_LBA48)) {
		iowrite32(0, atapi_reg);
		iowrite8(ioread8(clock) & ~sel66, clock);
	}
	/* Flip back to 33Mhz for PIO */
	if (adev->dma_mode > XFER_UDMA_2)
		iowrite8(ioread8(clock) & ~sel66, clock);
	ata_bmdma_stop(qc);
	pdc202xx_set_piomode(ap, adev);
}

/**
 *	pdc2026x_dev_config	-	device setup hook
 *	@adev: newly found device
 *
 *	Perform chip specific early setup. We need to lock the transfer
 *	sizes to 8bit to avoid making the state engine on the 2026x cards
 *	barf.
 */

static void pdc2026x_dev_config(struct ata_device *adev)
{
	adev->max_sectors = 256;
}

static int pdc2026x_port_start(struct ata_port *ap)
{
	void __iomem *bmdma = ap->ioaddr.bmdma_addr;
	if (bmdma) {
		/* Enable burst mode */
		u8 burst = ioread8(bmdma + 0x1f);
		iowrite8(burst | 0x01, bmdma + 0x1f);
	}
	return ata_bmdma_port_start(ap);
}

/**
 *	pdc2026x_check_atapi_dma - Check whether ATAPI DMA can be supported for this command
 *	@qc: Metadata associated with taskfile to check
 *
 *	Just say no - not supported on older Promise.
 *
 *	LOCKING:
 *	None (inherited from caller).
 *
 *	RETURNS: 0 when ATAPI DMA can be used
 *		 1 otherwise
 */

static int pdc2026x_check_atapi_dma(struct ata_queued_cmd *qc)
{
	return 1;
}

static const struct scsi_host_template pdc202xx_sht = {
	ATA_BMDMA_SHT(DRV_NAME),
};

static struct ata_port_operations pdc2024x_port_ops = {
	.inherits		= &ata_bmdma_port_ops,

	.cable_detect		= ata_cable_40wire,
	.set_piomode		= pdc202xx_set_piomode,
	.set_dmamode		= pdc202xx_set_dmamode,

	.sff_exec_command	= pdc202xx_exec_command,
	.sff_irq_check		= pdc202xx_irq_check,
};

static struct ata_port_operations pdc2026x_port_ops = {
	.inherits		= &pdc2024x_port_ops,

	.check_atapi_dma	= pdc2026x_check_atapi_dma,
	.bmdma_start		= pdc2026x_bmdma_start,
	.bmdma_stop		= pdc2026x_bmdma_stop,

	.cable_detect		= pdc2026x_cable_detect,
	.dev_config		= pdc2026x_dev_config,

	.port_start		= pdc2026x_port_start,

	.sff_exec_command	= pdc202xx_exec_command,
	.sff_irq_check		= pdc202xx_irq_check,
};

static int pdc202xx_init_one(struct pci_dev *dev, const struct pci_device_id *id)
{
	static const struct ata_port_info info[3] = {
		{
			.flags = ATA_FLAG_SLAVE_POSS,
			.pio_mask = ATA_PIO4,
			.mwdma_mask = ATA_MWDMA2,
			.udma_mask = ATA_UDMA2,
			.port_ops = &pdc2024x_port_ops
		},
		{
			.flags = ATA_FLAG_SLAVE_POSS,
			.pio_mask = ATA_PIO4,
			.mwdma_mask = ATA_MWDMA2,
			.udma_mask = ATA_UDMA4,
			.port_ops = &pdc2026x_port_ops
		},
		{
			.flags = ATA_FLAG_SLAVE_POSS,
			.pio_mask = ATA_PIO4,
			.mwdma_mask = ATA_MWDMA2,
			.udma_mask = ATA_UDMA5,
			.port_ops = &pdc2026x_port_ops
		}

	};
	const struct ata_port_info *ppi[] = { &info[id->driver_data], NULL };

	if (dev->device == PCI_DEVICE_ID_PROMISE_20265) {
		struct pci_dev *bridge = dev->bus->self;
		/* Don't grab anything behind a Promise I2O RAID */
		if (bridge && bridge->vendor == PCI_VENDOR_ID_INTEL) {
			if (bridge->device == PCI_DEVICE_ID_INTEL_I960)
				return -ENODEV;
			if (bridge->device == PCI_DEVICE_ID_INTEL_I960RM)
				return -ENODEV;
		}
	}
	return ata_pci_bmdma_init_one(dev, ppi, &pdc202xx_sht, NULL, 0);
}

static const struct pci_device_id pdc202xx[] = {
	{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20246), 0 },
	{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20262), 1 },
	{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20263), 1 },
	{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20265), 2 },
	{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20267), 2 },

	{ },
};

static struct pci_driver pdc202xx_pci_driver = {
	.name 		= DRV_NAME,
	.id_table	= pdc202xx,
	.probe 		= pdc202xx_init_one,
	.remove		= ata_pci_remove_one,
#ifdef CONFIG_PM_SLEEP
	.suspend	= ata_pci_device_suspend,
	.resume		= ata_pci_device_resume,
#endif
};

module_pci_driver(pdc202xx_pci_driver);

MODULE_AUTHOR("Alan Cox");
MODULE_DESCRIPTION("low-level driver for Promise 2024x and 20262-20267");
MODULE_LICENSE("GPL");
MODULE_DEVICE_TABLE(pci, pdc202xx);
MODULE_VERSION(DRV_VERSION);
Commit	Line	Data
09c434b8	1	// SPDX-License-Identifier: GPL-2.0-only
669a5db4 JG	2	/*
	3	* pata_pdc202xx_old.c - Promise PDC202xx PATA for new ATA layer
	4	* (C) 2005 Red Hat Inc
ab771630	5	* Alan Cox <alan@lxorguk.ukuu.org.uk>
a75032e8	6	* (C) 2007,2009,2010 Bartlomiej Zolnierkiewicz
669a5db4 JG	7	*
	8	* Based in part on linux/drivers/ide/pci/pdc202xx_old.c
	9	*
	10	* First cut with LBA48/ATAPI
	11	*
	12	* TODO:
06b74dd2	13	* Channel interlock/reset on both required ?
669a5db4	14	*/
85cd7251	15
669a5db4 JG	16	#include <linux/kernel.h>
	17	#include <linux/module.h>
	18	#include <linux/pci.h>
669a5db4 JG	19	#include <linux/blkdev.h>
	20	#include <linux/delay.h>
	21	#include <scsi/scsi_host.h>
	22	#include <linux/libata.h>
	23
	24	#define DRV_NAME "pata_pdc202xx_old"
06b74dd2	25	#define DRV_VERSION "0.4.3"
669a5db4	26
a0fcdc02	27	static int pdc2026x_cable_detect(struct ata_port *ap)
669a5db4 JG	28	{
	29	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	30	u16 cis;
85cd7251	31
669a5db4 JG	32	pci_read_config_word(pdev, 0x50, &cis);
669a5db4 JG	33	if (cis & (1 << (10 + ap->port_no)))
a0ac38f1 AC	34	return ATA_CBL_PATA40;
a0ac38f1 AC	35	return ATA_CBL_PATA80;
669a5db4 JG	36	}
669a5db4 JG	37
750e519d	38	static void pdc202xx_exec_command(struct ata_port *ap,
a75032e8 BZ	39	const struct ata_taskfile *tf)
a75032e8 BZ	40	{
a75032e8 BZ	41	iowrite8(tf->command, ap->ioaddr.command_addr);
	42	ndelay(400);
	43	}
	44
606254e3 SS	45	static bool pdc202xx_irq_check(struct ata_port *ap)
	46	{
	47	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	48	unsigned long master = pci_resource_start(pdev, 4);
	49	u8 sc1d = inb(master + 0x1d);
	50
	51	if (ap->port_no) {
	52	/*
	53	* bit 7: error, bit 6: interrupting,
	54	* bit 5: FIFO full, bit 4: FIFO empty
	55	*/
	56	return sc1d & 0x40;
	57	} else {
	58	/*
	59	* bit 3: error, bit 2: interrupting,
	60	* bit 1: FIFO full, bit 0: FIFO empty
	61	*/
	62	return sc1d & 0x04;
	63	}
	64	}
	65
669a5db4	66	/**
ada406c8	67	* pdc202xx_configure_piomode - set chip PIO timing
669a5db4 JG	68	* @ap: ATA interface
	69	* @adev: ATA device
	70	* @pio: PIO mode
	71	*
	72	* Called to do the PIO mode setup. Our timing registers are shared
	73	* so a configure_dmamode call will undo any work we do here and vice
	74	* versa
	75	*/
85cd7251	76
ada406c8	77	static void pdc202xx_configure_piomode(struct ata_port ap, struct ata_device adev, int pio)
669a5db4 JG	78	{
669a5db4 JG	79	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
63ed7101	80	int port = 0x60 + 8 * ap->port_no + 4 * adev->devno;
217ca30f	81	static const u16 pio_timing[5] = {
669a5db4 JG	82	0x0913, 0x050C , 0x0308, 0x0206, 0x0104
	83	};
	84	u8 r_ap, r_bp;
	85
	86	pci_read_config_byte(pdev, port, &r_ap);
	87	pci_read_config_byte(pdev, port + 1, &r_bp);
	88	r_ap &= ~0x3F; /* Preserve ERRDY_EN, SYNC_IN */
63ed7101	89	r_bp &= ~0x1F;
669a5db4 JG	90	r_ap \|= (pio_timing[pio] >> 8);
669a5db4 JG	91	r_bp \|= (pio_timing[pio] & 0xFF);
85cd7251	92
669a5db4 JG	93	if (ata_pio_need_iordy(adev))
	94	r_ap \|= 0x20; /* IORDY enable */
	95	if (adev->class == ATA_DEV_ATA)
	96	r_ap \|= 0x10; /* FIFO enable */
	97	pci_write_config_byte(pdev, port, r_ap);
	98	pci_write_config_byte(pdev, port + 1, r_bp);
	99	}
	100
	101	/**
ada406c8	102	* pdc202xx_set_piomode - set initial PIO mode data
669a5db4 JG	103	* @ap: ATA interface
	104	* @adev: ATA device
	105	*
	106	* Called to do the PIO mode setup. Our timing registers are shared
	107	* but we want to set the PIO timing by default.
	108	*/
85cd7251	109
ada406c8	110	static void pdc202xx_set_piomode(struct ata_port ap, struct ata_device adev)
669a5db4	111	{
ada406c8	112	pdc202xx_configure_piomode(ap, adev, adev->pio_mode - XFER_PIO_0);
669a5db4 JG	113	}
	114
	115	/**
ffa137cb	116	* pdc202xx_set_dmamode - set DMA mode in chip
669a5db4 JG	117	* @ap: ATA interface
	118	* @adev: ATA device
	119	*
	120	* Load DMA cycle times into the chip ready for a DMA transfer
	121	* to occur.
	122	*/
85cd7251	123
ada406c8	124	static void pdc202xx_set_dmamode(struct ata_port ap, struct ata_device adev)
669a5db4 JG	125	{
669a5db4 JG	126	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
63ed7101	127	int port = 0x60 + 8 * ap->port_no + 4 * adev->devno;
669a5db4 JG	128	static u8 udma_timing[6][2] = {
	129	{ 0x60, 0x03 }, /* 33 Mhz Clock */
	130	{ 0x40, 0x02 },
	131	{ 0x20, 0x01 },
	132	{ 0x40, 0x02 }, /* 66 Mhz Clock */
	133	{ 0x20, 0x01 },
85cd7251	134	{ 0x20, 0x01 }
669a5db4	135	};
63ed7101	136	static u8 mdma_timing[3][2] = {
63ed7101	137	{ 0xe0, 0x0f },
06b74dd2 AC	138	{ 0x60, 0x04 },
06b74dd2 AC	139	{ 0x60, 0x03 },
63ed7101	140	};
669a5db4	141	u8 r_bp, r_cp;
85cd7251	142
669a5db4 JG	143	pci_read_config_byte(pdev, port + 1, &r_bp);
669a5db4 JG	144	pci_read_config_byte(pdev, port + 2, &r_cp);
85cd7251	145
63ed7101	146	r_bp &= ~0xE0;
669a5db4	147	r_cp &= ~0x0F;
85cd7251	148
669a5db4 JG	149	if (adev->dma_mode >= XFER_UDMA_0) {
	150	int speed = adev->dma_mode - XFER_UDMA_0;
	151	r_bp \|= udma_timing[speed][0];
	152	r_cp \|= udma_timing[speed][1];
85cd7251	153
669a5db4 JG	154	} else {
669a5db4 JG	155	int speed = adev->dma_mode - XFER_MW_DMA_0;
63ed7101 BZ	156	r_bp \|= mdma_timing[speed][0];
63ed7101 BZ	157	r_cp \|= mdma_timing[speed][1];
669a5db4 JG	158	}
	159	pci_write_config_byte(pdev, port + 1, r_bp);
	160	pci_write_config_byte(pdev, port + 2, r_cp);
85cd7251	161
669a5db4 JG	162	}
	163
	164	/**
	165	* pdc2026x_bmdma_start - DMA engine begin
	166	* @qc: ATA command
	167	*
	168	* In UDMA3 or higher we have to clock switch for the duration of the
	169	* DMA transfer sequence.
06b74dd2 AC	170	*
	171	* Note: The host lock held by the libata layer protects
	172	* us from two channels both trying to set DMA bits at once
669a5db4	173	*/
85cd7251	174
669a5db4 JG	175	static void pdc2026x_bmdma_start(struct ata_queued_cmd *qc)
	176	{
	177	struct ata_port *ap = qc->ap;
	178	struct ata_device *adev = qc->dev;
	179	struct ata_taskfile *tf = &qc->tf;
	180	int sel66 = ap->port_no ? 0x08: 0x02;
	181
0d5ff566 TH	182	void __iomem *master = ap->host->ports[0]->ioaddr.bmdma_addr;
	183	void __iomem *clock = master + 0x11;
	184	void __iomem atapi_reg = master + 0x20 + (4 ap->port_no);
85cd7251	185
669a5db4	186	u32 len;
85cd7251	187
669a5db4	188	/* Check we keep host level locking here */
6ad58b24	189	if (adev->dma_mode > XFER_UDMA_2)
0d5ff566	190	iowrite8(ioread8(clock) \| sel66, clock);
669a5db4	191	else
0d5ff566	192	iowrite8(ioread8(clock) & ~sel66, clock);
669a5db4	193
85cd7251	194	/* The DMA clocks may have been trashed by a reset. FIXME: make conditional
669a5db4	195	and move to qc_issue ? */
ada406c8	196	pdc202xx_set_dmamode(ap, qc->dev);
669a5db4 JG	197
669a5db4 JG	198	/* Cases the state machine will not complete correctly without help */
0dc36888	199	if ((tf->flags & ATA_TFLAG_LBA48) \|\| tf->protocol == ATAPI_PROT_DMA) {
5e518810	200	len = qc->nbytes / 2;
85cd7251	201
669a5db4 JG	202	if (tf->flags & ATA_TFLAG_WRITE)
	203	len \|= 0x06000000;
	204	else
	205	len \|= 0x05000000;
85cd7251	206
0d5ff566	207	iowrite32(len, atapi_reg);
669a5db4	208	}
85cd7251 JG	209
85cd7251 JG	210	/* Activate DMA */
669a5db4 JG	211	ata_bmdma_start(qc);
	212	}
	213
	214	/**
ffa137cb	215	* pdc2026x_bmdma_stop - DMA engine stop
669a5db4 JG	216	* @qc: ATA command
	217	*
	218	* After a DMA completes we need to put the clock back to 33MHz for
	219	* PIO timings.
06b74dd2 AC	220	*
	221	* Note: The host lock held by the libata layer protects
	222	* us from two channels both trying to set DMA bits at once
669a5db4	223	*/
85cd7251	224
669a5db4 JG	225	static void pdc2026x_bmdma_stop(struct ata_queued_cmd *qc)
	226	{
	227	struct ata_port *ap = qc->ap;
	228	struct ata_device *adev = qc->dev;
	229	struct ata_taskfile *tf = &qc->tf;
85cd7251	230
669a5db4 JG	231	int sel66 = ap->port_no ? 0x08: 0x02;
669a5db4 JG	232	/* The clock bits are in the same register for both channels */
0d5ff566 TH	233	void __iomem *master = ap->host->ports[0]->ioaddr.bmdma_addr;
	234	void __iomem *clock = master + 0x11;
	235	void __iomem atapi_reg = master + 0x20 + (4 ap->port_no);
85cd7251	236
669a5db4	237	/* Cases the state machine will not complete correctly */
0dc36888	238	if (tf->protocol == ATAPI_PROT_DMA \|\| (tf->flags & ATA_TFLAG_LBA48)) {
0d5ff566 TH	239	iowrite32(0, atapi_reg);
0d5ff566 TH	240	iowrite8(ioread8(clock) & ~sel66, clock);
669a5db4	241	}
669a5db4	242	/* Flip back to 33Mhz for PIO */
6ad58b24	243	if (adev->dma_mode > XFER_UDMA_2)
0d5ff566	244	iowrite8(ioread8(clock) & ~sel66, clock);
669a5db4	245	ata_bmdma_stop(qc);
36906d9b	246	pdc202xx_set_piomode(ap, adev);
669a5db4 JG	247	}
	248
	249	/**
	250	* pdc2026x_dev_config - device setup hook
669a5db4 JG	251	* @adev: newly found device
	252	*
	253	* Perform chip specific early setup. We need to lock the transfer
	254	* sizes to 8bit to avoid making the state engine on the 2026x cards
	255	* barf.
	256	*/
85cd7251	257
cd0d3bbc	258	static void pdc2026x_dev_config(struct ata_device *adev)
669a5db4 JG	259	{
	260	adev->max_sectors = 256;
	261	}
	262
36906d9b AC	263	static int pdc2026x_port_start(struct ata_port *ap)
	264	{
	265	void __iomem *bmdma = ap->ioaddr.bmdma_addr;
	266	if (bmdma) {
	267	/* Enable burst mode */
	268	u8 burst = ioread8(bmdma + 0x1f);
	269	iowrite8(burst \| 0x01, bmdma + 0x1f);
	270	}
c7087652	271	return ata_bmdma_port_start(ap);
36906d9b AC	272	}
36906d9b AC	273
aa8f2371 AC	274	/**
	275	* pdc2026x_check_atapi_dma - Check whether ATAPI DMA can be supported for this command
	276	* @qc: Metadata associated with taskfile to check
	277	*
	278	* Just say no - not supported on older Promise.
	279	*
	280	* LOCKING:
	281	* None (inherited from caller).
	282	*
	283	* RETURNS: 0 when ATAPI DMA can be used
	284	* 1 otherwise
	285	*/
	286
	287	static int pdc2026x_check_atapi_dma(struct ata_queued_cmd *qc)
	288	{
	289	return 1;
	290	}
	291
25df73d9	292	static const struct scsi_host_template pdc202xx_sht = {
68d1d07b	293	ATA_BMDMA_SHT(DRV_NAME),
669a5db4 JG	294	};
	295
	296	static struct ata_port_operations pdc2024x_port_ops = {
029cfd6b TH	297	.inherits = &ata_bmdma_port_ops,
	298
	299	.cable_detect = ata_cable_40wire,
	300	.set_piomode = pdc202xx_set_piomode,
	301	.set_dmamode = pdc202xx_set_dmamode,
a75032e8	302
750e519d	303	.sff_exec_command = pdc202xx_exec_command,
606254e3	304	.sff_irq_check = pdc202xx_irq_check,
85cd7251	305	};
669a5db4 JG	306
669a5db4 JG	307	static struct ata_port_operations pdc2026x_port_ops = {
029cfd6b TH	308	.inherits = &pdc2024x_port_ops,
	309
	310	.check_atapi_dma = pdc2026x_check_atapi_dma,
	311	.bmdma_start = pdc2026x_bmdma_start,
	312	.bmdma_stop = pdc2026x_bmdma_stop,
	313
	314	.cable_detect = pdc2026x_cable_detect,
	315	.dev_config = pdc2026x_dev_config,
	316
	317	.port_start = pdc2026x_port_start,
750e519d BZ	318
750e519d BZ	319	.sff_exec_command = pdc202xx_exec_command,
606254e3	320	.sff_irq_check = pdc202xx_irq_check,
85cd7251	321	};
669a5db4	322
ada406c8	323	static int pdc202xx_init_one(struct pci_dev dev, const struct pci_device_id id)
669a5db4	324	{
1626aeb8	325	static const struct ata_port_info info[3] = {
669a5db4	326	{
1d2808fd	327	.flags = ATA_FLAG_SLAVE_POSS,
14bdef98 EIB	328	.pio_mask = ATA_PIO4,
14bdef98 EIB	329	.mwdma_mask = ATA_MWDMA2,
669a5db4 JG	330	.udma_mask = ATA_UDMA2,
669a5db4 JG	331	.port_ops = &pdc2024x_port_ops
85cd7251	332	},
669a5db4	333	{
1d2808fd	334	.flags = ATA_FLAG_SLAVE_POSS,
14bdef98 EIB	335	.pio_mask = ATA_PIO4,
14bdef98 EIB	336	.mwdma_mask = ATA_MWDMA2,
669a5db4 JG	337	.udma_mask = ATA_UDMA4,
	338	.port_ops = &pdc2026x_port_ops
	339	},
	340	{
1d2808fd	341	.flags = ATA_FLAG_SLAVE_POSS,
14bdef98 EIB	342	.pio_mask = ATA_PIO4,
14bdef98 EIB	343	.mwdma_mask = ATA_MWDMA2,
669a5db4 JG	344	.udma_mask = ATA_UDMA5,
	345	.port_ops = &pdc2026x_port_ops
	346	}
85cd7251	347
669a5db4	348	};
1626aeb8	349	const struct ata_port_info *ppi[] = { &info[id->driver_data], NULL };
85cd7251	350
669a5db4 JG	351	if (dev->device == PCI_DEVICE_ID_PROMISE_20265) {
	352	struct pci_dev *bridge = dev->bus->self;
	353	/* Don't grab anything behind a Promise I2O RAID */
	354	if (bridge && bridge->vendor == PCI_VENDOR_ID_INTEL) {
b447916e	355	if (bridge->device == PCI_DEVICE_ID_INTEL_I960)
669a5db4	356	return -ENODEV;
b447916e	357	if (bridge->device == PCI_DEVICE_ID_INTEL_I960RM)
669a5db4 JG	358	return -ENODEV;
	359	}
	360	}
1c5afdf7	361	return ata_pci_bmdma_init_one(dev, ppi, &pdc202xx_sht, NULL, 0);
669a5db4 JG	362	}
669a5db4 JG	363
ada406c8	364	static const struct pci_device_id pdc202xx[] = {
2d2744fc JG	365	{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20246), 0 },
	366	{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20262), 1 },
	367	{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20263), 1 },
	368	{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20265), 2 },
	369	{ PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20267), 2 },
	370
	371	{ },
669a5db4 JG	372	};
669a5db4 JG	373
ada406c8	374	static struct pci_driver pdc202xx_pci_driver = {
2d2744fc	375	.name = DRV_NAME,
ada406c8 AC	376	.id_table = pdc202xx,
ada406c8 AC	377	.probe = pdc202xx_init_one,
62d64ae0	378	.remove = ata_pci_remove_one,
58eb8cd5	379	#ifdef CONFIG_PM_SLEEP
62d64ae0 A	380	.suspend = ata_pci_device_suspend,
62d64ae0 A	381	.resume = ata_pci_device_resume,
438ac6d5	382	#endif
669a5db4 JG	383	};
669a5db4 JG	384
2fc75da0	385	module_pci_driver(pdc202xx_pci_driver);
669a5db4	386
669a5db4 JG	387	MODULE_AUTHOR("Alan Cox");
	388	MODULE_DESCRIPTION("low-level driver for Promise 2024x and 20262-20267");
	389	MODULE_LICENSE("GPL");
ada406c8	390	MODULE_DEVICE_TABLE(pci, pdc202xx);
669a5db4	391	MODULE_VERSION(DRV_VERSION);