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libata: normalize port_info, port_operations and sht tables
[linux-2.6-block.git] / drivers / ata / pata_pdc2027x.c
CommitLineData
669a5db4
JG		 1/*
2 * Promise PATA TX2/TX4/TX2000/133 IDE driver for pdc20268 to pdc20277.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version
7 * 2 of the License, or (at your option) any later version.
8 *
9 * Ported to libata by:
10 * Albert Lee <albertcc@tw.ibm.com> IBM Corporation
11 *
12 * Copyright (C) 1998-2002 Andre Hedrick <andre@linux-ide.org>
13 * Portions Copyright (C) 1999 Promise Technology, Inc.
14 *
15 * Author: Frank Tiernan (frankt@promise.com)
16 * Released under terms of General Public License
17 *
18 *
19 * libata documentation is available via 'make {ps|pdf}docs',
20 * as Documentation/DocBook/libata.*
21 *
22 * Hardware information only available under NDA.
23 *
24 */
25#include <linux/kernel.h>
26#include <linux/module.h>
27#include <linux/pci.h>
28#include <linux/init.h>
29#include <linux/blkdev.h>
30#include <linux/delay.h>
31#include <linux/device.h>
32#include <scsi/scsi.h>
33#include <scsi/scsi_host.h>
34#include <scsi/scsi_cmnd.h>
35#include <linux/libata.h>
669a5db4
JG		 36
37#define DRV_NAME "pata_pdc2027x"
2a3103ce 38#define DRV_VERSION "1.0"
669a5db4
JG		 39#undef PDC_DEBUG
40
41#ifdef PDC_DEBUG
7f5e4e8d 42#define PDPRINTK(fmt, args...) printk(KERN_ERR "%s: " fmt, __func__, ## args)
669a5db4
JG		 43#else
44#define PDPRINTK(fmt, args...)
45#endif
46
47enum {
0d5ff566
TH		 48 PDC_MMIO_BAR = 5,
49
669a5db4
JG		 50 PDC_UDMA_100 = 0,
51 PDC_UDMA_133 = 1,
52
53 PDC_100_MHZ = 100000000,
54 PDC_133_MHZ = 133333333,
55
56 PDC_SYS_CTL = 0x1100,
57 PDC_ATA_CTL = 0x1104,
58 PDC_GLOBAL_CTL = 0x1108,
59 PDC_CTCR0 = 0x110C,
60 PDC_CTCR1 = 0x1110,
61 PDC_BYTE_COUNT = 0x1120,
62 PDC_PLL_CTL = 0x1202,
63};
64
65static int pdc2027x_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
669a5db4
JG		 66static void pdc2027x_error_handler(struct ata_port *ap);
67static void pdc2027x_set_piomode(struct ata_port *ap, struct ata_device *adev);
68static void pdc2027x_set_dmamode(struct ata_port *ap, struct ata_device *adev);
669a5db4 69static int pdc2027x_check_atapi_dma(struct ata_queued_cmd *qc);
9bedb799
AC		 70static unsigned long pdc2027x_mode_filter(struct ata_device *adev, unsigned long mask);
71static int pdc2027x_cable_detect(struct ata_port *ap);
0260731f 72static int pdc2027x_set_mode(struct ata_link *link, struct ata_device **r_failed);
669a5db4
JG		 73
74/*
75 * ATA Timing Tables based on 133MHz controller clock.
76 * These tables are only used when the controller is in 133MHz clock.
77 * If the controller is in 100MHz clock, the ASIC hardware will
78 * set the timing registers automatically when "set feature" command
79 * is issued to the device. However, if the controller clock is 133MHz,
80 * the following tables must be used.
81 */
82static struct pdc2027x_pio_timing {
83 u8 value0, value1, value2;
84} pdc2027x_pio_timing_tbl [] = {
85 { 0xfb, 0x2b, 0xac }, /* PIO mode 0 */
86 { 0x46, 0x29, 0xa4 }, /* PIO mode 1 */
87 { 0x23, 0x26, 0x64 }, /* PIO mode 2 */
88 { 0x27, 0x0d, 0x35 }, /* PIO mode 3, IORDY on, Prefetch off */
89 { 0x23, 0x09, 0x25 }, /* PIO mode 4, IORDY on, Prefetch off */
90};
91
92static struct pdc2027x_mdma_timing {
93 u8 value0, value1;
94} pdc2027x_mdma_timing_tbl [] = {
95 { 0xdf, 0x5f }, /* MDMA mode 0 */
96 { 0x6b, 0x27 }, /* MDMA mode 1 */
97 { 0x69, 0x25 }, /* MDMA mode 2 */
98};
99
100static struct pdc2027x_udma_timing {
101 u8 value0, value1, value2;
102} pdc2027x_udma_timing_tbl [] = {
103 { 0x4a, 0x0f, 0xd5 }, /* UDMA mode 0 */
104 { 0x3a, 0x0a, 0xd0 }, /* UDMA mode 1 */
105 { 0x2a, 0x07, 0xcd }, /* UDMA mode 2 */
106 { 0x1a, 0x05, 0xcd }, /* UDMA mode 3 */
107 { 0x1a, 0x03, 0xcd }, /* UDMA mode 4 */
108 { 0x1a, 0x02, 0xcb }, /* UDMA mode 5 */
109 { 0x1a, 0x01, 0xcb }, /* UDMA mode 6 */
110};
111
112static const struct pci_device_id pdc2027x_pci_tbl[] = {
2d2744fc
JG		 113 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20268), PDC_UDMA_100 },
114 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20269), PDC_UDMA_133 },
115 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20270), PDC_UDMA_100 },
116 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20271), PDC_UDMA_133 },
117 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20275), PDC_UDMA_133 },
118 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20276), PDC_UDMA_133 },
119 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20277), PDC_UDMA_133 },
120
669a5db4
JG		 121 { } /* terminate list */
122};
123
124static struct pci_driver pdc2027x_pci_driver = {
125 .name = DRV_NAME,
126 .id_table = pdc2027x_pci_tbl,
127 .probe = pdc2027x_init_one,
24dc5f33 128 .remove = ata_pci_remove_one,
669a5db4
JG		 129};
130
131static struct scsi_host_template pdc2027x_sht = {
132 .module = THIS_MODULE,
133 .name = DRV_NAME,
134 .ioctl = ata_scsi_ioctl,
135 .queuecommand = ata_scsi_queuecmd,
136 .can_queue = ATA_DEF_QUEUE,
137 .this_id = ATA_SHT_THIS_ID,
138 .sg_tablesize = LIBATA_MAX_PRD,
669a5db4
JG		 139 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
140 .emulated = ATA_SHT_EMULATED,
141 .use_clustering = ATA_SHT_USE_CLUSTERING,
142 .proc_name = DRV_NAME,
143 .dma_boundary = ATA_DMA_BOUNDARY,
144 .slave_configure = ata_scsi_slave_config,
afdfe899 145 .slave_destroy = ata_scsi_slave_destroy,
669a5db4
JG		 146 .bios_param = ata_std_bios_param,
147};
148
149static struct ata_port_operations pdc2027x_pata100_ops = {
9bedb799 150 .mode_filter = ata_pci_default_filter,
669a5db4
JG		 151
152 .tf_load = ata_tf_load,
153 .tf_read = ata_tf_read,
154 .check_status = ata_check_status,
155 .exec_command = ata_exec_command,
156 .dev_select = ata_std_dev_select,
157
158 .check_atapi_dma = pdc2027x_check_atapi_dma,
159 .bmdma_setup = ata_bmdma_setup,
160 .bmdma_start = ata_bmdma_start,
161 .bmdma_stop = ata_bmdma_stop,
162 .bmdma_status = ata_bmdma_status,
163 .qc_prep = ata_qc_prep,
164 .qc_issue = ata_qc_issue_prot,
0d5ff566 165 .data_xfer = ata_data_xfer,
669a5db4
JG		 166
167 .freeze = ata_bmdma_freeze,
168 .thaw = ata_bmdma_thaw,
169 .error_handler = pdc2027x_error_handler,
170 .post_internal_cmd = ata_bmdma_post_internal_cmd,
9bedb799 171 .cable_detect = pdc2027x_cable_detect,
669a5db4 172
669a5db4 173 .irq_clear = ata_bmdma_irq_clear,
246ce3b6 174 .irq_on = ata_irq_on,
669a5db4 175
81ad1837 176 .port_start = ata_sff_port_start,
669a5db4
JG		 177};
178
179static struct ata_port_operations pdc2027x_pata133_ops = {
669a5db4
JG		 180 .set_piomode = pdc2027x_set_piomode,
181 .set_dmamode = pdc2027x_set_dmamode,
9bedb799
AC		 182 .set_mode = pdc2027x_set_mode,
183 .mode_filter = pdc2027x_mode_filter,
669a5db4
JG		 184
185 .tf_load = ata_tf_load,
186 .tf_read = ata_tf_read,
187 .check_status = ata_check_status,
188 .exec_command = ata_exec_command,
189 .dev_select = ata_std_dev_select,
190
191 .check_atapi_dma = pdc2027x_check_atapi_dma,
192 .bmdma_setup = ata_bmdma_setup,
193 .bmdma_start = ata_bmdma_start,
194 .bmdma_stop = ata_bmdma_stop,
195 .bmdma_status = ata_bmdma_status,
196 .qc_prep = ata_qc_prep,
197 .qc_issue = ata_qc_issue_prot,
0d5ff566 198 .data_xfer = ata_data_xfer,
669a5db4
JG		 199
200 .freeze = ata_bmdma_freeze,
201 .thaw = ata_bmdma_thaw,
202 .error_handler = pdc2027x_error_handler,
203 .post_internal_cmd = ata_bmdma_post_internal_cmd,
9bedb799 204 .cable_detect = pdc2027x_cable_detect,
669a5db4 205
669a5db4 206 .irq_clear = ata_bmdma_irq_clear,
246ce3b6 207 .irq_on = ata_irq_on,
669a5db4 208
81ad1837 209 .port_start = ata_sff_port_start,
669a5db4
JG		 210};
211
212static struct ata_port_info pdc2027x_port_info[] = {
213 /* PDC_UDMA_100 */
214 {
669a5db4
JG		 215 .flags = ATA_FLAG_NO_LEGACY | ATA_FLAG_SLAVE_POSS |
216 ATA_FLAG_MMIO,
217 .pio_mask = 0x1f, /* pio0-4 */
218 .mwdma_mask = 0x07, /* mwdma0-2 */
219 .udma_mask = ATA_UDMA5, /* udma0-5 */
220 .port_ops = &pdc2027x_pata100_ops,
221 },
222 /* PDC_UDMA_133 */
223 {
669a5db4
JG		 224 .flags = ATA_FLAG_NO_LEGACY | ATA_FLAG_SLAVE_POSS |
225 ATA_FLAG_MMIO,
226 .pio_mask = 0x1f, /* pio0-4 */
227 .mwdma_mask = 0x07, /* mwdma0-2 */
228 .udma_mask = ATA_UDMA6, /* udma0-6 */
229 .port_ops = &pdc2027x_pata133_ops,
230 },
231};
232
233MODULE_AUTHOR("Andre Hedrick, Frank Tiernan, Albert Lee");
234MODULE_DESCRIPTION("libata driver module for Promise PDC20268 to PDC20277");
235MODULE_LICENSE("GPL");
236MODULE_VERSION(DRV_VERSION);
237MODULE_DEVICE_TABLE(pci, pdc2027x_pci_tbl);
238
239/**
240 * port_mmio - Get the MMIO address of PDC2027x extended registers
241 * @ap: Port
242 * @offset: offset from mmio base
243 */
7c250413 244static inline void __iomem *port_mmio(struct ata_port *ap, unsigned int offset)
669a5db4 245{
0d5ff566 246 return ap->host->iomap[PDC_MMIO_BAR] + ap->port_no * 0x100 + offset;
669a5db4
JG		 247}
248
249/**
250 * dev_mmio - Get the MMIO address of PDC2027x extended registers
251 * @ap: Port
252 * @adev: device
253 * @offset: offset from mmio base
254 */
7c250413 255static inline void __iomem *dev_mmio(struct ata_port *ap, struct ata_device *adev, unsigned int offset)
669a5db4
JG		 256{
257 u8 adj = (adev->devno) ? 0x08 : 0x00;
258 return port_mmio(ap, offset) + adj;
259}
260
261/**
9bedb799 262 * pdc2027x_pata_cable_detect - Probe host controller cable detect info
669a5db4
JG		 263 * @ap: Port for which cable detect info is desired
264 *
265 * Read 80c cable indicator from Promise extended register.
266 * This register is latched when the system is reset.
267 *
268 * LOCKING:
269 * None (inherited from caller).
270 */
9bedb799 271static int pdc2027x_cable_detect(struct ata_port *ap)
669a5db4
JG		 272{
273 u32 cgcr;
274
275 /* check cable detect results */
d2a84f47 276 cgcr = ioread32(port_mmio(ap, PDC_GLOBAL_CTL));
669a5db4
JG		 277 if (cgcr & (1 << 26))
278 goto cbl40;
279
280 PDPRINTK("No cable or 80-conductor cable on port %d\n", ap->port_no);
281
9bedb799 282 return ATA_CBL_PATA80;
669a5db4
JG		 283cbl40:
284 printk(KERN_INFO DRV_NAME ": 40-conductor cable detected on port %d\n", ap->port_no);
9bedb799 285 return ATA_CBL_PATA40;
669a5db4
JG		 286}
287
288/**
289 * pdc2027x_port_enabled - Check PDC ATA control register to see whether the port is enabled.
290 * @ap: Port to check
291 */
292static inline int pdc2027x_port_enabled(struct ata_port *ap)
293{
d2a84f47 294 return ioread8(port_mmio(ap, PDC_ATA_CTL)) & 0x02;
669a5db4
JG		 295}
296
297/**
298 * pdc2027x_prereset - prereset for PATA host controller
cc0680a5 299 * @link: Target link
d4b2bab4 300 * @deadline: deadline jiffies for the operation
669a5db4
JG		 301 *
302 * Probeinit including cable detection.
303 *
304 * LOCKING:
305 * None (inherited from caller).
306 */
307
cc0680a5 308static int pdc2027x_prereset(struct ata_link *link, unsigned long deadline)
669a5db4
JG		 309{
310 /* Check whether port enabled */
cc0680a5 311 if (!pdc2027x_port_enabled(link->ap))
c961922b 312 return -ENOENT;
cc0680a5 313 return ata_std_prereset(link, deadline);
669a5db4
JG		 314}
315
316/**
317 * pdc2027x_error_handler - Perform reset on PATA port and classify
318 * @ap: Port to reset
319 *
320 * Reset PATA phy and classify attached devices.
321 *
322 * LOCKING:
323 * None (inherited from caller).
324 */
325
326static void pdc2027x_error_handler(struct ata_port *ap)
327{
328 ata_bmdma_drive_eh(ap, pdc2027x_prereset, ata_std_softreset, NULL, ata_std_postreset);
329}
330
9bedb799
AC		 331/**
332 * pdc2720x_mode_filter - mode selection filter
333 * @adev: ATA device
334 * @mask: list of modes proposed
335 *
336 * Block UDMA on devices that cause trouble with this controller.
337 */
338
339static unsigned long pdc2027x_mode_filter(struct ata_device *adev, unsigned long mask)
340{
341 unsigned char model_num[ATA_ID_PROD_LEN + 1];
342 struct ata_device *pair = ata_dev_pair(adev);
343
344 if (adev->class != ATA_DEV_ATA || adev->devno == 0 || pair == NULL)
345 return ata_pci_default_filter(adev, mask);
346
347 /* Check for slave of a Maxtor at UDMA6 */
348 ata_id_c_string(pair->id, model_num, ATA_ID_PROD,
349 ATA_ID_PROD_LEN + 1);
350 /* If the master is a maxtor in UDMA6 then the slave should not use UDMA 6 */
4ca4e439 351 if (strstr(model_num, "Maxtor") == NULL && pair->dma_mode == XFER_UDMA_6)
9bedb799
AC		 352 mask &= ~ (1 << (6 + ATA_SHIFT_UDMA));
353
354 return ata_pci_default_filter(adev, mask);
355}
356
669a5db4
JG		 357/**
358 * pdc2027x_set_piomode - Initialize host controller PATA PIO timings
359 * @ap: Port to configure
360 * @adev: um
361 * @pio: PIO mode, 0 - 4
362 *
363 * Set PIO mode for device.
364 *
365 * LOCKING:
366 * None (inherited from caller).
367 */
368
369static void pdc2027x_set_piomode(struct ata_port *ap, struct ata_device *adev)
370{
371 unsigned int pio = adev->pio_mode - XFER_PIO_0;
372 u32 ctcr0, ctcr1;
373
374 PDPRINTK("adev->pio_mode[%X]\n", adev->pio_mode);
375
376 /* Sanity check */
377 if (pio > 4) {
378 printk(KERN_ERR DRV_NAME ": Unknown pio mode [%d] ignored\n", pio);
379 return;
380
381 }
382
383 /* Set the PIO timing registers using value table for 133MHz */
384 PDPRINTK("Set pio regs... \n");
385
d2a84f47 386 ctcr0 = ioread32(dev_mmio(ap, adev, PDC_CTCR0));
669a5db4
JG		 387 ctcr0 &= 0xffff0000;
388 ctcr0 |= pdc2027x_pio_timing_tbl[pio].value0 |
389 (pdc2027x_pio_timing_tbl[pio].value1 << 8);
d2a84f47 390 iowrite32(ctcr0, dev_mmio(ap, adev, PDC_CTCR0));
669a5db4 391
d2a84f47 392 ctcr1 = ioread32(dev_mmio(ap, adev, PDC_CTCR1));
669a5db4
JG		 393 ctcr1 &= 0x00ffffff;
394 ctcr1 |= (pdc2027x_pio_timing_tbl[pio].value2 << 24);
d2a84f47 395 iowrite32(ctcr1, dev_mmio(ap, adev, PDC_CTCR1));
669a5db4
JG		 396
397 PDPRINTK("Set pio regs done\n");
398
399 PDPRINTK("Set to pio mode[%u] \n", pio);
400}
401
402/**
403 * pdc2027x_set_dmamode - Initialize host controller PATA UDMA timings
404 * @ap: Port to configure
405 * @adev: um
406 * @udma: udma mode, XFER_UDMA_0 to XFER_UDMA_6
407 *
408 * Set UDMA mode for device.
409 *
410 * LOCKING:
411 * None (inherited from caller).
412 */
413static void pdc2027x_set_dmamode(struct ata_port *ap, struct ata_device *adev)
414{
415 unsigned int dma_mode = adev->dma_mode;
416 u32 ctcr0, ctcr1;
417
418 if ((dma_mode >= XFER_UDMA_0) &&
419 (dma_mode <= XFER_UDMA_6)) {
420 /* Set the UDMA timing registers with value table for 133MHz */
421 unsigned int udma_mode = dma_mode & 0x07;
422
423 if (dma_mode == XFER_UDMA_2) {
424 /*
425 * Turn off tHOLD.
426 * If tHOLD is '1', the hardware will add half clock for data hold time.
427 * This code segment seems to be no effect. tHOLD will be overwritten below.
428 */
d2a84f47
AC		 429 ctcr1 = ioread32(dev_mmio(ap, adev, PDC_CTCR1));
430 iowrite32(ctcr1 & ~(1 << 7), dev_mmio(ap, adev, PDC_CTCR1));
669a5db4
JG		 431 }
432
433 PDPRINTK("Set udma regs... \n");
434
d2a84f47 435 ctcr1 = ioread32(dev_mmio(ap, adev, PDC_CTCR1));
669a5db4
JG		 436 ctcr1 &= 0xff000000;
437 ctcr1 |= pdc2027x_udma_timing_tbl[udma_mode].value0 |
438 (pdc2027x_udma_timing_tbl[udma_mode].value1 << 8) |
439 (pdc2027x_udma_timing_tbl[udma_mode].value2 << 16);
d2a84f47 440 iowrite32(ctcr1, dev_mmio(ap, adev, PDC_CTCR1));
669a5db4
JG		 441
442 PDPRINTK("Set udma regs done\n");
443
444 PDPRINTK("Set to udma mode[%u] \n", udma_mode);
445
446 } else if ((dma_mode >= XFER_MW_DMA_0) &&
447 (dma_mode <= XFER_MW_DMA_2)) {
448 /* Set the MDMA timing registers with value table for 133MHz */
449 unsigned int mdma_mode = dma_mode & 0x07;
450
451 PDPRINTK("Set mdma regs... \n");
d2a84f47 452 ctcr0 = ioread32(dev_mmio(ap, adev, PDC_CTCR0));
669a5db4
JG		 453
454 ctcr0 &= 0x0000ffff;
455 ctcr0 |= (pdc2027x_mdma_timing_tbl[mdma_mode].value0 << 16) |
456 (pdc2027x_mdma_timing_tbl[mdma_mode].value1 << 24);
457
d2a84f47 458 iowrite32(ctcr0, dev_mmio(ap, adev, PDC_CTCR0));
669a5db4
JG		 459 PDPRINTK("Set mdma regs done\n");
460
461 PDPRINTK("Set to mdma mode[%u] \n", mdma_mode);
462 } else {
463 printk(KERN_ERR DRV_NAME ": Unknown dma mode [%u] ignored\n", dma_mode);
464 }
465}
466
467/**
9bedb799 468 * pdc2027x_set_mode - Set the timing registers back to correct values.
0260731f 469 * @link: link to configure
9bedb799 470 * @r_failed: Returned device for failure
669a5db4
JG		 471 *
472 * The pdc2027x hardware will look at "SET FEATURES" and change the timing registers
473 * automatically. The values set by the hardware might be incorrect, under 133Mhz PLL.
474 * This function overwrites the possibly incorrect values set by the hardware to be correct.
475 */
0260731f 476static int pdc2027x_set_mode(struct ata_link *link, struct ata_device **r_failed)
669a5db4 477{
0260731f 478 struct ata_port *ap = link->ap;
f58229f8
TH		 479 struct ata_device *dev;
480 int rc;
669a5db4 481
0260731f 482 rc = ata_do_set_mode(link, r_failed);
f58229f8
TH		 483 if (rc < 0)
484 return rc;
669a5db4 485
0260731f 486 ata_link_for_each_dev(dev, link) {
669a5db4
JG		 487 if (ata_dev_enabled(dev)) {
488
489 pdc2027x_set_piomode(ap, dev);
490
491 /*
492 * Enable prefetch if the device support PIO only.
493 */
494 if (dev->xfer_shift == ATA_SHIFT_PIO) {
d2a84f47 495 u32 ctcr1 = ioread32(dev_mmio(ap, dev, PDC_CTCR1));
669a5db4 496 ctcr1 |= (1 << 25);
d2a84f47 497 iowrite32(ctcr1, dev_mmio(ap, dev, PDC_CTCR1));
669a5db4
JG		 498
499 PDPRINTK("Turn on prefetch\n");
500 } else {
501 pdc2027x_set_dmamode(ap, dev);
502 }
503 }
504 }
9bedb799 505 return 0;
669a5db4
JG		 506}
507
508/**
509 * pdc2027x_check_atapi_dma - Check whether ATAPI DMA can be supported for this command
510 * @qc: Metadata associated with taskfile to check
511 *
512 * LOCKING:
513 * None (inherited from caller).
514 *
515 * RETURNS: 0 when ATAPI DMA can be used
516 * 1 otherwise
517 */
518static int pdc2027x_check_atapi_dma(struct ata_queued_cmd *qc)
519{
520 struct scsi_cmnd *cmd = qc->scsicmd;
521 u8 *scsicmd = cmd->cmnd;
522 int rc = 1; /* atapi dma off by default */
523
524 /*
525 * This workaround is from Promise's GPL driver.
526 * If ATAPI DMA is used for commands not in the
527 * following white list, say MODE_SENSE and REQUEST_SENSE,
528 * pdc2027x might hit the irq lost problem.
529 */
530 switch (scsicmd[0]) {
531 case READ_10:
532 case WRITE_10:
533 case READ_12:
534 case WRITE_12:
535 case READ_6:
536 case WRITE_6:
537 case 0xad: /* READ_DVD_STRUCTURE */
538 case 0xbe: /* READ_CD */
539 /* ATAPI DMA is ok */
540 rc = 0;
541 break;
542 default:
543 ;
544 }
545
546 return rc;
547}
548
549/**
550 * pdc_read_counter - Read the ctr counter
5d728824 551 * @host: target ATA host
669a5db4
JG		 552 */
553
5d728824 554static long pdc_read_counter(struct ata_host *host)
669a5db4 555{
5d728824 556 void __iomem *mmio_base = host->iomap[PDC_MMIO_BAR];
669a5db4
JG		 557 long counter;
558 int retry = 1;
559 u32 bccrl, bccrh, bccrlv, bccrhv;
560
561retry:
d2a84f47
AC		 562 bccrl = ioread32(mmio_base + PDC_BYTE_COUNT) & 0x7fff;
563 bccrh = ioread32(mmio_base + PDC_BYTE_COUNT + 0x100) & 0x7fff;
669a5db4
JG		 564
565 /* Read the counter values again for verification */
d2a84f47
AC		 566 bccrlv = ioread32(mmio_base + PDC_BYTE_COUNT) & 0x7fff;
567 bccrhv = ioread32(mmio_base + PDC_BYTE_COUNT + 0x100) & 0x7fff;
669a5db4
JG		 568
569 counter = (bccrh << 15) | bccrl;
570
571 PDPRINTK("bccrh [%X] bccrl [%X]\n", bccrh, bccrl);
572 PDPRINTK("bccrhv[%X] bccrlv[%X]\n", bccrhv, bccrlv);
573
574 /*
575 * The 30-bit decreasing counter are read by 2 pieces.
576 * Incorrect value may be read when both bccrh and bccrl are changing.
577 * Ex. When 7900 decrease to 78FF, wrong value 7800 might be read.
578 */
579 if (retry && !(bccrh == bccrhv && bccrl >= bccrlv)) {
580 retry--;
581 PDPRINTK("rereading counter\n");
582 goto retry;
583 }
584
585 return counter;
586}
587
588/**
589 * adjust_pll - Adjust the PLL input clock in Hz.
590 *
591 * @pdc_controller: controller specific information
5d728824 592 * @host: target ATA host
669a5db4
JG		 593 * @pll_clock: The input of PLL in HZ
594 */
5d728824 595static void pdc_adjust_pll(struct ata_host *host, long pll_clock, unsigned int board_idx)
669a5db4 596{
5d728824 597 void __iomem *mmio_base = host->iomap[PDC_MMIO_BAR];
669a5db4
JG		 598 u16 pll_ctl;
599 long pll_clock_khz = pll_clock / 1000;
600 long pout_required = board_idx? PDC_133_MHZ:PDC_100_MHZ;
601 long ratio = pout_required / pll_clock_khz;
602 int F, R;
603
604 /* Sanity check */
605 if (unlikely(pll_clock_khz < 5000L || pll_clock_khz > 70000L)) {
606 printk(KERN_ERR DRV_NAME ": Invalid PLL input clock %ldkHz, give up!\n", pll_clock_khz);
607 return;
608 }
609
610#ifdef PDC_DEBUG
611 PDPRINTK("pout_required is %ld\n", pout_required);
612
613 /* Show the current clock value of PLL control register
614 * (maybe already configured by the firmware)
615 */
d2a84f47 616 pll_ctl = ioread16(mmio_base + PDC_PLL_CTL);
669a5db4
JG		 617
618 PDPRINTK("pll_ctl[%X]\n", pll_ctl);
619#endif
620
621 /*
622 * Calculate the ratio of F, R and OD
623 * POUT = (F + 2) / (( R + 2) * NO)
624 */
625 if (ratio < 8600L) { /* 8.6x */
626 /* Using NO = 0x01, R = 0x0D */
627 R = 0x0d;
628 } else if (ratio < 12900L) { /* 12.9x */
629 /* Using NO = 0x01, R = 0x08 */
630 R = 0x08;
631 } else if (ratio < 16100L) { /* 16.1x */
632 /* Using NO = 0x01, R = 0x06 */
633 R = 0x06;
634 } else if (ratio < 64000L) { /* 64x */
635 R = 0x00;
636 } else {
637 /* Invalid ratio */
638 printk(KERN_ERR DRV_NAME ": Invalid ratio %ld, give up!\n", ratio);
639 return;
640 }
641
642 F = (ratio * (R+2)) / 1000 - 2;
643
644 if (unlikely(F < 0 || F > 127)) {
645 /* Invalid F */
646 printk(KERN_ERR DRV_NAME ": F[%d] invalid!\n", F);
647 return;
648 }
649
650 PDPRINTK("F[%d] R[%d] ratio*1000[%ld]\n", F, R, ratio);
651
652 pll_ctl = (R << 8) | F;
653
654 PDPRINTK("Writing pll_ctl[%X]\n", pll_ctl);
655
d2a84f47
AC		 656 iowrite16(pll_ctl, mmio_base + PDC_PLL_CTL);
657 ioread16(mmio_base + PDC_PLL_CTL); /* flush */
669a5db4
JG		 658
659 /* Wait the PLL circuit to be stable */
660 mdelay(30);
661
662#ifdef PDC_DEBUG
663 /*
664 * Show the current clock value of PLL control register
665 * (maybe configured by the firmware)
666 */
d2a84f47 667 pll_ctl = ioread16(mmio_base + PDC_PLL_CTL);
669a5db4
JG		 668
669 PDPRINTK("pll_ctl[%X]\n", pll_ctl);
670#endif
671
672 return;
673}
674
675/**
676 * detect_pll_input_clock - Detect the PLL input clock in Hz.
5d728824 677 * @host: target ATA host
669a5db4
JG		 678 * Ex. 16949000 on 33MHz PCI bus for pdc20275.
679 * Half of the PCI clock.
680 */
5d728824 681static long pdc_detect_pll_input_clock(struct ata_host *host)
669a5db4 682{
5d728824 683 void __iomem *mmio_base = host->iomap[PDC_MMIO_BAR];
669a5db4
JG		 684 u32 scr;
685 long start_count, end_count;
8c781bf7
AL		 686 struct timeval start_time, end_time;
687 long pll_clock, usec_elapsed;
669a5db4 688
669a5db4 689 /* Start the test mode */
d2a84f47 690 scr = ioread32(mmio_base + PDC_SYS_CTL);
669a5db4 691 PDPRINTK("scr[%X]\n", scr);
d2a84f47
AC		 692 iowrite32(scr | (0x01 << 14), mmio_base + PDC_SYS_CTL);
693 ioread32(mmio_base + PDC_SYS_CTL); /* flush */
669a5db4 694
78c4af0b
MP		 695 /* Read current counter value */
696 start_count = pdc_read_counter(host);
697 do_gettimeofday(&start_time);
698
669a5db4
JG		 699 /* Let the counter run for 100 ms. */
700 mdelay(100);
701
702 /* Read the counter values again */
5d728824 703 end_count = pdc_read_counter(host);
8c781bf7 704 do_gettimeofday(&end_time);
669a5db4
JG		 705
706 /* Stop the test mode */
d2a84f47 707 scr = ioread32(mmio_base + PDC_SYS_CTL);
669a5db4 708 PDPRINTK("scr[%X]\n", scr);
d2a84f47
AC		 709 iowrite32(scr & ~(0x01 << 14), mmio_base + PDC_SYS_CTL);
710 ioread32(mmio_base + PDC_SYS_CTL); /* flush */
669a5db4
JG		 711
712 /* calculate the input clock in Hz */
8c781bf7
AL		 713 usec_elapsed = (end_time.tv_sec - start_time.tv_sec) * 1000000 +
714 (end_time.tv_usec - start_time.tv_usec);
715
78c4af0b 716 pll_clock = ((start_count - end_count) & 0x3fffffff) / 100 *
8c781bf7 717 (100000000 / usec_elapsed);
669a5db4
JG		 718
719 PDPRINTK("start[%ld] end[%ld] \n", start_count, end_count);
720 PDPRINTK("PLL input clock[%ld]Hz\n", pll_clock);
721
722 return pll_clock;
723}
724
725/**
726 * pdc_hardware_init - Initialize the hardware.
5d728824
TH		 727 * @host: target ATA host
728 * @board_idx: board identifier
669a5db4 729 */
5d728824 730static int pdc_hardware_init(struct ata_host *host, unsigned int board_idx)
669a5db4
JG		 731{
732 long pll_clock;
733
734 /*
735 * Detect PLL input clock rate.
736 * On some system, where PCI bus is running at non-standard clock rate.
737 * Ex. 25MHz or 40MHz, we have to adjust the cycle_time.
738 * The pdc20275 controller employs PLL circuit to help correct timing registers setting.
739 */
5d728824 740 pll_clock = pdc_detect_pll_input_clock(host);
669a5db4 741
5d728824 742 dev_printk(KERN_INFO, host->dev, "PLL input clock %ld kHz\n", pll_clock/1000);
669a5db4
JG		 743
744 /* Adjust PLL control register */
5d728824 745 pdc_adjust_pll(host, pll_clock, board_idx);
669a5db4
JG		 746
747 return 0;
748}
749
750/**
751 * pdc_ata_setup_port - setup the mmio address
752 * @port: ata ioports to setup
753 * @base: base address
754 */
0d5ff566 755static void pdc_ata_setup_port(struct ata_ioports *port, void __iomem *base)
669a5db4
JG		 756{
757 port->cmd_addr =
758 port->data_addr = base;
759 port->feature_addr =
760 port->error_addr = base + 0x05;
761 port->nsect_addr = base + 0x0a;
762 port->lbal_addr = base + 0x0f;
763 port->lbam_addr = base + 0x10;
764 port->lbah_addr = base + 0x15;
765 port->device_addr = base + 0x1a;
766 port->command_addr =
767 port->status_addr = base + 0x1f;
768 port->altstatus_addr =
769 port->ctl_addr = base + 0x81a;
770}
771
772/**
773 * pdc2027x_init_one - PCI probe function
774 * Called when an instance of PCI adapter is inserted.
775 * This function checks whether the hardware is supported,
776 * initialize hardware and register an instance of ata_host to
5d728824 777 * libata. (implements struct pci_driver.probe() )
669a5db4
JG		 778 *
779 * @pdev: instance of pci_dev found
780 * @ent: matching entry in the id_tbl[]
781 */
782static int __devinit pdc2027x_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
783{
784 static int printed_version;
cbcdd875
TH		 785 static const unsigned long cmd_offset[] = { 0x17c0, 0x15c0 };
786 static const unsigned long bmdma_offset[] = { 0x1000, 0x1008 };
669a5db4 787 unsigned int board_idx = (unsigned int) ent->driver_data;
5d728824
TH		 788 const struct ata_port_info *ppi[] =
789 { &pdc2027x_port_info[board_idx], NULL };
790 struct ata_host *host;
7c250413 791 void __iomem *mmio_base;
cbcdd875 792 int i, rc;
669a5db4
JG		 793
794 if (!printed_version++)
795 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
796
5d728824
TH		 797 /* alloc host */
798 host = ata_host_alloc_pinfo(&pdev->dev, ppi, 2);
799 if (!host)
800 return -ENOMEM;
801
802 /* acquire resources and fill host */
24dc5f33 803 rc = pcim_enable_device(pdev);
669a5db4
JG		 804 if (rc)
805 return rc;
806
0d5ff566 807 rc = pcim_iomap_regions(pdev, 1 << PDC_MMIO_BAR, DRV_NAME);
669a5db4 808 if (rc)
24dc5f33 809 return rc;
5d728824 810 host->iomap = pcim_iomap_table(pdev);
669a5db4
JG		 811
812 rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
813 if (rc)
24dc5f33 814 return rc;
669a5db4
JG		 815
816 rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
817 if (rc)
24dc5f33 818 return rc;
669a5db4 819
5d728824 820 mmio_base = host->iomap[PDC_MMIO_BAR];
669a5db4 821
cbcdd875
TH		 822 for (i = 0; i < 2; i++) {
823 struct ata_port *ap = host->ports[i];
824
825 pdc_ata_setup_port(&ap->ioaddr, mmio_base + cmd_offset[i]);
826 ap->ioaddr.bmdma_addr = mmio_base + bmdma_offset[i];
827
828 ata_port_pbar_desc(ap, PDC_MMIO_BAR, -1, "mmio");
829 ata_port_pbar_desc(ap, PDC_MMIO_BAR, cmd_offset[i], "cmd");
830 }
0d5ff566 831
669a5db4
JG		 832 //pci_enable_intx(pdev);
833
834 /* initialize adapter */
5d728824 835 if (pdc_hardware_init(host, board_idx) != 0)
24dc5f33 836 return -EIO;
669a5db4 837
5d728824
TH		 838 pci_set_master(pdev);
839 return ata_host_activate(host, pdev->irq, ata_interrupt, IRQF_SHARED,
840 &pdc2027x_sht);
669a5db4
JG		 841}
842
843/**
844 * pdc2027x_init - Called after this module is loaded into the kernel.
845 */
846static int __init pdc2027x_init(void)
847{
72dc6794 848 return pci_register_driver(&pdc2027x_pci_driver);
669a5db4
JG		 849}
850
851/**
852 * pdc2027x_exit - Called before this module unloaded from the kernel
853 */
854static void __exit pdc2027x_exit(void)
855{
856 pci_unregister_driver(&pdc2027x_pci_driver);
857}
858
859module_init(pdc2027x_init);
860module_exit(pdc2027x_exit);
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