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libata: convert the remaining SATA drivers to new init model
[linux-block.git] / drivers / ata / pata_pdc2027x.c
CommitLineData
669a5db4
JG		 1/*
2 * Promise PATA TX2/TX4/TX2000/133 IDE driver for pdc20268 to pdc20277.
3 *
4 * This program is free software; you can redistribute it and/or
5 * modify it under the terms of the GNU General Public License
6 * as published by the Free Software Foundation; either version
7 * 2 of the License, or (at your option) any later version.
8 *
9 * Ported to libata by:
10 * Albert Lee <albertcc@tw.ibm.com> IBM Corporation
11 *
12 * Copyright (C) 1998-2002 Andre Hedrick <andre@linux-ide.org>
13 * Portions Copyright (C) 1999 Promise Technology, Inc.
14 *
15 * Author: Frank Tiernan (frankt@promise.com)
16 * Released under terms of General Public License
17 *
18 *
19 * libata documentation is available via 'make {ps|pdf}docs',
20 * as Documentation/DocBook/libata.*
21 *
22 * Hardware information only available under NDA.
23 *
24 */
25#include <linux/kernel.h>
26#include <linux/module.h>
27#include <linux/pci.h>
28#include <linux/init.h>
29#include <linux/blkdev.h>
30#include <linux/delay.h>
31#include <linux/device.h>
32#include <scsi/scsi.h>
33#include <scsi/scsi_host.h>
34#include <scsi/scsi_cmnd.h>
35#include <linux/libata.h>
669a5db4
JG		 36
37#define DRV_NAME "pata_pdc2027x"
9bedb799 38#define DRV_VERSION "0.9"
669a5db4
JG		 39#undef PDC_DEBUG
40
41#ifdef PDC_DEBUG
42#define PDPRINTK(fmt, args...) printk(KERN_ERR "%s: " fmt, __FUNCTION__, ## args)
43#else
44#define PDPRINTK(fmt, args...)
45#endif
46
47enum {
0d5ff566
TH		 48 PDC_MMIO_BAR = 5,
49
669a5db4
JG		 50 PDC_UDMA_100 = 0,
51 PDC_UDMA_133 = 1,
52
53 PDC_100_MHZ = 100000000,
54 PDC_133_MHZ = 133333333,
55
56 PDC_SYS_CTL = 0x1100,
57 PDC_ATA_CTL = 0x1104,
58 PDC_GLOBAL_CTL = 0x1108,
59 PDC_CTCR0 = 0x110C,
60 PDC_CTCR1 = 0x1110,
61 PDC_BYTE_COUNT = 0x1120,
62 PDC_PLL_CTL = 0x1202,
63};
64
65static int pdc2027x_init_one(struct pci_dev *pdev, const struct pci_device_id *ent);
669a5db4
JG		 66static void pdc2027x_error_handler(struct ata_port *ap);
67static void pdc2027x_set_piomode(struct ata_port *ap, struct ata_device *adev);
68static void pdc2027x_set_dmamode(struct ata_port *ap, struct ata_device *adev);
669a5db4 69static int pdc2027x_check_atapi_dma(struct ata_queued_cmd *qc);
9bedb799
AC		 70static unsigned long pdc2027x_mode_filter(struct ata_device *adev, unsigned long mask);
71static int pdc2027x_cable_detect(struct ata_port *ap);
72static int pdc2027x_set_mode(struct ata_port *ap, struct ata_device **r_failed);
669a5db4
JG		 73
74/*
75 * ATA Timing Tables based on 133MHz controller clock.
76 * These tables are only used when the controller is in 133MHz clock.
77 * If the controller is in 100MHz clock, the ASIC hardware will
78 * set the timing registers automatically when "set feature" command
79 * is issued to the device. However, if the controller clock is 133MHz,
80 * the following tables must be used.
81 */
82static struct pdc2027x_pio_timing {
83 u8 value0, value1, value2;
84} pdc2027x_pio_timing_tbl [] = {
85 { 0xfb, 0x2b, 0xac }, /* PIO mode 0 */
86 { 0x46, 0x29, 0xa4 }, /* PIO mode 1 */
87 { 0x23, 0x26, 0x64 }, /* PIO mode 2 */
88 { 0x27, 0x0d, 0x35 }, /* PIO mode 3, IORDY on, Prefetch off */
89 { 0x23, 0x09, 0x25 }, /* PIO mode 4, IORDY on, Prefetch off */
90};
91
92static struct pdc2027x_mdma_timing {
93 u8 value0, value1;
94} pdc2027x_mdma_timing_tbl [] = {
95 { 0xdf, 0x5f }, /* MDMA mode 0 */
96 { 0x6b, 0x27 }, /* MDMA mode 1 */
97 { 0x69, 0x25 }, /* MDMA mode 2 */
98};
99
100static struct pdc2027x_udma_timing {
101 u8 value0, value1, value2;
102} pdc2027x_udma_timing_tbl [] = {
103 { 0x4a, 0x0f, 0xd5 }, /* UDMA mode 0 */
104 { 0x3a, 0x0a, 0xd0 }, /* UDMA mode 1 */
105 { 0x2a, 0x07, 0xcd }, /* UDMA mode 2 */
106 { 0x1a, 0x05, 0xcd }, /* UDMA mode 3 */
107 { 0x1a, 0x03, 0xcd }, /* UDMA mode 4 */
108 { 0x1a, 0x02, 0xcb }, /* UDMA mode 5 */
109 { 0x1a, 0x01, 0xcb }, /* UDMA mode 6 */
110};
111
112static const struct pci_device_id pdc2027x_pci_tbl[] = {
2d2744fc
JG		 113 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20268), PDC_UDMA_100 },
114 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20269), PDC_UDMA_133 },
115 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20270), PDC_UDMA_100 },
116 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20271), PDC_UDMA_133 },
117 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20275), PDC_UDMA_133 },
118 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20276), PDC_UDMA_133 },
119 { PCI_VDEVICE(PROMISE, PCI_DEVICE_ID_PROMISE_20277), PDC_UDMA_133 },
120
669a5db4
JG		 121 { } /* terminate list */
122};
123
124static struct pci_driver pdc2027x_pci_driver = {
125 .name = DRV_NAME,
126 .id_table = pdc2027x_pci_tbl,
127 .probe = pdc2027x_init_one,
24dc5f33 128 .remove = ata_pci_remove_one,
669a5db4
JG		 129};
130
131static struct scsi_host_template pdc2027x_sht = {
132 .module = THIS_MODULE,
133 .name = DRV_NAME,
134 .ioctl = ata_scsi_ioctl,
135 .queuecommand = ata_scsi_queuecmd,
136 .can_queue = ATA_DEF_QUEUE,
137 .this_id = ATA_SHT_THIS_ID,
138 .sg_tablesize = LIBATA_MAX_PRD,
669a5db4
JG		 139 .cmd_per_lun = ATA_SHT_CMD_PER_LUN,
140 .emulated = ATA_SHT_EMULATED,
141 .use_clustering = ATA_SHT_USE_CLUSTERING,
142 .proc_name = DRV_NAME,
143 .dma_boundary = ATA_DMA_BOUNDARY,
144 .slave_configure = ata_scsi_slave_config,
afdfe899 145 .slave_destroy = ata_scsi_slave_destroy,
669a5db4
JG		 146 .bios_param = ata_std_bios_param,
147};
148
149static struct ata_port_operations pdc2027x_pata100_ops = {
150 .port_disable = ata_port_disable,
9bedb799 151 .mode_filter = ata_pci_default_filter,
669a5db4
JG		 152
153 .tf_load = ata_tf_load,
154 .tf_read = ata_tf_read,
155 .check_status = ata_check_status,
156 .exec_command = ata_exec_command,
157 .dev_select = ata_std_dev_select,
158
159 .check_atapi_dma = pdc2027x_check_atapi_dma,
160 .bmdma_setup = ata_bmdma_setup,
161 .bmdma_start = ata_bmdma_start,
162 .bmdma_stop = ata_bmdma_stop,
163 .bmdma_status = ata_bmdma_status,
164 .qc_prep = ata_qc_prep,
165 .qc_issue = ata_qc_issue_prot,
0d5ff566 166 .data_xfer = ata_data_xfer,
669a5db4
JG		 167
168 .freeze = ata_bmdma_freeze,
169 .thaw = ata_bmdma_thaw,
170 .error_handler = pdc2027x_error_handler,
171 .post_internal_cmd = ata_bmdma_post_internal_cmd,
9bedb799 172 .cable_detect = pdc2027x_cable_detect,
669a5db4
JG		 173
174 .irq_handler = ata_interrupt,
175 .irq_clear = ata_bmdma_irq_clear,
246ce3b6
AI		 176 .irq_on = ata_irq_on,
177 .irq_ack = ata_irq_ack,
669a5db4
JG		 178
179 .port_start = ata_port_start,
669a5db4
JG		 180};
181
182static struct ata_port_operations pdc2027x_pata133_ops = {
183 .port_disable = ata_port_disable,
184 .set_piomode = pdc2027x_set_piomode,
185 .set_dmamode = pdc2027x_set_dmamode,
9bedb799
AC		 186 .set_mode = pdc2027x_set_mode,
187 .mode_filter = pdc2027x_mode_filter,
669a5db4
JG		 188
189 .tf_load = ata_tf_load,
190 .tf_read = ata_tf_read,
191 .check_status = ata_check_status,
192 .exec_command = ata_exec_command,
193 .dev_select = ata_std_dev_select,
194
195 .check_atapi_dma = pdc2027x_check_atapi_dma,
196 .bmdma_setup = ata_bmdma_setup,
197 .bmdma_start = ata_bmdma_start,
198 .bmdma_stop = ata_bmdma_stop,
199 .bmdma_status = ata_bmdma_status,
200 .qc_prep = ata_qc_prep,
201 .qc_issue = ata_qc_issue_prot,
0d5ff566 202 .data_xfer = ata_data_xfer,
669a5db4
JG		 203
204 .freeze = ata_bmdma_freeze,
205 .thaw = ata_bmdma_thaw,
206 .error_handler = pdc2027x_error_handler,
207 .post_internal_cmd = ata_bmdma_post_internal_cmd,
9bedb799 208 .cable_detect = pdc2027x_cable_detect,
669a5db4
JG		 209
210 .irq_handler = ata_interrupt,
211 .irq_clear = ata_bmdma_irq_clear,
246ce3b6
AI		 212 .irq_on = ata_irq_on,
213 .irq_ack = ata_irq_ack,
669a5db4
JG		 214
215 .port_start = ata_port_start,
669a5db4
JG		 216};
217
218static struct ata_port_info pdc2027x_port_info[] = {
219 /* PDC_UDMA_100 */
220 {
221 .sht = &pdc2027x_sht,
222 .flags = ATA_FLAG_NO_LEGACY | ATA_FLAG_SLAVE_POSS |
223 ATA_FLAG_MMIO,
224 .pio_mask = 0x1f, /* pio0-4 */
225 .mwdma_mask = 0x07, /* mwdma0-2 */
226 .udma_mask = ATA_UDMA5, /* udma0-5 */
227 .port_ops = &pdc2027x_pata100_ops,
228 },
229 /* PDC_UDMA_133 */
230 {
231 .sht = &pdc2027x_sht,
232 .flags = ATA_FLAG_NO_LEGACY | ATA_FLAG_SLAVE_POSS |
233 ATA_FLAG_MMIO,
234 .pio_mask = 0x1f, /* pio0-4 */
235 .mwdma_mask = 0x07, /* mwdma0-2 */
236 .udma_mask = ATA_UDMA6, /* udma0-6 */
237 .port_ops = &pdc2027x_pata133_ops,
238 },
239};
240
241MODULE_AUTHOR("Andre Hedrick, Frank Tiernan, Albert Lee");
242MODULE_DESCRIPTION("libata driver module for Promise PDC20268 to PDC20277");
243MODULE_LICENSE("GPL");
244MODULE_VERSION(DRV_VERSION);
245MODULE_DEVICE_TABLE(pci, pdc2027x_pci_tbl);
246
247/**
248 * port_mmio - Get the MMIO address of PDC2027x extended registers
249 * @ap: Port
250 * @offset: offset from mmio base
251 */
7c250413 252static inline void __iomem *port_mmio(struct ata_port *ap, unsigned int offset)
669a5db4 253{
0d5ff566 254 return ap->host->iomap[PDC_MMIO_BAR] + ap->port_no * 0x100 + offset;
669a5db4
JG		 255}
256
257/**
258 * dev_mmio - Get the MMIO address of PDC2027x extended registers
259 * @ap: Port
260 * @adev: device
261 * @offset: offset from mmio base
262 */
7c250413 263static inline void __iomem *dev_mmio(struct ata_port *ap, struct ata_device *adev, unsigned int offset)
669a5db4
JG		 264{
265 u8 adj = (adev->devno) ? 0x08 : 0x00;
266 return port_mmio(ap, offset) + adj;
267}
268
269/**
9bedb799 270 * pdc2027x_pata_cable_detect - Probe host controller cable detect info
669a5db4
JG		 271 * @ap: Port for which cable detect info is desired
272 *
273 * Read 80c cable indicator from Promise extended register.
274 * This register is latched when the system is reset.
275 *
276 * LOCKING:
277 * None (inherited from caller).
278 */
9bedb799 279static int pdc2027x_cable_detect(struct ata_port *ap)
669a5db4
JG		 280{
281 u32 cgcr;
282
283 /* check cable detect results */
284 cgcr = readl(port_mmio(ap, PDC_GLOBAL_CTL));
285 if (cgcr & (1 << 26))
286 goto cbl40;
287
288 PDPRINTK("No cable or 80-conductor cable on port %d\n", ap->port_no);
289
9bedb799 290 return ATA_CBL_PATA80;
669a5db4
JG		 291cbl40:
292 printk(KERN_INFO DRV_NAME ": 40-conductor cable detected on port %d\n", ap->port_no);
9bedb799 293 return ATA_CBL_PATA40;
669a5db4
JG		 294}
295
296/**
297 * pdc2027x_port_enabled - Check PDC ATA control register to see whether the port is enabled.
298 * @ap: Port to check
299 */
300static inline int pdc2027x_port_enabled(struct ata_port *ap)
301{
302 return readb(port_mmio(ap, PDC_ATA_CTL)) & 0x02;
303}
304
305/**
306 * pdc2027x_prereset - prereset for PATA host controller
307 * @ap: Target port
308 *
309 * Probeinit including cable detection.
310 *
311 * LOCKING:
312 * None (inherited from caller).
313 */
314
315static int pdc2027x_prereset(struct ata_port *ap)
316{
317 /* Check whether port enabled */
c961922b
AC		 318 if (!pdc2027x_port_enabled(ap))
319 return -ENOENT;
669a5db4
JG		 320 return ata_std_prereset(ap);
321}
322
323/**
324 * pdc2027x_error_handler - Perform reset on PATA port and classify
325 * @ap: Port to reset
326 *
327 * Reset PATA phy and classify attached devices.
328 *
329 * LOCKING:
330 * None (inherited from caller).
331 */
332
333static void pdc2027x_error_handler(struct ata_port *ap)
334{
335 ata_bmdma_drive_eh(ap, pdc2027x_prereset, ata_std_softreset, NULL, ata_std_postreset);
336}
337
9bedb799
AC		 338/**
339 * pdc2720x_mode_filter - mode selection filter
340 * @adev: ATA device
341 * @mask: list of modes proposed
342 *
343 * Block UDMA on devices that cause trouble with this controller.
344 */
345
346static unsigned long pdc2027x_mode_filter(struct ata_device *adev, unsigned long mask)
347{
348 unsigned char model_num[ATA_ID_PROD_LEN + 1];
349 struct ata_device *pair = ata_dev_pair(adev);
350
351 if (adev->class != ATA_DEV_ATA || adev->devno == 0 || pair == NULL)
352 return ata_pci_default_filter(adev, mask);
353
354 /* Check for slave of a Maxtor at UDMA6 */
355 ata_id_c_string(pair->id, model_num, ATA_ID_PROD,
356 ATA_ID_PROD_LEN + 1);
357 /* If the master is a maxtor in UDMA6 then the slave should not use UDMA 6 */
358 if(strstr(model_num, "Maxtor") == 0 && pair->dma_mode == XFER_UDMA_6)
359 mask &= ~ (1 << (6 + ATA_SHIFT_UDMA));
360
361 return ata_pci_default_filter(adev, mask);
362}
363
669a5db4
JG		 364/**
365 * pdc2027x_set_piomode - Initialize host controller PATA PIO timings
366 * @ap: Port to configure
367 * @adev: um
368 * @pio: PIO mode, 0 - 4
369 *
370 * Set PIO mode for device.
371 *
372 * LOCKING:
373 * None (inherited from caller).
374 */
375
376static void pdc2027x_set_piomode(struct ata_port *ap, struct ata_device *adev)
377{
378 unsigned int pio = adev->pio_mode - XFER_PIO_0;
379 u32 ctcr0, ctcr1;
380
381 PDPRINTK("adev->pio_mode[%X]\n", adev->pio_mode);
382
383 /* Sanity check */
384 if (pio > 4) {
385 printk(KERN_ERR DRV_NAME ": Unknown pio mode [%d] ignored\n", pio);
386 return;
387
388 }
389
390 /* Set the PIO timing registers using value table for 133MHz */
391 PDPRINTK("Set pio regs... \n");
392
393 ctcr0 = readl(dev_mmio(ap, adev, PDC_CTCR0));
394 ctcr0 &= 0xffff0000;
395 ctcr0 |= pdc2027x_pio_timing_tbl[pio].value0 |
396 (pdc2027x_pio_timing_tbl[pio].value1 << 8);
397 writel(ctcr0, dev_mmio(ap, adev, PDC_CTCR0));
398
399 ctcr1 = readl(dev_mmio(ap, adev, PDC_CTCR1));
400 ctcr1 &= 0x00ffffff;
401 ctcr1 |= (pdc2027x_pio_timing_tbl[pio].value2 << 24);
402 writel(ctcr1, dev_mmio(ap, adev, PDC_CTCR1));
403
404 PDPRINTK("Set pio regs done\n");
405
406 PDPRINTK("Set to pio mode[%u] \n", pio);
407}
408
409/**
410 * pdc2027x_set_dmamode - Initialize host controller PATA UDMA timings
411 * @ap: Port to configure
412 * @adev: um
413 * @udma: udma mode, XFER_UDMA_0 to XFER_UDMA_6
414 *
415 * Set UDMA mode for device.
416 *
417 * LOCKING:
418 * None (inherited from caller).
419 */
420static void pdc2027x_set_dmamode(struct ata_port *ap, struct ata_device *adev)
421{
422 unsigned int dma_mode = adev->dma_mode;
423 u32 ctcr0, ctcr1;
424
425 if ((dma_mode >= XFER_UDMA_0) &&
426 (dma_mode <= XFER_UDMA_6)) {
427 /* Set the UDMA timing registers with value table for 133MHz */
428 unsigned int udma_mode = dma_mode & 0x07;
429
430 if (dma_mode == XFER_UDMA_2) {
431 /*
432 * Turn off tHOLD.
433 * If tHOLD is '1', the hardware will add half clock for data hold time.
434 * This code segment seems to be no effect. tHOLD will be overwritten below.
435 */
436 ctcr1 = readl(dev_mmio(ap, adev, PDC_CTCR1));
437 writel(ctcr1 & ~(1 << 7), dev_mmio(ap, adev, PDC_CTCR1));
438 }
439
440 PDPRINTK("Set udma regs... \n");
441
442 ctcr1 = readl(dev_mmio(ap, adev, PDC_CTCR1));
443 ctcr1 &= 0xff000000;
444 ctcr1 |= pdc2027x_udma_timing_tbl[udma_mode].value0 |
445 (pdc2027x_udma_timing_tbl[udma_mode].value1 << 8) |
446 (pdc2027x_udma_timing_tbl[udma_mode].value2 << 16);
447 writel(ctcr1, dev_mmio(ap, adev, PDC_CTCR1));
448
449 PDPRINTK("Set udma regs done\n");
450
451 PDPRINTK("Set to udma mode[%u] \n", udma_mode);
452
453 } else if ((dma_mode >= XFER_MW_DMA_0) &&
454 (dma_mode <= XFER_MW_DMA_2)) {
455 /* Set the MDMA timing registers with value table for 133MHz */
456 unsigned int mdma_mode = dma_mode & 0x07;
457
458 PDPRINTK("Set mdma regs... \n");
459 ctcr0 = readl(dev_mmio(ap, adev, PDC_CTCR0));
460
461 ctcr0 &= 0x0000ffff;
462 ctcr0 |= (pdc2027x_mdma_timing_tbl[mdma_mode].value0 << 16) |
463 (pdc2027x_mdma_timing_tbl[mdma_mode].value1 << 24);
464
465 writel(ctcr0, dev_mmio(ap, adev, PDC_CTCR0));
466 PDPRINTK("Set mdma regs done\n");
467
468 PDPRINTK("Set to mdma mode[%u] \n", mdma_mode);
469 } else {
470 printk(KERN_ERR DRV_NAME ": Unknown dma mode [%u] ignored\n", dma_mode);
471 }
472}
473
474/**
9bedb799 475 * pdc2027x_set_mode - Set the timing registers back to correct values.
669a5db4 476 * @ap: Port to configure
9bedb799 477 * @r_failed: Returned device for failure
669a5db4
JG		 478 *
479 * The pdc2027x hardware will look at "SET FEATURES" and change the timing registers
480 * automatically. The values set by the hardware might be incorrect, under 133Mhz PLL.
481 * This function overwrites the possibly incorrect values set by the hardware to be correct.
482 */
9bedb799 483static int pdc2027x_set_mode(struct ata_port *ap, struct ata_device **r_failed)
669a5db4
JG		 484{
485 int i;
486
9bedb799
AC		 487 i = ata_do_set_mode(ap, r_failed);
488 if (i < 0)
489 return i;
490
669a5db4
JG		 491 for (i = 0; i < ATA_MAX_DEVICES; i++) {
492 struct ata_device *dev = &ap->device[i];
493
494 if (ata_dev_enabled(dev)) {
495
496 pdc2027x_set_piomode(ap, dev);
497
498 /*
499 * Enable prefetch if the device support PIO only.
500 */
501 if (dev->xfer_shift == ATA_SHIFT_PIO) {
502 u32 ctcr1 = readl(dev_mmio(ap, dev, PDC_CTCR1));
503 ctcr1 |= (1 << 25);
504 writel(ctcr1, dev_mmio(ap, dev, PDC_CTCR1));
505
506 PDPRINTK("Turn on prefetch\n");
507 } else {
508 pdc2027x_set_dmamode(ap, dev);
509 }
510 }
511 }
9bedb799 512 return 0;
669a5db4
JG		 513}
514
515/**
516 * pdc2027x_check_atapi_dma - Check whether ATAPI DMA can be supported for this command
517 * @qc: Metadata associated with taskfile to check
518 *
519 * LOCKING:
520 * None (inherited from caller).
521 *
522 * RETURNS: 0 when ATAPI DMA can be used
523 * 1 otherwise
524 */
525static int pdc2027x_check_atapi_dma(struct ata_queued_cmd *qc)
526{
527 struct scsi_cmnd *cmd = qc->scsicmd;
528 u8 *scsicmd = cmd->cmnd;
529 int rc = 1; /* atapi dma off by default */
530
531 /*
532 * This workaround is from Promise's GPL driver.
533 * If ATAPI DMA is used for commands not in the
534 * following white list, say MODE_SENSE and REQUEST_SENSE,
535 * pdc2027x might hit the irq lost problem.
536 */
537 switch (scsicmd[0]) {
538 case READ_10:
539 case WRITE_10:
540 case READ_12:
541 case WRITE_12:
542 case READ_6:
543 case WRITE_6:
544 case 0xad: /* READ_DVD_STRUCTURE */
545 case 0xbe: /* READ_CD */
546 /* ATAPI DMA is ok */
547 rc = 0;
548 break;
549 default:
550 ;
551 }
552
553 return rc;
554}
555
556/**
557 * pdc_read_counter - Read the ctr counter
558 * @probe_ent: for the port address
559 */
560
561static long pdc_read_counter(struct ata_probe_ent *probe_ent)
562{
0d5ff566 563 void __iomem *mmio_base = probe_ent->iomap[PDC_MMIO_BAR];
669a5db4
JG		 564 long counter;
565 int retry = 1;
566 u32 bccrl, bccrh, bccrlv, bccrhv;
567
568retry:
0d5ff566
TH		 569 bccrl = readl(mmio_base + PDC_BYTE_COUNT) & 0xffff;
570 bccrh = readl(mmio_base + PDC_BYTE_COUNT + 0x100) & 0xffff;
669a5db4
JG		 571 rmb();
572
573 /* Read the counter values again for verification */
0d5ff566
TH		 574 bccrlv = readl(mmio_base + PDC_BYTE_COUNT) & 0xffff;
575 bccrhv = readl(mmio_base + PDC_BYTE_COUNT + 0x100) & 0xffff;
669a5db4
JG		 576 rmb();
577
578 counter = (bccrh << 15) | bccrl;
579
580 PDPRINTK("bccrh [%X] bccrl [%X]\n", bccrh, bccrl);
581 PDPRINTK("bccrhv[%X] bccrlv[%X]\n", bccrhv, bccrlv);
582
583 /*
584 * The 30-bit decreasing counter are read by 2 pieces.
585 * Incorrect value may be read when both bccrh and bccrl are changing.
586 * Ex. When 7900 decrease to 78FF, wrong value 7800 might be read.
587 */
588 if (retry && !(bccrh == bccrhv && bccrl >= bccrlv)) {
589 retry--;
590 PDPRINTK("rereading counter\n");
591 goto retry;
592 }
593
594 return counter;
595}
596
597/**
598 * adjust_pll - Adjust the PLL input clock in Hz.
599 *
600 * @pdc_controller: controller specific information
601 * @probe_ent: For the port address
602 * @pll_clock: The input of PLL in HZ
603 */
604static void pdc_adjust_pll(struct ata_probe_ent *probe_ent, long pll_clock, unsigned int board_idx)
605{
0d5ff566 606 void __iomem *mmio_base = probe_ent->iomap[PDC_MMIO_BAR];
669a5db4
JG		 607 u16 pll_ctl;
608 long pll_clock_khz = pll_clock / 1000;
609 long pout_required = board_idx? PDC_133_MHZ:PDC_100_MHZ;
610 long ratio = pout_required / pll_clock_khz;
611 int F, R;
612
613 /* Sanity check */
614 if (unlikely(pll_clock_khz < 5000L || pll_clock_khz > 70000L)) {
615 printk(KERN_ERR DRV_NAME ": Invalid PLL input clock %ldkHz, give up!\n", pll_clock_khz);
616 return;
617 }
618
619#ifdef PDC_DEBUG
620 PDPRINTK("pout_required is %ld\n", pout_required);
621
622 /* Show the current clock value of PLL control register
623 * (maybe already configured by the firmware)
624 */
0d5ff566 625 pll_ctl = readw(mmio_base + PDC_PLL_CTL);
669a5db4
JG		 626
627 PDPRINTK("pll_ctl[%X]\n", pll_ctl);
628#endif
629
630 /*
631 * Calculate the ratio of F, R and OD
632 * POUT = (F + 2) / (( R + 2) * NO)
633 */
634 if (ratio < 8600L) { /* 8.6x */
635 /* Using NO = 0x01, R = 0x0D */
636 R = 0x0d;
637 } else if (ratio < 12900L) { /* 12.9x */
638 /* Using NO = 0x01, R = 0x08 */
639 R = 0x08;
640 } else if (ratio < 16100L) { /* 16.1x */
641 /* Using NO = 0x01, R = 0x06 */
642 R = 0x06;
643 } else if (ratio < 64000L) { /* 64x */
644 R = 0x00;
645 } else {
646 /* Invalid ratio */
647 printk(KERN_ERR DRV_NAME ": Invalid ratio %ld, give up!\n", ratio);
648 return;
649 }
650
651 F = (ratio * (R+2)) / 1000 - 2;
652
653 if (unlikely(F < 0 || F > 127)) {
654 /* Invalid F */
655 printk(KERN_ERR DRV_NAME ": F[%d] invalid!\n", F);
656 return;
657 }
658
659 PDPRINTK("F[%d] R[%d] ratio*1000[%ld]\n", F, R, ratio);
660
661 pll_ctl = (R << 8) | F;
662
663 PDPRINTK("Writing pll_ctl[%X]\n", pll_ctl);
664
0d5ff566
TH		 665 writew(pll_ctl, mmio_base + PDC_PLL_CTL);
666 readw(mmio_base + PDC_PLL_CTL); /* flush */
669a5db4
JG		 667
668 /* Wait the PLL circuit to be stable */
669 mdelay(30);
670
671#ifdef PDC_DEBUG
672 /*
673 * Show the current clock value of PLL control register
674 * (maybe configured by the firmware)
675 */
0d5ff566 676 pll_ctl = readw(mmio_base + PDC_PLL_CTL);
669a5db4
JG		 677
678 PDPRINTK("pll_ctl[%X]\n", pll_ctl);
679#endif
680
681 return;
682}
683
684/**
685 * detect_pll_input_clock - Detect the PLL input clock in Hz.
686 * @probe_ent: for the port address
687 * Ex. 16949000 on 33MHz PCI bus for pdc20275.
688 * Half of the PCI clock.
689 */
690static long pdc_detect_pll_input_clock(struct ata_probe_ent *probe_ent)
691{
0d5ff566 692 void __iomem *mmio_base = probe_ent->iomap[PDC_MMIO_BAR];
669a5db4
JG		 693 u32 scr;
694 long start_count, end_count;
695 long pll_clock;
696
697 /* Read current counter value */
698 start_count = pdc_read_counter(probe_ent);
699
700 /* Start the test mode */
0d5ff566 701 scr = readl(mmio_base + PDC_SYS_CTL);
669a5db4 702 PDPRINTK("scr[%X]\n", scr);
0d5ff566
TH		 703 writel(scr | (0x01 << 14), mmio_base + PDC_SYS_CTL);
704 readl(mmio_base + PDC_SYS_CTL); /* flush */
669a5db4
JG		 705
706 /* Let the counter run for 100 ms. */
707 mdelay(100);
708
709 /* Read the counter values again */
710 end_count = pdc_read_counter(probe_ent);
711
712 /* Stop the test mode */
0d5ff566 713 scr = readl(mmio_base + PDC_SYS_CTL);
669a5db4 714 PDPRINTK("scr[%X]\n", scr);
0d5ff566
TH		 715 writel(scr & ~(0x01 << 14), mmio_base + PDC_SYS_CTL);
716 readl(mmio_base + PDC_SYS_CTL); /* flush */
669a5db4
JG		 717
718 /* calculate the input clock in Hz */
719 pll_clock = (start_count - end_count) * 10;
720
721 PDPRINTK("start[%ld] end[%ld] \n", start_count, end_count);
722 PDPRINTK("PLL input clock[%ld]Hz\n", pll_clock);
723
724 return pll_clock;
725}
726
727/**
728 * pdc_hardware_init - Initialize the hardware.
729 * @pdev: instance of pci_dev found
730 * @pdc_controller: controller specific information
731 * @pe: for the port address
732 */
733static int pdc_hardware_init(struct pci_dev *pdev, struct ata_probe_ent *pe, unsigned int board_idx)
734{
735 long pll_clock;
736
737 /*
738 * Detect PLL input clock rate.
739 * On some system, where PCI bus is running at non-standard clock rate.
740 * Ex. 25MHz or 40MHz, we have to adjust the cycle_time.
741 * The pdc20275 controller employs PLL circuit to help correct timing registers setting.
742 */
743 pll_clock = pdc_detect_pll_input_clock(pe);
744
745 if (pll_clock < 0) /* counter overflow? Try again. */
746 pll_clock = pdc_detect_pll_input_clock(pe);
747
748 dev_printk(KERN_INFO, &pdev->dev, "PLL input clock %ld kHz\n", pll_clock/1000);
749
750 /* Adjust PLL control register */
751 pdc_adjust_pll(pe, pll_clock, board_idx);
752
753 return 0;
754}
755
756/**
757 * pdc_ata_setup_port - setup the mmio address
758 * @port: ata ioports to setup
759 * @base: base address
760 */
0d5ff566 761static void pdc_ata_setup_port(struct ata_ioports *port, void __iomem *base)
669a5db4
JG		 762{
763 port->cmd_addr =
764 port->data_addr = base;
765 port->feature_addr =
766 port->error_addr = base + 0x05;
767 port->nsect_addr = base + 0x0a;
768 port->lbal_addr = base + 0x0f;
769 port->lbam_addr = base + 0x10;
770 port->lbah_addr = base + 0x15;
771 port->device_addr = base + 0x1a;
772 port->command_addr =
773 port->status_addr = base + 0x1f;
774 port->altstatus_addr =
775 port->ctl_addr = base + 0x81a;
776}
777
778/**
779 * pdc2027x_init_one - PCI probe function
780 * Called when an instance of PCI adapter is inserted.
781 * This function checks whether the hardware is supported,
782 * initialize hardware and register an instance of ata_host to
783 * libata by providing struct ata_probe_ent and ata_device_add().
784 * (implements struct pci_driver.probe() )
785 *
786 * @pdev: instance of pci_dev found
787 * @ent: matching entry in the id_tbl[]
788 */
789static int __devinit pdc2027x_init_one(struct pci_dev *pdev, const struct pci_device_id *ent)
790{
791 static int printed_version;
792 unsigned int board_idx = (unsigned int) ent->driver_data;
793
24dc5f33 794 struct ata_probe_ent *probe_ent;
7c250413 795 void __iomem *mmio_base;
669a5db4
JG		 796 int rc;
797
798 if (!printed_version++)
799 dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
800
24dc5f33 801 rc = pcim_enable_device(pdev);
669a5db4
JG		 802 if (rc)
803 return rc;
804
0d5ff566 805 rc = pcim_iomap_regions(pdev, 1 << PDC_MMIO_BAR, DRV_NAME);
669a5db4 806 if (rc)
24dc5f33 807 return rc;
669a5db4
JG		 808
809 rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
810 if (rc)
24dc5f33 811 return rc;
669a5db4
JG		 812
813 rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
814 if (rc)
24dc5f33 815 return rc;
669a5db4
JG		 816
817 /* Prepare the probe entry */
24dc5f33
TH		 818 probe_ent = devm_kzalloc(&pdev->dev, sizeof(*probe_ent), GFP_KERNEL);
819 if (probe_ent == NULL)
820 return -ENOMEM;
669a5db4
JG		 821
822 probe_ent->dev = pci_dev_to_dev(pdev);
823 INIT_LIST_HEAD(&probe_ent->node);
824
669a5db4
JG		 825 probe_ent->sht = pdc2027x_port_info[board_idx].sht;
826 probe_ent->port_flags = pdc2027x_port_info[board_idx].flags;
827 probe_ent->pio_mask = pdc2027x_port_info[board_idx].pio_mask;
828 probe_ent->mwdma_mask = pdc2027x_port_info[board_idx].mwdma_mask;
829 probe_ent->udma_mask = pdc2027x_port_info[board_idx].udma_mask;
830 probe_ent->port_ops = pdc2027x_port_info[board_idx].port_ops;
831
832 probe_ent->irq = pdev->irq;
38515e90 833 probe_ent->irq_flags = IRQF_SHARED;
0d5ff566
TH		 834 probe_ent->iomap = pcim_iomap_table(pdev);
835
836 mmio_base = probe_ent->iomap[PDC_MMIO_BAR];
669a5db4 837
0d5ff566
TH		 838 pdc_ata_setup_port(&probe_ent->port[0], mmio_base + 0x17c0);
839 probe_ent->port[0].bmdma_addr = mmio_base + 0x1000;
840 pdc_ata_setup_port(&probe_ent->port[1], mmio_base + 0x15c0);
841 probe_ent->port[1].bmdma_addr = mmio_base + 0x1008;
669a5db4
JG		 842
843 probe_ent->n_ports = 2;
844
845 pci_set_master(pdev);
846 //pci_enable_intx(pdev);
847
848 /* initialize adapter */
849 if (pdc_hardware_init(pdev, probe_ent, board_idx) != 0)
24dc5f33 850 return -EIO;
669a5db4 851
24dc5f33
TH		 852 if (!ata_device_add(probe_ent))
853 return -ENODEV;
669a5db4 854
24dc5f33 855 devm_kfree(&pdev->dev, probe_ent);
669a5db4 856 return 0;
669a5db4
JG		 857}
858
859/**
860 * pdc2027x_init - Called after this module is loaded into the kernel.
861 */
862static int __init pdc2027x_init(void)
863{
72dc6794 864 return pci_register_driver(&pdc2027x_pci_driver);
669a5db4
JG		 865}
866
867/**
868 * pdc2027x_exit - Called before this module unloaded from the kernel
869 */
870static void __exit pdc2027x_exit(void)
871{
872 pci_unregister_driver(&pdc2027x_pci_driver);
873}
874
875module_init(pdc2027x_init);
876module_exit(pdc2027x_exit);
Linux 6.x block layer and io_uring tree(s)