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669a5db4 JG |
1 | /* |
2 | * pata_oldpiix.c - Intel PATA/SATA controllers | |
3 | * | |
4 | * (C) 2005 Red Hat <alan@redhat.com> | |
5 | * | |
6 | * Some parts based on ata_piix.c by Jeff Garzik and others. | |
7 | * | |
8 | * Early PIIX differs significantly from the later PIIX as it lacks | |
9 | * SITRE and the slave timing registers. This means that you have to | |
10 | * set timing per channel, or be clever. Libata tells us whenever it | |
11 | * does drive selection and we use this to reload the timings. | |
12 | * | |
13 | * Because of these behaviour differences PIIX gets its own driver module. | |
14 | */ | |
15 | ||
16 | #include <linux/kernel.h> | |
17 | #include <linux/module.h> | |
18 | #include <linux/pci.h> | |
19 | #include <linux/init.h> | |
20 | #include <linux/blkdev.h> | |
21 | #include <linux/delay.h> | |
22 | #include <linux/device.h> | |
23 | #include <scsi/scsi_host.h> | |
24 | #include <linux/libata.h> | |
25 | #include <linux/ata.h> | |
26 | ||
27 | #define DRV_NAME "pata_oldpiix" | |
a0fcdc02 | 28 | #define DRV_VERSION "0.5.5" |
669a5db4 JG |
29 | |
30 | /** | |
31 | * oldpiix_pre_reset - probe begin | |
cc0680a5 | 32 | * @link: ATA link |
d4b2bab4 | 33 | * @deadline: deadline jiffies for the operation |
669a5db4 JG |
34 | * |
35 | * Set up cable type and use generic probe init | |
36 | */ | |
37 | ||
cc0680a5 | 38 | static int oldpiix_pre_reset(struct ata_link *link, unsigned long deadline) |
669a5db4 | 39 | { |
cc0680a5 | 40 | struct ata_port *ap = link->ap; |
669a5db4 JG |
41 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); |
42 | static const struct pci_bits oldpiix_enable_bits[] = { | |
43 | { 0x41U, 1U, 0x80UL, 0x80UL }, /* port 0 */ | |
44 | { 0x43U, 1U, 0x80UL, 0x80UL }, /* port 1 */ | |
45 | }; | |
46 | ||
c961922b AC |
47 | if (!pci_test_config_bits(pdev, &oldpiix_enable_bits[ap->port_no])) |
48 | return -ENOENT; | |
d4b2bab4 | 49 | |
cc0680a5 | 50 | return ata_std_prereset(link, deadline); |
669a5db4 JG |
51 | } |
52 | ||
53 | /** | |
54 | * oldpiix_pata_error_handler - Probe specified port on PATA host controller | |
55 | * @ap: Port to probe | |
56 | * @classes: | |
57 | * | |
58 | * LOCKING: | |
59 | * None (inherited from caller). | |
60 | */ | |
61 | ||
62 | static void oldpiix_pata_error_handler(struct ata_port *ap) | |
63 | { | |
64 | ata_bmdma_drive_eh(ap, oldpiix_pre_reset, ata_std_softreset, NULL, ata_std_postreset); | |
65 | } | |
66 | ||
67 | /** | |
68 | * oldpiix_set_piomode - Initialize host controller PATA PIO timings | |
69 | * @ap: Port whose timings we are configuring | |
a0fcdc02 | 70 | * @adev: Device whose timings we are configuring |
669a5db4 JG |
71 | * |
72 | * Set PIO mode for device, in host controller PCI config space. | |
73 | * | |
74 | * LOCKING: | |
75 | * None (inherited from caller). | |
76 | */ | |
77 | ||
78 | static void oldpiix_set_piomode (struct ata_port *ap, struct ata_device *adev) | |
79 | { | |
80 | unsigned int pio = adev->pio_mode - XFER_PIO_0; | |
81 | struct pci_dev *dev = to_pci_dev(ap->host->dev); | |
82 | unsigned int idetm_port= ap->port_no ? 0x42 : 0x40; | |
83 | u16 idetm_data; | |
84 | int control = 0; | |
85 | ||
86 | /* | |
87 | * See Intel Document 298600-004 for the timing programing rules | |
88 | * for PIIX/ICH. Note that the early PIIX does not have the slave | |
89 | * timing port at 0x44. | |
90 | */ | |
91 | ||
92 | static const /* ISP RTC */ | |
93 | u8 timings[][2] = { { 0, 0 }, | |
94 | { 0, 0 }, | |
95 | { 1, 0 }, | |
96 | { 2, 1 }, | |
97 | { 2, 3 }, }; | |
98 | ||
409ba47c SS |
99 | if (pio > 1) |
100 | control |= 1; /* TIME */ | |
669a5db4 | 101 | if (ata_pio_need_iordy(adev)) |
409ba47c | 102 | control |= 2; /* IE */ |
669a5db4 | 103 | |
409ba47c | 104 | /* Intel specifies that the prefetch/posting is for disk only */ |
669a5db4 | 105 | if (adev->class == ATA_DEV_ATA) |
409ba47c | 106 | control |= 4; /* PPE */ |
669a5db4 JG |
107 | |
108 | pci_read_config_word(dev, idetm_port, &idetm_data); | |
109 | ||
409ba47c SS |
110 | /* |
111 | * Set PPE, IE and TIME as appropriate. | |
112 | * Clear the other drive's timing bits. | |
113 | */ | |
669a5db4 JG |
114 | if (adev->devno == 0) { |
115 | idetm_data &= 0xCCE0; | |
116 | idetm_data |= control; | |
117 | } else { | |
118 | idetm_data &= 0xCC0E; | |
119 | idetm_data |= (control << 4); | |
120 | } | |
121 | idetm_data |= (timings[pio][0] << 12) | | |
122 | (timings[pio][1] << 8); | |
123 | pci_write_config_word(dev, idetm_port, idetm_data); | |
124 | ||
125 | /* Track which port is configured */ | |
126 | ap->private_data = adev; | |
127 | } | |
128 | ||
129 | /** | |
130 | * oldpiix_set_dmamode - Initialize host controller PATA DMA timings | |
131 | * @ap: Port whose timings we are configuring | |
132 | * @adev: Device to program | |
133 | * @isich: True if the device is an ICH and has IOCFG registers | |
134 | * | |
135 | * Set MWDMA mode for device, in host controller PCI config space. | |
136 | * | |
137 | * LOCKING: | |
138 | * None (inherited from caller). | |
139 | */ | |
140 | ||
141 | static void oldpiix_set_dmamode (struct ata_port *ap, struct ata_device *adev) | |
142 | { | |
143 | struct pci_dev *dev = to_pci_dev(ap->host->dev); | |
144 | u8 idetm_port = ap->port_no ? 0x42 : 0x40; | |
145 | u16 idetm_data; | |
146 | ||
147 | static const /* ISP RTC */ | |
148 | u8 timings[][2] = { { 0, 0 }, | |
149 | { 0, 0 }, | |
150 | { 1, 0 }, | |
151 | { 2, 1 }, | |
152 | { 2, 3 }, }; | |
153 | ||
154 | /* | |
155 | * MWDMA is driven by the PIO timings. We must also enable | |
156 | * IORDY unconditionally along with TIME1. PPE has already | |
157 | * been set when the PIO timing was set. | |
158 | */ | |
159 | ||
160 | unsigned int mwdma = adev->dma_mode - XFER_MW_DMA_0; | |
161 | unsigned int control; | |
162 | const unsigned int needed_pio[3] = { | |
163 | XFER_PIO_0, XFER_PIO_3, XFER_PIO_4 | |
164 | }; | |
165 | int pio = needed_pio[mwdma] - XFER_PIO_0; | |
166 | ||
167 | pci_read_config_word(dev, idetm_port, &idetm_data); | |
168 | ||
169 | control = 3; /* IORDY|TIME0 */ | |
170 | /* Intel specifies that the PPE functionality is for disk only */ | |
171 | if (adev->class == ATA_DEV_ATA) | |
172 | control |= 4; /* PPE enable */ | |
173 | ||
174 | /* If the drive MWDMA is faster than it can do PIO then | |
175 | we must force PIO into PIO0 */ | |
176 | ||
177 | if (adev->pio_mode < needed_pio[mwdma]) | |
178 | /* Enable DMA timing only */ | |
179 | control |= 8; /* PIO cycles in PIO0 */ | |
180 | ||
181 | /* Mask out the relevant control and timing bits we will load. Also | |
182 | clear the other drive TIME register as a precaution */ | |
183 | if (adev->devno == 0) { | |
184 | idetm_data &= 0xCCE0; | |
185 | idetm_data |= control; | |
186 | } else { | |
187 | idetm_data &= 0xCC0E; | |
188 | idetm_data |= (control << 4); | |
189 | } | |
190 | idetm_data |= (timings[pio][0] << 12) | (timings[pio][1] << 8); | |
191 | pci_write_config_word(dev, idetm_port, idetm_data); | |
192 | ||
193 | /* Track which port is configured */ | |
194 | ap->private_data = adev; | |
195 | } | |
196 | ||
197 | /** | |
198 | * oldpiix_qc_issue_prot - command issue | |
199 | * @qc: command pending | |
200 | * | |
201 | * Called when the libata layer is about to issue a command. We wrap | |
202 | * this interface so that we can load the correct ATA timings if | |
3a4fa0a2 | 203 | * necessary. Our logic also clears TIME0/TIME1 for the other device so |
669a5db4 JG |
204 | * that, even if we get this wrong, cycles to the other device will |
205 | * be made PIO0. | |
206 | */ | |
207 | ||
208 | static unsigned int oldpiix_qc_issue_prot(struct ata_queued_cmd *qc) | |
209 | { | |
210 | struct ata_port *ap = qc->ap; | |
211 | struct ata_device *adev = qc->dev; | |
212 | ||
213 | if (adev != ap->private_data) { | |
b7939b14 | 214 | oldpiix_set_piomode(ap, adev); |
669a5db4 JG |
215 | if (adev->dma_mode) |
216 | oldpiix_set_dmamode(ap, adev); | |
669a5db4 JG |
217 | } |
218 | return ata_qc_issue_prot(qc); | |
219 | } | |
220 | ||
221 | ||
222 | static struct scsi_host_template oldpiix_sht = { | |
68d1d07b | 223 | ATA_BMDMA_SHT(DRV_NAME), |
669a5db4 JG |
224 | }; |
225 | ||
029cfd6b TH |
226 | static struct ata_port_operations oldpiix_pata_ops = { |
227 | .inherits = &ata_bmdma_port_ops, | |
228 | .qc_issue = oldpiix_qc_issue_prot, | |
229 | .cable_detect = ata_cable_40wire, | |
669a5db4 JG |
230 | .set_piomode = oldpiix_set_piomode, |
231 | .set_dmamode = oldpiix_set_dmamode, | |
669a5db4 | 232 | .error_handler = oldpiix_pata_error_handler, |
669a5db4 JG |
233 | }; |
234 | ||
235 | ||
236 | /** | |
237 | * oldpiix_init_one - Register PIIX ATA PCI device with kernel services | |
238 | * @pdev: PCI device to register | |
239 | * @ent: Entry in oldpiix_pci_tbl matching with @pdev | |
240 | * | |
241 | * Called from kernel PCI layer. We probe for combined mode (sigh), | |
242 | * and then hand over control to libata, for it to do the rest. | |
243 | * | |
244 | * LOCKING: | |
245 | * Inherited from PCI layer (may sleep). | |
246 | * | |
247 | * RETURNS: | |
248 | * Zero on success, or -ERRNO value. | |
249 | */ | |
250 | ||
251 | static int oldpiix_init_one (struct pci_dev *pdev, const struct pci_device_id *ent) | |
252 | { | |
253 | static int printed_version; | |
1626aeb8 | 254 | static const struct ata_port_info info = { |
1d2808fd | 255 | .flags = ATA_FLAG_SLAVE_POSS, |
669a5db4 JG |
256 | .pio_mask = 0x1f, /* pio0-4 */ |
257 | .mwdma_mask = 0x07, /* mwdma1-2 */ | |
258 | .port_ops = &oldpiix_pata_ops, | |
259 | }; | |
1626aeb8 | 260 | const struct ata_port_info *ppi[] = { &info, NULL }; |
669a5db4 JG |
261 | |
262 | if (!printed_version++) | |
263 | dev_printk(KERN_DEBUG, &pdev->dev, | |
264 | "version " DRV_VERSION "\n"); | |
265 | ||
887125e3 | 266 | return ata_pci_init_one(pdev, ppi, &oldpiix_sht, NULL); |
669a5db4 JG |
267 | } |
268 | ||
269 | static const struct pci_device_id oldpiix_pci_tbl[] = { | |
2d2744fc JG |
270 | { PCI_VDEVICE(INTEL, 0x1230), }, |
271 | ||
669a5db4 JG |
272 | { } /* terminate list */ |
273 | }; | |
274 | ||
275 | static struct pci_driver oldpiix_pci_driver = { | |
276 | .name = DRV_NAME, | |
277 | .id_table = oldpiix_pci_tbl, | |
278 | .probe = oldpiix_init_one, | |
279 | .remove = ata_pci_remove_one, | |
438ac6d5 | 280 | #ifdef CONFIG_PM |
30ced0f0 A |
281 | .suspend = ata_pci_device_suspend, |
282 | .resume = ata_pci_device_resume, | |
438ac6d5 | 283 | #endif |
669a5db4 JG |
284 | }; |
285 | ||
286 | static int __init oldpiix_init(void) | |
287 | { | |
288 | return pci_register_driver(&oldpiix_pci_driver); | |
289 | } | |
290 | ||
291 | static void __exit oldpiix_exit(void) | |
292 | { | |
293 | pci_unregister_driver(&oldpiix_pci_driver); | |
294 | } | |
295 | ||
669a5db4 JG |
296 | module_init(oldpiix_init); |
297 | module_exit(oldpiix_exit); | |
298 | ||
299 | MODULE_AUTHOR("Alan Cox"); | |
300 | MODULE_DESCRIPTION("SCSI low-level driver for early PIIX series controllers"); | |
301 | MODULE_LICENSE("GPL"); | |
302 | MODULE_DEVICE_TABLE(pci, oldpiix_pci_tbl); | |
303 | MODULE_VERSION(DRV_VERSION); | |
304 |