Commit | Line | Data |
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3c929c6f DD |
1 | /* |
2 | * Driver for the Octeon bootbus compact flash. | |
3 | * | |
4 | * This file is subject to the terms and conditions of the GNU General Public | |
5 | * License. See the file "COPYING" in the main directory of this archive | |
6 | * for more details. | |
7 | * | |
43f01da0 | 8 | * Copyright (C) 2005 - 2012 Cavium Inc. |
3c929c6f DD |
9 | * Copyright (C) 2008 Wind River Systems |
10 | */ | |
11 | ||
12 | #include <linux/kernel.h> | |
13 | #include <linux/module.h> | |
14 | #include <linux/libata.h> | |
43f01da0 | 15 | #include <linux/hrtimer.h> |
5a0e3ad6 | 16 | #include <linux/slab.h> |
43f01da0 DD |
17 | #include <linux/irq.h> |
18 | #include <linux/of.h> | |
19 | #include <linux/of_platform.h> | |
3c929c6f | 20 | #include <linux/platform_device.h> |
3c929c6f | 21 | #include <scsi/scsi_host.h> |
c206a389 | 22 | #include <trace/events/libata.h> |
1007c4bc | 23 | #include <asm/byteorder.h> |
3c929c6f DD |
24 | #include <asm/octeon/octeon.h> |
25 | ||
26 | /* | |
27 | * The Octeon bootbus compact flash interface is connected in at least | |
28 | * 3 different configurations on various evaluation boards: | |
29 | * | |
30 | * -- 8 bits no irq, no DMA | |
31 | * -- 16 bits no irq, no DMA | |
32 | * -- 16 bits True IDE mode with DMA, but no irq. | |
33 | * | |
34 | * In the last case the DMA engine can generate an interrupt when the | |
35 | * transfer is complete. For the first two cases only PIO is supported. | |
36 | * | |
37 | */ | |
38 | ||
39 | #define DRV_NAME "pata_octeon_cf" | |
43f01da0 DD |
40 | #define DRV_VERSION "2.2" |
41 | ||
42 | /* Poll interval in nS. */ | |
43 | #define OCTEON_CF_BUSY_POLL_INTERVAL 500000 | |
3c929c6f | 44 | |
43f01da0 DD |
45 | #define DMA_CFG 0 |
46 | #define DMA_TIM 0x20 | |
47 | #define DMA_INT 0x38 | |
48 | #define DMA_INT_EN 0x50 | |
3c929c6f DD |
49 | |
50 | struct octeon_cf_port { | |
43f01da0 | 51 | struct hrtimer delayed_finish; |
3c929c6f DD |
52 | struct ata_port *ap; |
53 | int dma_finished; | |
43f01da0 DD |
54 | void *c0; |
55 | unsigned int cs0; | |
56 | unsigned int cs1; | |
57 | bool is_true_ide; | |
58 | u64 dma_base; | |
3c929c6f DD |
59 | }; |
60 | ||
61 | static struct scsi_host_template octeon_cf_sht = { | |
62 | ATA_PIO_SHT(DRV_NAME), | |
63 | }; | |
64 | ||
43f01da0 DD |
65 | static int enable_dma; |
66 | module_param(enable_dma, int, 0444); | |
67 | MODULE_PARM_DESC(enable_dma, | |
68 | "Enable use of DMA on interfaces that support it (0=no dma [default], 1=use dma)"); | |
69 | ||
3c929c6f DD |
70 | /** |
71 | * Convert nanosecond based time to setting used in the | |
72 | * boot bus timing register, based on timing multiple | |
73 | */ | |
74 | static unsigned int ns_to_tim_reg(unsigned int tim_mult, unsigned int nsecs) | |
75 | { | |
3c929c6f DD |
76 | /* |
77 | * Compute # of eclock periods to get desired duration in | |
78 | * nanoseconds. | |
79 | */ | |
9c2fd3fb | 80 | return DIV_ROUND_UP(nsecs * (octeon_get_io_clock_rate() / 1000000), |
3c929c6f | 81 | 1000 * tim_mult); |
3c929c6f DD |
82 | } |
83 | ||
43f01da0 | 84 | static void octeon_cf_set_boot_reg_cfg(int cs, unsigned int multiplier) |
3c929c6f DD |
85 | { |
86 | union cvmx_mio_boot_reg_cfgx reg_cfg; | |
43f01da0 DD |
87 | unsigned int tim_mult; |
88 | ||
89 | switch (multiplier) { | |
90 | case 8: | |
91 | tim_mult = 3; | |
92 | break; | |
93 | case 4: | |
94 | tim_mult = 0; | |
95 | break; | |
96 | case 2: | |
97 | tim_mult = 2; | |
98 | break; | |
99 | default: | |
100 | tim_mult = 1; | |
101 | break; | |
102 | } | |
103 | ||
3c929c6f DD |
104 | reg_cfg.u64 = cvmx_read_csr(CVMX_MIO_BOOT_REG_CFGX(cs)); |
105 | reg_cfg.s.dmack = 0; /* Don't assert DMACK on access */ | |
43f01da0 | 106 | reg_cfg.s.tim_mult = tim_mult; /* Timing mutiplier */ |
3c929c6f DD |
107 | reg_cfg.s.rd_dly = 0; /* Sample on falling edge of BOOT_OE */ |
108 | reg_cfg.s.sam = 0; /* Don't combine write and output enable */ | |
109 | reg_cfg.s.we_ext = 0; /* No write enable extension */ | |
110 | reg_cfg.s.oe_ext = 0; /* No read enable extension */ | |
111 | reg_cfg.s.en = 1; /* Enable this region */ | |
112 | reg_cfg.s.orbit = 0; /* Don't combine with previous region */ | |
113 | reg_cfg.s.ale = 0; /* Don't do address multiplexing */ | |
114 | cvmx_write_csr(CVMX_MIO_BOOT_REG_CFGX(cs), reg_cfg.u64); | |
115 | } | |
116 | ||
117 | /** | |
118 | * Called after libata determines the needed PIO mode. This | |
119 | * function programs the Octeon bootbus regions to support the | |
120 | * timing requirements of the PIO mode. | |
121 | * | |
122 | * @ap: ATA port information | |
123 | * @dev: ATA device | |
124 | */ | |
125 | static void octeon_cf_set_piomode(struct ata_port *ap, struct ata_device *dev) | |
126 | { | |
43f01da0 | 127 | struct octeon_cf_port *cf_port = ap->private_data; |
3c929c6f | 128 | union cvmx_mio_boot_reg_timx reg_tim; |
3c929c6f DD |
129 | int T; |
130 | struct ata_timing timing; | |
131 | ||
43f01da0 | 132 | unsigned int div; |
3c929c6f DD |
133 | int use_iordy; |
134 | int trh; | |
135 | int pause; | |
136 | /* These names are timing parameters from the ATA spec */ | |
3c929c6f | 137 | int t2; |
3c929c6f | 138 | |
43f01da0 DD |
139 | /* |
140 | * A divisor value of four will overflow the timing fields at | |
141 | * clock rates greater than 800MHz | |
142 | */ | |
143 | if (octeon_get_io_clock_rate() <= 800000000) | |
144 | div = 4; | |
145 | else | |
146 | div = 8; | |
147 | T = (int)((1000000000000LL * div) / octeon_get_io_clock_rate()); | |
3c929c6f | 148 | |
02d9d3cb | 149 | BUG_ON(ata_timing_compute(dev, dev->pio_mode, &timing, T, T)); |
3c929c6f | 150 | |
3c929c6f DD |
151 | t2 = timing.active; |
152 | if (t2) | |
153 | t2--; | |
3c929c6f | 154 | |
43f01da0 | 155 | trh = ns_to_tim_reg(div, 20); |
3c929c6f DD |
156 | if (trh) |
157 | trh--; | |
158 | ||
43f01da0 DD |
159 | pause = (int)timing.cycle - (int)timing.active - |
160 | (int)timing.setup - trh; | |
161 | if (pause < 0) | |
162 | pause = 0; | |
3c929c6f DD |
163 | if (pause) |
164 | pause--; | |
165 | ||
43f01da0 DD |
166 | octeon_cf_set_boot_reg_cfg(cf_port->cs0, div); |
167 | if (cf_port->is_true_ide) | |
3c929c6f | 168 | /* True IDE mode, program both chip selects. */ |
43f01da0 | 169 | octeon_cf_set_boot_reg_cfg(cf_port->cs1, div); |
3c929c6f DD |
170 | |
171 | ||
172 | use_iordy = ata_pio_need_iordy(dev); | |
173 | ||
43f01da0 | 174 | reg_tim.u64 = cvmx_read_csr(CVMX_MIO_BOOT_REG_TIMX(cf_port->cs0)); |
3c929c6f DD |
175 | /* Disable page mode */ |
176 | reg_tim.s.pagem = 0; | |
177 | /* Enable dynamic timing */ | |
178 | reg_tim.s.waitm = use_iordy; | |
179 | /* Pages are disabled */ | |
180 | reg_tim.s.pages = 0; | |
181 | /* We don't use multiplexed address mode */ | |
182 | reg_tim.s.ale = 0; | |
183 | /* Not used */ | |
184 | reg_tim.s.page = 0; | |
185 | /* Time after IORDY to coninue to assert the data */ | |
186 | reg_tim.s.wait = 0; | |
187 | /* Time to wait to complete the cycle. */ | |
188 | reg_tim.s.pause = pause; | |
189 | /* How long to hold after a write to de-assert CE. */ | |
190 | reg_tim.s.wr_hld = trh; | |
191 | /* How long to wait after a read to de-assert CE. */ | |
192 | reg_tim.s.rd_hld = trh; | |
193 | /* How long write enable is asserted */ | |
194 | reg_tim.s.we = t2; | |
195 | /* How long read enable is asserted */ | |
196 | reg_tim.s.oe = t2; | |
197 | /* Time after CE that read/write starts */ | |
43f01da0 | 198 | reg_tim.s.ce = ns_to_tim_reg(div, 5); |
3c929c6f DD |
199 | /* Time before CE that address is valid */ |
200 | reg_tim.s.adr = 0; | |
201 | ||
202 | /* Program the bootbus region timing for the data port chip select. */ | |
43f01da0 DD |
203 | cvmx_write_csr(CVMX_MIO_BOOT_REG_TIMX(cf_port->cs0), reg_tim.u64); |
204 | if (cf_port->is_true_ide) | |
3c929c6f | 205 | /* True IDE mode, program both chip selects. */ |
43f01da0 DD |
206 | cvmx_write_csr(CVMX_MIO_BOOT_REG_TIMX(cf_port->cs1), |
207 | reg_tim.u64); | |
3c929c6f DD |
208 | } |
209 | ||
210 | static void octeon_cf_set_dmamode(struct ata_port *ap, struct ata_device *dev) | |
211 | { | |
43f01da0 DD |
212 | struct octeon_cf_port *cf_port = ap->private_data; |
213 | union cvmx_mio_boot_pin_defs pin_defs; | |
3c929c6f DD |
214 | union cvmx_mio_boot_dma_timx dma_tim; |
215 | unsigned int oe_a; | |
216 | unsigned int oe_n; | |
217 | unsigned int dma_ackh; | |
218 | unsigned int dma_arq; | |
219 | unsigned int pause; | |
220 | unsigned int T0, Tkr, Td; | |
221 | unsigned int tim_mult; | |
43f01da0 | 222 | int c; |
3c929c6f DD |
223 | |
224 | const struct ata_timing *timing; | |
225 | ||
226 | timing = ata_timing_find_mode(dev->dma_mode); | |
227 | T0 = timing->cycle; | |
228 | Td = timing->active; | |
229 | Tkr = timing->recover; | |
230 | dma_ackh = timing->dmack_hold; | |
231 | ||
232 | dma_tim.u64 = 0; | |
233 | /* dma_tim.s.tim_mult = 0 --> 4x */ | |
234 | tim_mult = 4; | |
235 | ||
236 | /* not spec'ed, value in eclocks, not affected by tim_mult */ | |
237 | dma_arq = 8; | |
238 | pause = 25 - dma_arq * 1000 / | |
43f01da0 | 239 | (octeon_get_io_clock_rate() / 1000000); /* Tz */ |
3c929c6f DD |
240 | |
241 | oe_a = Td; | |
242 | /* Tkr from cf spec, lengthened to meet T0 */ | |
243 | oe_n = max(T0 - oe_a, Tkr); | |
244 | ||
43f01da0 DD |
245 | pin_defs.u64 = cvmx_read_csr(CVMX_MIO_BOOT_PIN_DEFS); |
246 | ||
247 | /* DMA channel number. */ | |
248 | c = (cf_port->dma_base & 8) >> 3; | |
249 | ||
250 | /* Invert the polarity if the default is 0*/ | |
251 | dma_tim.s.dmack_pi = (pin_defs.u64 & (1ull << (11 + c))) ? 0 : 1; | |
3c929c6f DD |
252 | |
253 | dma_tim.s.oe_n = ns_to_tim_reg(tim_mult, oe_n); | |
254 | dma_tim.s.oe_a = ns_to_tim_reg(tim_mult, oe_a); | |
255 | ||
256 | /* | |
257 | * This is tI, C.F. spec. says 0, but Sony CF card requires | |
258 | * more, we use 20 nS. | |
259 | */ | |
87c8b22b | 260 | dma_tim.s.dmack_s = ns_to_tim_reg(tim_mult, 20); |
3c929c6f DD |
261 | dma_tim.s.dmack_h = ns_to_tim_reg(tim_mult, dma_ackh); |
262 | ||
263 | dma_tim.s.dmarq = dma_arq; | |
264 | dma_tim.s.pause = ns_to_tim_reg(tim_mult, pause); | |
265 | ||
266 | dma_tim.s.rd_dly = 0; /* Sample right on edge */ | |
267 | ||
268 | /* writes only */ | |
269 | dma_tim.s.we_n = ns_to_tim_reg(tim_mult, oe_n); | |
270 | dma_tim.s.we_a = ns_to_tim_reg(tim_mult, oe_a); | |
271 | ||
cb3f48fc | 272 | ata_dev_dbg(dev, "ns to ticks (mult %d) of %d is: %d\n", tim_mult, 60, |
3c929c6f | 273 | ns_to_tim_reg(tim_mult, 60)); |
cb3f48fc | 274 | ata_dev_dbg(dev, "oe_n: %d, oe_a: %d, dmack_s: %d, dmack_h: %d, dmarq: %d, pause: %d\n", |
3c929c6f DD |
275 | dma_tim.s.oe_n, dma_tim.s.oe_a, dma_tim.s.dmack_s, |
276 | dma_tim.s.dmack_h, dma_tim.s.dmarq, dma_tim.s.pause); | |
277 | ||
43f01da0 | 278 | cvmx_write_csr(cf_port->dma_base + DMA_TIM, dma_tim.u64); |
3c929c6f DD |
279 | } |
280 | ||
281 | /** | |
282 | * Handle an 8 bit I/O request. | |
283 | * | |
989e0aac | 284 | * @qc: Queued command |
3c929c6f DD |
285 | * @buffer: Data buffer |
286 | * @buflen: Length of the buffer. | |
287 | * @rw: True to write. | |
288 | */ | |
989e0aac | 289 | static unsigned int octeon_cf_data_xfer8(struct ata_queued_cmd *qc, |
3c929c6f DD |
290 | unsigned char *buffer, |
291 | unsigned int buflen, | |
292 | int rw) | |
293 | { | |
989e0aac | 294 | struct ata_port *ap = qc->dev->link->ap; |
3c929c6f DD |
295 | void __iomem *data_addr = ap->ioaddr.data_addr; |
296 | unsigned long words; | |
297 | int count; | |
298 | ||
299 | words = buflen; | |
300 | if (rw) { | |
301 | count = 16; | |
302 | while (words--) { | |
303 | iowrite8(*buffer, data_addr); | |
304 | buffer++; | |
305 | /* | |
306 | * Every 16 writes do a read so the bootbus | |
307 | * FIFO doesn't fill up. | |
308 | */ | |
309 | if (--count == 0) { | |
310 | ioread8(ap->ioaddr.altstatus_addr); | |
311 | count = 16; | |
312 | } | |
313 | } | |
314 | } else { | |
315 | ioread8_rep(data_addr, buffer, words); | |
316 | } | |
317 | return buflen; | |
318 | } | |
319 | ||
320 | /** | |
321 | * Handle a 16 bit I/O request. | |
322 | * | |
989e0aac | 323 | * @qc: Queued command |
3c929c6f DD |
324 | * @buffer: Data buffer |
325 | * @buflen: Length of the buffer. | |
326 | * @rw: True to write. | |
327 | */ | |
989e0aac | 328 | static unsigned int octeon_cf_data_xfer16(struct ata_queued_cmd *qc, |
3c929c6f DD |
329 | unsigned char *buffer, |
330 | unsigned int buflen, | |
331 | int rw) | |
332 | { | |
989e0aac | 333 | struct ata_port *ap = qc->dev->link->ap; |
3c929c6f DD |
334 | void __iomem *data_addr = ap->ioaddr.data_addr; |
335 | unsigned long words; | |
336 | int count; | |
337 | ||
338 | words = buflen / 2; | |
339 | if (rw) { | |
340 | count = 16; | |
341 | while (words--) { | |
342 | iowrite16(*(uint16_t *)buffer, data_addr); | |
343 | buffer += sizeof(uint16_t); | |
344 | /* | |
345 | * Every 16 writes do a read so the bootbus | |
346 | * FIFO doesn't fill up. | |
347 | */ | |
348 | if (--count == 0) { | |
349 | ioread8(ap->ioaddr.altstatus_addr); | |
350 | count = 16; | |
351 | } | |
352 | } | |
353 | } else { | |
354 | while (words--) { | |
355 | *(uint16_t *)buffer = ioread16(data_addr); | |
356 | buffer += sizeof(uint16_t); | |
357 | } | |
358 | } | |
359 | /* Transfer trailing 1 byte, if any. */ | |
360 | if (unlikely(buflen & 0x01)) { | |
361 | __le16 align_buf[1] = { 0 }; | |
362 | ||
363 | if (rw == READ) { | |
364 | align_buf[0] = cpu_to_le16(ioread16(data_addr)); | |
365 | memcpy(buffer, align_buf, 1); | |
366 | } else { | |
367 | memcpy(align_buf, buffer, 1); | |
368 | iowrite16(le16_to_cpu(align_buf[0]), data_addr); | |
369 | } | |
370 | words++; | |
371 | } | |
372 | return buflen; | |
373 | } | |
374 | ||
375 | /** | |
376 | * Read the taskfile for 16bit non-True IDE only. | |
377 | */ | |
378 | static void octeon_cf_tf_read16(struct ata_port *ap, struct ata_taskfile *tf) | |
379 | { | |
380 | u16 blob; | |
381 | /* The base of the registers is at ioaddr.data_addr. */ | |
382 | void __iomem *base = ap->ioaddr.data_addr; | |
383 | ||
384 | blob = __raw_readw(base + 0xc); | |
385 | tf->feature = blob >> 8; | |
386 | ||
387 | blob = __raw_readw(base + 2); | |
388 | tf->nsect = blob & 0xff; | |
389 | tf->lbal = blob >> 8; | |
390 | ||
391 | blob = __raw_readw(base + 4); | |
392 | tf->lbam = blob & 0xff; | |
393 | tf->lbah = blob >> 8; | |
394 | ||
395 | blob = __raw_readw(base + 6); | |
396 | tf->device = blob & 0xff; | |
397 | tf->command = blob >> 8; | |
398 | ||
399 | if (tf->flags & ATA_TFLAG_LBA48) { | |
400 | if (likely(ap->ioaddr.ctl_addr)) { | |
401 | iowrite8(tf->ctl | ATA_HOB, ap->ioaddr.ctl_addr); | |
402 | ||
403 | blob = __raw_readw(base + 0xc); | |
404 | tf->hob_feature = blob >> 8; | |
405 | ||
406 | blob = __raw_readw(base + 2); | |
407 | tf->hob_nsect = blob & 0xff; | |
408 | tf->hob_lbal = blob >> 8; | |
409 | ||
410 | blob = __raw_readw(base + 4); | |
411 | tf->hob_lbam = blob & 0xff; | |
412 | tf->hob_lbah = blob >> 8; | |
413 | ||
414 | iowrite8(tf->ctl, ap->ioaddr.ctl_addr); | |
415 | ap->last_ctl = tf->ctl; | |
416 | } else { | |
417 | WARN_ON(1); | |
418 | } | |
419 | } | |
420 | } | |
421 | ||
422 | static u8 octeon_cf_check_status16(struct ata_port *ap) | |
423 | { | |
424 | u16 blob; | |
425 | void __iomem *base = ap->ioaddr.data_addr; | |
426 | ||
427 | blob = __raw_readw(base + 6); | |
428 | return blob >> 8; | |
429 | } | |
430 | ||
431 | static int octeon_cf_softreset16(struct ata_link *link, unsigned int *classes, | |
432 | unsigned long deadline) | |
433 | { | |
434 | struct ata_port *ap = link->ap; | |
435 | void __iomem *base = ap->ioaddr.data_addr; | |
436 | int rc; | |
437 | u8 err; | |
438 | ||
3c929c6f DD |
439 | __raw_writew(ap->ctl, base + 0xe); |
440 | udelay(20); | |
441 | __raw_writew(ap->ctl | ATA_SRST, base + 0xe); | |
442 | udelay(20); | |
443 | __raw_writew(ap->ctl, base + 0xe); | |
444 | ||
445 | rc = ata_sff_wait_after_reset(link, 1, deadline); | |
446 | if (rc) { | |
a9a79dfe | 447 | ata_link_err(link, "SRST failed (errno=%d)\n", rc); |
3c929c6f DD |
448 | return rc; |
449 | } | |
450 | ||
451 | /* determine by signature whether we have ATA or ATAPI devices */ | |
452 | classes[0] = ata_sff_dev_classify(&link->device[0], 1, &err); | |
3c929c6f DD |
453 | return 0; |
454 | } | |
455 | ||
456 | /** | |
457 | * Load the taskfile for 16bit non-True IDE only. The device_addr is | |
458 | * not loaded, we do this as part of octeon_cf_exec_command16. | |
459 | */ | |
460 | static void octeon_cf_tf_load16(struct ata_port *ap, | |
461 | const struct ata_taskfile *tf) | |
462 | { | |
463 | unsigned int is_addr = tf->flags & ATA_TFLAG_ISADDR; | |
464 | /* The base of the registers is at ioaddr.data_addr. */ | |
465 | void __iomem *base = ap->ioaddr.data_addr; | |
466 | ||
467 | if (tf->ctl != ap->last_ctl) { | |
468 | iowrite8(tf->ctl, ap->ioaddr.ctl_addr); | |
469 | ap->last_ctl = tf->ctl; | |
470 | ata_wait_idle(ap); | |
471 | } | |
472 | if (is_addr && (tf->flags & ATA_TFLAG_LBA48)) { | |
473 | __raw_writew(tf->hob_feature << 8, base + 0xc); | |
474 | __raw_writew(tf->hob_nsect | tf->hob_lbal << 8, base + 2); | |
475 | __raw_writew(tf->hob_lbam | tf->hob_lbah << 8, base + 4); | |
3c929c6f DD |
476 | } |
477 | if (is_addr) { | |
478 | __raw_writew(tf->feature << 8, base + 0xc); | |
479 | __raw_writew(tf->nsect | tf->lbal << 8, base + 2); | |
480 | __raw_writew(tf->lbam | tf->lbah << 8, base + 4); | |
3c929c6f DD |
481 | } |
482 | ata_wait_idle(ap); | |
483 | } | |
484 | ||
485 | ||
486 | static void octeon_cf_dev_select(struct ata_port *ap, unsigned int device) | |
487 | { | |
488 | /* There is only one device, do nothing. */ | |
489 | return; | |
490 | } | |
491 | ||
492 | /* | |
493 | * Issue ATA command to host controller. The device_addr is also sent | |
494 | * as it must be written in a combined write with the command. | |
495 | */ | |
496 | static void octeon_cf_exec_command16(struct ata_port *ap, | |
497 | const struct ata_taskfile *tf) | |
498 | { | |
499 | /* The base of the registers is at ioaddr.data_addr. */ | |
500 | void __iomem *base = ap->ioaddr.data_addr; | |
c206a389 | 501 | u16 blob = 0; |
3c929c6f | 502 | |
c206a389 | 503 | if (tf->flags & ATA_TFLAG_DEVICE) |
3c929c6f | 504 | blob = tf->device; |
3c929c6f | 505 | |
3c929c6f DD |
506 | blob |= (tf->command << 8); |
507 | __raw_writew(blob, base + 6); | |
508 | ||
3c929c6f DD |
509 | ata_wait_idle(ap); |
510 | } | |
511 | ||
43f01da0 | 512 | static void octeon_cf_ata_port_noaction(struct ata_port *ap) |
3c929c6f | 513 | { |
3c929c6f DD |
514 | } |
515 | ||
3c929c6f DD |
516 | static void octeon_cf_dma_setup(struct ata_queued_cmd *qc) |
517 | { | |
518 | struct ata_port *ap = qc->ap; | |
519 | struct octeon_cf_port *cf_port; | |
520 | ||
2d1299aa | 521 | cf_port = ap->private_data; |
3c929c6f DD |
522 | /* issue r/w command */ |
523 | qc->cursg = qc->sg; | |
524 | cf_port->dma_finished = 0; | |
525 | ap->ops->sff_exec_command(ap, &qc->tf); | |
3c929c6f DD |
526 | } |
527 | ||
528 | /** | |
529 | * Start a DMA transfer that was already setup | |
530 | * | |
531 | * @qc: Information about the DMA | |
532 | */ | |
533 | static void octeon_cf_dma_start(struct ata_queued_cmd *qc) | |
534 | { | |
43f01da0 | 535 | struct octeon_cf_port *cf_port = qc->ap->private_data; |
3c929c6f DD |
536 | union cvmx_mio_boot_dma_cfgx mio_boot_dma_cfg; |
537 | union cvmx_mio_boot_dma_intx mio_boot_dma_int; | |
538 | struct scatterlist *sg; | |
539 | ||
3c929c6f DD |
540 | /* Get the scatter list entry we need to DMA into */ |
541 | sg = qc->cursg; | |
542 | BUG_ON(!sg); | |
543 | ||
544 | /* | |
545 | * Clear the DMA complete status. | |
546 | */ | |
547 | mio_boot_dma_int.u64 = 0; | |
548 | mio_boot_dma_int.s.done = 1; | |
43f01da0 | 549 | cvmx_write_csr(cf_port->dma_base + DMA_INT, mio_boot_dma_int.u64); |
3c929c6f DD |
550 | |
551 | /* Enable the interrupt. */ | |
43f01da0 | 552 | cvmx_write_csr(cf_port->dma_base + DMA_INT_EN, mio_boot_dma_int.u64); |
3c929c6f DD |
553 | |
554 | /* Set the direction of the DMA */ | |
555 | mio_boot_dma_cfg.u64 = 0; | |
1007c4bc DD |
556 | #ifdef __LITTLE_ENDIAN |
557 | mio_boot_dma_cfg.s.endian = 1; | |
558 | #endif | |
3c929c6f DD |
559 | mio_boot_dma_cfg.s.en = 1; |
560 | mio_boot_dma_cfg.s.rw = ((qc->tf.flags & ATA_TFLAG_WRITE) != 0); | |
561 | ||
562 | /* | |
563 | * Don't stop the DMA if the device deasserts DMARQ. Many | |
564 | * compact flashes deassert DMARQ for a short time between | |
565 | * sectors. Instead of stopping and restarting the DMA, we'll | |
566 | * let the hardware do it. If the DMA is really stopped early | |
567 | * due to an error condition, a later timeout will force us to | |
568 | * stop. | |
569 | */ | |
570 | mio_boot_dma_cfg.s.clr = 0; | |
571 | ||
572 | /* Size is specified in 16bit words and minus one notation */ | |
573 | mio_boot_dma_cfg.s.size = sg_dma_len(sg) / 2 - 1; | |
574 | ||
575 | /* We need to swap the high and low bytes of every 16 bits */ | |
576 | mio_boot_dma_cfg.s.swap8 = 1; | |
577 | ||
578 | mio_boot_dma_cfg.s.adr = sg_dma_address(sg); | |
579 | ||
43f01da0 | 580 | cvmx_write_csr(cf_port->dma_base + DMA_CFG, mio_boot_dma_cfg.u64); |
3c929c6f DD |
581 | } |
582 | ||
583 | /** | |
584 | * | |
585 | * LOCKING: | |
586 | * spin_lock_irqsave(host lock) | |
587 | * | |
588 | */ | |
589 | static unsigned int octeon_cf_dma_finished(struct ata_port *ap, | |
590 | struct ata_queued_cmd *qc) | |
591 | { | |
592 | struct ata_eh_info *ehi = &ap->link.eh_info; | |
43f01da0 | 593 | struct octeon_cf_port *cf_port = ap->private_data; |
3c929c6f DD |
594 | union cvmx_mio_boot_dma_cfgx dma_cfg; |
595 | union cvmx_mio_boot_dma_intx dma_int; | |
3c929c6f DD |
596 | u8 status; |
597 | ||
b875b39e | 598 | trace_ata_bmdma_stop(ap, &qc->tf, qc->tag); |
3c929c6f DD |
599 | |
600 | if (ap->hsm_task_state != HSM_ST_LAST) | |
601 | return 0; | |
602 | ||
43f01da0 | 603 | dma_cfg.u64 = cvmx_read_csr(cf_port->dma_base + DMA_CFG); |
3c929c6f DD |
604 | if (dma_cfg.s.size != 0xfffff) { |
605 | /* Error, the transfer was not complete. */ | |
606 | qc->err_mask |= AC_ERR_HOST_BUS; | |
607 | ap->hsm_task_state = HSM_ST_ERR; | |
608 | } | |
609 | ||
610 | /* Stop and clear the dma engine. */ | |
611 | dma_cfg.u64 = 0; | |
612 | dma_cfg.s.size = -1; | |
43f01da0 | 613 | cvmx_write_csr(cf_port->dma_base + DMA_CFG, dma_cfg.u64); |
3c929c6f DD |
614 | |
615 | /* Disable the interrupt. */ | |
616 | dma_int.u64 = 0; | |
43f01da0 | 617 | cvmx_write_csr(cf_port->dma_base + DMA_INT_EN, dma_int.u64); |
3c929c6f DD |
618 | |
619 | /* Clear the DMA complete status */ | |
620 | dma_int.s.done = 1; | |
43f01da0 | 621 | cvmx_write_csr(cf_port->dma_base + DMA_INT, dma_int.u64); |
3c929c6f DD |
622 | |
623 | status = ap->ops->sff_check_status(ap); | |
624 | ||
625 | ata_sff_hsm_move(ap, qc, status, 0); | |
626 | ||
627 | if (unlikely(qc->err_mask) && (qc->tf.protocol == ATA_PROT_DMA)) | |
628 | ata_ehi_push_desc(ehi, "DMA stat 0x%x", status); | |
629 | ||
630 | return 1; | |
631 | } | |
632 | ||
633 | /* | |
634 | * Check if any queued commands have more DMAs, if so start the next | |
635 | * transfer, else do end of transfer handling. | |
636 | */ | |
637 | static irqreturn_t octeon_cf_interrupt(int irq, void *dev_instance) | |
638 | { | |
639 | struct ata_host *host = dev_instance; | |
640 | struct octeon_cf_port *cf_port; | |
641 | int i; | |
642 | unsigned int handled = 0; | |
643 | unsigned long flags; | |
644 | ||
645 | spin_lock_irqsave(&host->lock, flags); | |
646 | ||
3c929c6f DD |
647 | for (i = 0; i < host->n_ports; i++) { |
648 | u8 status; | |
649 | struct ata_port *ap; | |
650 | struct ata_queued_cmd *qc; | |
651 | union cvmx_mio_boot_dma_intx dma_int; | |
652 | union cvmx_mio_boot_dma_cfgx dma_cfg; | |
3c929c6f DD |
653 | |
654 | ap = host->ports[i]; | |
2d1299aa | 655 | cf_port = ap->private_data; |
43f01da0 DD |
656 | |
657 | dma_int.u64 = cvmx_read_csr(cf_port->dma_base + DMA_INT); | |
658 | dma_cfg.u64 = cvmx_read_csr(cf_port->dma_base + DMA_CFG); | |
3c929c6f DD |
659 | |
660 | qc = ata_qc_from_tag(ap, ap->link.active_tag); | |
661 | ||
43f01da0 DD |
662 | if (!qc || (qc->tf.flags & ATA_TFLAG_POLLING)) |
663 | continue; | |
664 | ||
665 | if (dma_int.s.done && !dma_cfg.s.en) { | |
666 | if (!sg_is_last(qc->cursg)) { | |
667 | qc->cursg = sg_next(qc->cursg); | |
3c929c6f | 668 | handled = 1; |
c206a389 | 669 | trace_ata_bmdma_start(ap, &qc->tf, qc->tag); |
43f01da0 DD |
670 | octeon_cf_dma_start(qc); |
671 | continue; | |
3c929c6f | 672 | } else { |
43f01da0 | 673 | cf_port->dma_finished = 1; |
3c929c6f DD |
674 | } |
675 | } | |
43f01da0 DD |
676 | if (!cf_port->dma_finished) |
677 | continue; | |
678 | status = ioread8(ap->ioaddr.altstatus_addr); | |
679 | if (status & (ATA_BUSY | ATA_DRQ)) { | |
680 | /* | |
681 | * We are busy, try to handle it later. This | |
682 | * is the DMA finished interrupt, and it could | |
683 | * take a little while for the card to be | |
684 | * ready for more commands. | |
685 | */ | |
686 | /* Clear DMA irq. */ | |
687 | dma_int.u64 = 0; | |
688 | dma_int.s.done = 1; | |
689 | cvmx_write_csr(cf_port->dma_base + DMA_INT, | |
690 | dma_int.u64); | |
691 | hrtimer_start_range_ns(&cf_port->delayed_finish, | |
692 | ns_to_ktime(OCTEON_CF_BUSY_POLL_INTERVAL), | |
693 | OCTEON_CF_BUSY_POLL_INTERVAL / 5, | |
694 | HRTIMER_MODE_REL); | |
695 | handled = 1; | |
696 | } else { | |
697 | handled |= octeon_cf_dma_finished(ap, qc); | |
698 | } | |
3c929c6f DD |
699 | } |
700 | spin_unlock_irqrestore(&host->lock, flags); | |
3c929c6f DD |
701 | return IRQ_RETVAL(handled); |
702 | } | |
703 | ||
43f01da0 | 704 | static enum hrtimer_restart octeon_cf_delayed_finish(struct hrtimer *hrt) |
3c929c6f | 705 | { |
43f01da0 | 706 | struct octeon_cf_port *cf_port = container_of(hrt, |
3c929c6f | 707 | struct octeon_cf_port, |
43f01da0 | 708 | delayed_finish); |
3c929c6f DD |
709 | struct ata_port *ap = cf_port->ap; |
710 | struct ata_host *host = ap->host; | |
711 | struct ata_queued_cmd *qc; | |
712 | unsigned long flags; | |
713 | u8 status; | |
43f01da0 | 714 | enum hrtimer_restart rv = HRTIMER_NORESTART; |
3c929c6f DD |
715 | |
716 | spin_lock_irqsave(&host->lock, flags); | |
717 | ||
718 | /* | |
719 | * If the port is not waiting for completion, it must have | |
720 | * handled it previously. The hsm_task_state is | |
721 | * protected by host->lock. | |
722 | */ | |
723 | if (ap->hsm_task_state != HSM_ST_LAST || !cf_port->dma_finished) | |
724 | goto out; | |
725 | ||
726 | status = ioread8(ap->ioaddr.altstatus_addr); | |
727 | if (status & (ATA_BUSY | ATA_DRQ)) { | |
728 | /* Still busy, try again. */ | |
43f01da0 DD |
729 | hrtimer_forward_now(hrt, |
730 | ns_to_ktime(OCTEON_CF_BUSY_POLL_INTERVAL)); | |
731 | rv = HRTIMER_RESTART; | |
3c929c6f DD |
732 | goto out; |
733 | } | |
734 | qc = ata_qc_from_tag(ap, ap->link.active_tag); | |
43f01da0 | 735 | if (qc && (!(qc->tf.flags & ATA_TFLAG_POLLING))) |
3c929c6f DD |
736 | octeon_cf_dma_finished(ap, qc); |
737 | out: | |
738 | spin_unlock_irqrestore(&host->lock, flags); | |
43f01da0 | 739 | return rv; |
3c929c6f DD |
740 | } |
741 | ||
742 | static void octeon_cf_dev_config(struct ata_device *dev) | |
743 | { | |
744 | /* | |
745 | * A maximum of 2^20 - 1 16 bit transfers are possible with | |
746 | * the bootbus DMA. So we need to throttle max_sectors to | |
747 | * (2^12 - 1 == 4095) to assure that this can never happen. | |
748 | */ | |
749 | dev->max_sectors = min(dev->max_sectors, 4095U); | |
750 | } | |
751 | ||
3c929c6f DD |
752 | /* |
753 | * We don't do ATAPI DMA so return 0. | |
754 | */ | |
755 | static int octeon_cf_check_atapi_dma(struct ata_queued_cmd *qc) | |
756 | { | |
757 | return 0; | |
758 | } | |
759 | ||
760 | static unsigned int octeon_cf_qc_issue(struct ata_queued_cmd *qc) | |
761 | { | |
762 | struct ata_port *ap = qc->ap; | |
763 | ||
764 | switch (qc->tf.protocol) { | |
765 | case ATA_PROT_DMA: | |
766 | WARN_ON(qc->tf.flags & ATA_TFLAG_POLLING); | |
767 | ||
c206a389 | 768 | trace_ata_tf_load(ap, &qc->tf); |
3c929c6f | 769 | ap->ops->sff_tf_load(ap, &qc->tf); /* load tf registers */ |
c206a389 | 770 | trace_ata_bmdma_setup(ap, &qc->tf, qc->tag); |
3c929c6f | 771 | octeon_cf_dma_setup(qc); /* set up dma */ |
c206a389 | 772 | trace_ata_bmdma_start(ap, &qc->tf, qc->tag); |
3c929c6f DD |
773 | octeon_cf_dma_start(qc); /* initiate dma */ |
774 | ap->hsm_task_state = HSM_ST_LAST; | |
775 | break; | |
776 | ||
777 | case ATAPI_PROT_DMA: | |
778 | dev_err(ap->dev, "Error, ATAPI not supported\n"); | |
779 | BUG(); | |
780 | ||
781 | default: | |
782 | return ata_sff_qc_issue(qc); | |
783 | } | |
784 | ||
785 | return 0; | |
786 | } | |
787 | ||
788 | static struct ata_port_operations octeon_cf_ops = { | |
789 | .inherits = &ata_sff_port_ops, | |
790 | .check_atapi_dma = octeon_cf_check_atapi_dma, | |
791 | .qc_prep = ata_noop_qc_prep, | |
792 | .qc_issue = octeon_cf_qc_issue, | |
793 | .sff_dev_select = octeon_cf_dev_select, | |
43f01da0 DD |
794 | .sff_irq_on = octeon_cf_ata_port_noaction, |
795 | .sff_irq_clear = octeon_cf_ata_port_noaction, | |
3c929c6f DD |
796 | .cable_detect = ata_cable_40wire, |
797 | .set_piomode = octeon_cf_set_piomode, | |
798 | .set_dmamode = octeon_cf_set_dmamode, | |
799 | .dev_config = octeon_cf_dev_config, | |
800 | }; | |
801 | ||
0ec24914 | 802 | static int octeon_cf_probe(struct platform_device *pdev) |
3c929c6f DD |
803 | { |
804 | struct resource *res_cs0, *res_cs1; | |
805 | ||
43f01da0 DD |
806 | bool is_16bit; |
807 | const __be32 *cs_num; | |
808 | struct property *reg_prop; | |
809 | int n_addr, n_size, reg_len; | |
810 | struct device_node *node; | |
3c929c6f DD |
811 | void __iomem *cs0; |
812 | void __iomem *cs1 = NULL; | |
813 | struct ata_host *host; | |
814 | struct ata_port *ap; | |
3c929c6f DD |
815 | int irq = 0; |
816 | irq_handler_t irq_handler = NULL; | |
817 | void __iomem *base; | |
818 | struct octeon_cf_port *cf_port; | |
43f01da0 | 819 | int rv = -ENOMEM; |
be1dc3fb | 820 | u32 bus_width; |
3c929c6f | 821 | |
43f01da0 DD |
822 | node = pdev->dev.of_node; |
823 | if (node == NULL) | |
3c929c6f DD |
824 | return -EINVAL; |
825 | ||
7a56c0ba | 826 | cf_port = devm_kzalloc(&pdev->dev, sizeof(*cf_port), GFP_KERNEL); |
43f01da0 DD |
827 | if (!cf_port) |
828 | return -ENOMEM; | |
3c929c6f | 829 | |
be1dc3fb | 830 | cf_port->is_true_ide = of_property_read_bool(node, "cavium,true-ide"); |
3c929c6f | 831 | |
be1dc3fb SS |
832 | if (of_property_read_u32(node, "cavium,bus-width", &bus_width) == 0) |
833 | is_16bit = (bus_width == 16); | |
43f01da0 DD |
834 | else |
835 | is_16bit = false; | |
3c929c6f | 836 | |
43f01da0 DD |
837 | n_addr = of_n_addr_cells(node); |
838 | n_size = of_n_size_cells(node); | |
3c929c6f | 839 | |
43f01da0 | 840 | reg_prop = of_find_property(node, "reg", ®_len); |
7a56c0ba BZ |
841 | if (!reg_prop || reg_len < sizeof(__be32)) |
842 | return -EINVAL; | |
843 | ||
43f01da0 DD |
844 | cs_num = reg_prop->value; |
845 | cf_port->cs0 = be32_to_cpup(cs_num); | |
846 | ||
847 | if (cf_port->is_true_ide) { | |
848 | struct device_node *dma_node; | |
849 | dma_node = of_parse_phandle(node, | |
850 | "cavium,dma-engine-handle", 0); | |
851 | if (dma_node) { | |
852 | struct platform_device *dma_dev; | |
853 | dma_dev = of_find_device_by_node(dma_node); | |
854 | if (dma_dev) { | |
855 | struct resource *res_dma; | |
856 | int i; | |
857 | res_dma = platform_get_resource(dma_dev, IORESOURCE_MEM, 0); | |
858 | if (!res_dma) { | |
859 | of_node_put(dma_node); | |
7a56c0ba | 860 | return -EINVAL; |
43f01da0 | 861 | } |
4bdc0d67 | 862 | cf_port->dma_base = (u64)devm_ioremap(&pdev->dev, res_dma->start, |
43f01da0 | 863 | resource_size(res_dma)); |
43f01da0 DD |
864 | if (!cf_port->dma_base) { |
865 | of_node_put(dma_node); | |
7a56c0ba | 866 | return -EINVAL; |
43f01da0 DD |
867 | } |
868 | ||
43f01da0 | 869 | i = platform_get_irq(dma_dev, 0); |
bfc1f378 | 870 | if (i > 0) { |
43f01da0 | 871 | irq = i; |
bfc1f378 SS |
872 | irq_handler = octeon_cf_interrupt; |
873 | } | |
43f01da0 DD |
874 | } |
875 | of_node_put(dma_node); | |
876 | } | |
877 | res_cs1 = platform_get_resource(pdev, IORESOURCE_MEM, 1); | |
7a56c0ba BZ |
878 | if (!res_cs1) |
879 | return -EINVAL; | |
880 | ||
4bdc0d67 | 881 | cs1 = devm_ioremap(&pdev->dev, res_cs1->start, |
b1cbe7d6 | 882 | resource_size(res_cs1)); |
3c929c6f | 883 | if (!cs1) |
7a56c0ba BZ |
884 | return rv; |
885 | ||
886 | if (reg_len < (n_addr + n_size + 1) * sizeof(__be32)) | |
887 | return -EINVAL; | |
43f01da0 | 888 | |
43f01da0 DD |
889 | cs_num += n_addr + n_size; |
890 | cf_port->cs1 = be32_to_cpup(cs_num); | |
3c929c6f DD |
891 | } |
892 | ||
43f01da0 | 893 | res_cs0 = platform_get_resource(pdev, IORESOURCE_MEM, 0); |
7a56c0ba BZ |
894 | if (!res_cs0) |
895 | return -EINVAL; | |
43f01da0 | 896 | |
4bdc0d67 | 897 | cs0 = devm_ioremap(&pdev->dev, res_cs0->start, |
43f01da0 | 898 | resource_size(res_cs0)); |
43f01da0 | 899 | if (!cs0) |
7a56c0ba | 900 | return rv; |
3c929c6f DD |
901 | |
902 | /* allocate host */ | |
903 | host = ata_host_alloc(&pdev->dev, 1); | |
904 | if (!host) | |
7a56c0ba | 905 | return rv; |
3c929c6f DD |
906 | |
907 | ap = host->ports[0]; | |
908 | ap->private_data = cf_port; | |
43f01da0 | 909 | pdev->dev.platform_data = cf_port; |
3c929c6f DD |
910 | cf_port->ap = ap; |
911 | ap->ops = &octeon_cf_ops; | |
14bdef98 | 912 | ap->pio_mask = ATA_PIO6; |
9cbe056f | 913 | ap->flags |= ATA_FLAG_NO_ATAPI | ATA_FLAG_PIO_POLLING; |
3c929c6f | 914 | |
43f01da0 DD |
915 | if (!is_16bit) { |
916 | base = cs0 + 0x800; | |
3c929c6f DD |
917 | ap->ioaddr.cmd_addr = base; |
918 | ata_sff_std_ports(&ap->ioaddr); | |
919 | ||
920 | ap->ioaddr.altstatus_addr = base + 0xe; | |
921 | ap->ioaddr.ctl_addr = base + 0xe; | |
922 | octeon_cf_ops.sff_data_xfer = octeon_cf_data_xfer8; | |
43f01da0 DD |
923 | } else if (cf_port->is_true_ide) { |
924 | base = cs0; | |
3c929c6f DD |
925 | ap->ioaddr.cmd_addr = base + (ATA_REG_CMD << 1) + 1; |
926 | ap->ioaddr.data_addr = base + (ATA_REG_DATA << 1); | |
927 | ap->ioaddr.error_addr = base + (ATA_REG_ERR << 1) + 1; | |
928 | ap->ioaddr.feature_addr = base + (ATA_REG_FEATURE << 1) + 1; | |
929 | ap->ioaddr.nsect_addr = base + (ATA_REG_NSECT << 1) + 1; | |
930 | ap->ioaddr.lbal_addr = base + (ATA_REG_LBAL << 1) + 1; | |
931 | ap->ioaddr.lbam_addr = base + (ATA_REG_LBAM << 1) + 1; | |
932 | ap->ioaddr.lbah_addr = base + (ATA_REG_LBAH << 1) + 1; | |
933 | ap->ioaddr.device_addr = base + (ATA_REG_DEVICE << 1) + 1; | |
934 | ap->ioaddr.status_addr = base + (ATA_REG_STATUS << 1) + 1; | |
935 | ap->ioaddr.command_addr = base + (ATA_REG_CMD << 1) + 1; | |
936 | ap->ioaddr.altstatus_addr = cs1 + (6 << 1) + 1; | |
937 | ap->ioaddr.ctl_addr = cs1 + (6 << 1) + 1; | |
938 | octeon_cf_ops.sff_data_xfer = octeon_cf_data_xfer16; | |
939 | ||
43f01da0 | 940 | ap->mwdma_mask = enable_dma ? ATA_MWDMA4 : 0; |
3c929c6f | 941 | |
43f01da0 DD |
942 | /* True IDE mode needs a timer to poll for not-busy. */ |
943 | hrtimer_init(&cf_port->delayed_finish, CLOCK_MONOTONIC, | |
944 | HRTIMER_MODE_REL); | |
945 | cf_port->delayed_finish.function = octeon_cf_delayed_finish; | |
3c929c6f DD |
946 | } else { |
947 | /* 16 bit but not True IDE */ | |
43f01da0 | 948 | base = cs0 + 0x800; |
3c929c6f DD |
949 | octeon_cf_ops.sff_data_xfer = octeon_cf_data_xfer16; |
950 | octeon_cf_ops.softreset = octeon_cf_softreset16; | |
951 | octeon_cf_ops.sff_check_status = octeon_cf_check_status16; | |
952 | octeon_cf_ops.sff_tf_read = octeon_cf_tf_read16; | |
953 | octeon_cf_ops.sff_tf_load = octeon_cf_tf_load16; | |
954 | octeon_cf_ops.sff_exec_command = octeon_cf_exec_command16; | |
955 | ||
956 | ap->ioaddr.data_addr = base + ATA_REG_DATA; | |
957 | ap->ioaddr.nsect_addr = base + ATA_REG_NSECT; | |
958 | ap->ioaddr.lbal_addr = base + ATA_REG_LBAL; | |
959 | ap->ioaddr.ctl_addr = base + 0xe; | |
960 | ap->ioaddr.altstatus_addr = base + 0xe; | |
961 | } | |
43f01da0 DD |
962 | cf_port->c0 = ap->ioaddr.ctl_addr; |
963 | ||
105f4ade RK |
964 | rv = dma_coerce_mask_and_coherent(&pdev->dev, DMA_BIT_MASK(64)); |
965 | if (rv) | |
966 | return rv; | |
3c929c6f DD |
967 | |
968 | ata_port_desc(ap, "cmd %p ctl %p", base, ap->ioaddr.ctl_addr); | |
969 | ||
43f01da0 DD |
970 | dev_info(&pdev->dev, "version " DRV_VERSION" %d bit%s.\n", |
971 | is_16bit ? 16 : 8, | |
972 | cf_port->is_true_ide ? ", True IDE" : ""); | |
3c929c6f | 973 | |
43f01da0 DD |
974 | return ata_host_activate(host, irq, irq_handler, |
975 | IRQF_SHARED, &octeon_cf_sht); | |
43f01da0 DD |
976 | } |
977 | ||
978 | static void octeon_cf_shutdown(struct device *dev) | |
979 | { | |
980 | union cvmx_mio_boot_dma_cfgx dma_cfg; | |
981 | union cvmx_mio_boot_dma_intx dma_int; | |
982 | ||
61b8c345 | 983 | struct octeon_cf_port *cf_port = dev_get_platdata(dev); |
43f01da0 DD |
984 | |
985 | if (cf_port->dma_base) { | |
986 | /* Stop and clear the dma engine. */ | |
987 | dma_cfg.u64 = 0; | |
988 | dma_cfg.s.size = -1; | |
989 | cvmx_write_csr(cf_port->dma_base + DMA_CFG, dma_cfg.u64); | |
990 | ||
991 | /* Disable the interrupt. */ | |
992 | dma_int.u64 = 0; | |
993 | cvmx_write_csr(cf_port->dma_base + DMA_INT_EN, dma_int.u64); | |
994 | ||
995 | /* Clear the DMA complete status */ | |
996 | dma_int.s.done = 1; | |
997 | cvmx_write_csr(cf_port->dma_base + DMA_INT, dma_int.u64); | |
998 | ||
999 | __raw_writeb(0, cf_port->c0); | |
1000 | udelay(20); | |
1001 | __raw_writeb(ATA_SRST, cf_port->c0); | |
1002 | udelay(20); | |
1003 | __raw_writeb(0, cf_port->c0); | |
1004 | mdelay(100); | |
1005 | } | |
3c929c6f DD |
1006 | } |
1007 | ||
79af3ae6 | 1008 | static const struct of_device_id octeon_cf_match[] = { |
43f01da0 DD |
1009 | { |
1010 | .compatible = "cavium,ebt3000-compact-flash", | |
1011 | }, | |
1012 | {}, | |
1013 | }; | |
4710f2fa | 1014 | MODULE_DEVICE_TABLE(of, octeon_cf_match); |
43f01da0 | 1015 | |
3c929c6f DD |
1016 | static struct platform_driver octeon_cf_driver = { |
1017 | .probe = octeon_cf_probe, | |
1018 | .driver = { | |
1019 | .name = DRV_NAME, | |
43f01da0 DD |
1020 | .of_match_table = octeon_cf_match, |
1021 | .shutdown = octeon_cf_shutdown | |
3c929c6f DD |
1022 | }, |
1023 | }; | |
1024 | ||
1025 | static int __init octeon_cf_init(void) | |
1026 | { | |
1027 | return platform_driver_register(&octeon_cf_driver); | |
1028 | } | |
1029 | ||
1030 | ||
1031 | MODULE_AUTHOR("David Daney <ddaney@caviumnetworks.com>"); | |
1032 | MODULE_DESCRIPTION("low-level driver for Cavium OCTEON Compact Flash PATA"); | |
1033 | MODULE_LICENSE("GPL"); | |
1034 | MODULE_VERSION(DRV_VERSION); | |
1035 | MODULE_ALIAS("platform:" DRV_NAME); | |
1036 | ||
1037 | module_init(octeon_cf_init); |