[linux-2.6-block.git] / drivers / ata / pata_mpc52xx.c

/*
 * drivers/ata/pata_mpc52xx.c
 *
 * libata driver for the Freescale MPC52xx on-chip IDE interface
 *
 * Copyright (C) 2006 Sylvain Munaut <tnt@246tNt.com>
 * Copyright (C) 2003 Mipsys - Benjamin Herrenschmidt
 *
 * This file is licensed under the terms of the GNU General Public License
 * version 2. This program is licensed "as is" without any warranty of any
 * kind, whether express or implied.
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/slab.h>
#include <linux/delay.h>
#include <linux/libata.h>

#include <asm/io.h>
#include <asm/types.h>
#include <asm/prom.h>
#include <asm/of_platform.h>
#include <asm/mpc52xx.h>


#define DRV_NAME	"mpc52xx_ata"
#define DRV_VERSION	"0.1.0"


/* Private structures used by the driver */
struct mpc52xx_ata_timings {
	u32	pio1;
	u32	pio2;
};

struct mpc52xx_ata_priv {
	unsigned int			ipb_period;
	struct mpc52xx_ata __iomem *	ata_regs;
	int				ata_irq;
	struct mpc52xx_ata_timings	timings[2];
	int				csel;
};


/* ATAPI-4 PIO specs (in ns) */
static const int ataspec_t0[5]    = {600, 383, 240, 180, 120};
static const int ataspec_t1[5]    = { 70,  50,  30,  30,  25};
static const int ataspec_t2_8[5]  = {290, 290, 290,  80,  70};
static const int ataspec_t2_16[5] = {165, 125, 100,  80,  70};
static const int ataspec_t2i[5]   = {  0,   0,   0,  70,  25};
static const int ataspec_t4[5]    = { 30,  20,  15,  10,  10};
static const int ataspec_ta[5]    = { 35,  35,  35,  35,  35};

#define CALC_CLKCYC(c,v) ((((v)+(c)-1)/(c)))


/* Bit definitions inside the registers */
#define MPC52xx_ATA_HOSTCONF_SMR	0x80000000UL /* State machine reset */
#define MPC52xx_ATA_HOSTCONF_FR		0x40000000UL /* FIFO Reset */
#define MPC52xx_ATA_HOSTCONF_IE		0x02000000UL /* Enable interrupt in PIO */
#define MPC52xx_ATA_HOSTCONF_IORDY	0x01000000UL /* Drive supports IORDY protocol */

#define MPC52xx_ATA_HOSTSTAT_TIP	0x80000000UL /* Transaction in progress */
#define MPC52xx_ATA_HOSTSTAT_UREP	0x40000000UL /* UDMA Read Extended Pause */
#define MPC52xx_ATA_HOSTSTAT_RERR	0x02000000UL /* Read Error */
#define MPC52xx_ATA_HOSTSTAT_WERR	0x01000000UL /* Write Error */

#define MPC52xx_ATA_FIFOSTAT_EMPTY	0x01 /* FIFO Empty */

#define MPC52xx_ATA_DMAMODE_WRITE	0x01 /* Write DMA */
#define MPC52xx_ATA_DMAMODE_READ	0x02 /* Read DMA */
#define MPC52xx_ATA_DMAMODE_UDMA	0x04 /* UDMA enabled */
#define MPC52xx_ATA_DMAMODE_IE		0x08 /* Enable drive interrupt to CPU in DMA mode */
#define MPC52xx_ATA_DMAMODE_FE		0x10 /* FIFO Flush enable in Rx mode */
#define MPC52xx_ATA_DMAMODE_FR		0x20 /* FIFO Reset */
#define MPC52xx_ATA_DMAMODE_HUT		0x40 /* Host UDMA burst terminate */


/* Structure of the hardware registers */
struct mpc52xx_ata {

	/* Host interface registers */
	u32 config;		/* ATA + 0x00 Host configuration */
	u32 host_status;	/* ATA + 0x04 Host controller status */
	u32 pio1;		/* ATA + 0x08 PIO Timing 1 */
	u32 pio2;		/* ATA + 0x0c PIO Timing 2 */
	u32 mdma1;		/* ATA + 0x10 MDMA Timing 1 */
	u32 mdma2;		/* ATA + 0x14 MDMA Timing 2 */
	u32 udma1;		/* ATA + 0x18 UDMA Timing 1 */
	u32 udma2;		/* ATA + 0x1c UDMA Timing 2 */
	u32 udma3;		/* ATA + 0x20 UDMA Timing 3 */
	u32 udma4;		/* ATA + 0x24 UDMA Timing 4 */
	u32 udma5;		/* ATA + 0x28 UDMA Timing 5 */
	u32 share_cnt;		/* ATA + 0x2c ATA share counter */
	u32 reserved0[3];

	/* FIFO registers */
	u32 fifo_data;		/* ATA + 0x3c */
	u8  fifo_status_frame;	/* ATA + 0x40 */
	u8  fifo_status;	/* ATA + 0x41 */
	u16 reserved7[1];
	u8  fifo_control;	/* ATA + 0x44 */
	u8  reserved8[5];
	u16 fifo_alarm;		/* ATA + 0x4a */
	u16 reserved9;
	u16 fifo_rdp;		/* ATA + 0x4e */
	u16 reserved10;
	u16 fifo_wrp;		/* ATA + 0x52 */
	u16 reserved11;
	u16 fifo_lfrdp;		/* ATA + 0x56 */
	u16 reserved12;
	u16 fifo_lfwrp;		/* ATA + 0x5a */

	/* Drive TaskFile registers */
	u8  tf_control;		/* ATA + 0x5c TASKFILE Control/Alt Status */
	u8  reserved13[3];
	u16 tf_data;		/* ATA + 0x60 TASKFILE Data */
	u16 reserved14;
	u8  tf_features;	/* ATA + 0x64 TASKFILE Features/Error */
	u8  reserved15[3];
	u8  tf_sec_count;	/* ATA + 0x68 TASKFILE Sector Count */
	u8  reserved16[3];
	u8  tf_sec_num;		/* ATA + 0x6c TASKFILE Sector Number */
	u8  reserved17[3];
	u8  tf_cyl_low;		/* ATA + 0x70 TASKFILE Cylinder Low */
	u8  reserved18[3];
	u8  tf_cyl_high;	/* ATA + 0x74 TASKFILE Cylinder High */
	u8  reserved19[3];
	u8  tf_dev_head;	/* ATA + 0x78 TASKFILE Device/Head */
	u8  reserved20[3];
	u8  tf_command;		/* ATA + 0x7c TASKFILE Command/Status */
	u8  dma_mode;		/* ATA + 0x7d ATA Host DMA Mode configuration */
	u8  reserved21[2];
};


/* ======================================================================== */
/* Aux fns                                                                  */
/* ======================================================================== */


/* MPC52xx low level hw control */

static int
mpc52xx_ata_compute_pio_timings(struct mpc52xx_ata_priv *priv, int dev, int pio)
{
	struct mpc52xx_ata_timings *timing = &priv->timings[dev];
	unsigned int ipb_period = priv->ipb_period;
	unsigned int t0, t1, t2_8, t2_16, t2i, t4, ta;

	if ((pio<0) || (pio>4))
		return -EINVAL;

	t0	= CALC_CLKCYC(ipb_period, 1000 * ataspec_t0[pio]);
	t1	= CALC_CLKCYC(ipb_period, 1000 * ataspec_t1[pio]);
	t2_8	= CALC_CLKCYC(ipb_period, 1000 * ataspec_t2_8[pio]);
	t2_16	= CALC_CLKCYC(ipb_period, 1000 * ataspec_t2_16[pio]);
	t2i	= CALC_CLKCYC(ipb_period, 1000 * ataspec_t2i[pio]);
	t4	= CALC_CLKCYC(ipb_period, 1000 * ataspec_t4[pio]);
	ta	= CALC_CLKCYC(ipb_period, 1000 * ataspec_ta[pio]);

	timing->pio1 = (t0 << 24) | (t2_8 << 16) | (t2_16 << 8) | (t2i);
	timing->pio2 = (t4 << 24) | (t1 << 16) | (ta << 8);

	return 0;
}

static void
mpc52xx_ata_apply_timings(struct mpc52xx_ata_priv *priv, int device)
{
	struct mpc52xx_ata __iomem *regs = priv->ata_regs;
	struct mpc52xx_ata_timings *timing = &priv->timings[device];

	out_be32(&regs->pio1,  timing->pio1);
	out_be32(&regs->pio2,  timing->pio2);
	out_be32(&regs->mdma1, 0);
	out_be32(&regs->mdma2, 0);
	out_be32(&regs->udma1, 0);
	out_be32(&regs->udma2, 0);
	out_be32(&regs->udma3, 0);
	out_be32(&regs->udma4, 0);
	out_be32(&regs->udma5, 0);

	priv->csel = device;
}

static int
mpc52xx_ata_hw_init(struct mpc52xx_ata_priv *priv)
{
	struct mpc52xx_ata __iomem *regs = priv->ata_regs;
	int tslot;

	/* Clear share_cnt (all sample code do this ...) */
	out_be32(&regs->share_cnt, 0);

	/* Configure and reset host */
	out_be32(&regs->config,
			MPC52xx_ATA_HOSTCONF_IE |
			MPC52xx_ATA_HOSTCONF_IORDY |
			MPC52xx_ATA_HOSTCONF_SMR |
			MPC52xx_ATA_HOSTCONF_FR);

	udelay(10);

	out_be32(&regs->config,
			MPC52xx_ATA_HOSTCONF_IE |
			MPC52xx_ATA_HOSTCONF_IORDY);

	/* Set the time slot to 1us */
	tslot = CALC_CLKCYC(priv->ipb_period, 1000000);
	out_be32(&regs->share_cnt, tslot << 16 );

	/* Init timings to PIO0 */
	memset(priv->timings, 0x00, 2*sizeof(struct mpc52xx_ata_timings));

	mpc52xx_ata_compute_pio_timings(priv, 0, 0);
	mpc52xx_ata_compute_pio_timings(priv, 1, 0);

	mpc52xx_ata_apply_timings(priv, 0);

	return 0;
}


/* ======================================================================== */
/* libata driver                                                            */
/* ======================================================================== */

static void
mpc52xx_ata_set_piomode(struct ata_port *ap, struct ata_device *adev)
{
	struct mpc52xx_ata_priv *priv = ap->host->private_data;
	int pio, rv;

	pio = adev->pio_mode - XFER_PIO_0;

	rv = mpc52xx_ata_compute_pio_timings(priv, adev->devno, pio);

	if (rv) {
		printk(KERN_ERR DRV_NAME
			": Trying to select invalid PIO mode %d\n", pio);
		return;
	}

	mpc52xx_ata_apply_timings(priv, adev->devno);
}
static void
mpc52xx_ata_dev_select(struct ata_port *ap, unsigned int device)
{
	struct mpc52xx_ata_priv *priv = ap->host->private_data;

	if (device != priv->csel)
		mpc52xx_ata_apply_timings(priv, device);

	ata_std_dev_select(ap,device);
}

static void
mpc52xx_ata_error_handler(struct ata_port *ap)
{
	ata_bmdma_drive_eh(ap, ata_std_prereset, ata_std_softreset, NULL,
			ata_std_postreset);
}


static struct scsi_host_template mpc52xx_ata_sht = {
	.module			= THIS_MODULE,
	.name			= DRV_NAME,
	.ioctl			= ata_scsi_ioctl,
	.queuecommand		= ata_scsi_queuecmd,
	.can_queue		= ATA_DEF_QUEUE,
	.this_id		= ATA_SHT_THIS_ID,
	.sg_tablesize		= LIBATA_MAX_PRD,
	.max_sectors		= ATA_MAX_SECTORS,
	.cmd_per_lun		= ATA_SHT_CMD_PER_LUN,
	.emulated		= ATA_SHT_EMULATED,
	.use_clustering		= ATA_SHT_USE_CLUSTERING,
	.proc_name		= DRV_NAME,
	.dma_boundary		= ATA_DMA_BOUNDARY,
	.slave_configure	= ata_scsi_slave_config,
	.bios_param		= ata_std_bios_param,
};

static struct ata_port_operations mpc52xx_ata_port_ops = {
	.port_disable		= ata_port_disable,
	.set_piomode		= mpc52xx_ata_set_piomode,
	.dev_select		= mpc52xx_ata_dev_select,
	.tf_load		= ata_tf_load,
	.tf_read		= ata_tf_read,
	.check_status		= ata_check_status,
	.exec_command		= ata_exec_command,
	.freeze			= ata_bmdma_freeze,
	.thaw			= ata_bmdma_thaw,
	.error_handler		= mpc52xx_ata_error_handler,
	.qc_prep		= ata_qc_prep,
	.qc_issue		= ata_qc_issue_prot,
	.data_xfer		= ata_mmio_data_xfer,
	.irq_handler		= ata_interrupt,
	.irq_clear		= ata_bmdma_irq_clear,
	.port_start		= ata_port_start,
	.port_stop		= ata_port_stop,
	.host_stop		= ata_host_stop,
};

static struct ata_probe_ent mpc52xx_ata_probe_ent = {
	.port_ops	= &mpc52xx_ata_port_ops,
	.sht		= &mpc52xx_ata_sht,
	.n_ports	= 1,
	.pio_mask	= 0x1f,		/* Up to PIO4 */
	.mwdma_mask	= 0x00,		/* No MWDMA   */
	.udma_mask	= 0x00,		/* No UDMA    */
	.port_flags	= ATA_FLAG_SLAVE_POSS | ATA_FLAG_SRST | ATA_FLAG_MMIO,
	.irq_flags	= 0,
};

static int __devinit
mpc52xx_ata_init_one(struct device *dev, struct mpc52xx_ata_priv *priv)
{
	struct ata_probe_ent *ae = &mpc52xx_ata_probe_ent;
	struct ata_ioports *aio = &ae->port[0];
	int rv;

	INIT_LIST_HEAD(&ae->node);
	ae->dev = dev;
	ae->irq = priv->ata_irq;

	aio->cmd_addr		= 0;	/* Don't have a classic reg block */
	aio->altstatus_addr	= (unsigned long)&priv->ata_regs->tf_control;
	aio->ctl_addr		= (unsigned long)&priv->ata_regs->tf_control;
	aio->data_addr		= (unsigned long)&priv->ata_regs->tf_data;
	aio->error_addr		= (unsigned long)&priv->ata_regs->tf_features;
	aio->feature_addr	= (unsigned long)&priv->ata_regs->tf_features;
	aio->nsect_addr		= (unsigned long)&priv->ata_regs->tf_sec_count;
	aio->lbal_addr		= (unsigned long)&priv->ata_regs->tf_sec_num;
	aio->lbam_addr		= (unsigned long)&priv->ata_regs->tf_cyl_low;
	aio->lbah_addr		= (unsigned long)&priv->ata_regs->tf_cyl_high;
	aio->device_addr	= (unsigned long)&priv->ata_regs->tf_dev_head;
	aio->status_addr	= (unsigned long)&priv->ata_regs->tf_command;
	aio->command_addr	= (unsigned long)&priv->ata_regs->tf_command;

	ae->private_data = priv;

	rv = ata_device_add(ae);

	return rv ? 0 : -EINVAL;
}

static struct mpc52xx_ata_priv *
mpc52xx_ata_remove_one(struct device *dev)
{
	struct ata_host *host = dev_get_drvdata(dev);
	struct mpc52xx_ata_priv *priv = host->private_data;

	ata_host_remove(host);

	return priv;
}


/* ======================================================================== */
/* OF Platform driver                                                       */
/* ======================================================================== */

static int __devinit
mpc52xx_ata_probe(struct of_device *op, const struct of_device_id *match)
{
	unsigned int ipb_freq;
	struct resource res_mem;
	int ata_irq = NO_IRQ;
	struct mpc52xx_ata __iomem *ata_regs = NULL;
	struct mpc52xx_ata_priv *priv = NULL;
	int rv;

	/* Get ipb frequency */
	ipb_freq = mpc52xx_find_ipb_freq(op->node);
	if (!ipb_freq) {
		printk(KERN_ERR DRV_NAME ": "
			"Unable to find IPB Bus frequency\n" );
		return -ENODEV;
	}

	/* Get IRQ and register */
	rv = of_address_to_resource(op->node, 0, &res_mem);
	if (rv) {
		printk(KERN_ERR DRV_NAME ": "
			"Error while parsing device node resource\n" );
		return rv;
	}

	ata_irq = irq_of_parse_and_map(op->node, 0);
	if (ata_irq == NO_IRQ) {
		printk(KERN_ERR DRV_NAME ": "
			"Error while mapping the irq\n");
		return -EINVAL;
	}

	/* Request mem region */
	if (!request_mem_region(res_mem.start,
				sizeof(struct mpc52xx_ata), DRV_NAME)) {
		printk(KERN_ERR DRV_NAME ": "
			"Error while requesting mem region\n");
		irq_dispose_mapping(ata_irq);
		return -EBUSY;
	}

	/* Remap registers */
	ata_regs = ioremap(res_mem.start, sizeof(struct mpc52xx_ata));
	if (!ata_regs) {
		printk(KERN_ERR DRV_NAME ": "
			"Error while mapping register set\n");
		rv = -ENOMEM;
		goto err;
	}

	/* Prepare our private structure */
	priv = kmalloc(sizeof(struct mpc52xx_ata_priv), GFP_ATOMIC);
	if (!priv) {
		printk(KERN_ERR DRV_NAME ": "
			"Error while allocating private structure\n");
		rv = -ENOMEM;
		goto err;
	}

	priv->ipb_period = 1000000000 / (ipb_freq / 1000);
	priv->ata_regs = ata_regs;
	priv->ata_irq = ata_irq;
	priv->csel = -1;

	/* Init the hw */
	rv = mpc52xx_ata_hw_init(priv);
	if (rv) {
		printk(KERN_ERR DRV_NAME ": Error during HW init\n");
		goto err;
	}

	/* Register ourselves to libata */
	rv = mpc52xx_ata_init_one(&op->dev, priv);
	if (rv) {
		printk(KERN_ERR DRV_NAME ": "
			"Error while registering to ATA layer\n");
		return rv;
	}

	/* Done */
	return 0;

	/* Error path */
err:
	kfree(priv);

	if (ata_regs)
		iounmap(ata_regs);

	release_mem_region(res_mem.start, sizeof(struct mpc52xx_ata));

	irq_dispose_mapping(ata_irq);

	return rv;
}

static int
mpc52xx_ata_remove(struct of_device *op)
{
	struct mpc52xx_ata_priv *priv;
	struct resource res_mem;
	int rv;

	/* Unregister */
	priv = mpc52xx_ata_remove_one(&op->dev);

	/* Free everything */
	iounmap(priv->ata_regs);

	rv = of_address_to_resource(op->node, 0, &res_mem);
	if (rv) {
		printk(KERN_ERR DRV_NAME ": "
			"Error while parsing device node resource\n");
		printk(KERN_ERR DRV_NAME ": "
			"Zone may not be properly released\n");
	} else
		release_mem_region(res_mem.start, sizeof(struct mpc52xx_ata));

	irq_dispose_mapping(priv->ata_irq);

	kfree(priv);

	return 0;
}


#ifdef CONFIG_PM

static int
mpc52xx_ata_suspend(struct of_device *op, pm_message_t state)
{
	return 0;	/* FIXME : What to do here ? */
}

static int
mpc52xx_ata_resume(struct of_device *op)
{
	return 0;	/* FIXME : What to do here ? */
}

#endif


static struct of_device_id mpc52xx_ata_of_match[] = {
	{
		.compatible = "mpc5200-ata",
	},
	{
		.compatible = "mpc52xx-ata",
	},
	{},
};


static struct of_platform_driver mpc52xx_ata_of_platform_driver = {
	.owner		= THIS_MODULE,
	.name		= DRV_NAME,
	.match_table	= mpc52xx_ata_of_match,
	.probe		= mpc52xx_ata_probe,
	.remove		= mpc52xx_ata_remove,
#ifdef CONFIG_PM
	.suspend	= mpc52xx_ata_suspend,
	.resume		= mpc52xx_ata_resume,
#endif
	.driver		= {
		.name	= DRV_NAME,
		.owner	= THIS_MODULE,
	},
};


/* ======================================================================== */
/* Module                                                                   */
/* ======================================================================== */

static int __init
mpc52xx_ata_init(void)
{
	printk(KERN_INFO "ata: MPC52xx IDE/ATA libata driver\n");
	return of_register_platform_driver(&mpc52xx_ata_of_platform_driver);
}

static void __exit
mpc52xx_ata_exit(void)
{
	of_unregister_platform_driver(&mpc52xx_ata_of_platform_driver);
}

module_init(mpc52xx_ata_init);
module_exit(mpc52xx_ata_exit);

MODULE_AUTHOR("Sylvain Munaut <tnt@246tNt.com>");
MODULE_DESCRIPTION("Freescale MPC52xx IDE/ATA libata driver");
MODULE_LICENSE("GPL");
MODULE_DEVICE_TABLE(of, mpc52xx_ata_of_match);
MODULE_VERSION(DRV_VERSION);
Commit	Line	Data
155d2916 SM	1	/*
	2	* drivers/ata/pata_mpc52xx.c
	3	*
	4	* libata driver for the Freescale MPC52xx on-chip IDE interface
	5	*
	6	* Copyright (C) 2006 Sylvain Munaut <tnt@246tNt.com>
	7	* Copyright (C) 2003 Mipsys - Benjamin Herrenschmidt
	8	*
	9	* This file is licensed under the terms of the GNU General Public License
	10	* version 2. This program is licensed "as is" without any warranty of any
	11	* kind, whether express or implied.
	12	*/
	13
	14	#include <linux/kernel.h>
	15	#include <linux/module.h>
	16	#include <linux/slab.h>
	17	#include <linux/delay.h>
	18	#include <linux/libata.h>
	19
	20	#include <asm/io.h>
	21	#include <asm/types.h>
	22	#include <asm/prom.h>
	23	#include <asm/of_platform.h>
	24	#include <asm/mpc52xx.h>
	25
	26
	27	#define DRV_NAME "mpc52xx_ata"
	28	#define DRV_VERSION "0.1.0"
	29
	30
	31	/* Private structures used by the driver */
	32	struct mpc52xx_ata_timings {
	33	u32 pio1;
	34	u32 pio2;
	35	};
	36
	37	struct mpc52xx_ata_priv {
	38	unsigned int ipb_period;
	39	struct mpc52xx_ata __iomem * ata_regs;
	40	int ata_irq;
	41	struct mpc52xx_ata_timings timings[2];
	42	int csel;
	43	};
	44
	45
	46	/* ATAPI-4 PIO specs (in ns) */
	47	static const int ataspec_t0[5] = {600, 383, 240, 180, 120};
	48	static const int ataspec_t1[5] = { 70, 50, 30, 30, 25};
	49	static const int ataspec_t2_8[5] = {290, 290, 290, 80, 70};
	50	static const int ataspec_t2_16[5] = {165, 125, 100, 80, 70};
	51	static const int ataspec_t2i[5] = { 0, 0, 0, 70, 25};
	52	static const int ataspec_t4[5] = { 30, 20, 15, 10, 10};
	53	static const int ataspec_ta[5] = { 35, 35, 35, 35, 35};
	54
	55	#define CALC_CLKCYC(c,v) ((((v)+(c)-1)/(c)))
	56
	57
	58	/* Bit definitions inside the registers */
	59	#define MPC52xx_ATA_HOSTCONF_SMR 0x80000000UL /* State machine reset */
	60	#define MPC52xx_ATA_HOSTCONF_FR 0x40000000UL /* FIFO Reset */
	61	#define MPC52xx_ATA_HOSTCONF_IE 0x02000000UL /* Enable interrupt in PIO */
	62	#define MPC52xx_ATA_HOSTCONF_IORDY 0x01000000UL /* Drive supports IORDY protocol */
	63
	64	#define MPC52xx_ATA_HOSTSTAT_TIP 0x80000000UL /* Transaction in progress */
65	#define MPC52xx_ATA_HOSTSTAT_UREP 0x40000000UL /* UDMA Read Extended Pause */
66	#define MPC52xx_ATA_HOSTSTAT_RERR 0x02000000UL /* Read Error */
67	#define MPC52xx_ATA_HOSTSTAT_WERR 0x01000000UL /* Write Error */
68
69	#define MPC52xx_ATA_FIFOSTAT_EMPTY 0x01 /* FIFO Empty */
70
71	#define MPC52xx_ATA_DMAMODE_WRITE 0x01 /* Write DMA */
72	#define MPC52xx_ATA_DMAMODE_READ 0x02 /* Read DMA */
73	#define MPC52xx_ATA_DMAMODE_UDMA 0x04 /* UDMA enabled */
74	#define MPC52xx_ATA_DMAMODE_IE 0x08 /* Enable drive interrupt to CPU in DMA mode */
75	#define MPC52xx_ATA_DMAMODE_FE 0x10 /* FIFO Flush enable in Rx mode */
76	#define MPC52xx_ATA_DMAMODE_FR 0x20 /* FIFO Reset */
77	#define MPC52xx_ATA_DMAMODE_HUT 0x40 /* Host UDMA burst terminate */
78
79
80	/* Structure of the hardware registers */
81	struct mpc52xx_ata {
82
83	/* Host interface registers */
84	u32 config; /* ATA + 0x00 Host configuration */
85	u32 host_status; /* ATA + 0x04 Host controller status */
86	u32 pio1; /* ATA + 0x08 PIO Timing 1 */
87	u32 pio2; /* ATA + 0x0c PIO Timing 2 */
88	u32 mdma1; /* ATA + 0x10 MDMA Timing 1 */
89	u32 mdma2; /* ATA + 0x14 MDMA Timing 2 */
90	u32 udma1; /* ATA + 0x18 UDMA Timing 1 */
91	u32 udma2; /* ATA + 0x1c UDMA Timing 2 */
92	u32 udma3; /* ATA + 0x20 UDMA Timing 3 */
93	u32 udma4; /* ATA + 0x24 UDMA Timing 4 */
94	u32 udma5; /* ATA + 0x28 UDMA Timing 5 */
95	u32 share_cnt; /* ATA + 0x2c ATA share counter */
96	u32 reserved0[3];
97
98	/* FIFO registers */
99	u32 fifo_data; /* ATA + 0x3c */
100	u8 fifo_status_frame; /* ATA + 0x40 */
101	u8 fifo_status; /* ATA + 0x41 */
102	u16 reserved7[1];
103	u8 fifo_control; /* ATA + 0x44 */
104	u8 reserved8[5];
105	u16 fifo_alarm; /* ATA + 0x4a */
106	u16 reserved9;
107	u16 fifo_rdp; /* ATA + 0x4e */
108	u16 reserved10;
109	u16 fifo_wrp; /* ATA + 0x52 */
110	u16 reserved11;
111	u16 fifo_lfrdp; /* ATA + 0x56 */
112	u16 reserved12;
113	u16 fifo_lfwrp; /* ATA + 0x5a */
114
115	/* Drive TaskFile registers */
116	u8 tf_control; /* ATA + 0x5c TASKFILE Control/Alt Status */
117	u8 reserved13[3];
118	u16 tf_data; /* ATA + 0x60 TASKFILE Data */
119	u16 reserved14;
120	u8 tf_features; /* ATA + 0x64 TASKFILE Features/Error */
121	u8 reserved15[3];
122	u8 tf_sec_count; /* ATA + 0x68 TASKFILE Sector Count */
123	u8 reserved16[3];
124	u8 tf_sec_num; /* ATA + 0x6c TASKFILE Sector Number */
125	u8 reserved17[3];
126	u8 tf_cyl_low; /* ATA + 0x70 TASKFILE Cylinder Low */
127	u8 reserved18[3];
128	u8 tf_cyl_high; /* ATA + 0x74 TASKFILE Cylinder High */
129	u8 reserved19[3];
130	u8 tf_dev_head; /* ATA + 0x78 TASKFILE Device/Head */
131	u8 reserved20[3];
132	u8 tf_command; /* ATA + 0x7c TASKFILE Command/Status */
133	u8 dma_mode; /* ATA + 0x7d ATA Host DMA Mode configuration */
134	u8 reserved21[2];
135	};
136
137
138	/* ======================================================================== */
139	/* Aux fns */
140	/* ======================================================================== */
141
142
143	/* MPC52xx low level hw control */
144
145	static int
146	mpc52xx_ata_compute_pio_timings(struct mpc52xx_ata_priv *priv, int dev, int pio)
147	{
148	struct mpc52xx_ata_timings *timing = &priv->timings[dev];
149	unsigned int ipb_period = priv->ipb_period;
150	unsigned int t0, t1, t2_8, t2_16, t2i, t4, ta;
151
152	if ((pio<0) \|\| (pio>4))
153	return -EINVAL;
154
155	t0 = CALC_CLKCYC(ipb_period, 1000 * ataspec_t0[pio]);
156	t1 = CALC_CLKCYC(ipb_period, 1000 * ataspec_t1[pio]);
157	t2_8 = CALC_CLKCYC(ipb_period, 1000 * ataspec_t2_8[pio]);
158	t2_16 = CALC_CLKCYC(ipb_period, 1000 * ataspec_t2_16[pio]);
159	t2i = CALC_CLKCYC(ipb_period, 1000 * ataspec_t2i[pio]);
160	t4 = CALC_CLKCYC(ipb_period, 1000 * ataspec_t4[pio]);
161	ta = CALC_CLKCYC(ipb_period, 1000 * ataspec_ta[pio]);
162
163	timing->pio1 = (t0 << 24) \| (t2_8 << 16) \| (t2_16 << 8) \| (t2i);
164	timing->pio2 = (t4 << 24) \| (t1 << 16) \| (ta << 8);
165
166	return 0;
167	}
168
169	static void
170	mpc52xx_ata_apply_timings(struct mpc52xx_ata_priv *priv, int device)
171	{
172	struct mpc52xx_ata __iomem *regs = priv->ata_regs;
173	struct mpc52xx_ata_timings *timing = &priv->timings[device];
174
175	out_be32(&regs->pio1, timing->pio1);
176	out_be32(&regs->pio2, timing->pio2);
177	out_be32(&regs->mdma1, 0);
178	out_be32(&regs->mdma2, 0);
179	out_be32(&regs->udma1, 0);
180	out_be32(&regs->udma2, 0);
181	out_be32(&regs->udma3, 0);
182	out_be32(&regs->udma4, 0);
183	out_be32(&regs->udma5, 0);
184
185	priv->csel = device;
186	}
187
188	static int
189	mpc52xx_ata_hw_init(struct mpc52xx_ata_priv *priv)
190	{
191	struct mpc52xx_ata __iomem *regs = priv->ata_regs;
192	int tslot;
193
194	/* Clear share_cnt (all sample code do this ...) */
195	out_be32(&regs->share_cnt, 0);
196
197	/* Configure and reset host */
198	out_be32(&regs->config,
199	MPC52xx_ATA_HOSTCONF_IE \|
200	MPC52xx_ATA_HOSTCONF_IORDY \|
201	MPC52xx_ATA_HOSTCONF_SMR \|
202	MPC52xx_ATA_HOSTCONF_FR);
203
204	udelay(10);
205
206	out_be32(&regs->config,
207	MPC52xx_ATA_HOSTCONF_IE \|
208	MPC52xx_ATA_HOSTCONF_IORDY);
209
210	/* Set the time slot to 1us */
211	tslot = CALC_CLKCYC(priv->ipb_period, 1000000);
212	out_be32(&regs->share_cnt, tslot << 16 );
213
214	/* Init timings to PIO0 */
215	memset(priv->timings, 0x00, 2*sizeof(struct mpc52xx_ata_timings));
216
217	mpc52xx_ata_compute_pio_timings(priv, 0, 0);
218	mpc52xx_ata_compute_pio_timings(priv, 1, 0);
219
220	mpc52xx_ata_apply_timings(priv, 0);
221
222	return 0;
223	}
224
225
226	/* ======================================================================== */
227	/* libata driver */
228	/* ======================================================================== */
229
230	static void
231	mpc52xx_ata_set_piomode(struct ata_port ap, struct ata_device adev)
232	{
233	struct mpc52xx_ata_priv *priv = ap->host->private_data;
234	int pio, rv;
235
236	pio = adev->pio_mode - XFER_PIO_0;
237
238	rv = mpc52xx_ata_compute_pio_timings(priv, adev->devno, pio);
239
240	if (rv) {
241	printk(KERN_ERR DRV_NAME
242	": Trying to select invalid PIO mode %d\n", pio);
243	return;
244	}
245
246	mpc52xx_ata_apply_timings(priv, adev->devno);
247	}
248	static void
249	mpc52xx_ata_dev_select(struct ata_port *ap, unsigned int device)
250	{
251	struct mpc52xx_ata_priv *priv = ap->host->private_data;
252
253	if (device != priv->csel)
254	mpc52xx_ata_apply_timings(priv, device);
255
256	ata_std_dev_select(ap,device);
257	}
258
259	static void
260	mpc52xx_ata_error_handler(struct ata_port *ap)
261	{
262	ata_bmdma_drive_eh(ap, ata_std_prereset, ata_std_softreset, NULL,
263	ata_std_postreset);
264	}
265
266
267
268	static struct scsi_host_template mpc52xx_ata_sht = {
269	.module = THIS_MODULE,
270	.name = DRV_NAME,
271	.ioctl = ata_scsi_ioctl,
272	.queuecommand = ata_scsi_queuecmd,
273	.can_queue = ATA_DEF_QUEUE,
274	.this_id = ATA_SHT_THIS_ID,
275	.sg_tablesize = LIBATA_MAX_PRD,
276	.max_sectors = ATA_MAX_SECTORS,
277	.cmd_per_lun = ATA_SHT_CMD_PER_LUN,
278	.emulated = ATA_SHT_EMULATED,
279	.use_clustering = ATA_SHT_USE_CLUSTERING,
280	.proc_name = DRV_NAME,
281	.dma_boundary = ATA_DMA_BOUNDARY,
282	.slave_configure = ata_scsi_slave_config,
283	.bios_param = ata_std_bios_param,
284	};
285
286	static struct ata_port_operations mpc52xx_ata_port_ops = {
287	.port_disable = ata_port_disable,
288	.set_piomode = mpc52xx_ata_set_piomode,
289	.dev_select = mpc52xx_ata_dev_select,
290	.tf_load = ata_tf_load,
291	.tf_read = ata_tf_read,
292	.check_status = ata_check_status,
293	.exec_command = ata_exec_command,
294	.freeze = ata_bmdma_freeze,
295	.thaw = ata_bmdma_thaw,
296	.error_handler = mpc52xx_ata_error_handler,
297	.qc_prep = ata_qc_prep,
298	.qc_issue = ata_qc_issue_prot,
299	.data_xfer = ata_mmio_data_xfer,
300	.irq_handler = ata_interrupt,
301	.irq_clear = ata_bmdma_irq_clear,
302	.port_start = ata_port_start,
303	.port_stop = ata_port_stop,
304	.host_stop = ata_host_stop,
305	};
306
307	static struct ata_probe_ent mpc52xx_ata_probe_ent = {
308	.port_ops = &mpc52xx_ata_port_ops,
309	.sht = &mpc52xx_ata_sht,
310	.n_ports = 1,
311	.pio_mask = 0x1f, /* Up to PIO4 */
312	.mwdma_mask = 0x00, /* No MWDMA */
313	.udma_mask = 0x00, /* No UDMA */
314	.port_flags = ATA_FLAG_SLAVE_POSS \| ATA_FLAG_SRST \| ATA_FLAG_MMIO,
315	.irq_flags = 0,
316	};
317
318	static int __devinit
319	mpc52xx_ata_init_one(struct device dev, struct mpc52xx_ata_priv priv)
320	{
321	struct ata_probe_ent *ae = &mpc52xx_ata_probe_ent;
322	struct ata_ioports *aio = &ae->port[0];
323	int rv;
324
325	INIT_LIST_HEAD(&ae->node);
326	ae->dev = dev;
327	ae->irq = priv->ata_irq;
328
329	aio->cmd_addr = 0; /* Don't have a classic reg block */
330	aio->altstatus_addr = (unsigned long)&priv->ata_regs->tf_control;
331	aio->ctl_addr = (unsigned long)&priv->ata_regs->tf_control;
332	aio->data_addr = (unsigned long)&priv->ata_regs->tf_data;
333	aio->error_addr = (unsigned long)&priv->ata_regs->tf_features;
334	aio->feature_addr = (unsigned long)&priv->ata_regs->tf_features;
335	aio->nsect_addr = (unsigned long)&priv->ata_regs->tf_sec_count;
336	aio->lbal_addr = (unsigned long)&priv->ata_regs->tf_sec_num;
337	aio->lbam_addr = (unsigned long)&priv->ata_regs->tf_cyl_low;
338	aio->lbah_addr = (unsigned long)&priv->ata_regs->tf_cyl_high;
339	aio->device_addr = (unsigned long)&priv->ata_regs->tf_dev_head;
340	aio->status_addr = (unsigned long)&priv->ata_regs->tf_command;
341	aio->command_addr = (unsigned long)&priv->ata_regs->tf_command;
342
343	ae->private_data = priv;
344
345	rv = ata_device_add(ae);
346
347	return rv ? 0 : -EINVAL;
348	}
349
350	static struct mpc52xx_ata_priv *
351	mpc52xx_ata_remove_one(struct device *dev)
352	{
353	struct ata_host *host = dev_get_drvdata(dev);
354	struct mpc52xx_ata_priv *priv = host->private_data;
355
356	ata_host_remove(host);
357
358	return priv;
359	}
360
361
362	/* ======================================================================== */
363	/* OF Platform driver */
364	/* ======================================================================== */
365
366	static int __devinit
367	mpc52xx_ata_probe(struct of_device op, const struct of_device_id match)
368	{
369	unsigned int ipb_freq;
370	struct resource res_mem;
371	int ata_irq = NO_IRQ;
372	struct mpc52xx_ata __iomem *ata_regs = NULL;
373	struct mpc52xx_ata_priv *priv = NULL;
374	int rv;
375
376	/* Get ipb frequency */
377	ipb_freq = mpc52xx_find_ipb_freq(op->node);
378	if (!ipb_freq) {
379	printk(KERN_ERR DRV_NAME ": "
380	"Unable to find IPB Bus frequency\n" );
381	return -ENODEV;
382	}
383
384	/* Get IRQ and register */
385	rv = of_address_to_resource(op->node, 0, &res_mem);
386	if (rv) {
387	printk(KERN_ERR DRV_NAME ": "
388	"Error while parsing device node resource\n" );
389	return rv;
390	}
391
392	ata_irq = irq_of_parse_and_map(op->node, 0);
393	if (ata_irq == NO_IRQ) {
394	printk(KERN_ERR DRV_NAME ": "
395	"Error while mapping the irq\n");
396	return -EINVAL;
397	}
398
399	/* Request mem region */
400	if (!request_mem_region(res_mem.start,
401	sizeof(struct mpc52xx_ata), DRV_NAME)) {
402	printk(KERN_ERR DRV_NAME ": "
403	"Error while requesting mem region\n");
404	irq_dispose_mapping(ata_irq);
405	return -EBUSY;
406	}
407
408	/* Remap registers */
409	ata_regs = ioremap(res_mem.start, sizeof(struct mpc52xx_ata));
410	if (!ata_regs) {
411	printk(KERN_ERR DRV_NAME ": "
412	"Error while mapping register set\n");
413	rv = -ENOMEM;
414	goto err;
415	}
416
417	/* Prepare our private structure */
418	priv = kmalloc(sizeof(struct mpc52xx_ata_priv), GFP_ATOMIC);
419	if (!priv) {
420	printk(KERN_ERR DRV_NAME ": "
421	"Error while allocating private structure\n");
422	rv = -ENOMEM;
423	goto err;
424	}
425
426	priv->ipb_period = 1000000000 / (ipb_freq / 1000);
427	priv->ata_regs = ata_regs;
428	priv->ata_irq = ata_irq;
429	priv->csel = -1;
430
431	/* Init the hw */
432	rv = mpc52xx_ata_hw_init(priv);
433	if (rv) {
434	printk(KERN_ERR DRV_NAME ": Error during HW init\n");
435	goto err;
436	}
437
438	/* Register ourselves to libata */
439	rv = mpc52xx_ata_init_one(&op->dev, priv);
440	if (rv) {
441	printk(KERN_ERR DRV_NAME ": "
442	"Error while registering to ATA layer\n");
443	return rv;
444	}
445
446	/* Done */
447	return 0;
448
449	/* Error path */
450	err:
451	kfree(priv);
452
453	if (ata_regs)
454	iounmap(ata_regs);
455
456	release_mem_region(res_mem.start, sizeof(struct mpc52xx_ata));
457
458	irq_dispose_mapping(ata_irq);
459
460	return rv;
461	}
462
463	static int
464	mpc52xx_ata_remove(struct of_device *op)
465	{
466	struct mpc52xx_ata_priv *priv;
467	struct resource res_mem;
468	int rv;
469
470	/* Unregister */
471	priv = mpc52xx_ata_remove_one(&op->dev);
472
473	/* Free everything */
474	iounmap(priv->ata_regs);
475
476	rv = of_address_to_resource(op->node, 0, &res_mem);
477	if (rv) {
478	printk(KERN_ERR DRV_NAME ": "
479	"Error while parsing device node resource\n");
480	printk(KERN_ERR DRV_NAME ": "
481	"Zone may not be properly released\n");
482	} else
483	release_mem_region(res_mem.start, sizeof(struct mpc52xx_ata));
484
485	irq_dispose_mapping(priv->ata_irq);
486
487	kfree(priv);
488
489	return 0;
490	}
491
492
493	#ifdef CONFIG_PM
494
495	static int
496	mpc52xx_ata_suspend(struct of_device *op, pm_message_t state)
497	{
498	return 0; /* FIXME : What to do here ? */
499	}
500
501	static int
502	mpc52xx_ata_resume(struct of_device *op)
503	{
504	return 0; /* FIXME : What to do here ? */
505	}
506
507	#endif
508
509
510	static struct of_device_id mpc52xx_ata_of_match[] = {
511	{
512	.compatible = "mpc5200-ata",
513	},
514	{
515	.compatible = "mpc52xx-ata",
516	},
517	{},
518	};
519
520
521	static struct of_platform_driver mpc52xx_ata_of_platform_driver = {
522	.owner = THIS_MODULE,
523	.name = DRV_NAME,
524	.match_table = mpc52xx_ata_of_match,
525	.probe = mpc52xx_ata_probe,
526	.remove = mpc52xx_ata_remove,
527	#ifdef CONFIG_PM
528	.suspend = mpc52xx_ata_suspend,
529	.resume = mpc52xx_ata_resume,
530	#endif
531	.driver = {
532	.name = DRV_NAME,
533	.owner = THIS_MODULE,
534	},
535	};
536
537
538	/* ======================================================================== */
539	/* Module */
540	/* ======================================================================== */
541
542	static int __init
543	mpc52xx_ata_init(void)
544	{
545	printk(KERN_INFO "ata: MPC52xx IDE/ATA libata driver\n");
546	return of_register_platform_driver(&mpc52xx_ata_of_platform_driver);
547	}
548
549	static void __exit
550	mpc52xx_ata_exit(void)
551	{
552	of_unregister_platform_driver(&mpc52xx_ata_of_platform_driver);
553	}
554
555	module_init(mpc52xx_ata_init);
556	module_exit(mpc52xx_ata_exit);
557
558	MODULE_AUTHOR("Sylvain Munaut <tnt@246tNt.com>");
559	MODULE_DESCRIPTION("Freescale MPC52xx IDE/ATA libata driver");
560	MODULE_LICENSE("GPL");
561	MODULE_DEVICE_TABLE(of, mpc52xx_ata_of_match);
562	MODULE_VERSION(DRV_VERSION);
563