Commit | Line | Data |
---|---|---|
155d2916 SM |
1 | /* |
2 | * drivers/ata/pata_mpc52xx.c | |
3 | * | |
4 | * libata driver for the Freescale MPC52xx on-chip IDE interface | |
5 | * | |
6 | * Copyright (C) 2006 Sylvain Munaut <tnt@246tNt.com> | |
7 | * Copyright (C) 2003 Mipsys - Benjamin Herrenschmidt | |
8 | * | |
6b61e69e TY |
9 | * UDMA support based on patches by Freescale (Bernard Kuhn, John Rigby), |
10 | * Domen Puncer and Tim Yamin. | |
11 | * | |
155d2916 SM |
12 | * This file is licensed under the terms of the GNU General Public License |
13 | * version 2. This program is licensed "as is" without any warranty of any | |
14 | * kind, whether express or implied. | |
15 | */ | |
16 | ||
17 | #include <linux/kernel.h> | |
18 | #include <linux/module.h> | |
5a0e3ad6 | 19 | #include <linux/gfp.h> |
155d2916 SM |
20 | #include <linux/delay.h> |
21 | #include <linux/libata.h> | |
61e6ae71 | 22 | #include <linux/of.h> |
c956b92e CL |
23 | #include <linux/of_address.h> |
24 | #include <linux/of_irq.h> | |
61e6ae71 | 25 | #include <linux/platform_device.h> |
6b61e69e | 26 | #include <linux/types.h> |
155d2916 | 27 | |
6b61e69e | 28 | #include <asm/cacheflush.h> |
155d2916 SM |
29 | #include <asm/mpc52xx.h> |
30 | ||
9a322993 PDM |
31 | #include <linux/fsl/bestcomm/bestcomm.h> |
32 | #include <linux/fsl/bestcomm/bestcomm_priv.h> | |
33 | #include <linux/fsl/bestcomm/ata.h> | |
155d2916 SM |
34 | |
35 | #define DRV_NAME "mpc52xx_ata" | |
155d2916 SM |
36 | |
37 | /* Private structures used by the driver */ | |
38 | struct mpc52xx_ata_timings { | |
39 | u32 pio1; | |
40 | u32 pio2; | |
6b61e69e TY |
41 | u32 mdma1; |
42 | u32 mdma2; | |
43 | u32 udma1; | |
44 | u32 udma2; | |
45 | u32 udma3; | |
46 | u32 udma4; | |
47 | u32 udma5; | |
48 | int using_udma; | |
155d2916 SM |
49 | }; |
50 | ||
51 | struct mpc52xx_ata_priv { | |
52 | unsigned int ipb_period; | |
6b61e69e TY |
53 | struct mpc52xx_ata __iomem *ata_regs; |
54 | phys_addr_t ata_regs_pa; | |
155d2916 SM |
55 | int ata_irq; |
56 | struct mpc52xx_ata_timings timings[2]; | |
57 | int csel; | |
6b61e69e TY |
58 | |
59 | /* DMA */ | |
60 | struct bcom_task *dmatsk; | |
61 | const struct udmaspec *udmaspec; | |
62 | const struct mdmaspec *mdmaspec; | |
63 | int mpc52xx_ata_dma_last_write; | |
64 | int waiting_for_dma; | |
155d2916 SM |
65 | }; |
66 | ||
67 | ||
68 | /* ATAPI-4 PIO specs (in ns) */ | |
ec569af8 RF |
69 | static const u16 ataspec_t0[5] = {600, 383, 240, 180, 120}; |
70 | static const u16 ataspec_t1[5] = { 70, 50, 30, 30, 25}; | |
71 | static const u16 ataspec_t2_8[5] = {290, 290, 290, 80, 70}; | |
72 | static const u16 ataspec_t2_16[5] = {165, 125, 100, 80, 70}; | |
73 | static const u16 ataspec_t2i[5] = { 0, 0, 0, 70, 25}; | |
74 | static const u16 ataspec_t4[5] = { 30, 20, 15, 10, 10}; | |
75 | static const u16 ataspec_ta[5] = { 35, 35, 35, 35, 35}; | |
155d2916 SM |
76 | |
77 | #define CALC_CLKCYC(c,v) ((((v)+(c)-1)/(c))) | |
78 | ||
6b61e69e TY |
79 | /* ======================================================================== */ |
80 | ||
81 | /* ATAPI-4 MDMA specs (in clocks) */ | |
82 | struct mdmaspec { | |
ec569af8 RF |
83 | u8 t0M; |
84 | u8 td; | |
85 | u8 th; | |
86 | u8 tj; | |
87 | u8 tkw; | |
88 | u8 tm; | |
89 | u8 tn; | |
6b61e69e TY |
90 | }; |
91 | ||
92 | static const struct mdmaspec mdmaspec66[3] = { | |
93 | { .t0M = 32, .td = 15, .th = 2, .tj = 2, .tkw = 15, .tm = 4, .tn = 1 }, | |
94 | { .t0M = 10, .td = 6, .th = 1, .tj = 1, .tkw = 4, .tm = 2, .tn = 1 }, | |
95 | { .t0M = 8, .td = 5, .th = 1, .tj = 1, .tkw = 2, .tm = 2, .tn = 1 }, | |
96 | }; | |
97 | ||
98 | static const struct mdmaspec mdmaspec132[3] = { | |
99 | { .t0M = 64, .td = 29, .th = 3, .tj = 3, .tkw = 29, .tm = 7, .tn = 2 }, | |
100 | { .t0M = 20, .td = 11, .th = 2, .tj = 1, .tkw = 7, .tm = 4, .tn = 1 }, | |
101 | { .t0M = 16, .td = 10, .th = 2, .tj = 1, .tkw = 4, .tm = 4, .tn = 1 }, | |
102 | }; | |
103 | ||
104 | /* ATAPI-4 UDMA specs (in clocks) */ | |
105 | struct udmaspec { | |
ec569af8 RF |
106 | u8 tcyc; |
107 | u8 t2cyc; | |
108 | u8 tds; | |
109 | u8 tdh; | |
110 | u8 tdvs; | |
111 | u8 tdvh; | |
112 | u8 tfs; | |
113 | u8 tli; | |
114 | u8 tmli; | |
115 | u8 taz; | |
116 | u8 tzah; | |
117 | u8 tenv; | |
118 | u8 tsr; | |
119 | u8 trfs; | |
120 | u8 trp; | |
121 | u8 tack; | |
122 | u8 tss; | |
6b61e69e TY |
123 | }; |
124 | ||
125 | static const struct udmaspec udmaspec66[6] = { | |
126 | { .tcyc = 8, .t2cyc = 16, .tds = 1, .tdh = 1, .tdvs = 5, .tdvh = 1, | |
127 | .tfs = 16, .tli = 10, .tmli = 2, .taz = 1, .tzah = 2, .tenv = 2, | |
128 | .tsr = 3, .trfs = 5, .trp = 11, .tack = 2, .tss = 4, | |
129 | }, | |
130 | { .tcyc = 5, .t2cyc = 11, .tds = 1, .tdh = 1, .tdvs = 4, .tdvh = 1, | |
131 | .tfs = 14, .tli = 10, .tmli = 2, .taz = 1, .tzah = 2, .tenv = 2, | |
132 | .tsr = 2, .trfs = 5, .trp = 9, .tack = 2, .tss = 4, | |
133 | }, | |
134 | { .tcyc = 4, .t2cyc = 8, .tds = 1, .tdh = 1, .tdvs = 3, .tdvh = 1, | |
135 | .tfs = 12, .tli = 10, .tmli = 2, .taz = 1, .tzah = 2, .tenv = 2, | |
136 | .tsr = 2, .trfs = 4, .trp = 7, .tack = 2, .tss = 4, | |
137 | }, | |
138 | { .tcyc = 3, .t2cyc = 6, .tds = 1, .tdh = 1, .tdvs = 2, .tdvh = 1, | |
139 | .tfs = 9, .tli = 7, .tmli = 2, .taz = 1, .tzah = 2, .tenv = 2, | |
140 | .tsr = 2, .trfs = 4, .trp = 7, .tack = 2, .tss = 4, | |
141 | }, | |
142 | { .tcyc = 2, .t2cyc = 4, .tds = 1, .tdh = 1, .tdvs = 1, .tdvh = 1, | |
143 | .tfs = 8, .tli = 8, .tmli = 2, .taz = 1, .tzah = 2, .tenv = 2, | |
144 | .tsr = 2, .trfs = 4, .trp = 7, .tack = 2, .tss = 4, | |
145 | }, | |
146 | { .tcyc = 2, .t2cyc = 2, .tds = 1, .tdh = 1, .tdvs = 1, .tdvh = 1, | |
147 | .tfs = 6, .tli = 5, .tmli = 2, .taz = 1, .tzah = 2, .tenv = 2, | |
148 | .tsr = 2, .trfs = 4, .trp = 6, .tack = 2, .tss = 4, | |
149 | }, | |
150 | }; | |
151 | ||
152 | static const struct udmaspec udmaspec132[6] = { | |
153 | { .tcyc = 15, .t2cyc = 31, .tds = 2, .tdh = 1, .tdvs = 10, .tdvh = 1, | |
154 | .tfs = 30, .tli = 20, .tmli = 3, .taz = 2, .tzah = 3, .tenv = 3, | |
155 | .tsr = 7, .trfs = 10, .trp = 22, .tack = 3, .tss = 7, | |
156 | }, | |
157 | { .tcyc = 10, .t2cyc = 21, .tds = 2, .tdh = 1, .tdvs = 7, .tdvh = 1, | |
158 | .tfs = 27, .tli = 20, .tmli = 3, .taz = 2, .tzah = 3, .tenv = 3, | |
159 | .tsr = 4, .trfs = 10, .trp = 17, .tack = 3, .tss = 7, | |
160 | }, | |
161 | { .tcyc = 6, .t2cyc = 12, .tds = 1, .tdh = 1, .tdvs = 5, .tdvh = 1, | |
162 | .tfs = 23, .tli = 20, .tmli = 3, .taz = 2, .tzah = 3, .tenv = 3, | |
163 | .tsr = 3, .trfs = 8, .trp = 14, .tack = 3, .tss = 7, | |
164 | }, | |
165 | { .tcyc = 7, .t2cyc = 12, .tds = 1, .tdh = 1, .tdvs = 3, .tdvh = 1, | |
166 | .tfs = 15, .tli = 13, .tmli = 3, .taz = 2, .tzah = 3, .tenv = 3, | |
167 | .tsr = 3, .trfs = 8, .trp = 14, .tack = 3, .tss = 7, | |
168 | }, | |
169 | { .tcyc = 2, .t2cyc = 5, .tds = 0, .tdh = 0, .tdvs = 1, .tdvh = 1, | |
170 | .tfs = 16, .tli = 14, .tmli = 2, .taz = 1, .tzah = 2, .tenv = 2, | |
171 | .tsr = 2, .trfs = 7, .trp = 13, .tack = 2, .tss = 6, | |
172 | }, | |
173 | { .tcyc = 3, .t2cyc = 6, .tds = 1, .tdh = 1, .tdvs = 1, .tdvh = 1, | |
174 | .tfs = 12, .tli = 10, .tmli = 3, .taz = 2, .tzah = 3, .tenv = 3, | |
175 | .tsr = 3, .trfs = 7, .trp = 12, .tack = 3, .tss = 7, | |
176 | }, | |
177 | }; | |
178 | ||
179 | /* ======================================================================== */ | |
155d2916 SM |
180 | |
181 | /* Bit definitions inside the registers */ | |
182 | #define MPC52xx_ATA_HOSTCONF_SMR 0x80000000UL /* State machine reset */ | |
183 | #define MPC52xx_ATA_HOSTCONF_FR 0x40000000UL /* FIFO Reset */ | |
184 | #define MPC52xx_ATA_HOSTCONF_IE 0x02000000UL /* Enable interrupt in PIO */ | |
185 | #define MPC52xx_ATA_HOSTCONF_IORDY 0x01000000UL /* Drive supports IORDY protocol */ | |
186 | ||
187 | #define MPC52xx_ATA_HOSTSTAT_TIP 0x80000000UL /* Transaction in progress */ | |
188 | #define MPC52xx_ATA_HOSTSTAT_UREP 0x40000000UL /* UDMA Read Extended Pause */ | |
189 | #define MPC52xx_ATA_HOSTSTAT_RERR 0x02000000UL /* Read Error */ | |
190 | #define MPC52xx_ATA_HOSTSTAT_WERR 0x01000000UL /* Write Error */ | |
191 | ||
192 | #define MPC52xx_ATA_FIFOSTAT_EMPTY 0x01 /* FIFO Empty */ | |
6b61e69e | 193 | #define MPC52xx_ATA_FIFOSTAT_ERROR 0x40 /* FIFO Error */ |
155d2916 SM |
194 | |
195 | #define MPC52xx_ATA_DMAMODE_WRITE 0x01 /* Write DMA */ | |
196 | #define MPC52xx_ATA_DMAMODE_READ 0x02 /* Read DMA */ | |
197 | #define MPC52xx_ATA_DMAMODE_UDMA 0x04 /* UDMA enabled */ | |
198 | #define MPC52xx_ATA_DMAMODE_IE 0x08 /* Enable drive interrupt to CPU in DMA mode */ | |
199 | #define MPC52xx_ATA_DMAMODE_FE 0x10 /* FIFO Flush enable in Rx mode */ | |
200 | #define MPC52xx_ATA_DMAMODE_FR 0x20 /* FIFO Reset */ | |
201 | #define MPC52xx_ATA_DMAMODE_HUT 0x40 /* Host UDMA burst terminate */ | |
202 | ||
6b61e69e TY |
203 | #define MAX_DMA_BUFFERS 128 |
204 | #define MAX_DMA_BUFFER_SIZE 0x20000u | |
155d2916 SM |
205 | |
206 | /* Structure of the hardware registers */ | |
207 | struct mpc52xx_ata { | |
208 | ||
209 | /* Host interface registers */ | |
210 | u32 config; /* ATA + 0x00 Host configuration */ | |
211 | u32 host_status; /* ATA + 0x04 Host controller status */ | |
212 | u32 pio1; /* ATA + 0x08 PIO Timing 1 */ | |
213 | u32 pio2; /* ATA + 0x0c PIO Timing 2 */ | |
214 | u32 mdma1; /* ATA + 0x10 MDMA Timing 1 */ | |
215 | u32 mdma2; /* ATA + 0x14 MDMA Timing 2 */ | |
216 | u32 udma1; /* ATA + 0x18 UDMA Timing 1 */ | |
217 | u32 udma2; /* ATA + 0x1c UDMA Timing 2 */ | |
218 | u32 udma3; /* ATA + 0x20 UDMA Timing 3 */ | |
219 | u32 udma4; /* ATA + 0x24 UDMA Timing 4 */ | |
220 | u32 udma5; /* ATA + 0x28 UDMA Timing 5 */ | |
221 | u32 share_cnt; /* ATA + 0x2c ATA share counter */ | |
222 | u32 reserved0[3]; | |
223 | ||
224 | /* FIFO registers */ | |
225 | u32 fifo_data; /* ATA + 0x3c */ | |
226 | u8 fifo_status_frame; /* ATA + 0x40 */ | |
227 | u8 fifo_status; /* ATA + 0x41 */ | |
228 | u16 reserved7[1]; | |
229 | u8 fifo_control; /* ATA + 0x44 */ | |
230 | u8 reserved8[5]; | |
231 | u16 fifo_alarm; /* ATA + 0x4a */ | |
232 | u16 reserved9; | |
233 | u16 fifo_rdp; /* ATA + 0x4e */ | |
234 | u16 reserved10; | |
235 | u16 fifo_wrp; /* ATA + 0x52 */ | |
236 | u16 reserved11; | |
237 | u16 fifo_lfrdp; /* ATA + 0x56 */ | |
238 | u16 reserved12; | |
239 | u16 fifo_lfwrp; /* ATA + 0x5a */ | |
240 | ||
241 | /* Drive TaskFile registers */ | |
242 | u8 tf_control; /* ATA + 0x5c TASKFILE Control/Alt Status */ | |
243 | u8 reserved13[3]; | |
244 | u16 tf_data; /* ATA + 0x60 TASKFILE Data */ | |
245 | u16 reserved14; | |
246 | u8 tf_features; /* ATA + 0x64 TASKFILE Features/Error */ | |
247 | u8 reserved15[3]; | |
248 | u8 tf_sec_count; /* ATA + 0x68 TASKFILE Sector Count */ | |
249 | u8 reserved16[3]; | |
250 | u8 tf_sec_num; /* ATA + 0x6c TASKFILE Sector Number */ | |
251 | u8 reserved17[3]; | |
252 | u8 tf_cyl_low; /* ATA + 0x70 TASKFILE Cylinder Low */ | |
253 | u8 reserved18[3]; | |
254 | u8 tf_cyl_high; /* ATA + 0x74 TASKFILE Cylinder High */ | |
255 | u8 reserved19[3]; | |
256 | u8 tf_dev_head; /* ATA + 0x78 TASKFILE Device/Head */ | |
257 | u8 reserved20[3]; | |
258 | u8 tf_command; /* ATA + 0x7c TASKFILE Command/Status */ | |
259 | u8 dma_mode; /* ATA + 0x7d ATA Host DMA Mode configuration */ | |
260 | u8 reserved21[2]; | |
261 | }; | |
262 | ||
263 | ||
264 | /* ======================================================================== */ | |
265 | /* Aux fns */ | |
266 | /* ======================================================================== */ | |
267 | ||
268 | ||
269 | /* MPC52xx low level hw control */ | |
155d2916 SM |
270 | static int |
271 | mpc52xx_ata_compute_pio_timings(struct mpc52xx_ata_priv *priv, int dev, int pio) | |
272 | { | |
273 | struct mpc52xx_ata_timings *timing = &priv->timings[dev]; | |
274 | unsigned int ipb_period = priv->ipb_period; | |
ec569af8 | 275 | u32 t0, t1, t2_8, t2_16, t2i, t4, ta; |
155d2916 | 276 | |
6b61e69e | 277 | if ((pio < 0) || (pio > 4)) |
155d2916 SM |
278 | return -EINVAL; |
279 | ||
280 | t0 = CALC_CLKCYC(ipb_period, 1000 * ataspec_t0[pio]); | |
281 | t1 = CALC_CLKCYC(ipb_period, 1000 * ataspec_t1[pio]); | |
282 | t2_8 = CALC_CLKCYC(ipb_period, 1000 * ataspec_t2_8[pio]); | |
283 | t2_16 = CALC_CLKCYC(ipb_period, 1000 * ataspec_t2_16[pio]); | |
284 | t2i = CALC_CLKCYC(ipb_period, 1000 * ataspec_t2i[pio]); | |
285 | t4 = CALC_CLKCYC(ipb_period, 1000 * ataspec_t4[pio]); | |
286 | ta = CALC_CLKCYC(ipb_period, 1000 * ataspec_ta[pio]); | |
287 | ||
288 | timing->pio1 = (t0 << 24) | (t2_8 << 16) | (t2_16 << 8) | (t2i); | |
289 | timing->pio2 = (t4 << 24) | (t1 << 16) | (ta << 8); | |
290 | ||
291 | return 0; | |
292 | } | |
293 | ||
6b61e69e TY |
294 | static int |
295 | mpc52xx_ata_compute_mdma_timings(struct mpc52xx_ata_priv *priv, int dev, | |
296 | int speed) | |
297 | { | |
298 | struct mpc52xx_ata_timings *t = &priv->timings[dev]; | |
299 | const struct mdmaspec *s = &priv->mdmaspec[speed]; | |
300 | ||
301 | if (speed < 0 || speed > 2) | |
302 | return -EINVAL; | |
303 | ||
ec569af8 RF |
304 | t->mdma1 = ((u32)s->t0M << 24) | ((u32)s->td << 16) | ((u32)s->tkw << 8) | s->tm; |
305 | t->mdma2 = ((u32)s->th << 24) | ((u32)s->tj << 16) | ((u32)s->tn << 8); | |
6b61e69e TY |
306 | t->using_udma = 0; |
307 | ||
308 | return 0; | |
309 | } | |
310 | ||
311 | static int | |
312 | mpc52xx_ata_compute_udma_timings(struct mpc52xx_ata_priv *priv, int dev, | |
313 | int speed) | |
314 | { | |
315 | struct mpc52xx_ata_timings *t = &priv->timings[dev]; | |
316 | const struct udmaspec *s = &priv->udmaspec[speed]; | |
317 | ||
318 | if (speed < 0 || speed > 2) | |
319 | return -EINVAL; | |
320 | ||
ec569af8 RF |
321 | t->udma1 = ((u32)s->t2cyc << 24) | ((u32)s->tcyc << 16) | ((u32)s->tds << 8) | s->tdh; |
322 | t->udma2 = ((u32)s->tdvs << 24) | ((u32)s->tdvh << 16) | ((u32)s->tfs << 8) | s->tli; | |
323 | t->udma3 = ((u32)s->tmli << 24) | ((u32)s->taz << 16) | ((u32)s->tenv << 8) | s->tsr; | |
324 | t->udma4 = ((u32)s->tss << 24) | ((u32)s->trfs << 16) | ((u32)s->trp << 8) | s->tack; | |
325 | t->udma5 = (u32)s->tzah << 24; | |
6b61e69e TY |
326 | t->using_udma = 1; |
327 | ||
328 | return 0; | |
329 | } | |
330 | ||
155d2916 SM |
331 | static void |
332 | mpc52xx_ata_apply_timings(struct mpc52xx_ata_priv *priv, int device) | |
333 | { | |
334 | struct mpc52xx_ata __iomem *regs = priv->ata_regs; | |
335 | struct mpc52xx_ata_timings *timing = &priv->timings[device]; | |
336 | ||
337 | out_be32(®s->pio1, timing->pio1); | |
338 | out_be32(®s->pio2, timing->pio2); | |
6b61e69e TY |
339 | out_be32(®s->mdma1, timing->mdma1); |
340 | out_be32(®s->mdma2, timing->mdma2); | |
341 | out_be32(®s->udma1, timing->udma1); | |
342 | out_be32(®s->udma2, timing->udma2); | |
343 | out_be32(®s->udma3, timing->udma3); | |
344 | out_be32(®s->udma4, timing->udma4); | |
345 | out_be32(®s->udma5, timing->udma5); | |
155d2916 SM |
346 | priv->csel = device; |
347 | } | |
348 | ||
349 | static int | |
350 | mpc52xx_ata_hw_init(struct mpc52xx_ata_priv *priv) | |
351 | { | |
352 | struct mpc52xx_ata __iomem *regs = priv->ata_regs; | |
353 | int tslot; | |
354 | ||
355 | /* Clear share_cnt (all sample code do this ...) */ | |
356 | out_be32(®s->share_cnt, 0); | |
357 | ||
358 | /* Configure and reset host */ | |
359 | out_be32(®s->config, | |
360 | MPC52xx_ATA_HOSTCONF_IE | | |
361 | MPC52xx_ATA_HOSTCONF_IORDY | | |
362 | MPC52xx_ATA_HOSTCONF_SMR | | |
363 | MPC52xx_ATA_HOSTCONF_FR); | |
364 | ||
365 | udelay(10); | |
366 | ||
367 | out_be32(®s->config, | |
368 | MPC52xx_ATA_HOSTCONF_IE | | |
369 | MPC52xx_ATA_HOSTCONF_IORDY); | |
370 | ||
371 | /* Set the time slot to 1us */ | |
372 | tslot = CALC_CLKCYC(priv->ipb_period, 1000000); | |
6b61e69e | 373 | out_be32(®s->share_cnt, tslot << 16); |
155d2916 SM |
374 | |
375 | /* Init timings to PIO0 */ | |
376 | memset(priv->timings, 0x00, 2*sizeof(struct mpc52xx_ata_timings)); | |
377 | ||
378 | mpc52xx_ata_compute_pio_timings(priv, 0, 0); | |
379 | mpc52xx_ata_compute_pio_timings(priv, 1, 0); | |
380 | ||
381 | mpc52xx_ata_apply_timings(priv, 0); | |
382 | ||
383 | return 0; | |
384 | } | |
385 | ||
386 | ||
387 | /* ======================================================================== */ | |
388 | /* libata driver */ | |
389 | /* ======================================================================== */ | |
390 | ||
391 | static void | |
392 | mpc52xx_ata_set_piomode(struct ata_port *ap, struct ata_device *adev) | |
393 | { | |
394 | struct mpc52xx_ata_priv *priv = ap->host->private_data; | |
395 | int pio, rv; | |
396 | ||
397 | pio = adev->pio_mode - XFER_PIO_0; | |
398 | ||
399 | rv = mpc52xx_ata_compute_pio_timings(priv, adev->devno, pio); | |
400 | ||
401 | if (rv) { | |
6b61e69e TY |
402 | dev_err(ap->dev, "error: invalid PIO mode: %d\n", pio); |
403 | return; | |
404 | } | |
405 | ||
406 | mpc52xx_ata_apply_timings(priv, adev->devno); | |
407 | } | |
408 | ||
409 | static void | |
410 | mpc52xx_ata_set_dmamode(struct ata_port *ap, struct ata_device *adev) | |
411 | { | |
412 | struct mpc52xx_ata_priv *priv = ap->host->private_data; | |
413 | int rv; | |
414 | ||
415 | if (adev->dma_mode >= XFER_UDMA_0) { | |
416 | int dma = adev->dma_mode - XFER_UDMA_0; | |
417 | rv = mpc52xx_ata_compute_udma_timings(priv, adev->devno, dma); | |
418 | } else { | |
419 | int dma = adev->dma_mode - XFER_MW_DMA_0; | |
420 | rv = mpc52xx_ata_compute_mdma_timings(priv, adev->devno, dma); | |
421 | } | |
422 | ||
423 | if (rv) { | |
424 | dev_alert(ap->dev, | |
425 | "Trying to select invalid DMA mode %d\n", | |
426 | adev->dma_mode); | |
155d2916 SM |
427 | return; |
428 | } | |
429 | ||
430 | mpc52xx_ata_apply_timings(priv, adev->devno); | |
431 | } | |
6b61e69e | 432 | |
155d2916 SM |
433 | static void |
434 | mpc52xx_ata_dev_select(struct ata_port *ap, unsigned int device) | |
435 | { | |
436 | struct mpc52xx_ata_priv *priv = ap->host->private_data; | |
437 | ||
438 | if (device != priv->csel) | |
439 | mpc52xx_ata_apply_timings(priv, device); | |
440 | ||
6b61e69e TY |
441 | ata_sff_dev_select(ap, device); |
442 | } | |
443 | ||
444 | static int | |
445 | mpc52xx_ata_build_dmatable(struct ata_queued_cmd *qc) | |
446 | { | |
447 | struct ata_port *ap = qc->ap; | |
448 | struct mpc52xx_ata_priv *priv = ap->host->private_data; | |
449 | struct bcom_ata_bd *bd; | |
450 | unsigned int read = !(qc->tf.flags & ATA_TFLAG_WRITE), si; | |
451 | struct scatterlist *sg; | |
452 | int count = 0; | |
453 | ||
454 | if (read) | |
455 | bcom_ata_rx_prepare(priv->dmatsk); | |
456 | else | |
457 | bcom_ata_tx_prepare(priv->dmatsk); | |
458 | ||
459 | for_each_sg(qc->sg, sg, qc->n_elem, si) { | |
460 | dma_addr_t cur_addr = sg_dma_address(sg); | |
461 | u32 cur_len = sg_dma_len(sg); | |
462 | ||
463 | while (cur_len) { | |
464 | unsigned int tc = min(cur_len, MAX_DMA_BUFFER_SIZE); | |
465 | bd = (struct bcom_ata_bd *) | |
466 | bcom_prepare_next_buffer(priv->dmatsk); | |
467 | ||
468 | if (read) { | |
469 | bd->status = tc; | |
470 | bd->src_pa = (__force u32) priv->ata_regs_pa + | |
471 | offsetof(struct mpc52xx_ata, fifo_data); | |
472 | bd->dst_pa = (__force u32) cur_addr; | |
473 | } else { | |
474 | bd->status = tc; | |
475 | bd->src_pa = (__force u32) cur_addr; | |
476 | bd->dst_pa = (__force u32) priv->ata_regs_pa + | |
477 | offsetof(struct mpc52xx_ata, fifo_data); | |
478 | } | |
479 | ||
480 | bcom_submit_next_buffer(priv->dmatsk, NULL); | |
481 | ||
482 | cur_addr += tc; | |
483 | cur_len -= tc; | |
484 | count++; | |
485 | ||
486 | if (count > MAX_DMA_BUFFERS) { | |
487 | dev_alert(ap->dev, "dma table" | |
488 | "too small\n"); | |
489 | goto use_pio_instead; | |
490 | } | |
491 | } | |
492 | } | |
493 | return 1; | |
494 | ||
495 | use_pio_instead: | |
496 | bcom_ata_reset_bd(priv->dmatsk); | |
497 | return 0; | |
498 | } | |
499 | ||
500 | static void | |
501 | mpc52xx_bmdma_setup(struct ata_queued_cmd *qc) | |
502 | { | |
503 | struct ata_port *ap = qc->ap; | |
504 | struct mpc52xx_ata_priv *priv = ap->host->private_data; | |
505 | struct mpc52xx_ata __iomem *regs = priv->ata_regs; | |
506 | ||
507 | unsigned int read = !(qc->tf.flags & ATA_TFLAG_WRITE); | |
508 | u8 dma_mode; | |
509 | ||
510 | if (!mpc52xx_ata_build_dmatable(qc)) | |
511 | dev_alert(ap->dev, "%s: %i, return 1?\n", | |
512 | __func__, __LINE__); | |
513 | ||
514 | /* Check FIFO is OK... */ | |
515 | if (in_8(&priv->ata_regs->fifo_status) & MPC52xx_ATA_FIFOSTAT_ERROR) | |
516 | dev_alert(ap->dev, "%s: FIFO error detected: 0x%02x!\n", | |
517 | __func__, in_8(&priv->ata_regs->fifo_status)); | |
518 | ||
519 | if (read) { | |
520 | dma_mode = MPC52xx_ATA_DMAMODE_IE | MPC52xx_ATA_DMAMODE_READ | | |
521 | MPC52xx_ATA_DMAMODE_FE; | |
522 | ||
523 | /* Setup FIFO if direction changed */ | |
524 | if (priv->mpc52xx_ata_dma_last_write != 0) { | |
525 | priv->mpc52xx_ata_dma_last_write = 0; | |
526 | ||
527 | /* Configure FIFO with granularity to 7 */ | |
528 | out_8(®s->fifo_control, 7); | |
529 | out_be16(®s->fifo_alarm, 128); | |
530 | ||
531 | /* Set FIFO Reset bit (FR) */ | |
532 | out_8(®s->dma_mode, MPC52xx_ATA_DMAMODE_FR); | |
533 | } | |
534 | } else { | |
535 | dma_mode = MPC52xx_ATA_DMAMODE_IE | MPC52xx_ATA_DMAMODE_WRITE; | |
536 | ||
537 | /* Setup FIFO if direction changed */ | |
538 | if (priv->mpc52xx_ata_dma_last_write != 1) { | |
539 | priv->mpc52xx_ata_dma_last_write = 1; | |
540 | ||
541 | /* Configure FIFO with granularity to 4 */ | |
542 | out_8(®s->fifo_control, 4); | |
543 | out_be16(®s->fifo_alarm, 128); | |
544 | } | |
545 | } | |
546 | ||
547 | if (priv->timings[qc->dev->devno].using_udma) | |
548 | dma_mode |= MPC52xx_ATA_DMAMODE_UDMA; | |
549 | ||
550 | out_8(®s->dma_mode, dma_mode); | |
551 | priv->waiting_for_dma = ATA_DMA_ACTIVE; | |
552 | ||
553 | ata_wait_idle(ap); | |
554 | ap->ops->sff_exec_command(ap, &qc->tf); | |
555 | } | |
556 | ||
557 | static void | |
558 | mpc52xx_bmdma_start(struct ata_queued_cmd *qc) | |
559 | { | |
560 | struct ata_port *ap = qc->ap; | |
561 | struct mpc52xx_ata_priv *priv = ap->host->private_data; | |
562 | ||
563 | bcom_set_task_auto_start(priv->dmatsk->tasknum, priv->dmatsk->tasknum); | |
564 | bcom_enable(priv->dmatsk); | |
565 | } | |
566 | ||
567 | static void | |
568 | mpc52xx_bmdma_stop(struct ata_queued_cmd *qc) | |
569 | { | |
570 | struct ata_port *ap = qc->ap; | |
571 | struct mpc52xx_ata_priv *priv = ap->host->private_data; | |
572 | ||
573 | bcom_disable(priv->dmatsk); | |
574 | bcom_ata_reset_bd(priv->dmatsk); | |
575 | priv->waiting_for_dma = 0; | |
576 | ||
577 | /* Check FIFO is OK... */ | |
578 | if (in_8(&priv->ata_regs->fifo_status) & MPC52xx_ATA_FIFOSTAT_ERROR) | |
579 | dev_alert(ap->dev, "%s: FIFO error detected: 0x%02x!\n", | |
580 | __func__, in_8(&priv->ata_regs->fifo_status)); | |
581 | } | |
582 | ||
583 | static u8 | |
584 | mpc52xx_bmdma_status(struct ata_port *ap) | |
585 | { | |
586 | struct mpc52xx_ata_priv *priv = ap->host->private_data; | |
587 | ||
588 | /* Check FIFO is OK... */ | |
589 | if (in_8(&priv->ata_regs->fifo_status) & MPC52xx_ATA_FIFOSTAT_ERROR) { | |
590 | dev_alert(ap->dev, "%s: FIFO error detected: 0x%02x!\n", | |
591 | __func__, in_8(&priv->ata_regs->fifo_status)); | |
592 | return priv->waiting_for_dma | ATA_DMA_ERR; | |
593 | } | |
594 | ||
595 | return priv->waiting_for_dma; | |
596 | } | |
597 | ||
598 | static irqreturn_t | |
599 | mpc52xx_ata_task_irq(int irq, void *vpriv) | |
600 | { | |
601 | struct mpc52xx_ata_priv *priv = vpriv; | |
602 | while (bcom_buffer_done(priv->dmatsk)) | |
603 | bcom_retrieve_buffer(priv->dmatsk, NULL, NULL); | |
604 | ||
605 | priv->waiting_for_dma |= ATA_DMA_INTR; | |
606 | ||
607 | return IRQ_HANDLED; | |
155d2916 SM |
608 | } |
609 | ||
25df73d9 | 610 | static const struct scsi_host_template mpc52xx_ata_sht = { |
68d1d07b | 611 | ATA_PIO_SHT(DRV_NAME), |
155d2916 SM |
612 | }; |
613 | ||
614 | static struct ata_port_operations mpc52xx_ata_port_ops = { | |
77c5fd19 | 615 | .inherits = &ata_bmdma_port_ops, |
5682ed33 | 616 | .sff_dev_select = mpc52xx_ata_dev_select, |
029cfd6b | 617 | .set_piomode = mpc52xx_ata_set_piomode, |
6b61e69e TY |
618 | .set_dmamode = mpc52xx_ata_set_dmamode, |
619 | .bmdma_setup = mpc52xx_bmdma_setup, | |
620 | .bmdma_start = mpc52xx_bmdma_start, | |
621 | .bmdma_stop = mpc52xx_bmdma_stop, | |
622 | .bmdma_status = mpc52xx_bmdma_status, | |
623 | .qc_prep = ata_noop_qc_prep, | |
155d2916 SM |
624 | }; |
625 | ||
0ec24914 GKH |
626 | static int mpc52xx_ata_init_one(struct device *dev, |
627 | struct mpc52xx_ata_priv *priv, | |
628 | unsigned long raw_ata_regs, | |
629 | int mwdma_mask, int udma_mask) | |
155d2916 | 630 | { |
5d728824 TH |
631 | struct ata_host *host; |
632 | struct ata_port *ap; | |
633 | struct ata_ioports *aio; | |
5d728824 TH |
634 | |
635 | host = ata_host_alloc(dev, 1); | |
636 | if (!host) | |
637 | return -ENOMEM; | |
638 | ||
639 | ap = host->ports[0]; | |
640 | ap->flags |= ATA_FLAG_SLAVE_POSS; | |
6b61e69e TY |
641 | ap->pio_mask = ATA_PIO4; |
642 | ap->mwdma_mask = mwdma_mask; | |
643 | ap->udma_mask = udma_mask; | |
5d728824 TH |
644 | ap->ops = &mpc52xx_ata_port_ops; |
645 | host->private_data = priv; | |
646 | ||
647 | aio = &ap->ioaddr; | |
89952d13 | 648 | aio->cmd_addr = NULL; /* Don't have a classic reg block */ |
0d5ff566 TH |
649 | aio->altstatus_addr = &priv->ata_regs->tf_control; |
650 | aio->ctl_addr = &priv->ata_regs->tf_control; | |
651 | aio->data_addr = &priv->ata_regs->tf_data; | |
652 | aio->error_addr = &priv->ata_regs->tf_features; | |
653 | aio->feature_addr = &priv->ata_regs->tf_features; | |
654 | aio->nsect_addr = &priv->ata_regs->tf_sec_count; | |
655 | aio->lbal_addr = &priv->ata_regs->tf_sec_num; | |
656 | aio->lbam_addr = &priv->ata_regs->tf_cyl_low; | |
657 | aio->lbah_addr = &priv->ata_regs->tf_cyl_high; | |
658 | aio->device_addr = &priv->ata_regs->tf_dev_head; | |
659 | aio->status_addr = &priv->ata_regs->tf_command; | |
660 | aio->command_addr = &priv->ata_regs->tf_command; | |
155d2916 | 661 | |
cbcdd875 TH |
662 | ata_port_desc(ap, "ata_regs 0x%lx", raw_ata_regs); |
663 | ||
5d728824 | 664 | /* activate host */ |
c3b28894 | 665 | return ata_host_activate(host, priv->ata_irq, ata_bmdma_interrupt, 0, |
5d728824 | 666 | &mpc52xx_ata_sht); |
155d2916 SM |
667 | } |
668 | ||
155d2916 SM |
669 | /* ======================================================================== */ |
670 | /* OF Platform driver */ | |
671 | /* ======================================================================== */ | |
672 | ||
0ec24914 | 673 | static int mpc52xx_ata_probe(struct platform_device *op) |
155d2916 SM |
674 | { |
675 | unsigned int ipb_freq; | |
676 | struct resource res_mem; | |
6b61e69e | 677 | int ata_irq = 0; |
24dc5f33 | 678 | struct mpc52xx_ata __iomem *ata_regs; |
6b61e69e | 679 | struct mpc52xx_ata_priv *priv = NULL; |
d01159df | 680 | int rv, task_irq; |
6b61e69e TY |
681 | int mwdma_mask = 0, udma_mask = 0; |
682 | const __be32 *prop; | |
683 | int proplen; | |
d01159df | 684 | struct bcom_task *dmatsk; |
155d2916 SM |
685 | |
686 | /* Get ipb frequency */ | |
de06fba6 | 687 | ipb_freq = mpc5xxx_get_bus_frequency(&op->dev); |
155d2916 | 688 | if (!ipb_freq) { |
6b61e69e | 689 | dev_err(&op->dev, "could not determine IPB bus frequency\n"); |
155d2916 SM |
690 | return -ENODEV; |
691 | } | |
692 | ||
6b61e69e TY |
693 | /* Get device base address from device tree, request the region |
694 | * and ioremap it. */ | |
61c7a080 | 695 | rv = of_address_to_resource(op->dev.of_node, 0, &res_mem); |
155d2916 | 696 | if (rv) { |
6b61e69e | 697 | dev_err(&op->dev, "could not determine device base address\n"); |
155d2916 SM |
698 | return rv; |
699 | } | |
700 | ||
24dc5f33 | 701 | if (!devm_request_mem_region(&op->dev, res_mem.start, |
6b61e69e TY |
702 | sizeof(*ata_regs), DRV_NAME)) { |
703 | dev_err(&op->dev, "error requesting register region\n"); | |
704 | return -EBUSY; | |
155d2916 SM |
705 | } |
706 | ||
6b61e69e | 707 | ata_regs = devm_ioremap(&op->dev, res_mem.start, sizeof(*ata_regs)); |
155d2916 | 708 | if (!ata_regs) { |
6b61e69e | 709 | dev_err(&op->dev, "error mapping device registers\n"); |
d01159df | 710 | return -ENOMEM; |
155d2916 SM |
711 | } |
712 | ||
6b61e69e TY |
713 | /* |
714 | * By default, all DMA modes are disabled for the MPC5200. Some | |
715 | * boards don't have the required signals routed to make DMA work. | |
716 | * Also, the MPC5200B has a silicon bug that causes data corruption | |
717 | * with UDMA if it is used at the same time as the LocalPlus bus. | |
718 | * | |
719 | * Instead of trying to guess what modes are usable, check the | |
720 | * ATA device tree node to find out what DMA modes work on the board. | |
721 | * UDMA/MWDMA modes can also be forced by adding "libata.force=<mode>" | |
722 | * to the kernel boot parameters. | |
723 | * | |
724 | * The MPC5200 ATA controller supports MWDMA modes 0, 1 and 2 and | |
725 | * UDMA modes 0, 1 and 2. | |
726 | */ | |
61c7a080 | 727 | prop = of_get_property(op->dev.of_node, "mwdma-mode", &proplen); |
6b61e69e | 728 | if ((prop) && (proplen >= 4)) |
14bdef98 | 729 | mwdma_mask = ATA_MWDMA2 & ((1 << (*prop + 1)) - 1); |
61c7a080 | 730 | prop = of_get_property(op->dev.of_node, "udma-mode", &proplen); |
6b61e69e | 731 | if ((prop) && (proplen >= 4)) |
14bdef98 | 732 | udma_mask = ATA_UDMA2 & ((1 << (*prop + 1)) - 1); |
6b61e69e | 733 | |
61c7a080 | 734 | ata_irq = irq_of_parse_and_map(op->dev.of_node, 0); |
1dea5edc | 735 | if (!ata_irq) { |
6b61e69e TY |
736 | dev_err(&op->dev, "error mapping irq\n"); |
737 | return -EINVAL; | |
738 | } | |
739 | ||
155d2916 | 740 | /* Prepare our private structure */ |
cf369e4e | 741 | priv = devm_kzalloc(&op->dev, sizeof(*priv), GFP_KERNEL); |
155d2916 | 742 | if (!priv) { |
155d2916 | 743 | rv = -ENOMEM; |
d01159df | 744 | goto err1; |
155d2916 SM |
745 | } |
746 | ||
747 | priv->ipb_period = 1000000000 / (ipb_freq / 1000); | |
748 | priv->ata_regs = ata_regs; | |
6b61e69e | 749 | priv->ata_regs_pa = res_mem.start; |
155d2916 SM |
750 | priv->ata_irq = ata_irq; |
751 | priv->csel = -1; | |
6b61e69e TY |
752 | priv->mpc52xx_ata_dma_last_write = -1; |
753 | ||
754 | if (ipb_freq/1000000 == 66) { | |
755 | priv->mdmaspec = mdmaspec66; | |
756 | priv->udmaspec = udmaspec66; | |
757 | } else { | |
758 | priv->mdmaspec = mdmaspec132; | |
759 | priv->udmaspec = udmaspec132; | |
760 | } | |
761 | ||
762 | /* Allocate a BestComm task for DMA */ | |
763 | dmatsk = bcom_ata_init(MAX_DMA_BUFFERS, MAX_DMA_BUFFER_SIZE); | |
764 | if (!dmatsk) { | |
765 | dev_err(&op->dev, "bestcomm initialization failed\n"); | |
766 | rv = -ENOMEM; | |
d01159df | 767 | goto err1; |
6b61e69e TY |
768 | } |
769 | ||
770 | task_irq = bcom_get_task_irq(dmatsk); | |
d01159df | 771 | rv = devm_request_irq(&op->dev, task_irq, &mpc52xx_ata_task_irq, 0, |
6b61e69e | 772 | "ATA task", priv); |
d01159df | 773 | if (rv) { |
6b61e69e | 774 | dev_err(&op->dev, "error requesting DMA IRQ\n"); |
d01159df | 775 | goto err2; |
6b61e69e TY |
776 | } |
777 | priv->dmatsk = dmatsk; | |
155d2916 SM |
778 | |
779 | /* Init the hw */ | |
780 | rv = mpc52xx_ata_hw_init(priv); | |
781 | if (rv) { | |
6b61e69e | 782 | dev_err(&op->dev, "error initializing hardware\n"); |
d01159df | 783 | goto err2; |
155d2916 SM |
784 | } |
785 | ||
786 | /* Register ourselves to libata */ | |
6b61e69e TY |
787 | rv = mpc52xx_ata_init_one(&op->dev, priv, res_mem.start, |
788 | mwdma_mask, udma_mask); | |
155d2916 | 789 | if (rv) { |
6b61e69e | 790 | dev_err(&op->dev, "error registering with ATA layer\n"); |
d01159df | 791 | goto err2; |
155d2916 SM |
792 | } |
793 | ||
155d2916 SM |
794 | return 0; |
795 | ||
d01159df JL |
796 | err2: |
797 | irq_dispose_mapping(task_irq); | |
798 | bcom_ata_release(dmatsk); | |
799 | err1: | |
800 | irq_dispose_mapping(ata_irq); | |
155d2916 SM |
801 | return rv; |
802 | } | |
803 | ||
b5ba32b6 | 804 | static void mpc52xx_ata_remove(struct platform_device *op) |
155d2916 | 805 | { |
37e1b022 BN |
806 | struct ata_host *host = platform_get_drvdata(op); |
807 | struct mpc52xx_ata_priv *priv = host->private_data; | |
6b61e69e | 808 | int task_irq; |
155d2916 | 809 | |
6b61e69e | 810 | /* Deregister the ATA interface */ |
37e1b022 | 811 | ata_platform_remove_one(op); |
6b61e69e TY |
812 | |
813 | /* Clean up DMA */ | |
814 | task_irq = bcom_get_task_irq(priv->dmatsk); | |
815 | irq_dispose_mapping(task_irq); | |
816 | bcom_ata_release(priv->dmatsk); | |
155d2916 | 817 | irq_dispose_mapping(priv->ata_irq); |
155d2916 SM |
818 | } |
819 | ||
58eb8cd5 | 820 | #ifdef CONFIG_PM_SLEEP |
155d2916 | 821 | static int |
2dc11581 | 822 | mpc52xx_ata_suspend(struct platform_device *op, pm_message_t state) |
155d2916 | 823 | { |
d89995db | 824 | struct ata_host *host = platform_get_drvdata(op); |
35142ddb | 825 | |
ec87cf37 SS |
826 | ata_host_suspend(host, state); |
827 | return 0; | |
155d2916 SM |
828 | } |
829 | ||
830 | static int | |
2dc11581 | 831 | mpc52xx_ata_resume(struct platform_device *op) |
155d2916 | 832 | { |
d89995db | 833 | struct ata_host *host = platform_get_drvdata(op); |
35142ddb DP |
834 | struct mpc52xx_ata_priv *priv = host->private_data; |
835 | int rv; | |
836 | ||
837 | rv = mpc52xx_ata_hw_init(priv); | |
838 | if (rv) { | |
6b61e69e | 839 | dev_err(host->dev, "error initializing hardware\n"); |
35142ddb DP |
840 | return rv; |
841 | } | |
842 | ||
843 | ata_host_resume(host); | |
844 | ||
845 | return 0; | |
155d2916 | 846 | } |
155d2916 SM |
847 | #endif |
848 | ||
e3779f6a | 849 | static const struct of_device_id mpc52xx_ata_of_match[] = { |
66ffbe49 GL |
850 | { .compatible = "fsl,mpc5200-ata", }, |
851 | { .compatible = "mpc5200-ata", }, | |
5e776d7b | 852 | { /* sentinel */ } |
155d2916 SM |
853 | }; |
854 | ||
855 | ||
1c48a5c9 | 856 | static struct platform_driver mpc52xx_ata_of_platform_driver = { |
155d2916 | 857 | .probe = mpc52xx_ata_probe, |
b5ba32b6 | 858 | .remove_new = mpc52xx_ata_remove, |
58eb8cd5 | 859 | #ifdef CONFIG_PM_SLEEP |
155d2916 SM |
860 | .suspend = mpc52xx_ata_suspend, |
861 | .resume = mpc52xx_ata_resume, | |
862 | #endif | |
863 | .driver = { | |
864 | .name = DRV_NAME, | |
4018294b | 865 | .of_match_table = mpc52xx_ata_of_match, |
155d2916 SM |
866 | }, |
867 | }; | |
868 | ||
99c8ea3e | 869 | module_platform_driver(mpc52xx_ata_of_platform_driver); |
155d2916 SM |
870 | |
871 | MODULE_AUTHOR("Sylvain Munaut <tnt@246tNt.com>"); | |
872 | MODULE_DESCRIPTION("Freescale MPC52xx IDE/ATA libata driver"); | |
873 | MODULE_LICENSE("GPL"); | |
874 | MODULE_DEVICE_TABLE(of, mpc52xx_ata_of_match); | |
155d2916 | 875 |