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669a5db4 JG |
1 | /* |
2 | * pata-legacy.c - Legacy port PATA/SATA controller driver. | |
3 | * Copyright 2005/2006 Red Hat <alan@redhat.com>, all rights reserved. | |
4 | * | |
5 | * This program is free software; you can redistribute it and/or modify | |
6 | * it under the terms of the GNU General Public License as published by | |
7 | * the Free Software Foundation; either version 2, or (at your option) | |
8 | * any later version. | |
9 | * | |
10 | * This program is distributed in the hope that it will be useful, | |
11 | * but WITHOUT ANY WARRANTY; without even the implied warranty of | |
12 | * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the | |
13 | * GNU General Public License for more details. | |
14 | * | |
15 | * You should have received a copy of the GNU General Public License | |
16 | * along with this program; see the file COPYING. If not, write to | |
17 | * the Free Software Foundation, 675 Mass Ave, Cambridge, MA 02139, USA. | |
18 | * | |
19 | * An ATA driver for the legacy ATA ports. | |
20 | * | |
21 | * Data Sources: | |
22 | * Opti 82C465/82C611 support: Data sheets at opti-inc.com | |
23 | * HT6560 series: | |
24 | * Promise 20230/20620: | |
25 | * http://www.ryston.cz/petr/vlb/pdc20230b.html | |
26 | * http://www.ryston.cz/petr/vlb/pdc20230c.html | |
27 | * http://www.ryston.cz/petr/vlb/pdc20630.html | |
28 | * | |
29 | * Unsupported but docs exist: | |
30 | * Appian/Adaptec AIC25VL01/Cirrus Logic PD7220 | |
31 | * Winbond W83759A | |
32 | * | |
33 | * This driver handles legacy (that is "ISA/VLB side") IDE ports found | |
34 | * on PC class systems. There are three hybrid devices that are exceptions | |
35 | * The Cyrix 5510/5520 where a pre SFF ATA device is on the bridge and | |
36 | * the MPIIX where the tuning is PCI side but the IDE is "ISA side". | |
37 | * | |
38 | * Specific support is included for the ht6560a/ht6560b/opti82c611a/ | |
39 | * opti82c465mv/promise 20230c/20630 | |
40 | * | |
41 | * Use the autospeed and pio_mask options with: | |
42 | * Appian ADI/2 aka CLPD7220 or AIC25VL01. | |
43 | * Use the jumpers, autospeed and set pio_mask to the mode on the jumpers with | |
44 | * Goldstar GM82C711, PIC-1288A-125, UMC 82C871F, Winbond W83759, | |
45 | * Winbond W83759A, Promise PDC20230-B | |
46 | * | |
47 | * For now use autospeed and pio_mask as above with the W83759A. This may | |
48 | * change. | |
49 | * | |
50 | * TODO | |
51 | * Merge existing pata_qdi driver | |
52 | * | |
53 | */ | |
54 | ||
55 | #include <linux/kernel.h> | |
56 | #include <linux/module.h> | |
57 | #include <linux/pci.h> | |
58 | #include <linux/init.h> | |
59 | #include <linux/blkdev.h> | |
60 | #include <linux/delay.h> | |
61 | #include <scsi/scsi_host.h> | |
62 | #include <linux/ata.h> | |
63 | #include <linux/libata.h> | |
64 | #include <linux/platform_device.h> | |
65 | ||
66 | #define DRV_NAME "pata_legacy" | |
cb48cab7 | 67 | #define DRV_VERSION "0.5.4" |
669a5db4 JG |
68 | |
69 | #define NR_HOST 6 | |
70 | ||
71 | static int legacy_port[NR_HOST] = { 0x1f0, 0x170, 0x1e8, 0x168, 0x1e0, 0x160 }; | |
8b966ddd | 72 | static int legacy_irq[NR_HOST] = { 14, 15, 11, 10, 8, 12 }; |
669a5db4 JG |
73 | |
74 | struct legacy_data { | |
75 | unsigned long timing; | |
76 | u8 clock[2]; | |
77 | u8 last; | |
78 | int fast; | |
79 | struct platform_device *platform_dev; | |
80 | ||
81 | }; | |
82 | ||
83 | static struct legacy_data legacy_data[NR_HOST]; | |
84 | static struct ata_host *legacy_host[NR_HOST]; | |
85 | static int nr_legacy_host; | |
86 | ||
87 | ||
88 | static int probe_all; /* Set to check all ISA port ranges */ | |
89 | static int ht6560a; /* HT 6560A on primary 1, secondary 2, both 3 */ | |
90 | static int ht6560b; /* HT 6560A on primary 1, secondary 2, both 3 */ | |
91 | static int opti82c611a; /* Opti82c611A on primary 1, secondary 2, both 3 */ | |
f834e49f | 92 | static int opti82c46x; /* Opti 82c465MV present (pri/sec autodetect) */ |
669a5db4 JG |
93 | static int autospeed; /* Chip present which snoops speed changes */ |
94 | static int pio_mask = 0x1F; /* PIO range for autospeed devices */ | |
f834e49f | 95 | static int iordy_mask = 0xFFFFFFFF; /* Use iordy if available */ |
669a5db4 JG |
96 | |
97 | /** | |
98 | * legacy_set_mode - mode setting | |
99 | * @ap: IDE interface | |
b229a7b0 | 100 | * @unused: Device that failed when error is returned |
669a5db4 JG |
101 | * |
102 | * Use a non standard set_mode function. We don't want to be tuned. | |
103 | * | |
104 | * The BIOS configured everything. Our job is not to fiddle. Just use | |
105 | * whatever PIO the hardware is using and leave it at that. When we | |
106 | * get some kind of nice user driven API for control then we can | |
107 | * expand on this as per hdparm in the base kernel. | |
108 | */ | |
109 | ||
b229a7b0 | 110 | static int legacy_set_mode(struct ata_port *ap, struct ata_device **unused) |
669a5db4 JG |
111 | { |
112 | int i; | |
113 | ||
114 | for (i = 0; i < ATA_MAX_DEVICES; i++) { | |
115 | struct ata_device *dev = &ap->device[i]; | |
116 | if (ata_dev_enabled(dev)) { | |
f834e49f | 117 | ata_dev_printk(dev, KERN_INFO, "configured for PIO\n"); |
669a5db4 JG |
118 | dev->pio_mode = XFER_PIO_0; |
119 | dev->xfer_mode = XFER_PIO_0; | |
120 | dev->xfer_shift = ATA_SHIFT_PIO; | |
121 | dev->flags |= ATA_DFLAG_PIO; | |
122 | } | |
123 | } | |
b229a7b0 | 124 | return 0; |
669a5db4 JG |
125 | } |
126 | ||
127 | static struct scsi_host_template legacy_sht = { | |
128 | .module = THIS_MODULE, | |
129 | .name = DRV_NAME, | |
130 | .ioctl = ata_scsi_ioctl, | |
131 | .queuecommand = ata_scsi_queuecmd, | |
132 | .can_queue = ATA_DEF_QUEUE, | |
133 | .this_id = ATA_SHT_THIS_ID, | |
134 | .sg_tablesize = LIBATA_MAX_PRD, | |
669a5db4 JG |
135 | .cmd_per_lun = ATA_SHT_CMD_PER_LUN, |
136 | .emulated = ATA_SHT_EMULATED, | |
137 | .use_clustering = ATA_SHT_USE_CLUSTERING, | |
138 | .proc_name = DRV_NAME, | |
139 | .dma_boundary = ATA_DMA_BOUNDARY, | |
140 | .slave_configure = ata_scsi_slave_config, | |
afdfe899 | 141 | .slave_destroy = ata_scsi_slave_destroy, |
669a5db4 JG |
142 | .bios_param = ata_std_bios_param, |
143 | }; | |
144 | ||
145 | /* | |
146 | * These ops are used if the user indicates the hardware | |
147 | * snoops the commands to decide on the mode and handles the | |
148 | * mode selection "magically" itself. Several legacy controllers | |
149 | * do this. The mode range can be set if it is not 0x1F by setting | |
150 | * pio_mask as well. | |
151 | */ | |
152 | ||
153 | static struct ata_port_operations simple_port_ops = { | |
154 | .port_disable = ata_port_disable, | |
155 | .tf_load = ata_tf_load, | |
156 | .tf_read = ata_tf_read, | |
157 | .check_status = ata_check_status, | |
158 | .exec_command = ata_exec_command, | |
159 | .dev_select = ata_std_dev_select, | |
160 | ||
161 | .freeze = ata_bmdma_freeze, | |
162 | .thaw = ata_bmdma_thaw, | |
163 | .error_handler = ata_bmdma_error_handler, | |
164 | .post_internal_cmd = ata_bmdma_post_internal_cmd, | |
165 | ||
166 | .qc_prep = ata_qc_prep, | |
167 | .qc_issue = ata_qc_issue_prot, | |
bda30288 | 168 | |
0d5ff566 | 169 | .data_xfer = ata_data_xfer_noirq, |
669a5db4 JG |
170 | |
171 | .irq_handler = ata_interrupt, | |
172 | .irq_clear = ata_bmdma_irq_clear, | |
246ce3b6 AI |
173 | .irq_on = ata_irq_on, |
174 | .irq_ack = ata_irq_ack, | |
669a5db4 JG |
175 | |
176 | .port_start = ata_port_start, | |
669a5db4 JG |
177 | }; |
178 | ||
179 | static struct ata_port_operations legacy_port_ops = { | |
180 | .set_mode = legacy_set_mode, | |
181 | ||
182 | .port_disable = ata_port_disable, | |
183 | .tf_load = ata_tf_load, | |
184 | .tf_read = ata_tf_read, | |
185 | .check_status = ata_check_status, | |
186 | .exec_command = ata_exec_command, | |
187 | .dev_select = ata_std_dev_select, | |
188 | ||
bf7551c4 JG |
189 | .freeze = ata_bmdma_freeze, |
190 | .thaw = ata_bmdma_thaw, | |
669a5db4 | 191 | .error_handler = ata_bmdma_error_handler, |
bf7551c4 | 192 | .post_internal_cmd = ata_bmdma_post_internal_cmd, |
669a5db4 JG |
193 | |
194 | .qc_prep = ata_qc_prep, | |
195 | .qc_issue = ata_qc_issue_prot, | |
bda30288 | 196 | |
0d5ff566 | 197 | .data_xfer = ata_data_xfer_noirq, |
669a5db4 JG |
198 | |
199 | .irq_handler = ata_interrupt, | |
200 | .irq_clear = ata_bmdma_irq_clear, | |
246ce3b6 AI |
201 | .irq_on = ata_irq_on, |
202 | .irq_ack = ata_irq_ack, | |
669a5db4 JG |
203 | |
204 | .port_start = ata_port_start, | |
669a5db4 JG |
205 | }; |
206 | ||
207 | /* | |
208 | * Promise 20230C and 20620 support | |
209 | * | |
210 | * This controller supports PIO0 to PIO2. We set PIO timings conservatively to | |
211 | * allow for 50MHz Vesa Local Bus. The 20620 DMA support is weird being DMA to | |
212 | * controller and PIO'd to the host and not supported. | |
213 | */ | |
214 | ||
215 | static void pdc20230_set_piomode(struct ata_port *ap, struct ata_device *adev) | |
216 | { | |
217 | int tries = 5; | |
218 | int pio = adev->pio_mode - XFER_PIO_0; | |
219 | u8 rt; | |
220 | unsigned long flags; | |
85cd7251 | 221 | |
669a5db4 | 222 | /* Safe as UP only. Force I/Os to occur together */ |
85cd7251 | 223 | |
669a5db4 | 224 | local_irq_save(flags); |
85cd7251 | 225 | |
669a5db4 JG |
226 | /* Unlock the control interface */ |
227 | do | |
228 | { | |
229 | inb(0x1F5); | |
230 | outb(inb(0x1F2) | 0x80, 0x1F2); | |
231 | inb(0x1F2); | |
232 | inb(0x3F6); | |
233 | inb(0x3F6); | |
234 | inb(0x1F2); | |
235 | inb(0x1F2); | |
236 | } | |
237 | while((inb(0x1F2) & 0x80) && --tries); | |
238 | ||
239 | local_irq_restore(flags); | |
85cd7251 | 240 | |
669a5db4 JG |
241 | outb(inb(0x1F4) & 0x07, 0x1F4); |
242 | ||
243 | rt = inb(0x1F3); | |
244 | rt &= 0x07 << (3 * adev->devno); | |
245 | if (pio) | |
246 | rt |= (1 + 3 * pio) << (3 * adev->devno); | |
247 | ||
248 | udelay(100); | |
249 | outb(inb(0x1F2) | 0x01, 0x1F2); | |
250 | udelay(100); | |
251 | inb(0x1F5); | |
252 | ||
253 | } | |
254 | ||
255 | static void pdc_data_xfer_vlb(struct ata_device *adev, unsigned char *buf, unsigned int buflen, int write_data) | |
256 | { | |
257 | struct ata_port *ap = adev->ap; | |
258 | int slop = buflen & 3; | |
259 | unsigned long flags; | |
260 | ||
261 | if (ata_id_has_dword_io(adev->id)) { | |
262 | local_irq_save(flags); | |
263 | ||
264 | /* Perform the 32bit I/O synchronization sequence */ | |
0d5ff566 TH |
265 | ioread8(ap->ioaddr.nsect_addr); |
266 | ioread8(ap->ioaddr.nsect_addr); | |
267 | ioread8(ap->ioaddr.nsect_addr); | |
669a5db4 JG |
268 | |
269 | /* Now the data */ | |
270 | ||
271 | if (write_data) | |
0d5ff566 | 272 | iowrite32_rep(ap->ioaddr.data_addr, buf, buflen >> 2); |
669a5db4 | 273 | else |
0d5ff566 | 274 | ioread32_rep(ap->ioaddr.data_addr, buf, buflen >> 2); |
669a5db4 JG |
275 | |
276 | if (unlikely(slop)) { | |
277 | u32 pad; | |
278 | if (write_data) { | |
279 | memcpy(&pad, buf + buflen - slop, slop); | |
0d5ff566 TH |
280 | pad = le32_to_cpu(pad); |
281 | iowrite32(pad, ap->ioaddr.data_addr); | |
669a5db4 | 282 | } else { |
0d5ff566 TH |
283 | pad = ioread32(ap->ioaddr.data_addr); |
284 | pad = cpu_to_le16(pad); | |
669a5db4 JG |
285 | memcpy(buf + buflen - slop, &pad, slop); |
286 | } | |
287 | } | |
288 | local_irq_restore(flags); | |
289 | } | |
290 | else | |
0d5ff566 | 291 | ata_data_xfer_noirq(adev, buf, buflen, write_data); |
669a5db4 JG |
292 | } |
293 | ||
294 | static struct ata_port_operations pdc20230_port_ops = { | |
295 | .set_piomode = pdc20230_set_piomode, | |
296 | ||
297 | .port_disable = ata_port_disable, | |
298 | .tf_load = ata_tf_load, | |
299 | .tf_read = ata_tf_read, | |
300 | .check_status = ata_check_status, | |
301 | .exec_command = ata_exec_command, | |
302 | .dev_select = ata_std_dev_select, | |
303 | ||
bf7551c4 JG |
304 | .freeze = ata_bmdma_freeze, |
305 | .thaw = ata_bmdma_thaw, | |
669a5db4 | 306 | .error_handler = ata_bmdma_error_handler, |
bf7551c4 | 307 | .post_internal_cmd = ata_bmdma_post_internal_cmd, |
669a5db4 JG |
308 | |
309 | .qc_prep = ata_qc_prep, | |
310 | .qc_issue = ata_qc_issue_prot, | |
bda30288 | 311 | |
669a5db4 JG |
312 | .data_xfer = pdc_data_xfer_vlb, |
313 | ||
314 | .irq_handler = ata_interrupt, | |
315 | .irq_clear = ata_bmdma_irq_clear, | |
246ce3b6 AI |
316 | .irq_on = ata_irq_on, |
317 | .irq_ack = ata_irq_ack, | |
669a5db4 JG |
318 | |
319 | .port_start = ata_port_start, | |
669a5db4 JG |
320 | }; |
321 | ||
322 | /* | |
323 | * Holtek 6560A support | |
324 | * | |
325 | * This controller supports PIO0 to PIO2 (no IORDY even though higher timings | |
326 | * can be loaded). | |
327 | */ | |
328 | ||
329 | static void ht6560a_set_piomode(struct ata_port *ap, struct ata_device *adev) | |
330 | { | |
331 | u8 active, recover; | |
332 | struct ata_timing t; | |
333 | ||
334 | /* Get the timing data in cycles. For now play safe at 50Mhz */ | |
335 | ata_timing_compute(adev, adev->pio_mode, &t, 20000, 1000); | |
336 | ||
337 | active = FIT(t.active, 2, 15); | |
338 | recover = FIT(t.recover, 4, 15); | |
339 | ||
340 | inb(0x3E6); | |
341 | inb(0x3E6); | |
342 | inb(0x3E6); | |
343 | inb(0x3E6); | |
344 | ||
0d5ff566 TH |
345 | iowrite8(recover << 4 | active, ap->ioaddr.device_addr); |
346 | ioread8(ap->ioaddr.status_addr); | |
669a5db4 JG |
347 | } |
348 | ||
349 | static struct ata_port_operations ht6560a_port_ops = { | |
350 | .set_piomode = ht6560a_set_piomode, | |
351 | ||
352 | .port_disable = ata_port_disable, | |
353 | .tf_load = ata_tf_load, | |
354 | .tf_read = ata_tf_read, | |
355 | .check_status = ata_check_status, | |
356 | .exec_command = ata_exec_command, | |
357 | .dev_select = ata_std_dev_select, | |
358 | ||
bf7551c4 JG |
359 | .freeze = ata_bmdma_freeze, |
360 | .thaw = ata_bmdma_thaw, | |
669a5db4 | 361 | .error_handler = ata_bmdma_error_handler, |
bf7551c4 | 362 | .post_internal_cmd = ata_bmdma_post_internal_cmd, |
669a5db4 JG |
363 | |
364 | .qc_prep = ata_qc_prep, | |
365 | .qc_issue = ata_qc_issue_prot, | |
bda30288 | 366 | |
0d5ff566 | 367 | .data_xfer = ata_data_xfer, /* Check vlb/noirq */ |
669a5db4 JG |
368 | |
369 | .irq_handler = ata_interrupt, | |
370 | .irq_clear = ata_bmdma_irq_clear, | |
246ce3b6 AI |
371 | .irq_on = ata_irq_on, |
372 | .irq_ack = ata_irq_ack, | |
669a5db4 JG |
373 | |
374 | .port_start = ata_port_start, | |
669a5db4 JG |
375 | }; |
376 | ||
377 | /* | |
378 | * Holtek 6560B support | |
379 | * | |
380 | * This controller supports PIO0 to PIO4. We honour the BIOS/jumper FIFO setting | |
381 | * unless we see an ATAPI device in which case we force it off. | |
382 | * | |
383 | * FIXME: need to implement 2nd channel support. | |
384 | */ | |
385 | ||
386 | static void ht6560b_set_piomode(struct ata_port *ap, struct ata_device *adev) | |
387 | { | |
388 | u8 active, recover; | |
389 | struct ata_timing t; | |
390 | ||
391 | /* Get the timing data in cycles. For now play safe at 50Mhz */ | |
392 | ata_timing_compute(adev, adev->pio_mode, &t, 20000, 1000); | |
393 | ||
394 | active = FIT(t.active, 2, 15); | |
395 | recover = FIT(t.recover, 2, 16); | |
396 | recover &= 0x15; | |
397 | ||
398 | inb(0x3E6); | |
399 | inb(0x3E6); | |
400 | inb(0x3E6); | |
401 | inb(0x3E6); | |
402 | ||
0d5ff566 | 403 | iowrite8(recover << 4 | active, ap->ioaddr.device_addr); |
669a5db4 JG |
404 | |
405 | if (adev->class != ATA_DEV_ATA) { | |
406 | u8 rconf = inb(0x3E6); | |
407 | if (rconf & 0x24) { | |
408 | rconf &= ~ 0x24; | |
409 | outb(rconf, 0x3E6); | |
410 | } | |
411 | } | |
0d5ff566 | 412 | ioread8(ap->ioaddr.status_addr); |
669a5db4 JG |
413 | } |
414 | ||
415 | static struct ata_port_operations ht6560b_port_ops = { | |
416 | .set_piomode = ht6560b_set_piomode, | |
417 | ||
418 | .port_disable = ata_port_disable, | |
419 | .tf_load = ata_tf_load, | |
420 | .tf_read = ata_tf_read, | |
421 | .check_status = ata_check_status, | |
422 | .exec_command = ata_exec_command, | |
423 | .dev_select = ata_std_dev_select, | |
424 | ||
bf7551c4 JG |
425 | .freeze = ata_bmdma_freeze, |
426 | .thaw = ata_bmdma_thaw, | |
669a5db4 | 427 | .error_handler = ata_bmdma_error_handler, |
bf7551c4 | 428 | .post_internal_cmd = ata_bmdma_post_internal_cmd, |
669a5db4 JG |
429 | |
430 | .qc_prep = ata_qc_prep, | |
431 | .qc_issue = ata_qc_issue_prot, | |
bda30288 | 432 | |
0d5ff566 | 433 | .data_xfer = ata_data_xfer, /* FIXME: Check 32bit and noirq */ |
669a5db4 JG |
434 | |
435 | .irq_handler = ata_interrupt, | |
436 | .irq_clear = ata_bmdma_irq_clear, | |
246ce3b6 AI |
437 | .irq_on = ata_irq_on, |
438 | .irq_ack = ata_irq_ack, | |
669a5db4 JG |
439 | |
440 | .port_start = ata_port_start, | |
669a5db4 JG |
441 | }; |
442 | ||
443 | /* | |
444 | * Opti core chipset helpers | |
445 | */ | |
85cd7251 | 446 | |
669a5db4 JG |
447 | /** |
448 | * opti_syscfg - read OPTI chipset configuration | |
449 | * @reg: Configuration register to read | |
450 | * | |
451 | * Returns the value of an OPTI system board configuration register. | |
452 | */ | |
453 | ||
454 | static u8 opti_syscfg(u8 reg) | |
455 | { | |
456 | unsigned long flags; | |
457 | u8 r; | |
85cd7251 | 458 | |
669a5db4 JG |
459 | /* Uniprocessor chipset and must force cycles adjancent */ |
460 | local_irq_save(flags); | |
461 | outb(reg, 0x22); | |
462 | r = inb(0x24); | |
463 | local_irq_restore(flags); | |
464 | return r; | |
465 | } | |
466 | ||
467 | /* | |
468 | * Opti 82C611A | |
469 | * | |
470 | * This controller supports PIO0 to PIO3. | |
471 | */ | |
472 | ||
473 | static void opti82c611a_set_piomode(struct ata_port *ap, struct ata_device *adev) | |
474 | { | |
475 | u8 active, recover, setup; | |
476 | struct ata_timing t; | |
477 | struct ata_device *pair = ata_dev_pair(adev); | |
478 | int clock; | |
479 | int khz[4] = { 50000, 40000, 33000, 25000 }; | |
480 | u8 rc; | |
481 | ||
482 | /* Enter configuration mode */ | |
0d5ff566 TH |
483 | ioread16(ap->ioaddr.error_addr); |
484 | ioread16(ap->ioaddr.error_addr); | |
485 | iowrite8(3, ap->ioaddr.nsect_addr); | |
669a5db4 JG |
486 | |
487 | /* Read VLB clock strapping */ | |
0d5ff566 | 488 | clock = 1000000000 / khz[ioread8(ap->ioaddr.lbah_addr) & 0x03]; |
669a5db4 JG |
489 | |
490 | /* Get the timing data in cycles */ | |
491 | ata_timing_compute(adev, adev->pio_mode, &t, clock, 1000); | |
492 | ||
493 | /* Setup timing is shared */ | |
494 | if (pair) { | |
495 | struct ata_timing tp; | |
496 | ata_timing_compute(pair, pair->pio_mode, &tp, clock, 1000); | |
497 | ||
498 | ata_timing_merge(&t, &tp, &t, ATA_TIMING_SETUP); | |
499 | } | |
500 | ||
501 | active = FIT(t.active, 2, 17) - 2; | |
502 | recover = FIT(t.recover, 1, 16) - 1; | |
503 | setup = FIT(t.setup, 1, 4) - 1; | |
504 | ||
505 | /* Select the right timing bank for write timing */ | |
0d5ff566 | 506 | rc = ioread8(ap->ioaddr.lbal_addr); |
669a5db4 JG |
507 | rc &= 0x7F; |
508 | rc |= (adev->devno << 7); | |
0d5ff566 | 509 | iowrite8(rc, ap->ioaddr.lbal_addr); |
669a5db4 JG |
510 | |
511 | /* Write the timings */ | |
0d5ff566 | 512 | iowrite8(active << 4 | recover, ap->ioaddr.error_addr); |
669a5db4 JG |
513 | |
514 | /* Select the right bank for read timings, also | |
515 | load the shared timings for address */ | |
0d5ff566 | 516 | rc = ioread8(ap->ioaddr.device_addr); |
669a5db4 JG |
517 | rc &= 0xC0; |
518 | rc |= adev->devno; /* Index select */ | |
519 | rc |= (setup << 4) | 0x04; | |
0d5ff566 | 520 | iowrite8(rc, ap->ioaddr.device_addr); |
669a5db4 JG |
521 | |
522 | /* Load the read timings */ | |
0d5ff566 | 523 | iowrite8(active << 4 | recover, ap->ioaddr.data_addr); |
669a5db4 JG |
524 | |
525 | /* Ensure the timing register mode is right */ | |
0d5ff566 | 526 | rc = ioread8(ap->ioaddr.lbal_addr); |
669a5db4 JG |
527 | rc &= 0x73; |
528 | rc |= 0x84; | |
0d5ff566 | 529 | iowrite8(rc, ap->ioaddr.lbal_addr); |
669a5db4 JG |
530 | |
531 | /* Exit command mode */ | |
0d5ff566 | 532 | iowrite8(0x83, ap->ioaddr.nsect_addr); |
669a5db4 JG |
533 | } |
534 | ||
535 | ||
536 | static struct ata_port_operations opti82c611a_port_ops = { | |
537 | .set_piomode = opti82c611a_set_piomode, | |
538 | ||
539 | .port_disable = ata_port_disable, | |
540 | .tf_load = ata_tf_load, | |
541 | .tf_read = ata_tf_read, | |
542 | .check_status = ata_check_status, | |
543 | .exec_command = ata_exec_command, | |
544 | .dev_select = ata_std_dev_select, | |
545 | ||
bf7551c4 JG |
546 | .freeze = ata_bmdma_freeze, |
547 | .thaw = ata_bmdma_thaw, | |
669a5db4 | 548 | .error_handler = ata_bmdma_error_handler, |
bf7551c4 | 549 | .post_internal_cmd = ata_bmdma_post_internal_cmd, |
669a5db4 JG |
550 | |
551 | .qc_prep = ata_qc_prep, | |
552 | .qc_issue = ata_qc_issue_prot, | |
bda30288 | 553 | |
0d5ff566 | 554 | .data_xfer = ata_data_xfer, |
669a5db4 JG |
555 | |
556 | .irq_handler = ata_interrupt, | |
557 | .irq_clear = ata_bmdma_irq_clear, | |
246ce3b6 AI |
558 | .irq_on = ata_irq_on, |
559 | .irq_ack = ata_irq_ack, | |
669a5db4 JG |
560 | |
561 | .port_start = ata_port_start, | |
669a5db4 JG |
562 | }; |
563 | ||
564 | /* | |
565 | * Opti 82C465MV | |
566 | * | |
567 | * This controller supports PIO0 to PIO3. Unlike the 611A the MVB | |
568 | * version is dual channel but doesn't have a lot of unique registers. | |
569 | */ | |
570 | ||
571 | static void opti82c46x_set_piomode(struct ata_port *ap, struct ata_device *adev) | |
572 | { | |
573 | u8 active, recover, setup; | |
574 | struct ata_timing t; | |
575 | struct ata_device *pair = ata_dev_pair(adev); | |
576 | int clock; | |
577 | int khz[4] = { 50000, 40000, 33000, 25000 }; | |
578 | u8 rc; | |
579 | u8 sysclk; | |
580 | ||
581 | /* Get the clock */ | |
582 | sysclk = opti_syscfg(0xAC) & 0xC0; /* BIOS set */ | |
583 | ||
584 | /* Enter configuration mode */ | |
0d5ff566 TH |
585 | ioread16(ap->ioaddr.error_addr); |
586 | ioread16(ap->ioaddr.error_addr); | |
587 | iowrite8(3, ap->ioaddr.nsect_addr); | |
669a5db4 JG |
588 | |
589 | /* Read VLB clock strapping */ | |
590 | clock = 1000000000 / khz[sysclk]; | |
591 | ||
592 | /* Get the timing data in cycles */ | |
593 | ata_timing_compute(adev, adev->pio_mode, &t, clock, 1000); | |
594 | ||
595 | /* Setup timing is shared */ | |
596 | if (pair) { | |
597 | struct ata_timing tp; | |
598 | ata_timing_compute(pair, pair->pio_mode, &tp, clock, 1000); | |
599 | ||
600 | ata_timing_merge(&t, &tp, &t, ATA_TIMING_SETUP); | |
601 | } | |
602 | ||
603 | active = FIT(t.active, 2, 17) - 2; | |
604 | recover = FIT(t.recover, 1, 16) - 1; | |
605 | setup = FIT(t.setup, 1, 4) - 1; | |
606 | ||
607 | /* Select the right timing bank for write timing */ | |
0d5ff566 | 608 | rc = ioread8(ap->ioaddr.lbal_addr); |
669a5db4 JG |
609 | rc &= 0x7F; |
610 | rc |= (adev->devno << 7); | |
0d5ff566 | 611 | iowrite8(rc, ap->ioaddr.lbal_addr); |
669a5db4 JG |
612 | |
613 | /* Write the timings */ | |
0d5ff566 | 614 | iowrite8(active << 4 | recover, ap->ioaddr.error_addr); |
669a5db4 JG |
615 | |
616 | /* Select the right bank for read timings, also | |
617 | load the shared timings for address */ | |
0d5ff566 | 618 | rc = ioread8(ap->ioaddr.device_addr); |
669a5db4 JG |
619 | rc &= 0xC0; |
620 | rc |= adev->devno; /* Index select */ | |
621 | rc |= (setup << 4) | 0x04; | |
0d5ff566 | 622 | iowrite8(rc, ap->ioaddr.device_addr); |
669a5db4 JG |
623 | |
624 | /* Load the read timings */ | |
0d5ff566 | 625 | iowrite8(active << 4 | recover, ap->ioaddr.data_addr); |
669a5db4 JG |
626 | |
627 | /* Ensure the timing register mode is right */ | |
0d5ff566 | 628 | rc = ioread8(ap->ioaddr.lbal_addr); |
669a5db4 JG |
629 | rc &= 0x73; |
630 | rc |= 0x84; | |
0d5ff566 | 631 | iowrite8(rc, ap->ioaddr.lbal_addr); |
669a5db4 JG |
632 | |
633 | /* Exit command mode */ | |
0d5ff566 | 634 | iowrite8(0x83, ap->ioaddr.nsect_addr); |
669a5db4 JG |
635 | |
636 | /* We need to know this for quad device on the MVB */ | |
637 | ap->host->private_data = ap; | |
638 | } | |
639 | ||
640 | /** | |
641 | * opt82c465mv_qc_issue_prot - command issue | |
642 | * @qc: command pending | |
643 | * | |
644 | * Called when the libata layer is about to issue a command. We wrap | |
645 | * this interface so that we can load the correct ATA timings. The | |
646 | * MVB has a single set of timing registers and these are shared | |
647 | * across channels. As there are two registers we really ought to | |
648 | * track the last two used values as a sort of register window. For | |
649 | * now we just reload on a channel switch. On the single channel | |
650 | * setup this condition never fires so we do nothing extra. | |
651 | * | |
652 | * FIXME: dual channel needs ->serialize support | |
653 | */ | |
654 | ||
655 | static unsigned int opti82c46x_qc_issue_prot(struct ata_queued_cmd *qc) | |
656 | { | |
657 | struct ata_port *ap = qc->ap; | |
658 | struct ata_device *adev = qc->dev; | |
659 | ||
660 | /* If timings are set and for the wrong channel (2nd test is | |
661 | due to a libata shortcoming and will eventually go I hope) */ | |
662 | if (ap->host->private_data != ap->host | |
663 | && ap->host->private_data != NULL) | |
664 | opti82c46x_set_piomode(ap, adev); | |
665 | ||
666 | return ata_qc_issue_prot(qc); | |
667 | } | |
668 | ||
669 | static struct ata_port_operations opti82c46x_port_ops = { | |
670 | .set_piomode = opti82c46x_set_piomode, | |
671 | ||
672 | .port_disable = ata_port_disable, | |
673 | .tf_load = ata_tf_load, | |
674 | .tf_read = ata_tf_read, | |
675 | .check_status = ata_check_status, | |
676 | .exec_command = ata_exec_command, | |
677 | .dev_select = ata_std_dev_select, | |
678 | ||
bf7551c4 JG |
679 | .freeze = ata_bmdma_freeze, |
680 | .thaw = ata_bmdma_thaw, | |
669a5db4 | 681 | .error_handler = ata_bmdma_error_handler, |
bf7551c4 | 682 | .post_internal_cmd = ata_bmdma_post_internal_cmd, |
669a5db4 JG |
683 | |
684 | .qc_prep = ata_qc_prep, | |
685 | .qc_issue = opti82c46x_qc_issue_prot, | |
bda30288 | 686 | |
0d5ff566 | 687 | .data_xfer = ata_data_xfer, |
669a5db4 JG |
688 | |
689 | .irq_handler = ata_interrupt, | |
690 | .irq_clear = ata_bmdma_irq_clear, | |
246ce3b6 AI |
691 | .irq_on = ata_irq_on, |
692 | .irq_ack = ata_irq_ack, | |
669a5db4 JG |
693 | |
694 | .port_start = ata_port_start, | |
669a5db4 JG |
695 | }; |
696 | ||
697 | ||
698 | /** | |
699 | * legacy_init_one - attach a legacy interface | |
700 | * @port: port number | |
701 | * @io: I/O port start | |
702 | * @ctrl: control port | |
703 | * @irq: interrupt line | |
704 | * | |
705 | * Register an ISA bus IDE interface. Such interfaces are PIO and we | |
706 | * assume do not support IRQ sharing. | |
707 | */ | |
708 | ||
709 | static __init int legacy_init_one(int port, unsigned long io, unsigned long ctrl, int irq) | |
710 | { | |
711 | struct legacy_data *ld = &legacy_data[nr_legacy_host]; | |
712 | struct ata_probe_ent ae; | |
713 | struct platform_device *pdev; | |
669a5db4 | 714 | struct ata_port_operations *ops = &legacy_port_ops; |
0d5ff566 | 715 | void __iomem *io_addr, *ctrl_addr; |
669a5db4 JG |
716 | int pio_modes = pio_mask; |
717 | u32 mask = (1 << port); | |
f834e49f | 718 | u32 iordy = (iordy_mask & mask) ? 0: ATA_FLAG_NO_IORDY; |
24dc5f33 | 719 | int ret; |
669a5db4 JG |
720 | |
721 | pdev = platform_device_register_simple(DRV_NAME, nr_legacy_host, NULL, 0); | |
24dc5f33 TH |
722 | if (IS_ERR(pdev)) |
723 | return PTR_ERR(pdev); | |
724 | ||
725 | ret = -EBUSY; | |
726 | if (devm_request_region(&pdev->dev, io, 8, "pata_legacy") == NULL || | |
727 | devm_request_region(&pdev->dev, ctrl, 1, "pata_legacy") == NULL) | |
728 | goto fail; | |
669a5db4 | 729 | |
0d5ff566 TH |
730 | ret = -ENOMEM; |
731 | io_addr = devm_ioport_map(&pdev->dev, io, 8); | |
732 | ctrl_addr = devm_ioport_map(&pdev->dev, ctrl, 1); | |
733 | if (!io_addr || !ctrl_addr) | |
734 | goto fail; | |
735 | ||
669a5db4 JG |
736 | if (ht6560a & mask) { |
737 | ops = &ht6560a_port_ops; | |
738 | pio_modes = 0x07; | |
f834e49f | 739 | iordy = ATA_FLAG_NO_IORDY; |
669a5db4 JG |
740 | } |
741 | if (ht6560b & mask) { | |
742 | ops = &ht6560b_port_ops; | |
743 | pio_modes = 0x1F; | |
744 | } | |
745 | if (opti82c611a & mask) { | |
746 | ops = &opti82c611a_port_ops; | |
747 | pio_modes = 0x0F; | |
748 | } | |
749 | if (opti82c46x & mask) { | |
750 | ops = &opti82c46x_port_ops; | |
751 | pio_modes = 0x0F; | |
752 | } | |
753 | ||
754 | /* Probe for automatically detectable controllers */ | |
85cd7251 | 755 | |
669a5db4 JG |
756 | if (io == 0x1F0 && ops == &legacy_port_ops) { |
757 | unsigned long flags; | |
758 | ||
759 | local_irq_save(flags); | |
760 | ||
761 | /* Probes */ | |
762 | inb(0x1F5); | |
763 | outb(inb(0x1F2) | 0x80, 0x1F2); | |
764 | inb(0x1F2); | |
765 | inb(0x3F6); | |
766 | inb(0x3F6); | |
767 | inb(0x1F2); | |
768 | inb(0x1F2); | |
769 | ||
770 | if ((inb(0x1F2) & 0x80) == 0) { | |
771 | /* PDC20230c or 20630 ? */ | |
772 | printk(KERN_INFO "PDC20230-C/20630 VLB ATA controller detected.\n"); | |
773 | pio_modes = 0x07; | |
774 | ops = &pdc20230_port_ops; | |
f834e49f | 775 | iordy = ATA_FLAG_NO_IORDY; |
669a5db4 JG |
776 | udelay(100); |
777 | inb(0x1F5); | |
778 | } else { | |
779 | outb(0x55, 0x1F2); | |
780 | inb(0x1F2); | |
781 | inb(0x1F2); | |
782 | if (inb(0x1F2) == 0x00) { | |
783 | printk(KERN_INFO "PDC20230-B VLB ATA controller detected.\n"); | |
784 | } | |
785 | } | |
786 | local_irq_restore(flags); | |
787 | } | |
788 | ||
789 | ||
790 | /* Chip does mode setting by command snooping */ | |
791 | if (ops == &legacy_port_ops && (autospeed & mask)) | |
792 | ops = &simple_port_ops; | |
f834e49f | 793 | |
669a5db4 JG |
794 | memset(&ae, 0, sizeof(struct ata_probe_ent)); |
795 | INIT_LIST_HEAD(&ae.node); | |
796 | ae.dev = &pdev->dev; | |
797 | ae.port_ops = ops; | |
798 | ae.sht = &legacy_sht; | |
799 | ae.n_ports = 1; | |
800 | ae.pio_mask = pio_modes; | |
801 | ae.irq = irq; | |
802 | ae.irq_flags = 0; | |
f834e49f | 803 | ae.port_flags = ATA_FLAG_SLAVE_POSS|ATA_FLAG_SRST|iordy; |
0d5ff566 TH |
804 | ae.port[0].cmd_addr = io_addr; |
805 | ae.port[0].altstatus_addr = ctrl_addr; | |
806 | ae.port[0].ctl_addr = ctrl_addr; | |
669a5db4 JG |
807 | ata_std_ports(&ae.port[0]); |
808 | ae.private_data = ld; | |
809 | ||
24dc5f33 TH |
810 | ret = -ENODEV; |
811 | if (!ata_device_add(&ae)) | |
669a5db4 | 812 | goto fail; |
24dc5f33 | 813 | |
669a5db4 JG |
814 | legacy_host[nr_legacy_host++] = dev_get_drvdata(&pdev->dev); |
815 | ld->platform_dev = pdev; | |
816 | return 0; | |
817 | ||
818 | fail: | |
819 | platform_device_unregister(pdev); | |
669a5db4 JG |
820 | return ret; |
821 | } | |
822 | ||
823 | /** | |
824 | * legacy_check_special_cases - ATA special cases | |
825 | * @p: PCI device to check | |
826 | * @master: set this if we find an ATA master | |
827 | * @master: set this if we find an ATA secondary | |
828 | * | |
829 | * A small number of vendors implemented early PCI ATA interfaces on bridge logic | |
830 | * without the ATA interface being PCI visible. Where we have a matching PCI driver | |
831 | * we must skip the relevant device here. If we don't know about it then the legacy | |
832 | * driver is the right driver anyway. | |
833 | */ | |
834 | ||
835 | static void legacy_check_special_cases(struct pci_dev *p, int *primary, int *secondary) | |
836 | { | |
837 | /* Cyrix CS5510 pre SFF MWDMA ATA on the bridge */ | |
838 | if (p->vendor == 0x1078 && p->device == 0x0000) { | |
839 | *primary = *secondary = 1; | |
840 | return; | |
841 | } | |
842 | /* Cyrix CS5520 pre SFF MWDMA ATA on the bridge */ | |
843 | if (p->vendor == 0x1078 && p->device == 0x0002) { | |
844 | *primary = *secondary = 1; | |
845 | return; | |
846 | } | |
847 | /* Intel MPIIX - PIO ATA on non PCI side of bridge */ | |
848 | if (p->vendor == 0x8086 && p->device == 0x1234) { | |
849 | u16 r; | |
850 | pci_read_config_word(p, 0x6C, &r); | |
851 | if (r & 0x8000) { /* ATA port enabled */ | |
852 | if (r & 0x4000) | |
853 | *secondary = 1; | |
854 | else | |
855 | *primary = 1; | |
856 | } | |
857 | return; | |
858 | } | |
859 | } | |
860 | ||
861 | ||
862 | /** | |
863 | * legacy_init - attach legacy interfaces | |
864 | * | |
865 | * Attach legacy IDE interfaces by scanning the usual IRQ/port suspects. | |
866 | * Right now we do not scan the ide0 and ide1 address but should do so | |
867 | * for non PCI systems or systems with no PCI IDE legacy mode devices. | |
868 | * If you fix that note there are special cases to consider like VLB | |
869 | * drivers and CS5510/20. | |
870 | */ | |
871 | ||
872 | static __init int legacy_init(void) | |
873 | { | |
874 | int i; | |
875 | int ct = 0; | |
876 | int primary = 0; | |
877 | int secondary = 0; | |
878 | int last_port = NR_HOST; | |
879 | ||
880 | struct pci_dev *p = NULL; | |
881 | ||
882 | for_each_pci_dev(p) { | |
883 | int r; | |
884 | /* Check for any overlap of the system ATA mappings. Native mode controllers | |
885 | stuck on these addresses or some devices in 'raid' mode won't be found by | |
886 | the storage class test */ | |
887 | for (r = 0; r < 6; r++) { | |
888 | if (pci_resource_start(p, r) == 0x1f0) | |
889 | primary = 1; | |
890 | if (pci_resource_start(p, r) == 0x170) | |
891 | secondary = 1; | |
892 | } | |
893 | /* Check for special cases */ | |
894 | legacy_check_special_cases(p, &primary, &secondary); | |
895 | ||
896 | /* If PCI bus is present then don't probe for tertiary legacy ports */ | |
897 | if (probe_all == 0) | |
898 | last_port = 2; | |
899 | } | |
900 | ||
85cd7251 | 901 | /* If an OPTI 82C46X is present find out where the channels are */ |
669a5db4 JG |
902 | if (opti82c46x) { |
903 | static const char *optis[4] = { | |
904 | "3/463MV", "5MV", | |
905 | "5MVA", "5MVB" | |
906 | }; | |
907 | u8 chans = 1; | |
908 | u8 ctrl = (opti_syscfg(0x30) & 0xC0) >> 6; | |
85cd7251 | 909 | |
669a5db4 JG |
910 | opti82c46x = 3; /* Assume master and slave first */ |
911 | printk(KERN_INFO DRV_NAME ": Opti 82C46%s chipset support.\n", optis[ctrl]); | |
912 | if (ctrl == 3) | |
913 | chans = (opti_syscfg(0x3F) & 0x20) ? 2 : 1; | |
914 | ctrl = opti_syscfg(0xAC); | |
915 | /* Check enabled and this port is the 465MV port. On the | |
916 | MVB we may have two channels */ | |
917 | if (ctrl & 8) { | |
918 | if (ctrl & 4) | |
919 | opti82c46x = 2; /* Slave */ | |
920 | else | |
921 | opti82c46x = 1; /* Master */ | |
922 | if (chans == 2) | |
923 | opti82c46x = 3; /* Master and Slave */ | |
924 | } /* Slave only */ | |
925 | else if (chans == 1) | |
926 | opti82c46x = 1; | |
927 | } | |
928 | ||
929 | for (i = 0; i < last_port; i++) { | |
930 | /* Skip primary if we have seen a PCI one */ | |
931 | if (i == 0 && primary == 1) | |
932 | continue; | |
933 | /* Skip secondary if we have seen a PCI one */ | |
934 | if (i == 1 && secondary == 1) | |
935 | continue; | |
936 | if (legacy_init_one(i, legacy_port[i], | |
937 | legacy_port[i] + 0x0206, | |
938 | legacy_irq[i]) == 0) | |
939 | ct++; | |
940 | } | |
941 | if (ct != 0) | |
942 | return 0; | |
943 | return -ENODEV; | |
944 | } | |
945 | ||
946 | static __exit void legacy_exit(void) | |
947 | { | |
948 | int i; | |
949 | ||
950 | for (i = 0; i < nr_legacy_host; i++) { | |
951 | struct legacy_data *ld = &legacy_data[i]; | |
24dc5f33 TH |
952 | |
953 | ata_host_detach(legacy_host[i]); | |
669a5db4 JG |
954 | platform_device_unregister(ld->platform_dev); |
955 | if (ld->timing) | |
956 | release_region(ld->timing, 2); | |
669a5db4 JG |
957 | } |
958 | } | |
959 | ||
960 | MODULE_AUTHOR("Alan Cox"); | |
961 | MODULE_DESCRIPTION("low-level driver for legacy ATA"); | |
962 | MODULE_LICENSE("GPL"); | |
963 | MODULE_VERSION(DRV_VERSION); | |
964 | ||
965 | module_param(probe_all, int, 0); | |
966 | module_param(autospeed, int, 0); | |
967 | module_param(ht6560a, int, 0); | |
968 | module_param(ht6560b, int, 0); | |
969 | module_param(opti82c611a, int, 0); | |
970 | module_param(opti82c46x, int, 0); | |
971 | module_param(pio_mask, int, 0); | |
f834e49f | 972 | module_param(iordy_mask, int, 0); |
669a5db4 JG |
973 | |
974 | module_init(legacy_init); | |
975 | module_exit(legacy_exit); | |
976 |