[linux-2.6-block.git] / drivers / ata / pata_hpt3x3.c

/*
 *	pata_hpt3x3		-	HPT3x3 driver
 *	(c) Copyright 2005-2006 Red Hat
 *
 *	Was pata_hpt34x but the naming was confusing as it supported the
 *	343 and 363 so it has been renamed.
 *
 *	Based on:
 *	linux/drivers/ide/pci/hpt34x.c		Version 0.40	Sept 10, 2002
 *	Copyright (C) 1998-2000	Andre Hedrick <andre@linux-ide.org>
 *
 *	May be copied or modified under the terms of the GNU General Public
 *	License
 */

#include <linux/kernel.h>
#include <linux/module.h>
#include <linux/pci.h>
#include <linux/init.h>
#include <linux/blkdev.h>
#include <linux/delay.h>
#include <scsi/scsi_host.h>
#include <linux/libata.h>

#define DRV_NAME	"pata_hpt3x3"
#define DRV_VERSION	"0.5.3"

/**
 *	hpt3x3_set_piomode		-	PIO setup
 *	@ap: ATA interface
 *	@adev: device on the interface
 *
 *	Set our PIO requirements. This is fairly simple on the HPT3x3 as
 *	all we have to do is clear the MWDMA and UDMA bits then load the
 *	mode number.
 */

static void hpt3x3_set_piomode(struct ata_port *ap, struct ata_device *adev)
{
	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	u32 r1, r2;
	int dn = 2 * ap->port_no + adev->devno;

	pci_read_config_dword(pdev, 0x44, &r1);
	pci_read_config_dword(pdev, 0x48, &r2);
	/* Load the PIO timing number */
	r1 &= ~(7 << (3 * dn));
	r1 |= (adev->pio_mode - XFER_PIO_0) << (3 * dn);
	r2 &= ~(0x11 << dn);	/* Clear MWDMA and UDMA bits */

	pci_write_config_dword(pdev, 0x44, r1);
	pci_write_config_dword(pdev, 0x48, r2);
}

/**
 *	hpt3x3_set_dmamode		-	DMA timing setup
 *	@ap: ATA interface
 *	@adev: Device being configured
 *
 *	Set up the channel for MWDMA or UDMA modes. Much the same as with
 *	PIO, load the mode number and then set MWDMA or UDMA flag.
 *
 *	0x44 : bit 0-2 master mode, 3-5 slave mode, etc
 *	0x48 : bit 4/0 DMA/UDMA bit 5/1 for slave etc
 */

static void hpt3x3_set_dmamode(struct ata_port *ap, struct ata_device *adev)
{
	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	u32 r1, r2;
	int dn = 2 * ap->port_no + adev->devno;
	int mode_num = adev->dma_mode & 0x0F;

	pci_read_config_dword(pdev, 0x44, &r1);
	pci_read_config_dword(pdev, 0x48, &r2);
	/* Load the timing number */
	r1 &= ~(7 << (3 * dn));
	r1 |= (mode_num << (3 * dn));
	r2 &= ~(0x11 << dn);	/* Clear MWDMA and UDMA bits */

	if (adev->dma_mode >= XFER_UDMA_0)
		r2 |= (0x10 << dn);	/* Ultra mode */
	else
		r2 |= (0x01 << dn);	/* MWDMA */

	pci_write_config_dword(pdev, 0x44, r1);
	pci_write_config_dword(pdev, 0x48, r2);
}

/**
 *	hpt3x3_atapi_dma	-	ATAPI DMA check
 *	@qc: Queued command
 *
 *	Just say no - we don't do ATAPI DMA
 */

static int hpt3x3_atapi_dma(struct ata_queued_cmd *qc)
{
	return 1;
}

static struct scsi_host_template hpt3x3_sht = {
	.module			= THIS_MODULE,
	.name			= DRV_NAME,
	.ioctl			= ata_scsi_ioctl,
	.queuecommand		= ata_scsi_queuecmd,
	.can_queue		= ATA_DEF_QUEUE,
	.this_id		= ATA_SHT_THIS_ID,
	.sg_tablesize		= LIBATA_MAX_PRD,
	.cmd_per_lun		= ATA_SHT_CMD_PER_LUN,
	.emulated		= ATA_SHT_EMULATED,
	.use_clustering		= ATA_SHT_USE_CLUSTERING,
	.proc_name		= DRV_NAME,
	.dma_boundary		= ATA_DMA_BOUNDARY,
	.slave_configure	= ata_scsi_slave_config,
	.slave_destroy		= ata_scsi_slave_destroy,
	.bios_param		= ata_std_bios_param,
};

static struct ata_port_operations hpt3x3_port_ops = {
	.port_disable	= ata_port_disable,
	.set_piomode	= hpt3x3_set_piomode,
	.mode_filter	= ata_pci_default_filter,

	.tf_load	= ata_tf_load,
	.tf_read	= ata_tf_read,
	.check_status 	= ata_check_status,
	.exec_command	= ata_exec_command,
	.dev_select 	= ata_std_dev_select,

	.freeze		= ata_bmdma_freeze,
	.thaw		= ata_bmdma_thaw,
	.error_handler	= ata_bmdma_error_handler,
	.post_internal_cmd = ata_bmdma_post_internal_cmd,
	.cable_detect	= ata_cable_40wire,

	.bmdma_setup 	= ata_bmdma_setup,
	.bmdma_start 	= ata_bmdma_start,
	.bmdma_stop	= ata_bmdma_stop,
	.bmdma_status 	= ata_bmdma_status,
	.check_atapi_dma= hpt3x3_atapi_dma,

	.qc_prep 	= ata_qc_prep,
	.qc_issue	= ata_qc_issue_prot,

	.data_xfer	= ata_data_xfer,

	.irq_handler	= ata_interrupt,
	.irq_clear	= ata_bmdma_irq_clear,
	.irq_on		= ata_irq_on,
	.irq_ack	= ata_irq_ack,

	.port_start	= ata_port_start,
};

/**
 *	hpt3x3_init_chipset	-	chip setup
 *	@dev: PCI device
 *
 *	Perform the setup required at boot and on resume.
 */

static void hpt3x3_init_chipset(struct pci_dev *dev)
{
	u16 cmd;
	/* Initialize the board */
	pci_write_config_word(dev, 0x80, 0x00);
	/* Check if it is a 343 or a 363. 363 has COMMAND_MEMORY set */
	pci_read_config_word(dev, PCI_COMMAND, &cmd);
	if (cmd & PCI_COMMAND_MEMORY)
		pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0xF0);
	else
		pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x20);
}

/**
 *	hpt3x3_init_one		-	Initialise an HPT343/363
 *	@pdev: PCI device
 *	@id: Entry in match table
 *
 *	Perform basic initialisation. We set the device up so we access all
 *	ports via BAR4. This is neccessary to work around errata.
 */

static int hpt3x3_init_one(struct pci_dev *pdev, const struct pci_device_id *id)
{
	static int printed_version;
	static const struct ata_port_info info = {
		.sht = &hpt3x3_sht,
		.flags = ATA_FLAG_SLAVE_POSS,
		.pio_mask = 0x1f,
#if defined(CONFIG_PATA_HPT3X3_DMA)
		/* Further debug needed */
		.mwdma_mask = 0x07,
		.udma_mask = 0x07,
#endif
		.port_ops = &hpt3x3_port_ops
	};
	/* Register offsets of taskfiles in BAR4 area */
	static const u8 offset_cmd[2] = { 0x20, 0x28 };
	static const u8 offset_ctl[2] = { 0x36, 0x3E };
	const struct ata_port_info *ppi[] = { &info, NULL };
	struct ata_host *host;
	int i, rc;
	void __iomem *base;

	hpt3x3_init_chipset(pdev);

	if (!printed_version++)
		dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");

	host = ata_host_alloc_pinfo(&pdev->dev, ppi, 2);
	if (!host)
		return -ENOMEM;
	/* acquire resources and fill host */
	rc = pcim_enable_device(pdev);
	if (rc)
		return rc;

	/* Everything is relative to BAR4 if we set up this way */
	rc = pcim_iomap_regions(pdev, 1 << 4, DRV_NAME);
	if (rc == -EBUSY)
		pcim_pin_device(pdev);
	if (rc)
		return rc;
	host->iomap = pcim_iomap_table(pdev);
	rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
	if (rc)
		return rc;
	rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
	if (rc)
		return rc;

	base = host->iomap[4];	/* Bus mastering base */

	for (i = 0; i < host->n_ports; i++) {
		struct ata_ioports *ioaddr = &host->ports[i]->ioaddr;

		ioaddr->cmd_addr = base + offset_cmd[i];
		ioaddr->altstatus_addr =
		ioaddr->ctl_addr = base + offset_ctl[i];
		ioaddr->scr_addr = NULL;
		ata_std_ports(ioaddr);
		ioaddr->bmdma_addr = base + 8 * i;
	}
	pci_set_master(pdev);
	return ata_host_activate(host, pdev->irq, ata_interrupt, IRQF_SHARED,
				 &hpt3x3_sht);
}

#ifdef CONFIG_PM
static int hpt3x3_reinit_one(struct pci_dev *dev)
{
	hpt3x3_init_chipset(dev);
	return ata_pci_device_resume(dev);
}
#endif

static const struct pci_device_id hpt3x3[] = {
	{ PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT343), },

	{ },
};

static struct pci_driver hpt3x3_pci_driver = {
	.name 		= DRV_NAME,
	.id_table	= hpt3x3,
	.probe 		= hpt3x3_init_one,
	.remove		= ata_pci_remove_one,
#ifdef CONFIG_PM
	.suspend	= ata_pci_device_suspend,
	.resume		= hpt3x3_reinit_one,
#endif
};

static int __init hpt3x3_init(void)
{
	return pci_register_driver(&hpt3x3_pci_driver);
}


static void __exit hpt3x3_exit(void)
{
	pci_unregister_driver(&hpt3x3_pci_driver);
}


MODULE_AUTHOR("Alan Cox");
MODULE_DESCRIPTION("low-level driver for the Highpoint HPT343/363");
MODULE_LICENSE("GPL");
MODULE_DEVICE_TABLE(pci, hpt3x3);
MODULE_VERSION(DRV_VERSION);

module_init(hpt3x3_init);
module_exit(hpt3x3_exit);
Commit	Line	Data
669a5db4 JG	1	/*
	2	* pata_hpt3x3 - HPT3x3 driver
	3	* (c) Copyright 2005-2006 Red Hat
	4	*
	5	* Was pata_hpt34x but the naming was confusing as it supported the
	6	* 343 and 363 so it has been renamed.
	7	*
	8	* Based on:
	9	* linux/drivers/ide/pci/hpt34x.c Version 0.40 Sept 10, 2002
	10	* Copyright (C) 1998-2000 Andre Hedrick <andre@linux-ide.org>
	11	*
	12	* May be copied or modified under the terms of the GNU General Public
	13	* License
	14	*/
85cd7251	15
669a5db4 JG	16	#include <linux/kernel.h>
	17	#include <linux/module.h>
	18	#include <linux/pci.h>
	19	#include <linux/init.h>
	20	#include <linux/blkdev.h>
	21	#include <linux/delay.h>
	22	#include <scsi/scsi_host.h>
	23	#include <linux/libata.h>
	24
	25	#define DRV_NAME "pata_hpt3x3"
66e7da4e	26	#define DRV_VERSION "0.5.3"
669a5db4	27
669a5db4 JG	28	/**
	29	* hpt3x3_set_piomode - PIO setup
	30	* @ap: ATA interface
	31	* @adev: device on the interface
	32	*
	33	* Set our PIO requirements. This is fairly simple on the HPT3x3 as
	34	* all we have to do is clear the MWDMA and UDMA bits then load the
	35	* mode number.
	36	*/
	37
	38	static void hpt3x3_set_piomode(struct ata_port ap, struct ata_device adev)
	39	{
	40	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	41	u32 r1, r2;
	42	int dn = 2 * ap->port_no + adev->devno;
	43
	44	pci_read_config_dword(pdev, 0x44, &r1);
	45	pci_read_config_dword(pdev, 0x48, &r2);
	46	/* Load the PIO timing number */
	47	r1 &= ~(7 << (3 * dn));
	48	r1 \|= (adev->pio_mode - XFER_PIO_0) << (3 * dn);
	49	r2 &= ~(0x11 << dn); /* Clear MWDMA and UDMA bits */
	50
	51	pci_write_config_dword(pdev, 0x44, r1);
	52	pci_write_config_dword(pdev, 0x48, r2);
	53	}
	54
	55	/**
	56	* hpt3x3_set_dmamode - DMA timing setup
	57	* @ap: ATA interface
	58	* @adev: Device being configured
	59	*
	60	* Set up the channel for MWDMA or UDMA modes. Much the same as with
	61	* PIO, load the mode number and then set MWDMA or UDMA flag.
66e7da4e AC	62	*
	63	* 0x44 : bit 0-2 master mode, 3-5 slave mode, etc
	64	* 0x48 : bit 4/0 DMA/UDMA bit 5/1 for slave etc
669a5db4 JG	65	*/
	66
	67	static void hpt3x3_set_dmamode(struct ata_port ap, struct ata_device adev)
	68	{
	69	struct pci_dev *pdev = to_pci_dev(ap->host->dev);
	70	u32 r1, r2;
	71	int dn = 2 * ap->port_no + adev->devno;
	72	int mode_num = adev->dma_mode & 0x0F;
	73
	74	pci_read_config_dword(pdev, 0x44, &r1);
	75	pci_read_config_dword(pdev, 0x48, &r2);
	76	/* Load the timing number */
	77	r1 &= ~(7 << (3 * dn));
	78	r1 \|= (mode_num << (3 * dn));
	79	r2 &= ~(0x11 << dn); /* Clear MWDMA and UDMA bits */
	80
	81	if (adev->dma_mode >= XFER_UDMA_0)
66e7da4e	82	r2 \|= (0x10 << dn); /* Ultra mode */
669a5db4	83	else
66e7da4e	84	r2 \|= (0x01 << dn); /* MWDMA */
669a5db4 JG	85
	86	pci_write_config_dword(pdev, 0x44, r1);
	87	pci_write_config_dword(pdev, 0x48, r2);
	88	}
	89
66e7da4e AC	90	/**
	91	* hpt3x3_atapi_dma - ATAPI DMA check
	92	* @qc: Queued command
	93	*
	94	* Just say no - we don't do ATAPI DMA
	95	*/
	96
	97	static int hpt3x3_atapi_dma(struct ata_queued_cmd *qc)
	98	{
	99	return 1;
	100	}
	101
669a5db4 JG	102	static struct scsi_host_template hpt3x3_sht = {
	103	.module = THIS_MODULE,
	104	.name = DRV_NAME,
	105	.ioctl = ata_scsi_ioctl,
	106	.queuecommand = ata_scsi_queuecmd,
	107	.can_queue = ATA_DEF_QUEUE,
	108	.this_id = ATA_SHT_THIS_ID,
	109	.sg_tablesize = LIBATA_MAX_PRD,
669a5db4 JG	110	.cmd_per_lun = ATA_SHT_CMD_PER_LUN,
	111	.emulated = ATA_SHT_EMULATED,
	112	.use_clustering = ATA_SHT_USE_CLUSTERING,
	113	.proc_name = DRV_NAME,
	114	.dma_boundary = ATA_DMA_BOUNDARY,
	115	.slave_configure = ata_scsi_slave_config,
afdfe899	116	.slave_destroy = ata_scsi_slave_destroy,
669a5db4 JG	117	.bios_param = ata_std_bios_param,
	118	};
	119
	120	static struct ata_port_operations hpt3x3_port_ops = {
	121	.port_disable = ata_port_disable,
	122	.set_piomode = hpt3x3_set_piomode,
669a5db4 JG	123	.mode_filter = ata_pci_default_filter,
	124
	125	.tf_load = ata_tf_load,
	126	.tf_read = ata_tf_read,
	127	.check_status = ata_check_status,
	128	.exec_command = ata_exec_command,
	129	.dev_select = ata_std_dev_select,
	130
	131	.freeze = ata_bmdma_freeze,
	132	.thaw = ata_bmdma_thaw,
a73984a0	133	.error_handler = ata_bmdma_error_handler,
669a5db4	134	.post_internal_cmd = ata_bmdma_post_internal_cmd,
a73984a0	135	.cable_detect = ata_cable_40wire,
669a5db4 JG	136
	137	.bmdma_setup = ata_bmdma_setup,
	138	.bmdma_start = ata_bmdma_start,
	139	.bmdma_stop = ata_bmdma_stop,
	140	.bmdma_status = ata_bmdma_status,
66e7da4e	141	.check_atapi_dma= hpt3x3_atapi_dma,
669a5db4 JG	142
	143	.qc_prep = ata_qc_prep,
	144	.qc_issue = ata_qc_issue_prot,
bda30288	145
0d5ff566	146	.data_xfer = ata_data_xfer,
669a5db4 JG	147
	148	.irq_handler = ata_interrupt,
	149	.irq_clear = ata_bmdma_irq_clear,
246ce3b6 AI	150	.irq_on = ata_irq_on,
246ce3b6 AI	151	.irq_ack = ata_irq_ack,
669a5db4 JG	152
669a5db4 JG	153	.port_start = ata_port_start,
669a5db4 JG	154	};
669a5db4 JG	155
aff0df05 A	156	/**
	157	* hpt3x3_init_chipset - chip setup
	158	* @dev: PCI device
	159	*
	160	* Perform the setup required at boot and on resume.
	161	*/
f20b16ff	162
aff0df05 A	163	static void hpt3x3_init_chipset(struct pci_dev *dev)
	164	{
	165	u16 cmd;
	166	/* Initialize the board */
	167	pci_write_config_word(dev, 0x80, 0x00);
	168	/* Check if it is a 343 or a 363. 363 has COMMAND_MEMORY set */
	169	pci_read_config_word(dev, PCI_COMMAND, &cmd);
	170	if (cmd & PCI_COMMAND_MEMORY)
	171	pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0xF0);
	172	else
	173	pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x20);
	174	}
	175
669a5db4 JG	176	/**
669a5db4 JG	177	* hpt3x3_init_one - Initialise an HPT343/363
66e7da4e	178	* @pdev: PCI device
669a5db4 JG	179	* @id: Entry in match table
669a5db4 JG	180	*
66e7da4e AC	181	* Perform basic initialisation. We set the device up so we access all
66e7da4e AC	182	* ports via BAR4. This is neccessary to work around errata.
669a5db4 JG	183	*/
669a5db4 JG	184
66e7da4e	185	static int hpt3x3_init_one(struct pci_dev pdev, const struct pci_device_id id)
669a5db4	186	{
66e7da4e	187	static int printed_version;
1626aeb8	188	static const struct ata_port_info info = {
669a5db4	189	.sht = &hpt3x3_sht,
1d2808fd	190	.flags = ATA_FLAG_SLAVE_POSS,
669a5db4	191	.pio_mask = 0x1f,
66e7da4e AC	192	#if defined(CONFIG_PATA_HPT3X3_DMA)
66e7da4e AC	193	/* Further debug needed */
669a5db4 JG	194	.mwdma_mask = 0x07,
669a5db4 JG	195	.udma_mask = 0x07,
66e7da4e	196	#endif
669a5db4 JG	197	.port_ops = &hpt3x3_port_ops
669a5db4 JG	198	};
66e7da4e AC	199	/* Register offsets of taskfiles in BAR4 area */
	200	static const u8 offset_cmd[2] = { 0x20, 0x28 };
	201	static const u8 offset_ctl[2] = { 0x36, 0x3E };
1626aeb8	202	const struct ata_port_info *ppi[] = { &info, NULL };
66e7da4e AC	203	struct ata_host *host;
	204	int i, rc;
	205	void __iomem *base;
	206
	207	hpt3x3_init_chipset(pdev);
	208
	209	if (!printed_version++)
	210	dev_printk(KERN_DEBUG, &pdev->dev, "version " DRV_VERSION "\n");
	211
	212	host = ata_host_alloc_pinfo(&pdev->dev, ppi, 2);
	213	if (!host)
	214	return -ENOMEM;
	215	/* acquire resources and fill host */
	216	rc = pcim_enable_device(pdev);
	217	if (rc)
	218	return rc;
	219
	220	/* Everything is relative to BAR4 if we set up this way */
	221	rc = pcim_iomap_regions(pdev, 1 << 4, DRV_NAME);
	222	if (rc == -EBUSY)
	223	pcim_pin_device(pdev);
	224	if (rc)
	225	return rc;
	226	host->iomap = pcim_iomap_table(pdev);
	227	rc = pci_set_dma_mask(pdev, ATA_DMA_MASK);
	228	if (rc)
	229	return rc;
	230	rc = pci_set_consistent_dma_mask(pdev, ATA_DMA_MASK);
	231	if (rc)
	232	return rc;
	233
	234	base = host->iomap[4]; /* Bus mastering base */
	235
	236	for (i = 0; i < host->n_ports; i++) {
	237	struct ata_ioports *ioaddr = &host->ports[i]->ioaddr;
	238
	239	ioaddr->cmd_addr = base + offset_cmd[i];
	240	ioaddr->altstatus_addr =
	241	ioaddr->ctl_addr = base + offset_ctl[i];
	242	ioaddr->scr_addr = NULL;
	243	ata_std_ports(ioaddr);
	244	ioaddr->bmdma_addr = base + 8 * i;
	245	}
	246	pci_set_master(pdev);
	247	return ata_host_activate(host, pdev->irq, ata_interrupt, IRQF_SHARED,
	248	&hpt3x3_sht);
669a5db4 JG	249	}
669a5db4 JG	250
438ac6d5	251	#ifdef CONFIG_PM
aff0df05 A	252	static int hpt3x3_reinit_one(struct pci_dev *dev)
	253	{
	254	hpt3x3_init_chipset(dev);
	255	return ata_pci_device_resume(dev);
	256	}
438ac6d5	257	#endif
aff0df05	258
2d2744fc JG	259	static const struct pci_device_id hpt3x3[] = {
	260	{ PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT343), },
	261
	262	{ },
669a5db4 JG	263	};
	264
	265	static struct pci_driver hpt3x3_pci_driver = {
2d2744fc	266	.name = DRV_NAME,
669a5db4 JG	267	.id_table = hpt3x3,
669a5db4 JG	268	.probe = hpt3x3_init_one,
aff0df05	269	.remove = ata_pci_remove_one,
438ac6d5	270	#ifdef CONFIG_PM
aff0df05 A	271	.suspend = ata_pci_device_suspend,
aff0df05 A	272	.resume = hpt3x3_reinit_one,
438ac6d5	273	#endif
669a5db4 JG	274	};
	275
	276	static int __init hpt3x3_init(void)
	277	{
	278	return pci_register_driver(&hpt3x3_pci_driver);
	279	}
	280
	281
	282	static void __exit hpt3x3_exit(void)
	283	{
	284	pci_unregister_driver(&hpt3x3_pci_driver);
	285	}
	286
	287
	288	MODULE_AUTHOR("Alan Cox");
	289	MODULE_DESCRIPTION("low-level driver for the Highpoint HPT343/363");
	290	MODULE_LICENSE("GPL");
	291	MODULE_DEVICE_TABLE(pci, hpt3x3);
	292	MODULE_VERSION(DRV_VERSION);
	293
	294	module_init(hpt3x3_init);
	295	module_exit(hpt3x3_exit);