Commit | Line | Data |
---|---|---|
669a5db4 | 1 | /* |
0ca646db | 2 | * Libata driver for the HighPoint 371N, 372N, and 302N UDMA66 ATA controllers. |
669a5db4 JG |
3 | * |
4 | * This driver is heavily based upon: | |
5 | * | |
6 | * linux/drivers/ide/pci/hpt366.c Version 0.36 April 25, 2003 | |
7 | * | |
8 | * Copyright (C) 1999-2003 Andre Hedrick <andre@linux-ide.org> | |
9 | * Portions Copyright (C) 2001 Sun Microsystems, Inc. | |
10 | * Portions Copyright (C) 2003 Red Hat Inc | |
8e834c2e | 11 | * Portions Copyright (C) 2005-2010 MontaVista Software, Inc. |
669a5db4 JG |
12 | * |
13 | * | |
14 | * TODO | |
669a5db4 JG |
15 | * Work out best PLL policy |
16 | */ | |
17 | ||
18 | #include <linux/kernel.h> | |
19 | #include <linux/module.h> | |
20 | #include <linux/pci.h> | |
21 | #include <linux/init.h> | |
22 | #include <linux/blkdev.h> | |
23 | #include <linux/delay.h> | |
24 | #include <scsi/scsi_host.h> | |
25 | #include <linux/libata.h> | |
26 | ||
27 | #define DRV_NAME "pata_hpt3x2n" | |
8e834c2e | 28 | #define DRV_VERSION "0.3.11" |
669a5db4 JG |
29 | |
30 | enum { | |
31 | HPT_PCI_FAST = (1 << 31), | |
32 | PCI66 = (1 << 1), | |
33 | USE_DPLL = (1 << 0) | |
34 | }; | |
35 | ||
36 | struct hpt_clock { | |
37 | u8 xfer_speed; | |
38 | u32 timing; | |
39 | }; | |
40 | ||
41 | struct hpt_chip { | |
42 | const char *name; | |
43 | struct hpt_clock *clocks[3]; | |
44 | }; | |
45 | ||
46 | /* key for bus clock timings | |
47 | * bit | |
fd5e62e2 SS |
48 | * 0:3 data_high_time. Inactive time of DIOW_/DIOR_ for PIO and MW DMA. |
49 | * cycles = value + 1 | |
50 | * 4:8 data_low_time. Active time of DIOW_/DIOR_ for PIO and MW DMA. | |
51 | * cycles = value + 1 | |
52 | * 9:12 cmd_high_time. Inactive time of DIOW_/DIOR_ during task file | |
669a5db4 | 53 | * register access. |
fd5e62e2 | 54 | * 13:17 cmd_low_time. Active time of DIOW_/DIOR_ during task file |
669a5db4 | 55 | * register access. |
fd5e62e2 SS |
56 | * 18:20 udma_cycle_time. Clock cycles for UDMA xfer. |
57 | * 21 CLK frequency for UDMA: 0=ATA clock, 1=dual ATA clock. | |
58 | * 22:24 pre_high_time. Time to initialize 1st cycle for PIO and MW DMA xfer. | |
59 | * 25:27 cmd_pre_high_time. Time to initialize 1st PIO cycle for task file | |
669a5db4 | 60 | * register access. |
fd5e62e2 SS |
61 | * 28 UDMA enable. |
62 | * 29 DMA enable. | |
63 | * 30 PIO_MST enable. If set, the chip is in bus master mode during | |
64 | * PIO xfer. | |
65 | * 31 FIFO enable. Only for PIO. | |
669a5db4 | 66 | */ |
85cd7251 | 67 | |
669a5db4 JG |
68 | /* 66MHz DPLL clocks */ |
69 | ||
70 | static struct hpt_clock hpt3x2n_clocks[] = { | |
71 | { XFER_UDMA_7, 0x1c869c62 }, | |
72 | { XFER_UDMA_6, 0x1c869c62 }, | |
73 | { XFER_UDMA_5, 0x1c8a9c62 }, | |
74 | { XFER_UDMA_4, 0x1c8a9c62 }, | |
75 | { XFER_UDMA_3, 0x1c8e9c62 }, | |
76 | { XFER_UDMA_2, 0x1c929c62 }, | |
77 | { XFER_UDMA_1, 0x1c9a9c62 }, | |
78 | { XFER_UDMA_0, 0x1c829c62 }, | |
79 | ||
80 | { XFER_MW_DMA_2, 0x2c829c62 }, | |
81 | { XFER_MW_DMA_1, 0x2c829c66 }, | |
d413ff3e | 82 | { XFER_MW_DMA_0, 0x2c829d2e }, |
669a5db4 JG |
83 | |
84 | { XFER_PIO_4, 0x0c829c62 }, | |
85 | { XFER_PIO_3, 0x0c829c84 }, | |
86 | { XFER_PIO_2, 0x0c829ca6 }, | |
87 | { XFER_PIO_1, 0x0d029d26 }, | |
88 | { XFER_PIO_0, 0x0d029d5e }, | |
669a5db4 JG |
89 | }; |
90 | ||
91 | /** | |
92 | * hpt3x2n_find_mode - reset the hpt3x2n bus | |
93 | * @ap: ATA port | |
94 | * @speed: transfer mode | |
95 | * | |
96 | * Return the 32bit register programming information for this channel | |
97 | * that matches the speed provided. For the moment the clocks table | |
98 | * is hard coded but easy to change. This will be needed if we use | |
99 | * different DPLLs | |
100 | */ | |
85cd7251 | 101 | |
669a5db4 JG |
102 | static u32 hpt3x2n_find_mode(struct ata_port *ap, int speed) |
103 | { | |
104 | struct hpt_clock *clocks = hpt3x2n_clocks; | |
85cd7251 | 105 | |
669a5db4 JG |
106 | while(clocks->xfer_speed) { |
107 | if (clocks->xfer_speed == speed) | |
108 | return clocks->timing; | |
109 | clocks++; | |
110 | } | |
111 | BUG(); | |
112 | return 0xffffffffU; /* silence compiler warning */ | |
113 | } | |
114 | ||
8e834c2e SS |
115 | /** |
116 | * hpt372n_filter - mode selection filter | |
117 | * @adev: ATA device | |
118 | * @mask: mode mask | |
119 | * | |
120 | * The Marvell bridge chips used on the HighPoint SATA cards do not seem | |
121 | * to support the UltraDMA modes 1, 2, and 3 as well as any MWDMA modes... | |
122 | */ | |
123 | static unsigned long hpt372n_filter(struct ata_device *adev, unsigned long mask) | |
124 | { | |
125 | if (ata_id_is_sata(adev->id)) | |
126 | mask &= ~((0xE << ATA_SHIFT_UDMA) | ATA_MASK_MWDMA); | |
127 | ||
128 | return mask; | |
129 | } | |
130 | ||
669a5db4 | 131 | /** |
a0fcdc02 JG |
132 | * hpt3x2n_cable_detect - Detect the cable type |
133 | * @ap: ATA port to detect on | |
669a5db4 | 134 | * |
a0fcdc02 | 135 | * Return the cable type attached to this port |
669a5db4 | 136 | */ |
85cd7251 | 137 | |
a0fcdc02 | 138 | static int hpt3x2n_cable_detect(struct ata_port *ap) |
669a5db4 JG |
139 | { |
140 | u8 scr2, ata66; | |
141 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); | |
85cd7251 | 142 | |
669a5db4 JG |
143 | pci_read_config_byte(pdev, 0x5B, &scr2); |
144 | pci_write_config_byte(pdev, 0x5B, scr2 & ~0x01); | |
10a9c969 BZ |
145 | |
146 | udelay(10); /* debounce */ | |
147 | ||
669a5db4 JG |
148 | /* Cable register now active */ |
149 | pci_read_config_byte(pdev, 0x5A, &ata66); | |
150 | /* Restore state */ | |
151 | pci_write_config_byte(pdev, 0x5B, scr2); | |
85cd7251 | 152 | |
f3b1cf40 | 153 | if (ata66 & (2 >> ap->port_no)) |
a0fcdc02 | 154 | return ATA_CBL_PATA40; |
669a5db4 | 155 | else |
a0fcdc02 JG |
156 | return ATA_CBL_PATA80; |
157 | } | |
158 | ||
159 | /** | |
160 | * hpt3x2n_pre_reset - reset the hpt3x2n bus | |
cc0680a5 | 161 | * @link: ATA link to reset |
28e21c8c | 162 | * @deadline: deadline jiffies for the operation |
a0fcdc02 JG |
163 | * |
164 | * Perform the initial reset handling for the 3x2n series controllers. | |
165 | * Reset the hardware and state machine, | |
166 | */ | |
669a5db4 | 167 | |
a1efdaba | 168 | static int hpt3x2n_pre_reset(struct ata_link *link, unsigned long deadline) |
a0fcdc02 | 169 | { |
cc0680a5 | 170 | struct ata_port *ap = link->ap; |
a0fcdc02 | 171 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); |
669a5db4 | 172 | /* Reset the state machine */ |
28e21c8c | 173 | pci_write_config_byte(pdev, 0x50 + 4 * ap->port_no, 0x37); |
669a5db4 | 174 | udelay(100); |
d4b2bab4 | 175 | |
9363c382 | 176 | return ata_sff_prereset(link, deadline); |
669a5db4 | 177 | } |
85cd7251 | 178 | |
1a1b172b SS |
179 | static void hpt3x2n_set_mode(struct ata_port *ap, struct ata_device *adev, |
180 | u8 mode) | |
669a5db4 JG |
181 | { |
182 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); | |
183 | u32 addr1, addr2; | |
1a1b172b | 184 | u32 reg, timing, mask; |
669a5db4 JG |
185 | u8 fast; |
186 | ||
187 | addr1 = 0x40 + 4 * (adev->devno + 2 * ap->port_no); | |
188 | addr2 = 0x51 + 4 * ap->port_no; | |
85cd7251 | 189 | |
669a5db4 JG |
190 | /* Fast interrupt prediction disable, hold off interrupt disable */ |
191 | pci_read_config_byte(pdev, addr2, &fast); | |
192 | fast &= ~0x07; | |
193 | pci_write_config_byte(pdev, addr2, fast); | |
85cd7251 | 194 | |
1a1b172b SS |
195 | /* Determine timing mask and find matching mode entry */ |
196 | if (mode < XFER_MW_DMA_0) | |
197 | mask = 0xcfc3ffff; | |
198 | else if (mode < XFER_UDMA_0) | |
199 | mask = 0x31c001ff; | |
200 | else | |
201 | mask = 0x303c0000; | |
202 | ||
203 | timing = hpt3x2n_find_mode(ap, mode); | |
204 | ||
669a5db4 | 205 | pci_read_config_dword(pdev, addr1, ®); |
1a1b172b SS |
206 | reg = (reg & ~mask) | (timing & mask); |
207 | pci_write_config_dword(pdev, addr1, reg); | |
208 | } | |
209 | ||
210 | /** | |
211 | * hpt3x2n_set_piomode - PIO setup | |
212 | * @ap: ATA interface | |
213 | * @adev: device on the interface | |
214 | * | |
215 | * Perform PIO mode setup. | |
216 | */ | |
217 | ||
218 | static void hpt3x2n_set_piomode(struct ata_port *ap, struct ata_device *adev) | |
219 | { | |
220 | hpt3x2n_set_mode(ap, adev, adev->pio_mode); | |
669a5db4 JG |
221 | } |
222 | ||
223 | /** | |
224 | * hpt3x2n_set_dmamode - DMA timing setup | |
225 | * @ap: ATA interface | |
226 | * @adev: Device being configured | |
227 | * | |
1a1b172b | 228 | * Set up the channel for MWDMA or UDMA modes. |
669a5db4 | 229 | */ |
85cd7251 | 230 | |
669a5db4 JG |
231 | static void hpt3x2n_set_dmamode(struct ata_port *ap, struct ata_device *adev) |
232 | { | |
1a1b172b | 233 | hpt3x2n_set_mode(ap, adev, adev->dma_mode); |
669a5db4 JG |
234 | } |
235 | ||
236 | /** | |
237 | * hpt3x2n_bmdma_end - DMA engine stop | |
238 | * @qc: ATA command | |
239 | * | |
240 | * Clean up after the HPT3x2n and later DMA engine | |
241 | */ | |
85cd7251 | 242 | |
669a5db4 JG |
243 | static void hpt3x2n_bmdma_stop(struct ata_queued_cmd *qc) |
244 | { | |
245 | struct ata_port *ap = qc->ap; | |
246 | struct pci_dev *pdev = to_pci_dev(ap->host->dev); | |
247 | int mscreg = 0x50 + 2 * ap->port_no; | |
248 | u8 bwsr_stat, msc_stat; | |
85cd7251 | 249 | |
669a5db4 JG |
250 | pci_read_config_byte(pdev, 0x6A, &bwsr_stat); |
251 | pci_read_config_byte(pdev, mscreg, &msc_stat); | |
252 | if (bwsr_stat & (1 << ap->port_no)) | |
253 | pci_write_config_byte(pdev, mscreg, msc_stat | 0x30); | |
254 | ata_bmdma_stop(qc); | |
255 | } | |
256 | ||
257 | /** | |
258 | * hpt3x2n_set_clock - clock control | |
259 | * @ap: ATA port | |
260 | * @source: 0x21 or 0x23 for PLL or PCI sourced clock | |
261 | * | |
262 | * Switch the ATA bus clock between the PLL and PCI clock sources | |
263 | * while correctly isolating the bus and resetting internal logic | |
264 | * | |
265 | * We must use the DPLL for | |
266 | * - writing | |
267 | * - second channel UDMA7 (SATA ports) or higher | |
268 | * - 66MHz PCI | |
85cd7251 | 269 | * |
669a5db4 JG |
270 | * or we will underclock the device and get reduced performance. |
271 | */ | |
85cd7251 | 272 | |
669a5db4 JG |
273 | static void hpt3x2n_set_clock(struct ata_port *ap, int source) |
274 | { | |
256ace9b | 275 | void __iomem *bmdma = ap->ioaddr.bmdma_addr - ap->port_no * 8; |
85cd7251 | 276 | |
669a5db4 | 277 | /* Tristate the bus */ |
0d5ff566 TH |
278 | iowrite8(0x80, bmdma+0x73); |
279 | iowrite8(0x80, bmdma+0x77); | |
85cd7251 | 280 | |
669a5db4 | 281 | /* Switch clock and reset channels */ |
0d5ff566 TH |
282 | iowrite8(source, bmdma+0x7B); |
283 | iowrite8(0xC0, bmdma+0x79); | |
85cd7251 | 284 | |
256ace9b SS |
285 | /* Reset state machines, avoid enabling the disabled channels */ |
286 | iowrite8(ioread8(bmdma+0x70) | 0x32, bmdma+0x70); | |
287 | iowrite8(ioread8(bmdma+0x74) | 0x32, bmdma+0x74); | |
85cd7251 | 288 | |
669a5db4 | 289 | /* Complete reset */ |
0d5ff566 | 290 | iowrite8(0x00, bmdma+0x79); |
85cd7251 | 291 | |
669a5db4 | 292 | /* Reconnect channels to bus */ |
0d5ff566 TH |
293 | iowrite8(0x00, bmdma+0x73); |
294 | iowrite8(0x00, bmdma+0x77); | |
669a5db4 JG |
295 | } |
296 | ||
a52865c2 | 297 | static int hpt3x2n_use_dpll(struct ata_port *ap, int writing) |
669a5db4 JG |
298 | { |
299 | long flags = (long)ap->host->private_data; | |
256ace9b | 300 | |
669a5db4 | 301 | /* See if we should use the DPLL */ |
a52865c2 | 302 | if (writing) |
669a5db4 JG |
303 | return USE_DPLL; /* Needed for write */ |
304 | if (flags & PCI66) | |
305 | return USE_DPLL; /* Needed at 66Mhz */ | |
85cd7251 | 306 | return 0; |
669a5db4 JG |
307 | } |
308 | ||
256ace9b SS |
309 | static int hpt3x2n_qc_defer(struct ata_queued_cmd *qc) |
310 | { | |
311 | struct ata_port *ap = qc->ap; | |
312 | struct ata_port *alt = ap->host->ports[ap->port_no ^ 1]; | |
313 | int rc, flags = (long)ap->host->private_data; | |
314 | int dpll = hpt3x2n_use_dpll(ap, qc->tf.flags & ATA_TFLAG_WRITE); | |
315 | ||
316 | /* First apply the usual rules */ | |
317 | rc = ata_std_qc_defer(qc); | |
318 | if (rc != 0) | |
319 | return rc; | |
320 | ||
321 | if ((flags & USE_DPLL) != dpll && alt->qc_active) | |
322 | return ATA_DEFER_PORT; | |
323 | return 0; | |
324 | } | |
325 | ||
9363c382 | 326 | static unsigned int hpt3x2n_qc_issue(struct ata_queued_cmd *qc) |
669a5db4 | 327 | { |
669a5db4 JG |
328 | struct ata_port *ap = qc->ap; |
329 | int flags = (long)ap->host->private_data; | |
256ace9b | 330 | int dpll = hpt3x2n_use_dpll(ap, qc->tf.flags & ATA_TFLAG_WRITE); |
85cd7251 | 331 | |
256ace9b SS |
332 | if ((flags & USE_DPLL) != dpll) { |
333 | flags &= ~USE_DPLL; | |
334 | flags |= dpll; | |
335 | ap->host->private_data = (void *)(long)flags; | |
336 | ||
337 | hpt3x2n_set_clock(ap, dpll ? 0x21 : 0x23); | |
669a5db4 | 338 | } |
360ff783 | 339 | return ata_bmdma_qc_issue(qc); |
669a5db4 JG |
340 | } |
341 | ||
342 | static struct scsi_host_template hpt3x2n_sht = { | |
68d1d07b | 343 | ATA_BMDMA_SHT(DRV_NAME), |
669a5db4 JG |
344 | }; |
345 | ||
346 | /* | |
8e834c2e | 347 | * Configuration for HPT302N/371N. |
669a5db4 | 348 | */ |
85cd7251 | 349 | |
8e834c2e | 350 | static struct ata_port_operations hpt3xxn_port_ops = { |
029cfd6b | 351 | .inherits = &ata_bmdma_port_ops, |
85cd7251 | 352 | |
669a5db4 | 353 | .bmdma_stop = hpt3x2n_bmdma_stop, |
256ace9b SS |
354 | |
355 | .qc_defer = hpt3x2n_qc_defer, | |
9363c382 | 356 | .qc_issue = hpt3x2n_qc_issue, |
bda30288 | 357 | |
029cfd6b TH |
358 | .cable_detect = hpt3x2n_cable_detect, |
359 | .set_piomode = hpt3x2n_set_piomode, | |
360 | .set_dmamode = hpt3x2n_set_dmamode, | |
a1efdaba | 361 | .prereset = hpt3x2n_pre_reset, |
85cd7251 | 362 | }; |
669a5db4 | 363 | |
8e834c2e SS |
364 | /* |
365 | * Configuration for HPT372N. Same as 302N/371N but we have a mode filter. | |
366 | */ | |
367 | ||
368 | static struct ata_port_operations hpt372n_port_ops = { | |
369 | .inherits = &hpt3xxn_port_ops, | |
370 | .mode_filter = &hpt372n_filter, | |
371 | }; | |
372 | ||
669a5db4 JG |
373 | /** |
374 | * hpt3xn_calibrate_dpll - Calibrate the DPLL loop | |
85cd7251 | 375 | * @dev: PCI device |
669a5db4 JG |
376 | * |
377 | * Perform a calibration cycle on the HPT3xN DPLL. Returns 1 if this | |
378 | * succeeds | |
379 | */ | |
380 | ||
381 | static int hpt3xn_calibrate_dpll(struct pci_dev *dev) | |
382 | { | |
383 | u8 reg5b; | |
384 | u32 reg5c; | |
385 | int tries; | |
85cd7251 | 386 | |
669a5db4 JG |
387 | for(tries = 0; tries < 0x5000; tries++) { |
388 | udelay(50); | |
389 | pci_read_config_byte(dev, 0x5b, ®5b); | |
390 | if (reg5b & 0x80) { | |
391 | /* See if it stays set */ | |
392 | for(tries = 0; tries < 0x1000; tries ++) { | |
393 | pci_read_config_byte(dev, 0x5b, ®5b); | |
394 | /* Failed ? */ | |
395 | if ((reg5b & 0x80) == 0) | |
396 | return 0; | |
397 | } | |
398 | /* Turn off tuning, we have the DPLL set */ | |
399 | pci_read_config_dword(dev, 0x5c, ®5c); | |
400 | pci_write_config_dword(dev, 0x5c, reg5c & ~ 0x100); | |
401 | return 1; | |
402 | } | |
403 | } | |
404 | /* Never went stable */ | |
405 | return 0; | |
406 | } | |
407 | ||
408 | static int hpt3x2n_pci_clock(struct pci_dev *pdev) | |
409 | { | |
410 | unsigned long freq; | |
411 | u32 fcnt; | |
28e21c8c | 412 | unsigned long iobase = pci_resource_start(pdev, 4); |
85cd7251 | 413 | |
28e21c8c | 414 | fcnt = inl(iobase + 0x90); /* Not PCI readable for some chips */ |
669a5db4 JG |
415 | if ((fcnt >> 12) != 0xABCDE) { |
416 | printk(KERN_WARNING "hpt3xn: BIOS clock data not set.\n"); | |
417 | return 33; /* Not BIOS set */ | |
418 | } | |
419 | fcnt &= 0x1FF; | |
85cd7251 | 420 | |
669a5db4 | 421 | freq = (fcnt * 77) / 192; |
85cd7251 | 422 | |
669a5db4 JG |
423 | /* Clamp to bands */ |
424 | if (freq < 40) | |
425 | return 33; | |
426 | if (freq < 45) | |
427 | return 40; | |
428 | if (freq < 55) | |
429 | return 50; | |
430 | return 66; | |
431 | } | |
432 | ||
433 | /** | |
434 | * hpt3x2n_init_one - Initialise an HPT37X/302 | |
435 | * @dev: PCI device | |
436 | * @id: Entry in match table | |
437 | * | |
438 | * Initialise an HPT3x2n device. There are some interesting complications | |
439 | * here. Firstly the chip may report 366 and be one of several variants. | |
440 | * Secondly all the timings depend on the clock for the chip which we must | |
441 | * detect and look up | |
442 | * | |
443 | * This is the known chip mappings. It may be missing a couple of later | |
444 | * releases. | |
445 | * | |
446 | * Chip version PCI Rev Notes | |
447 | * HPT372 4 (HPT366) 5 Other driver | |
448 | * HPT372N 4 (HPT366) 6 UDMA133 | |
449 | * HPT372 5 (HPT372) 1 Other driver | |
450 | * HPT372N 5 (HPT372) 2 UDMA133 | |
451 | * HPT302 6 (HPT302) * Other driver | |
452 | * HPT302N 6 (HPT302) > 1 UDMA133 | |
453 | * HPT371 7 (HPT371) * Other driver | |
454 | * HPT371N 7 (HPT371) > 1 UDMA133 | |
455 | * HPT374 8 (HPT374) * Other driver | |
456 | * HPT372N 9 (HPT372N) * UDMA133 | |
457 | * | |
458 | * (1) UDMA133 support depends on the bus clock | |
669a5db4 | 459 | */ |
85cd7251 | 460 | |
669a5db4 JG |
461 | static int hpt3x2n_init_one(struct pci_dev *dev, const struct pci_device_id *id) |
462 | { | |
8e834c2e SS |
463 | /* HPT372N - UDMA133 */ |
464 | static const struct ata_port_info info_hpt372n = { | |
1d2808fd | 465 | .flags = ATA_FLAG_SLAVE_POSS, |
14bdef98 EIB |
466 | .pio_mask = ATA_PIO4, |
467 | .mwdma_mask = ATA_MWDMA2, | |
bf6263a8 | 468 | .udma_mask = ATA_UDMA6, |
8e834c2e | 469 | .port_ops = &hpt372n_port_ops |
669a5db4 | 470 | }; |
8e834c2e SS |
471 | /* HPT302N and HPT371N - UDMA133 */ |
472 | static const struct ata_port_info info_hpt3xxn = { | |
473 | .flags = ATA_FLAG_SLAVE_POSS, | |
474 | .pio_mask = ATA_PIO4, | |
475 | .mwdma_mask = ATA_MWDMA2, | |
476 | .udma_mask = ATA_UDMA6, | |
477 | .port_ops = &hpt3xxn_port_ops | |
478 | }; | |
479 | const struct ata_port_info *ppi[] = { &info_hpt3xxn, NULL }; | |
89d3b360 | 480 | u8 rev = dev->revision; |
669a5db4 | 481 | u8 irqmask; |
669a5db4 JG |
482 | unsigned int pci_mhz; |
483 | unsigned int f_low, f_high; | |
484 | int adjust; | |
28e21c8c | 485 | unsigned long iobase = pci_resource_start(dev, 4); |
256ace9b | 486 | void *hpriv = (void *)USE_DPLL; |
f08048e9 TH |
487 | int rc; |
488 | ||
489 | rc = pcim_enable_device(dev); | |
490 | if (rc) | |
491 | return rc; | |
85cd7251 | 492 | |
669a5db4 JG |
493 | switch(dev->device) { |
494 | case PCI_DEVICE_ID_TTI_HPT366: | |
8e834c2e | 495 | /* 372N if rev >= 6 */ |
89d3b360 | 496 | if (rev < 6) |
669a5db4 | 497 | return -ENODEV; |
8e834c2e | 498 | goto hpt372n; |
28e21c8c | 499 | case PCI_DEVICE_ID_TTI_HPT371: |
8e834c2e | 500 | /* 371N if rev >= 2 */ |
89d3b360 | 501 | if (rev < 2) |
28e21c8c | 502 | return -ENODEV; |
28e21c8c | 503 | break; |
669a5db4 | 504 | case PCI_DEVICE_ID_TTI_HPT372: |
8e834c2e | 505 | /* 372N if rev >= 2 */ |
89d3b360 | 506 | if (rev < 2) |
669a5db4 | 507 | return -ENODEV; |
8e834c2e | 508 | goto hpt372n; |
669a5db4 | 509 | case PCI_DEVICE_ID_TTI_HPT302: |
8e834c2e | 510 | /* 302N if rev >= 2 */ |
89d3b360 | 511 | if (rev < 2) |
669a5db4 JG |
512 | return -ENODEV; |
513 | break; | |
514 | case PCI_DEVICE_ID_TTI_HPT372N: | |
8e834c2e SS |
515 | hpt372n: |
516 | ppi[0] = &info_hpt372n; | |
669a5db4 JG |
517 | break; |
518 | default: | |
519 | printk(KERN_ERR "pata_hpt3x2n: PCI table is bogus please report (%d).\n", dev->device); | |
520 | return -ENODEV; | |
521 | } | |
522 | ||
523 | /* Ok so this is a chip we support */ | |
524 | ||
525 | pci_write_config_byte(dev, PCI_CACHE_LINE_SIZE, (L1_CACHE_BYTES / 4)); | |
526 | pci_write_config_byte(dev, PCI_LATENCY_TIMER, 0x78); | |
527 | pci_write_config_byte(dev, PCI_MIN_GNT, 0x08); | |
528 | pci_write_config_byte(dev, PCI_MAX_LAT, 0x08); | |
529 | ||
530 | pci_read_config_byte(dev, 0x5A, &irqmask); | |
531 | irqmask &= ~0x10; | |
532 | pci_write_config_byte(dev, 0x5a, irqmask); | |
533 | ||
28e21c8c AC |
534 | /* |
535 | * HPT371 chips physically have only one channel, the secondary one, | |
536 | * but the primary channel registers do exist! Go figure... | |
537 | * So, we manually disable the non-existing channel here | |
538 | * (if the BIOS hasn't done this already). | |
539 | */ | |
540 | if (dev->device == PCI_DEVICE_ID_TTI_HPT371) { | |
541 | u8 mcr1; | |
542 | pci_read_config_byte(dev, 0x50, &mcr1); | |
543 | mcr1 &= ~0x04; | |
544 | pci_write_config_byte(dev, 0x50, mcr1); | |
545 | } | |
546 | ||
669a5db4 JG |
547 | /* Tune the PLL. HPT recommend using 75 for SATA, 66 for UDMA133 or |
548 | 50 for UDMA100. Right now we always use 66 */ | |
85cd7251 | 549 | |
669a5db4 | 550 | pci_mhz = hpt3x2n_pci_clock(dev); |
85cd7251 | 551 | |
669a5db4 JG |
552 | f_low = (pci_mhz * 48) / 66; /* PCI Mhz for 66Mhz DPLL */ |
553 | f_high = f_low + 2; /* Tolerance */ | |
85cd7251 | 554 | |
669a5db4 JG |
555 | pci_write_config_dword(dev, 0x5C, (f_high << 16) | f_low | 0x100); |
556 | /* PLL clock */ | |
557 | pci_write_config_byte(dev, 0x5B, 0x21); | |
85cd7251 | 558 | |
669a5db4 JG |
559 | /* Unlike the 37x we don't try jiggling the frequency */ |
560 | for(adjust = 0; adjust < 8; adjust++) { | |
561 | if (hpt3xn_calibrate_dpll(dev)) | |
562 | break; | |
563 | pci_write_config_dword(dev, 0x5C, (f_high << 16) | f_low); | |
564 | } | |
28e21c8c | 565 | if (adjust == 8) { |
80b8987c | 566 | printk(KERN_ERR "pata_hpt3x2n: DPLL did not stabilize!\n"); |
28e21c8c AC |
567 | return -ENODEV; |
568 | } | |
669a5db4 | 569 | |
80b8987c SS |
570 | printk(KERN_INFO "pata_hpt37x: bus clock %dMHz, using 66MHz DPLL.\n", |
571 | pci_mhz); | |
669a5db4 JG |
572 | /* Set our private data up. We only need a few flags so we use |
573 | it directly */ | |
60661933 | 574 | if (pci_mhz > 60) |
256ace9b | 575 | hpriv = (void *)(PCI66 | USE_DPLL); |
60661933 SS |
576 | |
577 | /* | |
578 | * On HPT371N, if ATA clock is 66 MHz we must set bit 2 in | |
579 | * the MISC. register to stretch the UltraDMA Tss timing. | |
580 | * NOTE: This register is only writeable via I/O space. | |
581 | */ | |
582 | if (dev->device == PCI_DEVICE_ID_TTI_HPT371) | |
583 | outb(inb(iobase + 0x9c) | 0x04, iobase + 0x9c); | |
85cd7251 | 584 | |
669a5db4 | 585 | /* Now kick off ATA set up */ |
1c5afdf7 | 586 | return ata_pci_bmdma_init_one(dev, ppi, &hpt3x2n_sht, hpriv, 0); |
669a5db4 JG |
587 | } |
588 | ||
2d2744fc JG |
589 | static const struct pci_device_id hpt3x2n[] = { |
590 | { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT366), }, | |
28e21c8c | 591 | { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT371), }, |
2d2744fc JG |
592 | { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT372), }, |
593 | { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT302), }, | |
594 | { PCI_VDEVICE(TTI, PCI_DEVICE_ID_TTI_HPT372N), }, | |
595 | ||
596 | { }, | |
669a5db4 JG |
597 | }; |
598 | ||
599 | static struct pci_driver hpt3x2n_pci_driver = { | |
2d2744fc | 600 | .name = DRV_NAME, |
669a5db4 JG |
601 | .id_table = hpt3x2n, |
602 | .probe = hpt3x2n_init_one, | |
603 | .remove = ata_pci_remove_one | |
604 | }; | |
605 | ||
606 | static int __init hpt3x2n_init(void) | |
607 | { | |
608 | return pci_register_driver(&hpt3x2n_pci_driver); | |
609 | } | |
610 | ||
669a5db4 JG |
611 | static void __exit hpt3x2n_exit(void) |
612 | { | |
613 | pci_unregister_driver(&hpt3x2n_pci_driver); | |
614 | } | |
615 | ||
669a5db4 | 616 | MODULE_AUTHOR("Alan Cox"); |
0ca646db | 617 | MODULE_DESCRIPTION("low-level driver for the Highpoint HPT3xxN"); |
669a5db4 JG |
618 | MODULE_LICENSE("GPL"); |
619 | MODULE_DEVICE_TABLE(pci, hpt3x2n); | |
620 | MODULE_VERSION(DRV_VERSION); | |
621 | ||
622 | module_init(hpt3x2n_init); | |
623 | module_exit(hpt3x2n_exit); |